1 /* 2 * This file is subject to the terms and conditions of the GNU General Public 3 * License. See the file "COPYING" in the main directory of this archive 4 * for more details. 5 * 6 * Copyright (C) 2003, 2004 Ralf Baechle 7 * Copyright (C) 2004 Maciej W. Rozycki 8 */ 9 #ifndef __ASM_CPU_FEATURES_H 10 #define __ASM_CPU_FEATURES_H 11 12 #include <asm/cpu.h> 13 #include <asm/cpu-info.h> 14 #include <asm/isa-rev.h> 15 #include <cpu-feature-overrides.h> 16 17 #define __ase(ase) (cpu_data[0].ases & (ase)) 18 #define __opt(opt) (cpu_data[0].options & (opt)) 19 20 /* 21 * Check if MIPS_ISA_REV is >= isa *and* an option or ASE is detected during 22 * boot (typically by cpu_probe()). 23 * 24 * Note that these should only be used in cases where a kernel built for an 25 * older ISA *cannot* run on a CPU which supports the feature in question. For 26 * example this may be used for features introduced with MIPSr6, since a kernel 27 * built for an older ISA cannot run on a MIPSr6 CPU. This should not be used 28 * for MIPSr2 features however, since a MIPSr1 or earlier kernel might run on a 29 * MIPSr2 CPU. 30 */ 31 #define __isa_ge_and_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) && __ase(ase)) 32 #define __isa_ge_and_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) && __opt(opt)) 33 34 /* 35 * Check if MIPS_ISA_REV is >= isa *or* an option or ASE is detected during 36 * boot (typically by cpu_probe()). 37 * 38 * These are for use with features that are optional up until a particular ISA 39 * revision & then become required. 40 */ 41 #define __isa_ge_or_ase(isa, ase) ((MIPS_ISA_REV >= (isa)) || __ase(ase)) 42 #define __isa_ge_or_opt(isa, opt) ((MIPS_ISA_REV >= (isa)) || __opt(opt)) 43 44 /* 45 * Check if MIPS_ISA_REV is < isa *and* an option or ASE is detected during 46 * boot (typically by cpu_probe()). 47 * 48 * These are for use with features that are optional up until a particular ISA 49 * revision & are then removed - ie. no longer present in any CPU implementing 50 * the given ISA revision. 51 */ 52 #define __isa_lt_and_ase(isa, ase) ((MIPS_ISA_REV < (isa)) && __ase(ase)) 53 #define __isa_lt_and_opt(isa, opt) ((MIPS_ISA_REV < (isa)) && __opt(opt)) 54 55 /* 56 * SMP assumption: Options of CPU 0 are a superset of all processors. 57 * This is true for all known MIPS systems. 58 */ 59 #ifndef cpu_has_tlb 60 #define cpu_has_tlb __opt(MIPS_CPU_TLB) 61 #endif 62 #ifndef cpu_has_ftlb 63 #define cpu_has_ftlb __opt(MIPS_CPU_FTLB) 64 #endif 65 #ifndef cpu_has_tlbinv 66 #define cpu_has_tlbinv __opt(MIPS_CPU_TLBINV) 67 #endif 68 #ifndef cpu_has_segments 69 #define cpu_has_segments __opt(MIPS_CPU_SEGMENTS) 70 #endif 71 #ifndef cpu_has_eva 72 #define cpu_has_eva __opt(MIPS_CPU_EVA) 73 #endif 74 #ifndef cpu_has_htw 75 #define cpu_has_htw __opt(MIPS_CPU_HTW) 76 #endif 77 #ifndef cpu_has_ldpte 78 #define cpu_has_ldpte __opt(MIPS_CPU_LDPTE) 79 #endif 80 #ifndef cpu_has_rixiex 81 #define cpu_has_rixiex __isa_ge_or_opt(6, MIPS_CPU_RIXIEX) 82 #endif 83 #ifndef cpu_has_maar 84 #define cpu_has_maar __opt(MIPS_CPU_MAAR) 85 #endif 86 #ifndef cpu_has_rw_llb 87 #define cpu_has_rw_llb __isa_ge_or_opt(6, MIPS_CPU_RW_LLB) 88 #endif 89 90 /* 91 * For the moment we don't consider R6000 and R8000 so we can assume that 92 * anything that doesn't support R4000-style exceptions and interrupts is 93 * R3000-like. Users should still treat these two macro definitions as 94 * opaque. 95 */ 96 #ifndef cpu_has_3kex 97 #define cpu_has_3kex (!cpu_has_4kex) 98 #endif 99 #ifndef cpu_has_4kex 100 #define cpu_has_4kex __isa_ge_or_opt(1, MIPS_CPU_4KEX) 101 #endif 102 #ifndef cpu_has_3k_cache 103 #define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE) 104 #endif 105 #define cpu_has_6k_cache 0 106 #define cpu_has_8k_cache 0 107 #ifndef cpu_has_4k_cache 108 #define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE) 109 #endif 110 #ifndef cpu_has_tx39_cache 111 #define cpu_has_tx39_cache __opt(MIPS_CPU_TX39_CACHE) 112 #endif 113 #ifndef cpu_has_octeon_cache 114 #define cpu_has_octeon_cache 0 115 #endif 116 /* Don't override `cpu_has_fpu' to 1 or the "nofpu" option won't work. */ 117 #ifndef cpu_has_fpu 118 #define cpu_has_fpu (current_cpu_data.options & MIPS_CPU_FPU) 119 #define raw_cpu_has_fpu (raw_current_cpu_data.options & MIPS_CPU_FPU) 120 #else 121 #define raw_cpu_has_fpu cpu_has_fpu 122 #endif 123 #ifndef cpu_has_32fpr 124 #define cpu_has_32fpr __isa_ge_or_opt(1, MIPS_CPU_32FPR) 125 #endif 126 #ifndef cpu_has_counter 127 #define cpu_has_counter __opt(MIPS_CPU_COUNTER) 128 #endif 129 #ifndef cpu_has_watch 130 #define cpu_has_watch __opt(MIPS_CPU_WATCH) 131 #endif 132 #ifndef cpu_has_divec 133 #define cpu_has_divec __isa_ge_or_opt(1, MIPS_CPU_DIVEC) 134 #endif 135 #ifndef cpu_has_vce 136 #define cpu_has_vce __opt(MIPS_CPU_VCE) 137 #endif 138 #ifndef cpu_has_cache_cdex_p 139 #define cpu_has_cache_cdex_p __opt(MIPS_CPU_CACHE_CDEX_P) 140 #endif 141 #ifndef cpu_has_cache_cdex_s 142 #define cpu_has_cache_cdex_s __opt(MIPS_CPU_CACHE_CDEX_S) 143 #endif 144 #ifndef cpu_has_prefetch 145 #define cpu_has_prefetch __isa_ge_or_opt(1, MIPS_CPU_PREFETCH) 146 #endif 147 #ifndef cpu_has_mcheck 148 #define cpu_has_mcheck __isa_ge_or_opt(1, MIPS_CPU_MCHECK) 149 #endif 150 #ifndef cpu_has_ejtag 151 #define cpu_has_ejtag __opt(MIPS_CPU_EJTAG) 152 #endif 153 #ifndef cpu_has_llsc 154 #define cpu_has_llsc __isa_ge_or_opt(1, MIPS_CPU_LLSC) 155 #endif 156 #ifndef cpu_has_bp_ghist 157 #define cpu_has_bp_ghist __opt(MIPS_CPU_BP_GHIST) 158 #endif 159 #ifndef kernel_uses_llsc 160 #define kernel_uses_llsc cpu_has_llsc 161 #endif 162 #ifndef cpu_has_guestctl0ext 163 #define cpu_has_guestctl0ext __opt(MIPS_CPU_GUESTCTL0EXT) 164 #endif 165 #ifndef cpu_has_guestctl1 166 #define cpu_has_guestctl1 __opt(MIPS_CPU_GUESTCTL1) 167 #endif 168 #ifndef cpu_has_guestctl2 169 #define cpu_has_guestctl2 __opt(MIPS_CPU_GUESTCTL2) 170 #endif 171 #ifndef cpu_has_guestid 172 #define cpu_has_guestid __opt(MIPS_CPU_GUESTID) 173 #endif 174 #ifndef cpu_has_drg 175 #define cpu_has_drg __opt(MIPS_CPU_DRG) 176 #endif 177 #ifndef cpu_has_mips16 178 #define cpu_has_mips16 __isa_lt_and_ase(6, MIPS_ASE_MIPS16) 179 #endif 180 #ifndef cpu_has_mips16e2 181 #define cpu_has_mips16e2 __isa_lt_and_ase(6, MIPS_ASE_MIPS16E2) 182 #endif 183 #ifndef cpu_has_mdmx 184 #define cpu_has_mdmx __isa_lt_and_ase(6, MIPS_ASE_MDMX) 185 #endif 186 #ifndef cpu_has_mips3d 187 #define cpu_has_mips3d __isa_lt_and_ase(6, MIPS_ASE_MIPS3D) 188 #endif 189 #ifndef cpu_has_smartmips 190 #define cpu_has_smartmips __isa_lt_and_ase(6, MIPS_ASE_SMARTMIPS) 191 #endif 192 193 #ifndef cpu_has_rixi 194 #define cpu_has_rixi __isa_ge_or_opt(6, MIPS_CPU_RIXI) 195 #endif 196 197 #ifndef cpu_has_mmips 198 # ifdef CONFIG_SYS_SUPPORTS_MICROMIPS 199 # define cpu_has_mmips __opt(MIPS_CPU_MICROMIPS) 200 # else 201 # define cpu_has_mmips 0 202 # endif 203 #endif 204 205 #ifndef cpu_has_lpa 206 #define cpu_has_lpa __opt(MIPS_CPU_LPA) 207 #endif 208 #ifndef cpu_has_mvh 209 #define cpu_has_mvh __opt(MIPS_CPU_MVH) 210 #endif 211 #ifndef cpu_has_xpa 212 #define cpu_has_xpa (cpu_has_lpa && cpu_has_mvh) 213 #endif 214 #ifndef cpu_has_vtag_icache 215 #define cpu_has_vtag_icache (cpu_data[0].icache.flags & MIPS_CACHE_VTAG) 216 #endif 217 #ifndef cpu_has_dc_aliases 218 #define cpu_has_dc_aliases (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES) 219 #endif 220 #ifndef cpu_has_ic_fills_f_dc 221 #define cpu_has_ic_fills_f_dc (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC) 222 #endif 223 #ifndef cpu_has_pindexed_dcache 224 #define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX) 225 #endif 226 #ifndef cpu_has_local_ebase 227 #define cpu_has_local_ebase 1 228 #endif 229 230 /* 231 * I-Cache snoops remote store. This only matters on SMP. Some multiprocessors 232 * such as the R10000 have I-Caches that snoop local stores; the embedded ones 233 * don't. For maintaining I-cache coherency this means we need to flush the 234 * D-cache all the way back to whever the I-cache does refills from, so the 235 * I-cache has a chance to see the new data at all. Then we have to flush the 236 * I-cache also. 237 * Note we may have been rescheduled and may no longer be running on the CPU 238 * that did the store so we can't optimize this into only doing the flush on 239 * the local CPU. 240 */ 241 #ifndef cpu_icache_snoops_remote_store 242 #ifdef CONFIG_SMP 243 #define cpu_icache_snoops_remote_store (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE) 244 #else 245 #define cpu_icache_snoops_remote_store 1 246 #endif 247 #endif 248 249 /* __builtin_constant_p(cpu_has_mips_r) && cpu_has_mips_r */ 250 #if !((defined(cpu_has_mips32r1) && cpu_has_mips32r1) || \ 251 (defined(cpu_has_mips32r2) && cpu_has_mips32r2) || \ 252 (defined(cpu_has_mips32r6) && cpu_has_mips32r6) || \ 253 (defined(cpu_has_mips64r1) && cpu_has_mips64r1) || \ 254 (defined(cpu_has_mips64r2) && cpu_has_mips64r2) || \ 255 (defined(cpu_has_mips64r6) && cpu_has_mips64r6)) 256 #define CPU_NO_EFFICIENT_FFS 1 257 #endif 258 259 #ifndef cpu_has_mips_1 260 # define cpu_has_mips_1 (!cpu_has_mips_r6) 261 #endif 262 #ifndef cpu_has_mips_2 263 # define cpu_has_mips_2 (cpu_data[0].isa_level & MIPS_CPU_ISA_II) 264 #endif 265 #ifndef cpu_has_mips_3 266 # define cpu_has_mips_3 (cpu_data[0].isa_level & MIPS_CPU_ISA_III) 267 #endif 268 #ifndef cpu_has_mips_4 269 # define cpu_has_mips_4 (cpu_data[0].isa_level & MIPS_CPU_ISA_IV) 270 #endif 271 #ifndef cpu_has_mips_5 272 # define cpu_has_mips_5 (cpu_data[0].isa_level & MIPS_CPU_ISA_V) 273 #endif 274 #ifndef cpu_has_mips32r1 275 # define cpu_has_mips32r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1) 276 #endif 277 #ifndef cpu_has_mips32r2 278 # define cpu_has_mips32r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2) 279 #endif 280 #ifndef cpu_has_mips32r6 281 # define cpu_has_mips32r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R6) 282 #endif 283 #ifndef cpu_has_mips64r1 284 # define cpu_has_mips64r1 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1) 285 #endif 286 #ifndef cpu_has_mips64r2 287 # define cpu_has_mips64r2 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2) 288 #endif 289 #ifndef cpu_has_mips64r6 290 # define cpu_has_mips64r6 (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R6) 291 #endif 292 293 /* 294 * Shortcuts ... 295 */ 296 #define cpu_has_mips_2_3_4_5 (cpu_has_mips_2 | cpu_has_mips_3_4_5) 297 #define cpu_has_mips_3_4_5 (cpu_has_mips_3 | cpu_has_mips_4_5) 298 #define cpu_has_mips_4_5 (cpu_has_mips_4 | cpu_has_mips_5) 299 300 #define cpu_has_mips_2_3_4_5_r (cpu_has_mips_2 | cpu_has_mips_3_4_5_r) 301 #define cpu_has_mips_3_4_5_r (cpu_has_mips_3 | cpu_has_mips_4_5_r) 302 #define cpu_has_mips_4_5_r (cpu_has_mips_4 | cpu_has_mips_5_r) 303 #define cpu_has_mips_5_r (cpu_has_mips_5 | cpu_has_mips_r) 304 305 #define cpu_has_mips_3_4_5_64_r2_r6 \ 306 (cpu_has_mips_3 | cpu_has_mips_4_5_64_r2_r6) 307 #define cpu_has_mips_4_5_64_r2_r6 \ 308 (cpu_has_mips_4_5 | cpu_has_mips64r1 | \ 309 cpu_has_mips_r2 | cpu_has_mips_r6) 310 311 #define cpu_has_mips32 (cpu_has_mips32r1 | cpu_has_mips32r2 | cpu_has_mips32r6) 312 #define cpu_has_mips64 (cpu_has_mips64r1 | cpu_has_mips64r2 | cpu_has_mips64r6) 313 #define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1) 314 #define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2) 315 #define cpu_has_mips_r6 (cpu_has_mips32r6 | cpu_has_mips64r6) 316 #define cpu_has_mips_r (cpu_has_mips32r1 | cpu_has_mips32r2 | \ 317 cpu_has_mips32r6 | cpu_has_mips64r1 | \ 318 cpu_has_mips64r2 | cpu_has_mips64r6) 319 320 /* MIPSR2 and MIPSR6 have a lot of similarities */ 321 #define cpu_has_mips_r2_r6 (cpu_has_mips_r2 | cpu_has_mips_r6) 322 323 /* 324 * cpu_has_mips_r2_exec_hazard - return if IHB is required on current processor 325 * 326 * Returns non-zero value if the current processor implementation requires 327 * an IHB instruction to deal with an instruction hazard as per MIPS R2 328 * architecture specification, zero otherwise. 329 */ 330 #ifndef cpu_has_mips_r2_exec_hazard 331 #define cpu_has_mips_r2_exec_hazard \ 332 ({ \ 333 int __res; \ 334 \ 335 switch (current_cpu_type()) { \ 336 case CPU_M14KC: \ 337 case CPU_74K: \ 338 case CPU_1074K: \ 339 case CPU_PROAPTIV: \ 340 case CPU_P5600: \ 341 case CPU_M5150: \ 342 case CPU_QEMU_GENERIC: \ 343 case CPU_CAVIUM_OCTEON: \ 344 case CPU_CAVIUM_OCTEON_PLUS: \ 345 case CPU_CAVIUM_OCTEON2: \ 346 case CPU_CAVIUM_OCTEON3: \ 347 __res = 0; \ 348 break; \ 349 \ 350 default: \ 351 __res = 1; \ 352 } \ 353 \ 354 __res; \ 355 }) 356 #endif 357 358 /* 359 * MIPS32, MIPS64, VR5500, IDT32332, IDT32334 and maybe a few other 360 * pre-MIPS32/MIPS64 processors have CLO, CLZ. The IDT RC64574 is 64-bit and 361 * has CLO and CLZ but not DCLO nor DCLZ. For 64-bit kernels 362 * cpu_has_clo_clz also indicates the availability of DCLO and DCLZ. 363 */ 364 #ifndef cpu_has_clo_clz 365 #define cpu_has_clo_clz cpu_has_mips_r 366 #endif 367 368 /* 369 * MIPS32 R2, MIPS64 R2, Loongson 3A and Octeon have WSBH. 370 * MIPS64 R2, Loongson 3A and Octeon have WSBH, DSBH and DSHD. 371 * This indicates the availability of WSBH and in case of 64 bit CPUs also 372 * DSBH and DSHD. 373 */ 374 #ifndef cpu_has_wsbh 375 #define cpu_has_wsbh cpu_has_mips_r2 376 #endif 377 378 #ifndef cpu_has_dsp 379 #define cpu_has_dsp __ase(MIPS_ASE_DSP) 380 #endif 381 382 #ifndef cpu_has_dsp2 383 #define cpu_has_dsp2 __ase(MIPS_ASE_DSP2P) 384 #endif 385 386 #ifndef cpu_has_dsp3 387 #define cpu_has_dsp3 __ase(MIPS_ASE_DSP3) 388 #endif 389 390 #ifndef cpu_has_loongson_mmi 391 #define cpu_has_loongson_mmi __ase(MIPS_ASE_LOONGSON_MMI) 392 #endif 393 394 #ifndef cpu_has_loongson_cam 395 #define cpu_has_loongson_cam __ase(MIPS_ASE_LOONGSON_CAM) 396 #endif 397 398 #ifndef cpu_has_loongson_ext 399 #define cpu_has_loongson_ext __ase(MIPS_ASE_LOONGSON_EXT) 400 #endif 401 402 #ifndef cpu_has_loongson_ext2 403 #define cpu_has_loongson_ext2 __ase(MIPS_ASE_LOONGSON_EXT2) 404 #endif 405 406 #ifndef cpu_has_mipsmt 407 #define cpu_has_mipsmt __isa_lt_and_ase(6, MIPS_ASE_MIPSMT) 408 #endif 409 410 #ifndef cpu_has_vp 411 #define cpu_has_vp __isa_ge_and_opt(6, MIPS_CPU_VP) 412 #endif 413 414 #ifndef cpu_has_userlocal 415 #define cpu_has_userlocal __isa_ge_or_opt(6, MIPS_CPU_ULRI) 416 #endif 417 418 #ifdef CONFIG_32BIT 419 # ifndef cpu_has_nofpuex 420 # define cpu_has_nofpuex __isa_lt_and_opt(1, MIPS_CPU_NOFPUEX) 421 # endif 422 # ifndef cpu_has_64bits 423 # define cpu_has_64bits (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 424 # endif 425 # ifndef cpu_has_64bit_zero_reg 426 # define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT) 427 # endif 428 # ifndef cpu_has_64bit_gp_regs 429 # define cpu_has_64bit_gp_regs 0 430 # endif 431 # ifndef cpu_has_64bit_addresses 432 # define cpu_has_64bit_addresses 0 433 # endif 434 # ifndef cpu_vmbits 435 # define cpu_vmbits 31 436 # endif 437 #endif 438 439 #ifdef CONFIG_64BIT 440 # ifndef cpu_has_nofpuex 441 # define cpu_has_nofpuex 0 442 # endif 443 # ifndef cpu_has_64bits 444 # define cpu_has_64bits 1 445 # endif 446 # ifndef cpu_has_64bit_zero_reg 447 # define cpu_has_64bit_zero_reg 1 448 # endif 449 # ifndef cpu_has_64bit_gp_regs 450 # define cpu_has_64bit_gp_regs 1 451 # endif 452 # ifndef cpu_has_64bit_addresses 453 # define cpu_has_64bit_addresses 1 454 # endif 455 # ifndef cpu_vmbits 456 # define cpu_vmbits cpu_data[0].vmbits 457 # define __NEED_VMBITS_PROBE 458 # endif 459 #endif 460 461 #if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint) 462 # define cpu_has_vint __opt(MIPS_CPU_VINT) 463 #elif !defined(cpu_has_vint) 464 # define cpu_has_vint 0 465 #endif 466 467 #if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic) 468 # define cpu_has_veic __opt(MIPS_CPU_VEIC) 469 #elif !defined(cpu_has_veic) 470 # define cpu_has_veic 0 471 #endif 472 473 #ifndef cpu_has_inclusive_pcaches 474 #define cpu_has_inclusive_pcaches __opt(MIPS_CPU_INCLUSIVE_CACHES) 475 #endif 476 477 #ifndef cpu_dcache_line_size 478 #define cpu_dcache_line_size() cpu_data[0].dcache.linesz 479 #endif 480 #ifndef cpu_icache_line_size 481 #define cpu_icache_line_size() cpu_data[0].icache.linesz 482 #endif 483 #ifndef cpu_scache_line_size 484 #define cpu_scache_line_size() cpu_data[0].scache.linesz 485 #endif 486 #ifndef cpu_tcache_line_size 487 #define cpu_tcache_line_size() cpu_data[0].tcache.linesz 488 #endif 489 490 #ifndef cpu_hwrena_impl_bits 491 #define cpu_hwrena_impl_bits 0 492 #endif 493 494 #ifndef cpu_has_perf_cntr_intr_bit 495 #define cpu_has_perf_cntr_intr_bit __opt(MIPS_CPU_PCI) 496 #endif 497 498 #ifndef cpu_has_vz 499 #define cpu_has_vz __ase(MIPS_ASE_VZ) 500 #endif 501 502 #if defined(CONFIG_CPU_HAS_MSA) && !defined(cpu_has_msa) 503 # define cpu_has_msa __ase(MIPS_ASE_MSA) 504 #elif !defined(cpu_has_msa) 505 # define cpu_has_msa 0 506 #endif 507 508 #ifndef cpu_has_ufr 509 # define cpu_has_ufr __opt(MIPS_CPU_UFR) 510 #endif 511 512 #ifndef cpu_has_fre 513 # define cpu_has_fre __opt(MIPS_CPU_FRE) 514 #endif 515 516 #ifndef cpu_has_cdmm 517 # define cpu_has_cdmm __opt(MIPS_CPU_CDMM) 518 #endif 519 520 #ifndef cpu_has_small_pages 521 # define cpu_has_small_pages __opt(MIPS_CPU_SP) 522 #endif 523 524 #ifndef cpu_has_nan_legacy 525 #define cpu_has_nan_legacy __isa_lt_and_opt(6, MIPS_CPU_NAN_LEGACY) 526 #endif 527 #ifndef cpu_has_nan_2008 528 #define cpu_has_nan_2008 __isa_ge_or_opt(6, MIPS_CPU_NAN_2008) 529 #endif 530 531 #ifndef cpu_has_ebase_wg 532 # define cpu_has_ebase_wg __opt(MIPS_CPU_EBASE_WG) 533 #endif 534 535 #ifndef cpu_has_badinstr 536 # define cpu_has_badinstr __isa_ge_or_opt(6, MIPS_CPU_BADINSTR) 537 #endif 538 539 #ifndef cpu_has_badinstrp 540 # define cpu_has_badinstrp __isa_ge_or_opt(6, MIPS_CPU_BADINSTRP) 541 #endif 542 543 #ifndef cpu_has_contextconfig 544 # define cpu_has_contextconfig __opt(MIPS_CPU_CTXTC) 545 #endif 546 547 #ifndef cpu_has_perf 548 # define cpu_has_perf __opt(MIPS_CPU_PERF) 549 #endif 550 551 #ifdef CONFIG_SMP 552 /* 553 * Some systems share FTLB RAMs between threads within a core (siblings in 554 * kernel parlance). This means that FTLB entries may become invalid at almost 555 * any point when an entry is evicted due to a sibling thread writing an entry 556 * to the shared FTLB RAM. 557 * 558 * This is only relevant to SMP systems, and the only systems that exhibit this 559 * property implement MIPSr6 or higher so we constrain support for this to 560 * kernels that will run on such systems. 561 */ 562 # ifndef cpu_has_shared_ftlb_ram 563 # define cpu_has_shared_ftlb_ram \ 564 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_RAM) 565 # endif 566 567 /* 568 * Some systems take this a step further & share FTLB entries between siblings. 569 * This is implemented as TLB writes happening as usual, but if an entry 570 * written by a sibling exists in the shared FTLB for a translation which would 571 * otherwise cause a TLB refill exception then the CPU will use the entry 572 * written by its sibling rather than triggering a refill & writing a matching 573 * TLB entry for itself. 574 * 575 * This is naturally only valid if a TLB entry is known to be suitable for use 576 * on all siblings in a CPU, and so it only takes effect when MMIDs are in use 577 * rather than ASIDs or when a TLB entry is marked global. 578 */ 579 # ifndef cpu_has_shared_ftlb_entries 580 # define cpu_has_shared_ftlb_entries \ 581 __isa_ge_and_opt(6, MIPS_CPU_SHARED_FTLB_ENTRIES) 582 # endif 583 #endif /* SMP */ 584 585 #ifndef cpu_has_shared_ftlb_ram 586 # define cpu_has_shared_ftlb_ram 0 587 #endif 588 #ifndef cpu_has_shared_ftlb_entries 589 # define cpu_has_shared_ftlb_entries 0 590 #endif 591 592 #ifdef CONFIG_MIPS_MT_SMP 593 # define cpu_has_mipsmt_pertccounters \ 594 __isa_lt_and_opt(6, MIPS_CPU_MT_PER_TC_PERF_COUNTERS) 595 #else 596 # define cpu_has_mipsmt_pertccounters 0 597 #endif /* CONFIG_MIPS_MT_SMP */ 598 599 /* 600 * Guest capabilities 601 */ 602 #ifndef cpu_guest_has_conf1 603 #define cpu_guest_has_conf1 (cpu_data[0].guest.conf & (1 << 1)) 604 #endif 605 #ifndef cpu_guest_has_conf2 606 #define cpu_guest_has_conf2 (cpu_data[0].guest.conf & (1 << 2)) 607 #endif 608 #ifndef cpu_guest_has_conf3 609 #define cpu_guest_has_conf3 (cpu_data[0].guest.conf & (1 << 3)) 610 #endif 611 #ifndef cpu_guest_has_conf4 612 #define cpu_guest_has_conf4 (cpu_data[0].guest.conf & (1 << 4)) 613 #endif 614 #ifndef cpu_guest_has_conf5 615 #define cpu_guest_has_conf5 (cpu_data[0].guest.conf & (1 << 5)) 616 #endif 617 #ifndef cpu_guest_has_conf6 618 #define cpu_guest_has_conf6 (cpu_data[0].guest.conf & (1 << 6)) 619 #endif 620 #ifndef cpu_guest_has_conf7 621 #define cpu_guest_has_conf7 (cpu_data[0].guest.conf & (1 << 7)) 622 #endif 623 #ifndef cpu_guest_has_fpu 624 #define cpu_guest_has_fpu (cpu_data[0].guest.options & MIPS_CPU_FPU) 625 #endif 626 #ifndef cpu_guest_has_watch 627 #define cpu_guest_has_watch (cpu_data[0].guest.options & MIPS_CPU_WATCH) 628 #endif 629 #ifndef cpu_guest_has_contextconfig 630 #define cpu_guest_has_contextconfig (cpu_data[0].guest.options & MIPS_CPU_CTXTC) 631 #endif 632 #ifndef cpu_guest_has_segments 633 #define cpu_guest_has_segments (cpu_data[0].guest.options & MIPS_CPU_SEGMENTS) 634 #endif 635 #ifndef cpu_guest_has_badinstr 636 #define cpu_guest_has_badinstr (cpu_data[0].guest.options & MIPS_CPU_BADINSTR) 637 #endif 638 #ifndef cpu_guest_has_badinstrp 639 #define cpu_guest_has_badinstrp (cpu_data[0].guest.options & MIPS_CPU_BADINSTRP) 640 #endif 641 #ifndef cpu_guest_has_htw 642 #define cpu_guest_has_htw (cpu_data[0].guest.options & MIPS_CPU_HTW) 643 #endif 644 #ifndef cpu_guest_has_mvh 645 #define cpu_guest_has_mvh (cpu_data[0].guest.options & MIPS_CPU_MVH) 646 #endif 647 #ifndef cpu_guest_has_msa 648 #define cpu_guest_has_msa (cpu_data[0].guest.ases & MIPS_ASE_MSA) 649 #endif 650 #ifndef cpu_guest_has_kscr 651 #define cpu_guest_has_kscr(n) (cpu_data[0].guest.kscratch_mask & (1u << (n))) 652 #endif 653 #ifndef cpu_guest_has_rw_llb 654 #define cpu_guest_has_rw_llb (cpu_has_mips_r6 || (cpu_data[0].guest.options & MIPS_CPU_RW_LLB)) 655 #endif 656 #ifndef cpu_guest_has_perf 657 #define cpu_guest_has_perf (cpu_data[0].guest.options & MIPS_CPU_PERF) 658 #endif 659 #ifndef cpu_guest_has_maar 660 #define cpu_guest_has_maar (cpu_data[0].guest.options & MIPS_CPU_MAAR) 661 #endif 662 #ifndef cpu_guest_has_userlocal 663 #define cpu_guest_has_userlocal (cpu_data[0].guest.options & MIPS_CPU_ULRI) 664 #endif 665 666 /* 667 * Guest dynamic capabilities 668 */ 669 #ifndef cpu_guest_has_dyn_fpu 670 #define cpu_guest_has_dyn_fpu (cpu_data[0].guest.options_dyn & MIPS_CPU_FPU) 671 #endif 672 #ifndef cpu_guest_has_dyn_watch 673 #define cpu_guest_has_dyn_watch (cpu_data[0].guest.options_dyn & MIPS_CPU_WATCH) 674 #endif 675 #ifndef cpu_guest_has_dyn_contextconfig 676 #define cpu_guest_has_dyn_contextconfig (cpu_data[0].guest.options_dyn & MIPS_CPU_CTXTC) 677 #endif 678 #ifndef cpu_guest_has_dyn_perf 679 #define cpu_guest_has_dyn_perf (cpu_data[0].guest.options_dyn & MIPS_CPU_PERF) 680 #endif 681 #ifndef cpu_guest_has_dyn_msa 682 #define cpu_guest_has_dyn_msa (cpu_data[0].guest.ases_dyn & MIPS_ASE_MSA) 683 #endif 684 #ifndef cpu_guest_has_dyn_maar 685 #define cpu_guest_has_dyn_maar (cpu_data[0].guest.options_dyn & MIPS_CPU_MAAR) 686 #endif 687 688 #endif /* __ASM_CPU_FEATURES_H */ 689