1 /*
2 * PowerNV setup code.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #undef DEBUG
13
14 #include <linux/cpu.h>
15 #include <linux/errno.h>
16 #include <linux/sched.h>
17 #include <linux/kernel.h>
18 #include <linux/tty.h>
19 #include <linux/reboot.h>
20 #include <linux/init.h>
21 #include <linux/console.h>
22 #include <linux/delay.h>
23 #include <linux/irq.h>
24 #include <linux/seq_file.h>
25 #include <linux/of.h>
26 #include <linux/of_fdt.h>
27 #include <linux/interrupt.h>
28 #include <linux/bug.h>
29 #include <linux/pci.h>
30 #include <linux/cpufreq.h>
31
32 #include <asm/machdep.h>
33 #include <asm/firmware.h>
34 #include <asm/xics.h>
35 #include <asm/xive.h>
36 #include <asm/opal.h>
37 #include <asm/kexec.h>
38 #include <asm/smp.h>
39 #include <asm/tm.h>
40 #include <asm/setup.h>
41 #include <asm/security_features.h>
42
43 #include "powernv.h"
44
45
fw_feature_is(const char * state,const char * name,struct device_node * fw_features)46 static bool fw_feature_is(const char *state, const char *name,
47 struct device_node *fw_features)
48 {
49 struct device_node *np;
50 bool rc = false;
51
52 np = of_get_child_by_name(fw_features, name);
53 if (np) {
54 rc = of_property_read_bool(np, state);
55 of_node_put(np);
56 }
57
58 return rc;
59 }
60
init_fw_feat_flags(struct device_node * np)61 static void init_fw_feat_flags(struct device_node *np)
62 {
63 if (fw_feature_is("enabled", "inst-spec-barrier-ori31,31,0", np))
64 security_ftr_set(SEC_FTR_SPEC_BAR_ORI31);
65
66 if (fw_feature_is("enabled", "fw-bcctrl-serialized", np))
67 security_ftr_set(SEC_FTR_BCCTRL_SERIALISED);
68
69 if (fw_feature_is("enabled", "inst-l1d-flush-ori30,30,0", np))
70 security_ftr_set(SEC_FTR_L1D_FLUSH_ORI30);
71
72 if (fw_feature_is("enabled", "inst-l1d-flush-trig2", np))
73 security_ftr_set(SEC_FTR_L1D_FLUSH_TRIG2);
74
75 if (fw_feature_is("enabled", "fw-l1d-thread-split", np))
76 security_ftr_set(SEC_FTR_L1D_THREAD_PRIV);
77
78 if (fw_feature_is("enabled", "fw-count-cache-disabled", np))
79 security_ftr_set(SEC_FTR_COUNT_CACHE_DISABLED);
80
81 if (fw_feature_is("enabled", "fw-count-cache-flush-bcctr2,0,0", np))
82 security_ftr_set(SEC_FTR_BCCTR_FLUSH_ASSIST);
83
84 if (fw_feature_is("enabled", "needs-count-cache-flush-on-context-switch", np))
85 security_ftr_set(SEC_FTR_FLUSH_COUNT_CACHE);
86
87 /*
88 * The features below are enabled by default, so we instead look to see
89 * if firmware has *disabled* them, and clear them if so.
90 */
91 if (fw_feature_is("disabled", "speculation-policy-favor-security", np))
92 security_ftr_clear(SEC_FTR_FAVOUR_SECURITY);
93
94 if (fw_feature_is("disabled", "needs-l1d-flush-msr-pr-0-to-1", np))
95 security_ftr_clear(SEC_FTR_L1D_FLUSH_PR);
96
97 if (fw_feature_is("disabled", "needs-l1d-flush-msr-hv-1-to-0", np))
98 security_ftr_clear(SEC_FTR_L1D_FLUSH_HV);
99
100 if (fw_feature_is("disabled", "needs-spec-barrier-for-bound-checks", np))
101 security_ftr_clear(SEC_FTR_BNDS_CHK_SPEC_BAR);
102 }
103
pnv_setup_rfi_flush(void)104 static void pnv_setup_rfi_flush(void)
105 {
106 struct device_node *np, *fw_features;
107 enum l1d_flush_type type;
108 bool enable;
109
110 /* Default to fallback in case fw-features are not available */
111 type = L1D_FLUSH_FALLBACK;
112
113 np = of_find_node_by_name(NULL, "ibm,opal");
114 fw_features = of_get_child_by_name(np, "fw-features");
115 of_node_put(np);
116
117 if (fw_features) {
118 init_fw_feat_flags(fw_features);
119 of_node_put(fw_features);
120
121 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_TRIG2))
122 type = L1D_FLUSH_MTTRIG;
123
124 if (security_ftr_enabled(SEC_FTR_L1D_FLUSH_ORI30))
125 type = L1D_FLUSH_ORI;
126 }
127
128 /*
129 * If we are non-Power9 bare metal, we don't need to flush on kernel
130 * entry or after user access: they fix a P9 specific vulnerability.
131 */
132 if (!pvr_version_is(PVR_POWER9)) {
133 security_ftr_clear(SEC_FTR_L1D_FLUSH_ENTRY);
134 security_ftr_clear(SEC_FTR_L1D_FLUSH_UACCESS);
135 }
136
137 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) && \
138 (security_ftr_enabled(SEC_FTR_L1D_FLUSH_PR) || \
139 security_ftr_enabled(SEC_FTR_L1D_FLUSH_HV));
140
141 setup_rfi_flush(type, enable);
142 setup_count_cache_flush();
143
144 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
145 security_ftr_enabled(SEC_FTR_L1D_FLUSH_ENTRY);
146 setup_entry_flush(enable);
147
148 enable = security_ftr_enabled(SEC_FTR_FAVOUR_SECURITY) &&
149 security_ftr_enabled(SEC_FTR_L1D_FLUSH_UACCESS);
150 setup_uaccess_flush(enable);
151 }
152
pnv_setup_arch(void)153 static void __init pnv_setup_arch(void)
154 {
155 set_arch_panic_timeout(10, ARCH_PANIC_TIMEOUT);
156
157 pnv_setup_rfi_flush();
158 setup_stf_barrier();
159
160 /* Initialize SMP */
161 pnv_smp_init();
162
163 /* Setup PCI */
164 pnv_pci_init();
165
166 /* Setup RTC and NVRAM callbacks */
167 if (firmware_has_feature(FW_FEATURE_OPAL))
168 opal_nvram_init();
169
170 /* Enable NAP mode */
171 powersave_nap = 1;
172
173 /* XXX PMCS */
174 }
175
pnv_init(void)176 static void __init pnv_init(void)
177 {
178 /*
179 * Initialize the LPC bus now so that legacy serial
180 * ports can be found on it
181 */
182 opal_lpc_init();
183
184 #ifdef CONFIG_HVC_OPAL
185 if (firmware_has_feature(FW_FEATURE_OPAL))
186 hvc_opal_init_early();
187 else
188 #endif
189 add_preferred_console("hvc", 0, NULL);
190 }
191
pnv_init_IRQ(void)192 static void __init pnv_init_IRQ(void)
193 {
194 /* Try using a XIVE if available, otherwise use a XICS */
195 if (!xive_native_init())
196 xics_init();
197
198 WARN_ON(!ppc_md.get_irq);
199 }
200
pnv_show_cpuinfo(struct seq_file * m)201 static void pnv_show_cpuinfo(struct seq_file *m)
202 {
203 struct device_node *root;
204 const char *model = "";
205
206 root = of_find_node_by_path("/");
207 if (root)
208 model = of_get_property(root, "model", NULL);
209 seq_printf(m, "machine\t\t: PowerNV %s\n", model);
210 if (firmware_has_feature(FW_FEATURE_OPAL))
211 seq_printf(m, "firmware\t: OPAL\n");
212 else
213 seq_printf(m, "firmware\t: BML\n");
214 of_node_put(root);
215 if (radix_enabled())
216 seq_printf(m, "MMU\t\t: Radix\n");
217 else
218 seq_printf(m, "MMU\t\t: Hash\n");
219 }
220
pnv_prepare_going_down(void)221 static void pnv_prepare_going_down(void)
222 {
223 /*
224 * Disable all notifiers from OPAL, we can't
225 * service interrupts anymore anyway
226 */
227 opal_event_shutdown();
228
229 /* Print flash update message if one is scheduled. */
230 opal_flash_update_print_message();
231
232 smp_send_stop();
233
234 hard_irq_disable();
235 }
236
pnv_restart(char * cmd)237 static void __noreturn pnv_restart(char *cmd)
238 {
239 long rc = OPAL_BUSY;
240
241 pnv_prepare_going_down();
242
243 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
244 rc = opal_cec_reboot();
245 if (rc == OPAL_BUSY_EVENT)
246 opal_poll_events(NULL);
247 else
248 mdelay(10);
249 }
250 for (;;)
251 opal_poll_events(NULL);
252 }
253
pnv_power_off(void)254 static void __noreturn pnv_power_off(void)
255 {
256 long rc = OPAL_BUSY;
257
258 pnv_prepare_going_down();
259
260 while (rc == OPAL_BUSY || rc == OPAL_BUSY_EVENT) {
261 rc = opal_cec_power_down(0);
262 if (rc == OPAL_BUSY_EVENT)
263 opal_poll_events(NULL);
264 else
265 mdelay(10);
266 }
267 for (;;)
268 opal_poll_events(NULL);
269 }
270
pnv_halt(void)271 static void __noreturn pnv_halt(void)
272 {
273 pnv_power_off();
274 }
275
pnv_progress(char * s,unsigned short hex)276 static void pnv_progress(char *s, unsigned short hex)
277 {
278 }
279
pnv_shutdown(void)280 static void pnv_shutdown(void)
281 {
282 /* Let the PCI code clear up IODA tables */
283 pnv_pci_shutdown();
284
285 /*
286 * Stop OPAL activity: Unregister all OPAL interrupts so they
287 * don't fire up while we kexec and make sure all potentially
288 * DMA'ing ops are complete (such as dump retrieval).
289 */
290 opal_shutdown();
291 }
292
293 #ifdef CONFIG_KEXEC_CORE
pnv_kexec_wait_secondaries_down(void)294 static void pnv_kexec_wait_secondaries_down(void)
295 {
296 int my_cpu, i, notified = -1;
297
298 my_cpu = get_cpu();
299
300 for_each_online_cpu(i) {
301 uint8_t status;
302 int64_t rc, timeout = 1000;
303
304 if (i == my_cpu)
305 continue;
306
307 for (;;) {
308 rc = opal_query_cpu_status(get_hard_smp_processor_id(i),
309 &status);
310 if (rc != OPAL_SUCCESS || status != OPAL_THREAD_STARTED)
311 break;
312 barrier();
313 if (i != notified) {
314 printk(KERN_INFO "kexec: waiting for cpu %d "
315 "(physical %d) to enter OPAL\n",
316 i, paca_ptrs[i]->hw_cpu_id);
317 notified = i;
318 }
319
320 /*
321 * On crash secondaries might be unreachable or hung,
322 * so timeout if we've waited too long
323 * */
324 mdelay(1);
325 if (timeout-- == 0) {
326 printk(KERN_ERR "kexec: timed out waiting for "
327 "cpu %d (physical %d) to enter OPAL\n",
328 i, paca_ptrs[i]->hw_cpu_id);
329 break;
330 }
331 }
332 }
333 }
334
pnv_kexec_cpu_down(int crash_shutdown,int secondary)335 static void pnv_kexec_cpu_down(int crash_shutdown, int secondary)
336 {
337 u64 reinit_flags;
338
339 if (xive_enabled())
340 xive_teardown_cpu();
341 else
342 xics_kexec_teardown_cpu(secondary);
343
344 /* On OPAL, we return all CPUs to firmware */
345 if (!firmware_has_feature(FW_FEATURE_OPAL))
346 return;
347
348 if (secondary) {
349 /* Return secondary CPUs to firmware on OPAL v3 */
350 mb();
351 get_paca()->kexec_state = KEXEC_STATE_REAL_MODE;
352 mb();
353
354 /* Return the CPU to OPAL */
355 opal_return_cpu();
356 } else {
357 /* Primary waits for the secondaries to have reached OPAL */
358 pnv_kexec_wait_secondaries_down();
359
360 /* Switch XIVE back to emulation mode */
361 if (xive_enabled())
362 xive_shutdown();
363
364 /*
365 * We might be running as little-endian - now that interrupts
366 * are disabled, reset the HILE bit to big-endian so we don't
367 * take interrupts in the wrong endian later
368 *
369 * We reinit to enable both radix and hash on P9 to ensure
370 * the mode used by the next kernel is always supported.
371 */
372 reinit_flags = OPAL_REINIT_CPUS_HILE_BE;
373 if (cpu_has_feature(CPU_FTR_ARCH_300))
374 reinit_flags |= OPAL_REINIT_CPUS_MMU_RADIX |
375 OPAL_REINIT_CPUS_MMU_HASH;
376 opal_reinit_cpus(reinit_flags);
377 }
378 }
379 #endif /* CONFIG_KEXEC_CORE */
380
381 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
pnv_memory_block_size(void)382 static unsigned long pnv_memory_block_size(void)
383 {
384 return 256UL * 1024 * 1024;
385 }
386 #endif
387
pnv_setup_machdep_opal(void)388 static void __init pnv_setup_machdep_opal(void)
389 {
390 ppc_md.get_boot_time = opal_get_boot_time;
391 ppc_md.restart = pnv_restart;
392 pm_power_off = pnv_power_off;
393 ppc_md.halt = pnv_halt;
394 /* ppc_md.system_reset_exception gets filled in by pnv_smp_init() */
395 ppc_md.machine_check_exception = opal_machine_check;
396 ppc_md.mce_check_early_recovery = opal_mce_check_early_recovery;
397 ppc_md.hmi_exception_early = opal_hmi_exception_early;
398 ppc_md.handle_hmi_exception = opal_handle_hmi_exception;
399 }
400
pnv_probe(void)401 static int __init pnv_probe(void)
402 {
403 if (!of_machine_is_compatible("ibm,powernv"))
404 return 0;
405
406 if (firmware_has_feature(FW_FEATURE_OPAL))
407 pnv_setup_machdep_opal();
408
409 pr_debug("PowerNV detected !\n");
410
411 pnv_init();
412
413 return 1;
414 }
415
416 #ifdef CONFIG_PPC_TRANSACTIONAL_MEM
pnv_tm_init(void)417 void __init pnv_tm_init(void)
418 {
419 if (!firmware_has_feature(FW_FEATURE_OPAL) ||
420 !pvr_version_is(PVR_POWER9) ||
421 early_cpu_has_feature(CPU_FTR_TM))
422 return;
423
424 if (opal_reinit_cpus(OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED) != OPAL_SUCCESS)
425 return;
426
427 pr_info("Enabling TM (Transactional Memory) with Suspend Disabled\n");
428 cur_cpu_spec->cpu_features |= CPU_FTR_TM;
429 /* Make sure "normal" HTM is off (it should be) */
430 cur_cpu_spec->cpu_user_features2 &= ~PPC_FEATURE2_HTM;
431 /* Turn on no suspend mode, and HTM no SC */
432 cur_cpu_spec->cpu_user_features2 |= PPC_FEATURE2_HTM_NO_SUSPEND | \
433 PPC_FEATURE2_HTM_NOSC;
434 tm_suspend_disabled = true;
435 }
436 #endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
437
438 /*
439 * Returns the cpu frequency for 'cpu' in Hz. This is used by
440 * /proc/cpuinfo
441 */
pnv_get_proc_freq(unsigned int cpu)442 static unsigned long pnv_get_proc_freq(unsigned int cpu)
443 {
444 unsigned long ret_freq;
445
446 ret_freq = cpufreq_get(cpu) * 1000ul;
447
448 /*
449 * If the backend cpufreq driver does not exist,
450 * then fallback to old way of reporting the clockrate.
451 */
452 if (!ret_freq)
453 ret_freq = ppc_proc_freq;
454 return ret_freq;
455 }
456
define_machine(powernv)457 define_machine(powernv) {
458 .name = "PowerNV",
459 .probe = pnv_probe,
460 .setup_arch = pnv_setup_arch,
461 .init_IRQ = pnv_init_IRQ,
462 .show_cpuinfo = pnv_show_cpuinfo,
463 .get_proc_freq = pnv_get_proc_freq,
464 .progress = pnv_progress,
465 .machine_shutdown = pnv_shutdown,
466 .power_save = NULL,
467 .calibrate_decr = generic_calibrate_decr,
468 #ifdef CONFIG_KEXEC_CORE
469 .kexec_cpu_down = pnv_kexec_cpu_down,
470 #endif
471 #ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
472 .memory_block_size = pnv_memory_block_size,
473 #endif
474 };
475