1 /*
2 * SMP support for PowerNV machines.
3 *
4 * Copyright 2011 IBM Corp.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/sched.h>
15 #include <linux/sched/hotplug.h>
16 #include <linux/smp.h>
17 #include <linux/interrupt.h>
18 #include <linux/delay.h>
19 #include <linux/init.h>
20 #include <linux/spinlock.h>
21 #include <linux/cpu.h>
22
23 #include <asm/irq.h>
24 #include <asm/smp.h>
25 #include <asm/paca.h>
26 #include <asm/machdep.h>
27 #include <asm/cputable.h>
28 #include <asm/firmware.h>
29 #include <asm/vdso_datapage.h>
30 #include <asm/cputhreads.h>
31 #include <asm/xics.h>
32 #include <asm/xive.h>
33 #include <asm/opal.h>
34 #include <asm/runlatch.h>
35 #include <asm/code-patching.h>
36 #include <asm/dbell.h>
37 #include <asm/kvm_ppc.h>
38 #include <asm/ppc-opcode.h>
39 #include <asm/cpuidle.h>
40 #include <asm/kexec.h>
41 #include <asm/reg.h>
42 #include <asm/powernv.h>
43
44 #include "powernv.h"
45
46 #ifdef DEBUG
47 #include <asm/udbg.h>
48 #define DBG(fmt...) udbg_printf(fmt)
49 #else
50 #define DBG(fmt...) do { } while (0)
51 #endif
52
pnv_smp_setup_cpu(int cpu)53 static void pnv_smp_setup_cpu(int cpu)
54 {
55 /*
56 * P9 workaround for CI vector load (see traps.c),
57 * enable the corresponding HMI interrupt
58 */
59 if (pvr_version_is(PVR_POWER9))
60 mtspr(SPRN_HMEER, mfspr(SPRN_HMEER) | PPC_BIT(17));
61
62 if (xive_enabled())
63 xive_smp_setup_cpu();
64 else if (cpu != boot_cpuid)
65 xics_setup_cpu();
66 }
67
pnv_smp_kick_cpu(int nr)68 static int pnv_smp_kick_cpu(int nr)
69 {
70 unsigned int pcpu;
71 unsigned long start_here =
72 __pa(ppc_function_entry(generic_secondary_smp_init));
73 long rc;
74 uint8_t status;
75
76 if (nr < 0 || nr >= nr_cpu_ids)
77 return -EINVAL;
78
79 pcpu = get_hard_smp_processor_id(nr);
80 /*
81 * If we already started or OPAL is not supported, we just
82 * kick the CPU via the PACA
83 */
84 if (paca_ptrs[nr]->cpu_start || !firmware_has_feature(FW_FEATURE_OPAL))
85 goto kick;
86
87 /*
88 * At this point, the CPU can either be spinning on the way in
89 * from kexec or be inside OPAL waiting to be started for the
90 * first time. OPAL v3 allows us to query OPAL to know if it
91 * has the CPUs, so we do that
92 */
93 rc = opal_query_cpu_status(pcpu, &status);
94 if (rc != OPAL_SUCCESS) {
95 pr_warn("OPAL Error %ld querying CPU %d state\n", rc, nr);
96 return -ENODEV;
97 }
98
99 /*
100 * Already started, just kick it, probably coming from
101 * kexec and spinning
102 */
103 if (status == OPAL_THREAD_STARTED)
104 goto kick;
105
106 /*
107 * Available/inactive, let's kick it
108 */
109 if (status == OPAL_THREAD_INACTIVE) {
110 pr_devel("OPAL: Starting CPU %d (HW 0x%x)...\n", nr, pcpu);
111 rc = opal_start_cpu(pcpu, start_here);
112 if (rc != OPAL_SUCCESS) {
113 pr_warn("OPAL Error %ld starting CPU %d\n", rc, nr);
114 return -ENODEV;
115 }
116 } else {
117 /*
118 * An unavailable CPU (or any other unknown status)
119 * shouldn't be started. It should also
120 * not be in the possible map but currently it can
121 * happen
122 */
123 pr_devel("OPAL: CPU %d (HW 0x%x) is unavailable"
124 " (status %d)...\n", nr, pcpu, status);
125 return -ENODEV;
126 }
127
128 kick:
129 return smp_generic_kick_cpu(nr);
130 }
131
132 #ifdef CONFIG_HOTPLUG_CPU
133
pnv_smp_cpu_disable(void)134 static int pnv_smp_cpu_disable(void)
135 {
136 int cpu = smp_processor_id();
137
138 /* This is identical to pSeries... might consolidate by
139 * moving migrate_irqs_away to a ppc_md with default to
140 * the generic fixup_irqs. --BenH.
141 */
142 set_cpu_online(cpu, false);
143 vdso_data->processorCount--;
144 if (cpu == boot_cpuid)
145 boot_cpuid = cpumask_any(cpu_online_mask);
146 if (xive_enabled())
147 xive_smp_disable_cpu();
148 else
149 xics_migrate_irqs_away();
150 return 0;
151 }
152
pnv_flush_interrupts(void)153 static void pnv_flush_interrupts(void)
154 {
155 if (cpu_has_feature(CPU_FTR_ARCH_300)) {
156 if (xive_enabled())
157 xive_flush_interrupt();
158 else
159 icp_opal_flush_interrupt();
160 } else {
161 icp_native_flush_interrupt();
162 }
163 }
164
pnv_smp_cpu_kill_self(void)165 static void pnv_smp_cpu_kill_self(void)
166 {
167 unsigned long srr1, unexpected_mask, wmask;
168 unsigned int cpu;
169 u64 lpcr_val;
170
171 /* Standard hot unplug procedure */
172
173 idle_task_exit();
174 cpu = smp_processor_id();
175 DBG("CPU%d offline\n", cpu);
176 generic_set_cpu_dead(cpu);
177 smp_wmb();
178
179 wmask = SRR1_WAKEMASK;
180 if (cpu_has_feature(CPU_FTR_ARCH_207S))
181 wmask = SRR1_WAKEMASK_P8;
182
183 /*
184 * This turns the irq soft-disabled state we're called with, into a
185 * hard-disabled state with pending irq_happened interrupts cleared.
186 *
187 * PACA_IRQ_DEC - Decrementer should be ignored.
188 * PACA_IRQ_HMI - Can be ignored, processing is done in real mode.
189 * PACA_IRQ_DBELL, EE, PMI - Unexpected.
190 */
191 hard_irq_disable();
192 if (generic_check_cpu_restart(cpu))
193 goto out;
194
195 unexpected_mask = ~(PACA_IRQ_DEC | PACA_IRQ_HMI | PACA_IRQ_HARD_DIS);
196 if (local_paca->irq_happened & unexpected_mask) {
197 if (local_paca->irq_happened & PACA_IRQ_EE)
198 pnv_flush_interrupts();
199 DBG("CPU%d Unexpected exit while offline irq_happened=%lx!\n",
200 cpu, local_paca->irq_happened);
201 }
202 local_paca->irq_happened = PACA_IRQ_HARD_DIS;
203
204 /*
205 * We don't want to take decrementer interrupts while we are
206 * offline, so clear LPCR:PECE1. We keep PECE2 (and
207 * LPCR_PECE_HVEE on P9) enabled so as to let IPIs in.
208 *
209 * If the CPU gets woken up by a special wakeup, ensure that
210 * the SLW engine sets LPCR with decrementer bit cleared, else
211 * the CPU will come back to the kernel due to a spurious
212 * wakeup.
213 */
214 lpcr_val = mfspr(SPRN_LPCR) & ~(u64)LPCR_PECE1;
215 pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
216
217 while (!generic_check_cpu_restart(cpu)) {
218 /*
219 * Clear IPI flag, since we don't handle IPIs while
220 * offline, except for those when changing micro-threading
221 * mode, which are handled explicitly below, and those
222 * for coming online, which are handled via
223 * generic_check_cpu_restart() calls.
224 */
225 kvmppc_clear_host_ipi(cpu);
226
227 srr1 = pnv_cpu_offline(cpu);
228
229 WARN_ON_ONCE(!irqs_disabled());
230 WARN_ON(lazy_irq_pending());
231
232 /*
233 * If the SRR1 value indicates that we woke up due to
234 * an external interrupt, then clear the interrupt.
235 * We clear the interrupt before checking for the
236 * reason, so as to avoid a race where we wake up for
237 * some other reason, find nothing and clear the interrupt
238 * just as some other cpu is sending us an interrupt.
239 * If we returned from power7_nap as a result of
240 * having finished executing in a KVM guest, then srr1
241 * contains 0.
242 */
243 if (((srr1 & wmask) == SRR1_WAKEEE) ||
244 ((srr1 & wmask) == SRR1_WAKEHVI)) {
245 pnv_flush_interrupts();
246 } else if ((srr1 & wmask) == SRR1_WAKEHDBELL) {
247 unsigned long msg = PPC_DBELL_TYPE(PPC_DBELL_SERVER);
248 asm volatile(PPC_MSGCLR(%0) : : "r" (msg));
249 } else if ((srr1 & wmask) == SRR1_WAKERESET) {
250 irq_set_pending_from_srr1(srr1);
251 /* Does not return */
252 }
253
254 smp_mb();
255
256 /*
257 * For kdump kernels, we process the ipi and jump to
258 * crash_ipi_callback
259 */
260 if (kdump_in_progress()) {
261 /*
262 * If we got to this point, we've not used
263 * NMI's, otherwise we would have gone
264 * via the SRR1_WAKERESET path. We are
265 * using regular IPI's for waking up offline
266 * threads.
267 */
268 struct pt_regs regs;
269
270 ppc_save_regs(®s);
271 crash_ipi_callback(®s);
272 /* Does not return */
273 }
274
275 if (cpu_core_split_required())
276 continue;
277
278 if (srr1 && !generic_check_cpu_restart(cpu))
279 DBG("CPU%d Unexpected exit while offline srr1=%lx!\n",
280 cpu, srr1);
281
282 }
283
284 /*
285 * Re-enable decrementer interrupts in LPCR.
286 *
287 * Further, we want stop states to be woken up by decrementer
288 * for non-hotplug cases. So program the LPCR via stop api as
289 * well.
290 */
291 lpcr_val = mfspr(SPRN_LPCR) | (u64)LPCR_PECE1;
292 pnv_program_cpu_hotplug_lpcr(cpu, lpcr_val);
293 out:
294 DBG("CPU%d coming online...\n", cpu);
295 }
296
297 #endif /* CONFIG_HOTPLUG_CPU */
298
pnv_cpu_bootable(unsigned int nr)299 static int pnv_cpu_bootable(unsigned int nr)
300 {
301 /*
302 * Starting with POWER8, the subcore logic relies on all threads of a
303 * core being booted so that they can participate in split mode
304 * switches. So on those machines we ignore the smt_enabled_at_boot
305 * setting (smt-enabled on the kernel command line).
306 */
307 if (cpu_has_feature(CPU_FTR_ARCH_207S))
308 return 1;
309
310 return smp_generic_cpu_bootable(nr);
311 }
312
pnv_smp_prepare_cpu(int cpu)313 static int pnv_smp_prepare_cpu(int cpu)
314 {
315 if (xive_enabled())
316 return xive_smp_prepare_cpu(cpu);
317 return 0;
318 }
319
320 /* Cause IPI as setup by the interrupt controller (xics or xive) */
321 static void (*ic_cause_ipi)(int cpu);
322
pnv_cause_ipi(int cpu)323 static void pnv_cause_ipi(int cpu)
324 {
325 if (doorbell_try_core_ipi(cpu))
326 return;
327
328 ic_cause_ipi(cpu);
329 }
330
pnv_smp_probe(void)331 static void __init pnv_smp_probe(void)
332 {
333 if (xive_enabled())
334 xive_smp_probe();
335 else
336 xics_smp_probe();
337
338 if (cpu_has_feature(CPU_FTR_DBELL)) {
339 ic_cause_ipi = smp_ops->cause_ipi;
340 WARN_ON(!ic_cause_ipi);
341
342 if (cpu_has_feature(CPU_FTR_ARCH_300))
343 smp_ops->cause_ipi = doorbell_global_ipi;
344 else
345 smp_ops->cause_ipi = pnv_cause_ipi;
346 }
347 }
348
pnv_system_reset_exception(struct pt_regs * regs)349 static int pnv_system_reset_exception(struct pt_regs *regs)
350 {
351 if (smp_handle_nmi_ipi(regs))
352 return 1;
353 return 0;
354 }
355
pnv_cause_nmi_ipi(int cpu)356 static int pnv_cause_nmi_ipi(int cpu)
357 {
358 int64_t rc;
359
360 if (cpu >= 0) {
361 int h = get_hard_smp_processor_id(cpu);
362
363 if (opal_check_token(OPAL_QUIESCE))
364 opal_quiesce(QUIESCE_HOLD, h);
365
366 rc = opal_signal_system_reset(h);
367
368 if (opal_check_token(OPAL_QUIESCE))
369 opal_quiesce(QUIESCE_RESUME, h);
370
371 if (rc != OPAL_SUCCESS)
372 return 0;
373 return 1;
374
375 } else if (cpu == NMI_IPI_ALL_OTHERS) {
376 bool success = true;
377 int c;
378
379 if (opal_check_token(OPAL_QUIESCE))
380 opal_quiesce(QUIESCE_HOLD, -1);
381
382 /*
383 * We do not use broadcasts (yet), because it's not clear
384 * exactly what semantics Linux wants or the firmware should
385 * provide.
386 */
387 for_each_online_cpu(c) {
388 if (c == smp_processor_id())
389 continue;
390
391 rc = opal_signal_system_reset(
392 get_hard_smp_processor_id(c));
393 if (rc != OPAL_SUCCESS)
394 success = false;
395 }
396
397 if (opal_check_token(OPAL_QUIESCE))
398 opal_quiesce(QUIESCE_RESUME, -1);
399
400 if (success)
401 return 1;
402
403 /*
404 * Caller will fall back to doorbells, which may pick
405 * up the remainders.
406 */
407 }
408
409 return 0;
410 }
411
412 static struct smp_ops_t pnv_smp_ops = {
413 .message_pass = NULL, /* Use smp_muxed_ipi_message_pass */
414 .cause_ipi = NULL, /* Filled at runtime by pnv_smp_probe() */
415 .cause_nmi_ipi = NULL,
416 .probe = pnv_smp_probe,
417 .prepare_cpu = pnv_smp_prepare_cpu,
418 .kick_cpu = pnv_smp_kick_cpu,
419 .setup_cpu = pnv_smp_setup_cpu,
420 .cpu_bootable = pnv_cpu_bootable,
421 #ifdef CONFIG_HOTPLUG_CPU
422 .cpu_disable = pnv_smp_cpu_disable,
423 .cpu_die = generic_cpu_die,
424 #endif /* CONFIG_HOTPLUG_CPU */
425 };
426
427 /* This is called very early during platform setup_arch */
pnv_smp_init(void)428 void __init pnv_smp_init(void)
429 {
430 if (opal_check_token(OPAL_SIGNAL_SYSTEM_RESET)) {
431 ppc_md.system_reset_exception = pnv_system_reset_exception;
432 pnv_smp_ops.cause_nmi_ipi = pnv_cause_nmi_ipi;
433 }
434 smp_ops = &pnv_smp_ops;
435
436 #ifdef CONFIG_HOTPLUG_CPU
437 ppc_md.cpu_die = pnv_smp_cpu_kill_self;
438 #ifdef CONFIG_KEXEC_CORE
439 crash_wake_offline = 1;
440 #endif
441 #endif
442 }
443