1 /*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * Authors: Thomas Abraham <thomas.ab@samsung.com>
4 * Chander Kashyap <k.chander@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Common Clock Framework support for Exynos5420 SoC.
11 */
12
13 #include <dt-bindings/clock/exynos5420.h>
14 #include <linux/slab.h>
15 #include <linux/clk-provider.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 #include <linux/syscore_ops.h>
19
20 #include "clk.h"
21 #include "clk-cpu.h"
22 #include "clk-exynos5-subcmu.h"
23
24 #define APLL_LOCK 0x0
25 #define APLL_CON0 0x100
26 #define SRC_CPU 0x200
27 #define DIV_CPU0 0x500
28 #define DIV_CPU1 0x504
29 #define GATE_BUS_CPU 0x700
30 #define GATE_SCLK_CPU 0x800
31 #define CLKOUT_CMU_CPU 0xa00
32 #define SRC_MASK_CPERI 0x4300
33 #define GATE_IP_G2D 0x8800
34 #define CPLL_LOCK 0x10020
35 #define DPLL_LOCK 0x10030
36 #define EPLL_LOCK 0x10040
37 #define RPLL_LOCK 0x10050
38 #define IPLL_LOCK 0x10060
39 #define SPLL_LOCK 0x10070
40 #define VPLL_LOCK 0x10080
41 #define MPLL_LOCK 0x10090
42 #define CPLL_CON0 0x10120
43 #define DPLL_CON0 0x10128
44 #define EPLL_CON0 0x10130
45 #define EPLL_CON1 0x10134
46 #define EPLL_CON2 0x10138
47 #define RPLL_CON0 0x10140
48 #define RPLL_CON1 0x10144
49 #define RPLL_CON2 0x10148
50 #define IPLL_CON0 0x10150
51 #define SPLL_CON0 0x10160
52 #define VPLL_CON0 0x10170
53 #define MPLL_CON0 0x10180
54 #define SRC_TOP0 0x10200
55 #define SRC_TOP1 0x10204
56 #define SRC_TOP2 0x10208
57 #define SRC_TOP3 0x1020c
58 #define SRC_TOP4 0x10210
59 #define SRC_TOP5 0x10214
60 #define SRC_TOP6 0x10218
61 #define SRC_TOP7 0x1021c
62 #define SRC_TOP8 0x10220 /* 5800 specific */
63 #define SRC_TOP9 0x10224 /* 5800 specific */
64 #define SRC_DISP10 0x1022c
65 #define SRC_MAU 0x10240
66 #define SRC_FSYS 0x10244
67 #define SRC_PERIC0 0x10250
68 #define SRC_PERIC1 0x10254
69 #define SRC_ISP 0x10270
70 #define SRC_CAM 0x10274 /* 5800 specific */
71 #define SRC_TOP10 0x10280
72 #define SRC_TOP11 0x10284
73 #define SRC_TOP12 0x10288
74 #define SRC_TOP13 0x1028c /* 5800 specific */
75 #define SRC_MASK_TOP0 0x10300
76 #define SRC_MASK_TOP1 0x10304
77 #define SRC_MASK_TOP2 0x10308
78 #define SRC_MASK_TOP7 0x1031c
79 #define SRC_MASK_DISP10 0x1032c
80 #define SRC_MASK_MAU 0x10334
81 #define SRC_MASK_FSYS 0x10340
82 #define SRC_MASK_PERIC0 0x10350
83 #define SRC_MASK_PERIC1 0x10354
84 #define SRC_MASK_ISP 0x10370
85 #define DIV_TOP0 0x10500
86 #define DIV_TOP1 0x10504
87 #define DIV_TOP2 0x10508
88 #define DIV_TOP8 0x10520 /* 5800 specific */
89 #define DIV_TOP9 0x10524 /* 5800 specific */
90 #define DIV_DISP10 0x1052c
91 #define DIV_MAU 0x10544
92 #define DIV_FSYS0 0x10548
93 #define DIV_FSYS1 0x1054c
94 #define DIV_FSYS2 0x10550
95 #define DIV_PERIC0 0x10558
96 #define DIV_PERIC1 0x1055c
97 #define DIV_PERIC2 0x10560
98 #define DIV_PERIC3 0x10564
99 #define DIV_PERIC4 0x10568
100 #define DIV_CAM 0x10574 /* 5800 specific */
101 #define SCLK_DIV_ISP0 0x10580
102 #define SCLK_DIV_ISP1 0x10584
103 #define DIV2_RATIO0 0x10590
104 #define DIV4_RATIO 0x105a0
105 #define GATE_BUS_TOP 0x10700
106 #define GATE_BUS_DISP1 0x10728
107 #define GATE_BUS_GEN 0x1073c
108 #define GATE_BUS_FSYS0 0x10740
109 #define GATE_BUS_FSYS2 0x10748
110 #define GATE_BUS_PERIC 0x10750
111 #define GATE_BUS_PERIC1 0x10754
112 #define GATE_BUS_PERIS0 0x10760
113 #define GATE_BUS_PERIS1 0x10764
114 #define GATE_BUS_NOC 0x10770
115 #define GATE_TOP_SCLK_ISP 0x10870
116 #define GATE_IP_GSCL0 0x10910
117 #define GATE_IP_GSCL1 0x10920
118 #define GATE_IP_CAM 0x10924 /* 5800 specific */
119 #define GATE_IP_MFC 0x1092c
120 #define GATE_IP_DISP1 0x10928
121 #define GATE_IP_G3D 0x10930
122 #define GATE_IP_GEN 0x10934
123 #define GATE_IP_FSYS 0x10944
124 #define GATE_IP_PERIC 0x10950
125 #define GATE_IP_PERIS 0x10960
126 #define GATE_IP_MSCL 0x10970
127 #define GATE_TOP_SCLK_GSCL 0x10820
128 #define GATE_TOP_SCLK_DISP1 0x10828
129 #define GATE_TOP_SCLK_MAU 0x1083c
130 #define GATE_TOP_SCLK_FSYS 0x10840
131 #define GATE_TOP_SCLK_PERIC 0x10850
132 #define TOP_SPARE2 0x10b08
133 #define BPLL_LOCK 0x20010
134 #define BPLL_CON0 0x20110
135 #define SRC_CDREX 0x20200
136 #define DIV_CDREX0 0x20500
137 #define DIV_CDREX1 0x20504
138 #define KPLL_LOCK 0x28000
139 #define KPLL_CON0 0x28100
140 #define SRC_KFC 0x28200
141 #define DIV_KFC0 0x28500
142
143 /* Exynos5x SoC type */
144 enum exynos5x_soc {
145 EXYNOS5420,
146 EXYNOS5800,
147 };
148
149 /* list of PLLs */
150 enum exynos5x_plls {
151 apll, cpll, dpll, epll, rpll, ipll, spll, vpll, mpll,
152 bpll, kpll,
153 nr_plls /* number of PLLs */
154 };
155
156 static void __iomem *reg_base;
157 static enum exynos5x_soc exynos5x_soc;
158
159 #ifdef CONFIG_PM_SLEEP
160 static struct samsung_clk_reg_dump *exynos5x_save;
161 static struct samsung_clk_reg_dump *exynos5800_save;
162
163 /*
164 * list of controller registers to be saved and restored during a
165 * suspend/resume cycle.
166 */
167 static const unsigned long exynos5x_clk_regs[] __initconst = {
168 SRC_CPU,
169 DIV_CPU0,
170 DIV_CPU1,
171 GATE_BUS_CPU,
172 GATE_SCLK_CPU,
173 CLKOUT_CMU_CPU,
174 APLL_CON0,
175 KPLL_CON0,
176 CPLL_CON0,
177 DPLL_CON0,
178 EPLL_CON0,
179 EPLL_CON1,
180 EPLL_CON2,
181 RPLL_CON0,
182 RPLL_CON1,
183 RPLL_CON2,
184 IPLL_CON0,
185 SPLL_CON0,
186 VPLL_CON0,
187 MPLL_CON0,
188 SRC_TOP0,
189 SRC_TOP1,
190 SRC_TOP2,
191 SRC_TOP3,
192 SRC_TOP4,
193 SRC_TOP5,
194 SRC_TOP6,
195 SRC_TOP7,
196 SRC_DISP10,
197 SRC_MAU,
198 SRC_FSYS,
199 SRC_PERIC0,
200 SRC_PERIC1,
201 SRC_TOP10,
202 SRC_TOP11,
203 SRC_TOP12,
204 SRC_MASK_TOP2,
205 SRC_MASK_TOP7,
206 SRC_MASK_DISP10,
207 SRC_MASK_FSYS,
208 SRC_MASK_PERIC0,
209 SRC_MASK_PERIC1,
210 SRC_MASK_TOP0,
211 SRC_MASK_TOP1,
212 SRC_MASK_MAU,
213 SRC_MASK_ISP,
214 SRC_ISP,
215 DIV_TOP0,
216 DIV_TOP1,
217 DIV_TOP2,
218 DIV_DISP10,
219 DIV_MAU,
220 DIV_FSYS0,
221 DIV_FSYS1,
222 DIV_FSYS2,
223 DIV_PERIC0,
224 DIV_PERIC1,
225 DIV_PERIC2,
226 DIV_PERIC3,
227 DIV_PERIC4,
228 SCLK_DIV_ISP0,
229 SCLK_DIV_ISP1,
230 DIV2_RATIO0,
231 DIV4_RATIO,
232 GATE_BUS_DISP1,
233 GATE_BUS_TOP,
234 GATE_BUS_GEN,
235 GATE_BUS_FSYS0,
236 GATE_BUS_FSYS2,
237 GATE_BUS_PERIC,
238 GATE_BUS_PERIC1,
239 GATE_BUS_PERIS0,
240 GATE_BUS_PERIS1,
241 GATE_BUS_NOC,
242 GATE_TOP_SCLK_ISP,
243 GATE_IP_GSCL0,
244 GATE_IP_GSCL1,
245 GATE_IP_MFC,
246 GATE_IP_DISP1,
247 GATE_IP_G3D,
248 GATE_IP_GEN,
249 GATE_IP_FSYS,
250 GATE_IP_PERIC,
251 GATE_IP_PERIS,
252 GATE_IP_MSCL,
253 GATE_TOP_SCLK_GSCL,
254 GATE_TOP_SCLK_DISP1,
255 GATE_TOP_SCLK_MAU,
256 GATE_TOP_SCLK_FSYS,
257 GATE_TOP_SCLK_PERIC,
258 TOP_SPARE2,
259 SRC_CDREX,
260 DIV_CDREX0,
261 DIV_CDREX1,
262 SRC_KFC,
263 DIV_KFC0,
264 };
265
266 static const unsigned long exynos5800_clk_regs[] __initconst = {
267 SRC_TOP8,
268 SRC_TOP9,
269 SRC_CAM,
270 SRC_TOP1,
271 DIV_TOP8,
272 DIV_TOP9,
273 DIV_CAM,
274 GATE_IP_CAM,
275 };
276
277 static const struct samsung_clk_reg_dump exynos5420_set_clksrc[] = {
278 { .offset = SRC_MASK_CPERI, .value = 0xffffffff, },
279 { .offset = SRC_MASK_TOP0, .value = 0x11111111, },
280 { .offset = SRC_MASK_TOP1, .value = 0x11101111, },
281 { .offset = SRC_MASK_TOP2, .value = 0x11111110, },
282 { .offset = SRC_MASK_TOP7, .value = 0x00111100, },
283 { .offset = SRC_MASK_DISP10, .value = 0x11111110, },
284 { .offset = SRC_MASK_MAU, .value = 0x10000000, },
285 { .offset = SRC_MASK_FSYS, .value = 0x11111110, },
286 { .offset = SRC_MASK_PERIC0, .value = 0x11111110, },
287 { .offset = SRC_MASK_PERIC1, .value = 0x11111100, },
288 { .offset = SRC_MASK_ISP, .value = 0x11111000, },
289 { .offset = GATE_BUS_TOP, .value = 0xffffffff, },
290 { .offset = GATE_BUS_DISP1, .value = 0xffffffff, },
291 { .offset = GATE_IP_PERIC, .value = 0xffffffff, },
292 { .offset = GATE_IP_PERIS, .value = 0xffffffff, },
293 };
294
exynos5420_clk_suspend(void)295 static int exynos5420_clk_suspend(void)
296 {
297 samsung_clk_save(reg_base, exynos5x_save,
298 ARRAY_SIZE(exynos5x_clk_regs));
299
300 if (exynos5x_soc == EXYNOS5800)
301 samsung_clk_save(reg_base, exynos5800_save,
302 ARRAY_SIZE(exynos5800_clk_regs));
303
304 samsung_clk_restore(reg_base, exynos5420_set_clksrc,
305 ARRAY_SIZE(exynos5420_set_clksrc));
306
307 return 0;
308 }
309
exynos5420_clk_resume(void)310 static void exynos5420_clk_resume(void)
311 {
312 samsung_clk_restore(reg_base, exynos5x_save,
313 ARRAY_SIZE(exynos5x_clk_regs));
314
315 if (exynos5x_soc == EXYNOS5800)
316 samsung_clk_restore(reg_base, exynos5800_save,
317 ARRAY_SIZE(exynos5800_clk_regs));
318 }
319
320 static struct syscore_ops exynos5420_clk_syscore_ops = {
321 .suspend = exynos5420_clk_suspend,
322 .resume = exynos5420_clk_resume,
323 };
324
exynos5420_clk_sleep_init(void)325 static void __init exynos5420_clk_sleep_init(void)
326 {
327 exynos5x_save = samsung_clk_alloc_reg_dump(exynos5x_clk_regs,
328 ARRAY_SIZE(exynos5x_clk_regs));
329 if (!exynos5x_save) {
330 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
331 __func__);
332 return;
333 }
334
335 if (exynos5x_soc == EXYNOS5800) {
336 exynos5800_save =
337 samsung_clk_alloc_reg_dump(exynos5800_clk_regs,
338 ARRAY_SIZE(exynos5800_clk_regs));
339 if (!exynos5800_save)
340 goto err_soc;
341 }
342
343 register_syscore_ops(&exynos5420_clk_syscore_ops);
344 return;
345 err_soc:
346 kfree(exynos5x_save);
347 pr_warn("%s: failed to allocate sleep save data, no sleep support!\n",
348 __func__);
349 return;
350 }
351 #else
exynos5420_clk_sleep_init(void)352 static void __init exynos5420_clk_sleep_init(void) {}
353 #endif
354
355 /* list of all parent clocks */
356 PNAME(mout_mspll_cpu_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
357 "mout_sclk_mpll", "mout_sclk_spll"};
358 PNAME(mout_cpu_p) = {"mout_apll" , "mout_mspll_cpu"};
359 PNAME(mout_kfc_p) = {"mout_kpll" , "mout_mspll_kfc"};
360 PNAME(mout_apll_p) = {"fin_pll", "fout_apll"};
361 PNAME(mout_bpll_p) = {"fin_pll", "fout_bpll"};
362 PNAME(mout_cpll_p) = {"fin_pll", "fout_cpll"};
363 PNAME(mout_dpll_p) = {"fin_pll", "fout_dpll"};
364 PNAME(mout_epll_p) = {"fin_pll", "fout_epll"};
365 PNAME(mout_ipll_p) = {"fin_pll", "fout_ipll"};
366 PNAME(mout_kpll_p) = {"fin_pll", "fout_kpll"};
367 PNAME(mout_mpll_p) = {"fin_pll", "fout_mpll"};
368 PNAME(mout_rpll_p) = {"fin_pll", "fout_rpll"};
369 PNAME(mout_spll_p) = {"fin_pll", "fout_spll"};
370 PNAME(mout_vpll_p) = {"fin_pll", "fout_vpll"};
371
372 PNAME(mout_group1_p) = {"mout_sclk_cpll", "mout_sclk_dpll",
373 "mout_sclk_mpll"};
374 PNAME(mout_group2_p) = {"fin_pll", "mout_sclk_cpll",
375 "mout_sclk_dpll", "mout_sclk_mpll", "mout_sclk_spll",
376 "mout_sclk_ipll", "mout_sclk_epll", "mout_sclk_rpll"};
377 PNAME(mout_group3_p) = {"mout_sclk_rpll", "mout_sclk_spll"};
378 PNAME(mout_group4_p) = {"mout_sclk_ipll", "mout_sclk_dpll", "mout_sclk_mpll"};
379 PNAME(mout_group5_p) = {"mout_sclk_vpll", "mout_sclk_dpll"};
380
381 PNAME(mout_fimd1_final_p) = {"mout_fimd1", "mout_fimd1_opt"};
382 PNAME(mout_sw_aclk66_p) = {"dout_aclk66", "mout_sclk_spll"};
383 PNAME(mout_user_aclk66_peric_p) = { "fin_pll", "mout_sw_aclk66"};
384 PNAME(mout_user_pclk66_gpio_p) = {"mout_sw_aclk66", "ff_sw_aclk66"};
385
386 PNAME(mout_sw_aclk200_fsys_p) = {"dout_aclk200_fsys", "mout_sclk_spll"};
387 PNAME(mout_sw_pclk200_fsys_p) = {"dout_pclk200_fsys", "mout_sclk_spll"};
388 PNAME(mout_user_pclk200_fsys_p) = {"fin_pll", "mout_sw_pclk200_fsys"};
389 PNAME(mout_user_aclk200_fsys_p) = {"fin_pll", "mout_sw_aclk200_fsys"};
390
391 PNAME(mout_sw_aclk200_fsys2_p) = {"dout_aclk200_fsys2", "mout_sclk_spll"};
392 PNAME(mout_user_aclk200_fsys2_p) = {"fin_pll", "mout_sw_aclk200_fsys2"};
393 PNAME(mout_sw_aclk100_noc_p) = {"dout_aclk100_noc", "mout_sclk_spll"};
394 PNAME(mout_user_aclk100_noc_p) = {"fin_pll", "mout_sw_aclk100_noc"};
395
396 PNAME(mout_sw_aclk400_wcore_p) = {"dout_aclk400_wcore", "mout_sclk_spll"};
397 PNAME(mout_aclk400_wcore_bpll_p) = {"mout_aclk400_wcore", "sclk_bpll"};
398 PNAME(mout_user_aclk400_wcore_p) = {"fin_pll", "mout_sw_aclk400_wcore"};
399
400 PNAME(mout_sw_aclk400_isp_p) = {"dout_aclk400_isp", "mout_sclk_spll"};
401 PNAME(mout_user_aclk400_isp_p) = {"fin_pll", "mout_sw_aclk400_isp"};
402
403 PNAME(mout_sw_aclk333_432_isp0_p) = {"dout_aclk333_432_isp0",
404 "mout_sclk_spll"};
405 PNAME(mout_user_aclk333_432_isp0_p) = {"fin_pll", "mout_sw_aclk333_432_isp0"};
406
407 PNAME(mout_sw_aclk333_432_isp_p) = {"dout_aclk333_432_isp", "mout_sclk_spll"};
408 PNAME(mout_user_aclk333_432_isp_p) = {"fin_pll", "mout_sw_aclk333_432_isp"};
409
410 PNAME(mout_sw_aclk200_p) = {"dout_aclk200", "mout_sclk_spll"};
411 PNAME(mout_user_aclk200_disp1_p) = {"fin_pll", "mout_sw_aclk200"};
412
413 PNAME(mout_sw_aclk400_mscl_p) = {"dout_aclk400_mscl", "mout_sclk_spll"};
414 PNAME(mout_user_aclk400_mscl_p) = {"fin_pll", "mout_sw_aclk400_mscl"};
415
416 PNAME(mout_sw_aclk333_p) = {"dout_aclk333", "mout_sclk_spll"};
417 PNAME(mout_user_aclk333_p) = {"fin_pll", "mout_sw_aclk333"};
418
419 PNAME(mout_sw_aclk166_p) = {"dout_aclk166", "mout_sclk_spll"};
420 PNAME(mout_user_aclk166_p) = {"fin_pll", "mout_sw_aclk166"};
421
422 PNAME(mout_sw_aclk266_p) = {"dout_aclk266", "mout_sclk_spll"};
423 PNAME(mout_user_aclk266_p) = {"fin_pll", "mout_sw_aclk266"};
424 PNAME(mout_user_aclk266_isp_p) = {"fin_pll", "mout_sw_aclk266"};
425
426 PNAME(mout_sw_aclk333_432_gscl_p) = {"dout_aclk333_432_gscl", "mout_sclk_spll"};
427 PNAME(mout_user_aclk333_432_gscl_p) = {"fin_pll", "mout_sw_aclk333_432_gscl"};
428
429 PNAME(mout_sw_aclk300_gscl_p) = {"dout_aclk300_gscl", "mout_sclk_spll"};
430 PNAME(mout_user_aclk300_gscl_p) = {"fin_pll", "mout_sw_aclk300_gscl"};
431
432 PNAME(mout_sw_aclk300_disp1_p) = {"dout_aclk300_disp1", "mout_sclk_spll"};
433 PNAME(mout_sw_aclk400_disp1_p) = {"dout_aclk400_disp1", "mout_sclk_spll"};
434 PNAME(mout_user_aclk300_disp1_p) = {"fin_pll", "mout_sw_aclk300_disp1"};
435 PNAME(mout_user_aclk400_disp1_p) = {"fin_pll", "mout_sw_aclk400_disp1"};
436
437 PNAME(mout_sw_aclk300_jpeg_p) = {"dout_aclk300_jpeg", "mout_sclk_spll"};
438 PNAME(mout_user_aclk300_jpeg_p) = {"fin_pll", "mout_sw_aclk300_jpeg"};
439
440 PNAME(mout_sw_aclk_g3d_p) = {"dout_aclk_g3d", "mout_sclk_spll"};
441 PNAME(mout_user_aclk_g3d_p) = {"fin_pll", "mout_sw_aclk_g3d"};
442
443 PNAME(mout_sw_aclk266_g2d_p) = {"dout_aclk266_g2d", "mout_sclk_spll"};
444 PNAME(mout_user_aclk266_g2d_p) = {"fin_pll", "mout_sw_aclk266_g2d"};
445
446 PNAME(mout_sw_aclk333_g2d_p) = {"dout_aclk333_g2d", "mout_sclk_spll"};
447 PNAME(mout_user_aclk333_g2d_p) = {"fin_pll", "mout_sw_aclk333_g2d"};
448
449 PNAME(mout_audio0_p) = {"fin_pll", "cdclk0", "mout_sclk_dpll",
450 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
451 "mout_sclk_epll", "mout_sclk_rpll"};
452 PNAME(mout_audio1_p) = {"fin_pll", "cdclk1", "mout_sclk_dpll",
453 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
454 "mout_sclk_epll", "mout_sclk_rpll"};
455 PNAME(mout_audio2_p) = {"fin_pll", "cdclk2", "mout_sclk_dpll",
456 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
457 "mout_sclk_epll", "mout_sclk_rpll"};
458 PNAME(mout_spdif_p) = {"fin_pll", "dout_audio0", "dout_audio1",
459 "dout_audio2", "spdif_extclk", "mout_sclk_ipll",
460 "mout_sclk_epll", "mout_sclk_rpll"};
461 PNAME(mout_hdmi_p) = {"dout_hdmi_pixel", "sclk_hdmiphy"};
462 PNAME(mout_maudio0_p) = {"fin_pll", "maudio_clk", "mout_sclk_dpll",
463 "mout_sclk_mpll", "mout_sclk_spll", "mout_sclk_ipll",
464 "mout_sclk_epll", "mout_sclk_rpll"};
465 PNAME(mout_mau_epll_clk_p) = {"mout_sclk_epll", "mout_sclk_dpll",
466 "mout_sclk_mpll", "mout_sclk_spll"};
467 PNAME(mout_mclk_cdrex_p) = {"mout_bpll", "mout_mx_mspll_ccore"};
468
469 /* List of parents specific to exynos5800 */
470 PNAME(mout_epll2_5800_p) = { "mout_sclk_epll", "ff_dout_epll2" };
471 PNAME(mout_group1_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
472 "mout_sclk_mpll", "ff_dout_spll2" };
473 PNAME(mout_group2_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
474 "mout_sclk_mpll", "ff_dout_spll2",
475 "mout_epll2", "mout_sclk_ipll" };
476 PNAME(mout_group3_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
477 "mout_sclk_mpll", "ff_dout_spll2",
478 "mout_epll2" };
479 PNAME(mout_group5_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
480 "mout_sclk_mpll", "mout_sclk_spll" };
481 PNAME(mout_group6_5800_p) = { "mout_sclk_ipll", "mout_sclk_dpll",
482 "mout_sclk_mpll", "ff_dout_spll2" };
483 PNAME(mout_group7_5800_p) = { "mout_sclk_cpll", "mout_sclk_dpll",
484 "mout_sclk_mpll", "mout_sclk_spll",
485 "mout_epll2", "mout_sclk_ipll" };
486 PNAME(mout_mx_mspll_ccore_p) = {"sclk_bpll", "mout_sclk_dpll",
487 "mout_sclk_mpll", "ff_dout_spll2",
488 "mout_sclk_spll", "mout_sclk_epll"};
489 PNAME(mout_mau_epll_clk_5800_p) = { "mout_sclk_epll", "mout_sclk_dpll",
490 "mout_sclk_mpll",
491 "ff_dout_spll2" };
492 PNAME(mout_group8_5800_p) = { "dout_aclk432_scaler", "dout_sclk_sw" };
493 PNAME(mout_group9_5800_p) = { "dout_osc_div", "mout_sw_aclk432_scaler" };
494 PNAME(mout_group10_5800_p) = { "dout_aclk432_cam", "dout_sclk_sw" };
495 PNAME(mout_group11_5800_p) = { "dout_osc_div", "mout_sw_aclk432_cam" };
496 PNAME(mout_group12_5800_p) = { "dout_aclkfl1_550_cam", "dout_sclk_sw" };
497 PNAME(mout_group13_5800_p) = { "dout_osc_div", "mout_sw_aclkfl1_550_cam" };
498 PNAME(mout_group14_5800_p) = { "dout_aclk550_cam", "dout_sclk_sw" };
499 PNAME(mout_group15_5800_p) = { "dout_osc_div", "mout_sw_aclk550_cam" };
500 PNAME(mout_group16_5800_p) = { "dout_osc_div", "mout_mau_epll_clk" };
501
502 /* fixed rate clocks generated outside the soc */
503 static struct samsung_fixed_rate_clock
504 exynos5x_fixed_rate_ext_clks[] __initdata = {
505 FRATE(CLK_FIN_PLL, "fin_pll", NULL, 0, 0),
506 };
507
508 /* fixed rate clocks generated inside the soc */
509 static const struct samsung_fixed_rate_clock exynos5x_fixed_rate_clks[] __initconst = {
510 FRATE(CLK_SCLK_HDMIPHY, "sclk_hdmiphy", NULL, 0, 24000000),
511 FRATE(0, "sclk_pwi", NULL, 0, 24000000),
512 FRATE(0, "sclk_usbh20", NULL, 0, 48000000),
513 FRATE(0, "mphy_refclk_ixtal24", NULL, 0, 48000000),
514 FRATE(0, "sclk_usbh20_scan_clk", NULL, 0, 480000000),
515 };
516
517 static const struct samsung_fixed_factor_clock
518 exynos5x_fixed_factor_clks[] __initconst = {
519 FFACTOR(0, "ff_hsic_12m", "fin_pll", 1, 2, 0),
520 FFACTOR(0, "ff_sw_aclk66", "mout_sw_aclk66", 1, 2, 0),
521 };
522
523 static const struct samsung_fixed_factor_clock
524 exynos5800_fixed_factor_clks[] __initconst = {
525 FFACTOR(0, "ff_dout_epll2", "mout_sclk_epll", 1, 2, 0),
526 FFACTOR(0, "ff_dout_spll2", "mout_sclk_spll", 1, 2, 0),
527 };
528
529 static const struct samsung_mux_clock exynos5800_mux_clks[] __initconst = {
530 MUX(0, "mout_aclk400_isp", mout_group3_5800_p, SRC_TOP0, 0, 3),
531 MUX(0, "mout_aclk400_mscl", mout_group3_5800_p, SRC_TOP0, 4, 3),
532 MUX(0, "mout_aclk400_wcore", mout_group2_5800_p, SRC_TOP0, 16, 3),
533 MUX(0, "mout_aclk100_noc", mout_group1_5800_p, SRC_TOP0, 20, 2),
534
535 MUX(0, "mout_aclk333_432_gscl", mout_group6_5800_p, SRC_TOP1, 0, 2),
536 MUX(0, "mout_aclk333_432_isp", mout_group6_5800_p, SRC_TOP1, 4, 2),
537 MUX(0, "mout_aclk333_432_isp0", mout_group6_5800_p, SRC_TOP1, 12, 2),
538 MUX(0, "mout_aclk266", mout_group5_5800_p, SRC_TOP1, 20, 2),
539 MUX(0, "mout_aclk333", mout_group1_5800_p, SRC_TOP1, 28, 2),
540
541 MUX(0, "mout_aclk400_disp1", mout_group7_5800_p, SRC_TOP2, 4, 3),
542 MUX(0, "mout_aclk333_g2d", mout_group5_5800_p, SRC_TOP2, 8, 2),
543 MUX(0, "mout_aclk266_g2d", mout_group5_5800_p, SRC_TOP2, 12, 2),
544 MUX(0, "mout_aclk300_jpeg", mout_group5_5800_p, SRC_TOP2, 20, 2),
545 MUX(0, "mout_aclk300_disp1", mout_group5_5800_p, SRC_TOP2, 24, 2),
546 MUX(0, "mout_aclk300_gscl", mout_group5_5800_p, SRC_TOP2, 28, 2),
547
548 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
549 mout_mx_mspll_ccore_p, SRC_TOP7, 16, 2),
550 MUX_F(CLK_MOUT_MAU_EPLL, "mout_mau_epll_clk", mout_mau_epll_clk_5800_p,
551 SRC_TOP7, 20, 2, CLK_SET_RATE_PARENT, 0),
552 MUX(0, "sclk_bpll", mout_bpll_p, SRC_TOP7, 24, 1),
553 MUX(0, "mout_epll2", mout_epll2_5800_p, SRC_TOP7, 28, 1),
554
555 MUX(0, "mout_aclk550_cam", mout_group3_5800_p, SRC_TOP8, 16, 3),
556 MUX(0, "mout_aclkfl1_550_cam", mout_group3_5800_p, SRC_TOP8, 20, 3),
557 MUX(0, "mout_aclk432_cam", mout_group6_5800_p, SRC_TOP8, 24, 2),
558 MUX(0, "mout_aclk432_scaler", mout_group6_5800_p, SRC_TOP8, 28, 2),
559
560 MUX_F(CLK_MOUT_USER_MAU_EPLL, "mout_user_mau_epll", mout_group16_5800_p,
561 SRC_TOP9, 8, 1, CLK_SET_RATE_PARENT, 0),
562 MUX(0, "mout_user_aclk550_cam", mout_group15_5800_p,
563 SRC_TOP9, 16, 1),
564 MUX(0, "mout_user_aclkfl1_550_cam", mout_group13_5800_p,
565 SRC_TOP9, 20, 1),
566 MUX(0, "mout_user_aclk432_cam", mout_group11_5800_p,
567 SRC_TOP9, 24, 1),
568 MUX(0, "mout_user_aclk432_scaler", mout_group9_5800_p,
569 SRC_TOP9, 28, 1),
570
571 MUX(0, "mout_sw_aclk550_cam", mout_group14_5800_p, SRC_TOP13, 16, 1),
572 MUX(0, "mout_sw_aclkfl1_550_cam", mout_group12_5800_p,
573 SRC_TOP13, 20, 1),
574 MUX(0, "mout_sw_aclk432_cam", mout_group10_5800_p,
575 SRC_TOP13, 24, 1),
576 MUX(0, "mout_sw_aclk432_scaler", mout_group8_5800_p,
577 SRC_TOP13, 28, 1),
578
579 MUX(0, "mout_fimd1", mout_group2_p, SRC_DISP10, 4, 3),
580 };
581
582 static const struct samsung_div_clock exynos5800_div_clks[] __initconst = {
583 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
584 "mout_aclk400_wcore", DIV_TOP0, 16, 3),
585 DIV(0, "dout_aclk550_cam", "mout_aclk550_cam",
586 DIV_TOP8, 16, 3),
587 DIV(0, "dout_aclkfl1_550_cam", "mout_aclkfl1_550_cam",
588 DIV_TOP8, 20, 3),
589 DIV(0, "dout_aclk432_cam", "mout_aclk432_cam",
590 DIV_TOP8, 24, 3),
591 DIV(0, "dout_aclk432_scaler", "mout_aclk432_scaler",
592 DIV_TOP8, 28, 3),
593
594 DIV(0, "dout_osc_div", "fin_pll", DIV_TOP9, 20, 3),
595 DIV(0, "dout_sclk_sw", "sclk_spll", DIV_TOP9, 24, 6),
596 };
597
598 static const struct samsung_gate_clock exynos5800_gate_clks[] __initconst = {
599 GATE(CLK_ACLK550_CAM, "aclk550_cam", "mout_user_aclk550_cam",
600 GATE_BUS_TOP, 24, CLK_IS_CRITICAL, 0),
601 GATE(CLK_ACLK432_SCALER, "aclk432_scaler", "mout_user_aclk432_scaler",
602 GATE_BUS_TOP, 27, CLK_IS_CRITICAL, 0),
603 GATE(CLK_MAU_EPLL, "mau_epll", "mout_user_mau_epll",
604 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
605 };
606
607 static const struct samsung_mux_clock exynos5420_mux_clks[] __initconst = {
608 MUX(0, "sclk_bpll", mout_bpll_p, TOP_SPARE2, 0, 1),
609 MUX(0, "mout_aclk400_wcore_bpll", mout_aclk400_wcore_bpll_p,
610 TOP_SPARE2, 4, 1),
611
612 MUX(0, "mout_aclk400_isp", mout_group1_p, SRC_TOP0, 0, 2),
613 MUX(0, "mout_aclk400_mscl", mout_group1_p, SRC_TOP0, 4, 2),
614 MUX(0, "mout_aclk400_wcore", mout_group1_p, SRC_TOP0, 16, 2),
615 MUX(0, "mout_aclk100_noc", mout_group1_p, SRC_TOP0, 20, 2),
616
617 MUX(0, "mout_aclk333_432_gscl", mout_group4_p, SRC_TOP1, 0, 2),
618 MUX(0, "mout_aclk333_432_isp", mout_group4_p,
619 SRC_TOP1, 4, 2),
620 MUX(0, "mout_aclk333_432_isp0", mout_group4_p, SRC_TOP1, 12, 2),
621 MUX(0, "mout_aclk266", mout_group1_p, SRC_TOP1, 20, 2),
622 MUX(0, "mout_aclk333", mout_group1_p, SRC_TOP1, 28, 2),
623
624 MUX(0, "mout_aclk400_disp1", mout_group1_p, SRC_TOP2, 4, 2),
625 MUX(0, "mout_aclk333_g2d", mout_group1_p, SRC_TOP2, 8, 2),
626 MUX(0, "mout_aclk266_g2d", mout_group1_p, SRC_TOP2, 12, 2),
627 MUX(0, "mout_aclk300_jpeg", mout_group1_p, SRC_TOP2, 20, 2),
628 MUX(0, "mout_aclk300_disp1", mout_group1_p, SRC_TOP2, 24, 2),
629 MUX(0, "mout_aclk300_gscl", mout_group1_p, SRC_TOP2, 28, 2),
630
631 MUX(CLK_MOUT_MX_MSPLL_CCORE, "mout_mx_mspll_ccore",
632 mout_group5_5800_p, SRC_TOP7, 16, 2),
633 MUX_F(0, "mout_mau_epll_clk", mout_mau_epll_clk_p, SRC_TOP7, 20, 2,
634 CLK_SET_RATE_PARENT, 0),
635
636 MUX(0, "mout_fimd1", mout_group3_p, SRC_DISP10, 4, 1),
637 };
638
639 static const struct samsung_div_clock exynos5420_div_clks[] __initconst = {
640 DIV(CLK_DOUT_ACLK400_WCORE, "dout_aclk400_wcore",
641 "mout_aclk400_wcore_bpll", DIV_TOP0, 16, 3),
642 };
643
644 static const struct samsung_gate_clock exynos5420_gate_clks[] __initconst = {
645 GATE(CLK_SECKEY, "seckey", "aclk66_psgen", GATE_BUS_PERIS1, 1, 0, 0),
646 GATE(CLK_MAU_EPLL, "mau_epll", "mout_mau_epll_clk",
647 SRC_MASK_TOP7, 20, CLK_SET_RATE_PARENT, 0),
648 };
649
650 static const struct samsung_mux_clock exynos5x_mux_clks[] __initconst = {
651 MUX(0, "mout_user_pclk66_gpio", mout_user_pclk66_gpio_p,
652 SRC_TOP7, 4, 1),
653 MUX(0, "mout_mspll_kfc", mout_mspll_cpu_p, SRC_TOP7, 8, 2),
654 MUX(0, "mout_mspll_cpu", mout_mspll_cpu_p, SRC_TOP7, 12, 2),
655
656 MUX_F(0, "mout_apll", mout_apll_p, SRC_CPU, 0, 1,
657 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
658 MUX(0, "mout_cpu", mout_cpu_p, SRC_CPU, 16, 1),
659 MUX_F(0, "mout_kpll", mout_kpll_p, SRC_KFC, 0, 1,
660 CLK_SET_RATE_PARENT | CLK_RECALC_NEW_RATES, 0),
661 MUX(0, "mout_kfc", mout_kfc_p, SRC_KFC, 16, 1),
662
663 MUX(0, "mout_aclk200", mout_group1_p, SRC_TOP0, 8, 2),
664 MUX(0, "mout_aclk200_fsys2", mout_group1_p, SRC_TOP0, 12, 2),
665 MUX(0, "mout_pclk200_fsys", mout_group1_p, SRC_TOP0, 24, 2),
666 MUX(0, "mout_aclk200_fsys", mout_group1_p, SRC_TOP0, 28, 2),
667
668 MUX(0, "mout_aclk66", mout_group1_p, SRC_TOP1, 8, 2),
669 MUX(0, "mout_aclk166", mout_group1_p, SRC_TOP1, 24, 2),
670
671 MUX(0, "mout_aclk_g3d", mout_group5_p, SRC_TOP2, 16, 1),
672
673 MUX(0, "mout_user_aclk400_isp", mout_user_aclk400_isp_p,
674 SRC_TOP3, 0, 1),
675 MUX(0, "mout_user_aclk400_mscl", mout_user_aclk400_mscl_p,
676 SRC_TOP3, 4, 1),
677 MUX(CLK_MOUT_USER_ACLK200_DISP1, "mout_user_aclk200_disp1",
678 mout_user_aclk200_disp1_p, SRC_TOP3, 8, 1),
679 MUX(0, "mout_user_aclk200_fsys2", mout_user_aclk200_fsys2_p,
680 SRC_TOP3, 12, 1),
681 MUX(0, "mout_user_aclk400_wcore", mout_user_aclk400_wcore_p,
682 SRC_TOP3, 16, 1),
683 MUX(0, "mout_user_aclk100_noc", mout_user_aclk100_noc_p,
684 SRC_TOP3, 20, 1),
685 MUX(0, "mout_user_pclk200_fsys", mout_user_pclk200_fsys_p,
686 SRC_TOP3, 24, 1),
687 MUX(0, "mout_user_aclk200_fsys", mout_user_aclk200_fsys_p,
688 SRC_TOP3, 28, 1),
689
690 MUX(0, "mout_user_aclk333_432_gscl", mout_user_aclk333_432_gscl_p,
691 SRC_TOP4, 0, 1),
692 MUX(0, "mout_user_aclk333_432_isp", mout_user_aclk333_432_isp_p,
693 SRC_TOP4, 4, 1),
694 MUX(0, "mout_user_aclk66_peric", mout_user_aclk66_peric_p,
695 SRC_TOP4, 8, 1),
696 MUX(0, "mout_user_aclk333_432_isp0", mout_user_aclk333_432_isp0_p,
697 SRC_TOP4, 12, 1),
698 MUX(0, "mout_user_aclk266_isp", mout_user_aclk266_isp_p,
699 SRC_TOP4, 16, 1),
700 MUX(0, "mout_user_aclk266", mout_user_aclk266_p, SRC_TOP4, 20, 1),
701 MUX(0, "mout_user_aclk166", mout_user_aclk166_p, SRC_TOP4, 24, 1),
702 MUX(CLK_MOUT_USER_ACLK333, "mout_user_aclk333", mout_user_aclk333_p,
703 SRC_TOP4, 28, 1),
704
705 MUX(CLK_MOUT_USER_ACLK400_DISP1, "mout_user_aclk400_disp1",
706 mout_user_aclk400_disp1_p, SRC_TOP5, 0, 1),
707 MUX(0, "mout_user_aclk66_psgen", mout_user_aclk66_peric_p,
708 SRC_TOP5, 4, 1),
709 MUX(0, "mout_user_aclk333_g2d", mout_user_aclk333_g2d_p,
710 SRC_TOP5, 8, 1),
711 MUX(0, "mout_user_aclk266_g2d", mout_user_aclk266_g2d_p,
712 SRC_TOP5, 12, 1),
713 MUX(CLK_MOUT_G3D, "mout_user_aclk_g3d", mout_user_aclk_g3d_p,
714 SRC_TOP5, 16, 1),
715 MUX(0, "mout_user_aclk300_jpeg", mout_user_aclk300_jpeg_p,
716 SRC_TOP5, 20, 1),
717 MUX(CLK_MOUT_USER_ACLK300_DISP1, "mout_user_aclk300_disp1",
718 mout_user_aclk300_disp1_p, SRC_TOP5, 24, 1),
719 MUX(CLK_MOUT_USER_ACLK300_GSCL, "mout_user_aclk300_gscl",
720 mout_user_aclk300_gscl_p, SRC_TOP5, 28, 1),
721
722 MUX(0, "mout_sclk_mpll", mout_mpll_p, SRC_TOP6, 0, 1),
723 MUX(CLK_MOUT_VPLL, "mout_sclk_vpll", mout_vpll_p, SRC_TOP6, 4, 1),
724 MUX(0, "mout_sclk_spll", mout_spll_p, SRC_TOP6, 8, 1),
725 MUX(0, "mout_sclk_ipll", mout_ipll_p, SRC_TOP6, 12, 1),
726 MUX(0, "mout_sclk_rpll", mout_rpll_p, SRC_TOP6, 16, 1),
727 MUX_F(CLK_MOUT_EPLL, "mout_sclk_epll", mout_epll_p, SRC_TOP6, 20, 1,
728 CLK_SET_RATE_PARENT, 0),
729 MUX(0, "mout_sclk_dpll", mout_dpll_p, SRC_TOP6, 24, 1),
730 MUX(0, "mout_sclk_cpll", mout_cpll_p, SRC_TOP6, 28, 1),
731
732 MUX(0, "mout_sw_aclk400_isp", mout_sw_aclk400_isp_p,
733 SRC_TOP10, 0, 1),
734 MUX(0, "mout_sw_aclk400_mscl", mout_sw_aclk400_mscl_p,
735 SRC_TOP10, 4, 1),
736 MUX(CLK_MOUT_SW_ACLK200, "mout_sw_aclk200", mout_sw_aclk200_p,
737 SRC_TOP10, 8, 1),
738 MUX(0, "mout_sw_aclk200_fsys2", mout_sw_aclk200_fsys2_p,
739 SRC_TOP10, 12, 1),
740 MUX(0, "mout_sw_aclk400_wcore", mout_sw_aclk400_wcore_p,
741 SRC_TOP10, 16, 1),
742 MUX(0, "mout_sw_aclk100_noc", mout_sw_aclk100_noc_p,
743 SRC_TOP10, 20, 1),
744 MUX(0, "mout_sw_pclk200_fsys", mout_sw_pclk200_fsys_p,
745 SRC_TOP10, 24, 1),
746 MUX(0, "mout_sw_aclk200_fsys", mout_sw_aclk200_fsys_p,
747 SRC_TOP10, 28, 1),
748
749 MUX(0, "mout_sw_aclk333_432_gscl", mout_sw_aclk333_432_gscl_p,
750 SRC_TOP11, 0, 1),
751 MUX(0, "mout_sw_aclk333_432_isp", mout_sw_aclk333_432_isp_p,
752 SRC_TOP11, 4, 1),
753 MUX(0, "mout_sw_aclk66", mout_sw_aclk66_p, SRC_TOP11, 8, 1),
754 MUX(0, "mout_sw_aclk333_432_isp0", mout_sw_aclk333_432_isp0_p,
755 SRC_TOP11, 12, 1),
756 MUX(0, "mout_sw_aclk266", mout_sw_aclk266_p, SRC_TOP11, 20, 1),
757 MUX(0, "mout_sw_aclk166", mout_sw_aclk166_p, SRC_TOP11, 24, 1),
758 MUX(CLK_MOUT_SW_ACLK333, "mout_sw_aclk333", mout_sw_aclk333_p,
759 SRC_TOP11, 28, 1),
760
761 MUX(CLK_MOUT_SW_ACLK400, "mout_sw_aclk400_disp1",
762 mout_sw_aclk400_disp1_p, SRC_TOP12, 4, 1),
763 MUX(0, "mout_sw_aclk333_g2d", mout_sw_aclk333_g2d_p,
764 SRC_TOP12, 8, 1),
765 MUX(0, "mout_sw_aclk266_g2d", mout_sw_aclk266_g2d_p,
766 SRC_TOP12, 12, 1),
767 MUX(0, "mout_sw_aclk_g3d", mout_sw_aclk_g3d_p, SRC_TOP12, 16, 1),
768 MUX(0, "mout_sw_aclk300_jpeg", mout_sw_aclk300_jpeg_p,
769 SRC_TOP12, 20, 1),
770 MUX(CLK_MOUT_SW_ACLK300, "mout_sw_aclk300_disp1",
771 mout_sw_aclk300_disp1_p, SRC_TOP12, 24, 1),
772 MUX(CLK_MOUT_SW_ACLK300_GSCL, "mout_sw_aclk300_gscl",
773 mout_sw_aclk300_gscl_p, SRC_TOP12, 28, 1),
774
775 /* DISP1 Block */
776 MUX(0, "mout_mipi1", mout_group2_p, SRC_DISP10, 16, 3),
777 MUX(0, "mout_dp1", mout_group2_p, SRC_DISP10, 20, 3),
778 MUX(0, "mout_pixel", mout_group2_p, SRC_DISP10, 24, 3),
779 MUX(CLK_MOUT_HDMI, "mout_hdmi", mout_hdmi_p, SRC_DISP10, 28, 1),
780 MUX(0, "mout_fimd1_opt", mout_group2_p, SRC_DISP10, 8, 3),
781
782 MUX(0, "mout_fimd1_final", mout_fimd1_final_p, TOP_SPARE2, 8, 1),
783
784 /* CDREX block */
785 MUX_F(CLK_MOUT_MCLK_CDREX, "mout_mclk_cdrex", mout_mclk_cdrex_p,
786 SRC_CDREX, 4, 1, CLK_SET_RATE_PARENT, 0),
787 MUX_F(CLK_MOUT_BPLL, "mout_bpll", mout_bpll_p, SRC_CDREX, 0, 1,
788 CLK_SET_RATE_PARENT, 0),
789
790 /* MAU Block */
791 MUX(CLK_MOUT_MAUDIO0, "mout_maudio0", mout_maudio0_p, SRC_MAU, 28, 3),
792
793 /* FSYS Block */
794 MUX(0, "mout_usbd301", mout_group2_p, SRC_FSYS, 4, 3),
795 MUX(0, "mout_mmc0", mout_group2_p, SRC_FSYS, 8, 3),
796 MUX(0, "mout_mmc1", mout_group2_p, SRC_FSYS, 12, 3),
797 MUX(0, "mout_mmc2", mout_group2_p, SRC_FSYS, 16, 3),
798 MUX(0, "mout_usbd300", mout_group2_p, SRC_FSYS, 20, 3),
799 MUX(0, "mout_unipro", mout_group2_p, SRC_FSYS, 24, 3),
800 MUX(0, "mout_mphy_refclk", mout_group2_p, SRC_FSYS, 28, 3),
801
802 /* PERIC Block */
803 MUX(0, "mout_uart0", mout_group2_p, SRC_PERIC0, 4, 3),
804 MUX(0, "mout_uart1", mout_group2_p, SRC_PERIC0, 8, 3),
805 MUX(0, "mout_uart2", mout_group2_p, SRC_PERIC0, 12, 3),
806 MUX(0, "mout_uart3", mout_group2_p, SRC_PERIC0, 16, 3),
807 MUX(0, "mout_pwm", mout_group2_p, SRC_PERIC0, 24, 3),
808 MUX(0, "mout_spdif", mout_spdif_p, SRC_PERIC0, 28, 3),
809 MUX(0, "mout_audio0", mout_audio0_p, SRC_PERIC1, 8, 3),
810 MUX(0, "mout_audio1", mout_audio1_p, SRC_PERIC1, 12, 3),
811 MUX(0, "mout_audio2", mout_audio2_p, SRC_PERIC1, 16, 3),
812 MUX(0, "mout_spi0", mout_group2_p, SRC_PERIC1, 20, 3),
813 MUX(0, "mout_spi1", mout_group2_p, SRC_PERIC1, 24, 3),
814 MUX(0, "mout_spi2", mout_group2_p, SRC_PERIC1, 28, 3),
815
816 /* ISP Block */
817 MUX(0, "mout_pwm_isp", mout_group2_p, SRC_ISP, 24, 3),
818 MUX(0, "mout_uart_isp", mout_group2_p, SRC_ISP, 20, 3),
819 MUX(0, "mout_spi0_isp", mout_group2_p, SRC_ISP, 12, 3),
820 MUX(0, "mout_spi1_isp", mout_group2_p, SRC_ISP, 16, 3),
821 MUX(0, "mout_isp_sensor", mout_group2_p, SRC_ISP, 28, 3),
822 };
823
824 static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
825 DIV(0, "div_arm", "mout_cpu", DIV_CPU0, 0, 3),
826 DIV(0, "sclk_apll", "mout_apll", DIV_CPU0, 24, 3),
827 DIV(0, "armclk2", "div_arm", DIV_CPU0, 28, 3),
828 DIV(0, "div_kfc", "mout_kfc", DIV_KFC0, 0, 3),
829 DIV(0, "sclk_kpll", "mout_kpll", DIV_KFC0, 24, 3),
830
831 DIV(CLK_DOUT_ACLK400_ISP, "dout_aclk400_isp", "mout_aclk400_isp",
832 DIV_TOP0, 0, 3),
833 DIV(CLK_DOUT_ACLK400_MSCL, "dout_aclk400_mscl", "mout_aclk400_mscl",
834 DIV_TOP0, 4, 3),
835 DIV(CLK_DOUT_ACLK200, "dout_aclk200", "mout_aclk200",
836 DIV_TOP0, 8, 3),
837 DIV(CLK_DOUT_ACLK200_FSYS2, "dout_aclk200_fsys2", "mout_aclk200_fsys2",
838 DIV_TOP0, 12, 3),
839 DIV(CLK_DOUT_ACLK100_NOC, "dout_aclk100_noc", "mout_aclk100_noc",
840 DIV_TOP0, 20, 3),
841 DIV(CLK_DOUT_PCLK200_FSYS, "dout_pclk200_fsys", "mout_pclk200_fsys",
842 DIV_TOP0, 24, 3),
843 DIV(CLK_DOUT_ACLK200_FSYS, "dout_aclk200_fsys", "mout_aclk200_fsys",
844 DIV_TOP0, 28, 3),
845 DIV(CLK_DOUT_ACLK333_432_GSCL, "dout_aclk333_432_gscl",
846 "mout_aclk333_432_gscl", DIV_TOP1, 0, 3),
847 DIV(CLK_DOUT_ACLK333_432_ISP, "dout_aclk333_432_isp",
848 "mout_aclk333_432_isp", DIV_TOP1, 4, 3),
849 DIV(CLK_DOUT_ACLK66, "dout_aclk66", "mout_aclk66",
850 DIV_TOP1, 8, 6),
851 DIV(CLK_DOUT_ACLK333_432_ISP0, "dout_aclk333_432_isp0",
852 "mout_aclk333_432_isp0", DIV_TOP1, 16, 3),
853 DIV(CLK_DOUT_ACLK266, "dout_aclk266", "mout_aclk266",
854 DIV_TOP1, 20, 3),
855 DIV(CLK_DOUT_ACLK166, "dout_aclk166", "mout_aclk166",
856 DIV_TOP1, 24, 3),
857 DIV(CLK_DOUT_ACLK333, "dout_aclk333", "mout_aclk333",
858 DIV_TOP1, 28, 3),
859
860 DIV(CLK_DOUT_ACLK333_G2D, "dout_aclk333_g2d", "mout_aclk333_g2d",
861 DIV_TOP2, 8, 3),
862 DIV(CLK_DOUT_ACLK266_G2D, "dout_aclk266_g2d", "mout_aclk266_g2d",
863 DIV_TOP2, 12, 3),
864 DIV(CLK_DOUT_ACLK_G3D, "dout_aclk_g3d", "mout_aclk_g3d", DIV_TOP2,
865 16, 3),
866 DIV(CLK_DOUT_ACLK300_JPEG, "dout_aclk300_jpeg", "mout_aclk300_jpeg",
867 DIV_TOP2, 20, 3),
868 DIV(CLK_DOUT_ACLK300_DISP1, "dout_aclk300_disp1",
869 "mout_aclk300_disp1", DIV_TOP2, 24, 3),
870 DIV(CLK_DOUT_ACLK300_GSCL, "dout_aclk300_gscl", "mout_aclk300_gscl",
871 DIV_TOP2, 28, 3),
872
873 /* DISP1 Block */
874 DIV(0, "dout_fimd1", "mout_fimd1_final", DIV_DISP10, 0, 4),
875 DIV(0, "dout_mipi1", "mout_mipi1", DIV_DISP10, 16, 8),
876 DIV(0, "dout_dp1", "mout_dp1", DIV_DISP10, 24, 4),
877 DIV(CLK_DOUT_PIXEL, "dout_hdmi_pixel", "mout_pixel", DIV_DISP10, 28, 4),
878 DIV(CLK_DOUT_ACLK400_DISP1, "dout_aclk400_disp1",
879 "mout_aclk400_disp1", DIV_TOP2, 4, 3),
880
881 /* CDREX Block */
882 DIV(CLK_DOUT_PCLK_CDREX, "dout_pclk_cdrex", "dout_aclk_cdrex1",
883 DIV_CDREX0, 28, 3),
884 DIV_F(CLK_DOUT_SCLK_CDREX, "dout_sclk_cdrex", "mout_mclk_cdrex",
885 DIV_CDREX0, 24, 3, CLK_SET_RATE_PARENT, 0),
886 DIV(CLK_DOUT_ACLK_CDREX1, "dout_aclk_cdrex1", "dout_clk2x_phy0",
887 DIV_CDREX0, 16, 3),
888 DIV(CLK_DOUT_CCLK_DREX0, "dout_cclk_drex0", "dout_clk2x_phy0",
889 DIV_CDREX0, 8, 3),
890 DIV(CLK_DOUT_CLK2X_PHY0, "dout_clk2x_phy0", "dout_sclk_cdrex",
891 DIV_CDREX0, 3, 5),
892
893 DIV(CLK_DOUT_PCLK_CORE_MEM, "dout_pclk_core_mem", "mout_mclk_cdrex",
894 DIV_CDREX1, 8, 3),
895
896 /* Audio Block */
897 DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
898 DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
899
900 /* USB3.0 */
901 DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
902 DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
903 DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
904 DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
905
906 /* MMC */
907 DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
908 DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),
909 DIV(0, "dout_mmc2", "mout_mmc2", DIV_FSYS1, 20, 10),
910
911 DIV(0, "dout_unipro", "mout_unipro", DIV_FSYS2, 24, 8),
912 DIV(0, "dout_mphy_refclk", "mout_mphy_refclk", DIV_FSYS2, 16, 8),
913
914 /* UART and PWM */
915 DIV(0, "dout_uart0", "mout_uart0", DIV_PERIC0, 8, 4),
916 DIV(0, "dout_uart1", "mout_uart1", DIV_PERIC0, 12, 4),
917 DIV(0, "dout_uart2", "mout_uart2", DIV_PERIC0, 16, 4),
918 DIV(0, "dout_uart3", "mout_uart3", DIV_PERIC0, 20, 4),
919 DIV(0, "dout_pwm", "mout_pwm", DIV_PERIC0, 28, 4),
920
921 /* SPI */
922 DIV(0, "dout_spi0", "mout_spi0", DIV_PERIC1, 20, 4),
923 DIV(0, "dout_spi1", "mout_spi1", DIV_PERIC1, 24, 4),
924 DIV(0, "dout_spi2", "mout_spi2", DIV_PERIC1, 28, 4),
925
926
927 /* PCM */
928 DIV(0, "dout_pcm1", "dout_audio1", DIV_PERIC2, 16, 8),
929 DIV(0, "dout_pcm2", "dout_audio2", DIV_PERIC2, 24, 8),
930
931 /* Audio - I2S */
932 DIV(0, "dout_i2s1", "dout_audio1", DIV_PERIC3, 6, 6),
933 DIV(0, "dout_i2s2", "dout_audio2", DIV_PERIC3, 12, 6),
934 DIV(0, "dout_audio0", "mout_audio0", DIV_PERIC3, 20, 4),
935 DIV(0, "dout_audio1", "mout_audio1", DIV_PERIC3, 24, 4),
936 DIV(0, "dout_audio2", "mout_audio2", DIV_PERIC3, 28, 4),
937
938 /* SPI Pre-Ratio */
939 DIV(0, "dout_spi0_pre", "dout_spi0", DIV_PERIC4, 8, 8),
940 DIV(0, "dout_spi1_pre", "dout_spi1", DIV_PERIC4, 16, 8),
941 DIV(0, "dout_spi2_pre", "dout_spi2", DIV_PERIC4, 24, 8),
942
943 /* GSCL Block */
944 DIV(0, "dout_gscl_blk_333", "aclk333_432_gscl", DIV2_RATIO0, 6, 2),
945
946 /* MSCL Block */
947 DIV(0, "dout_mscl_blk", "aclk400_mscl", DIV2_RATIO0, 28, 2),
948
949 /* PSGEN */
950 DIV(0, "dout_gen_blk", "mout_user_aclk266", DIV2_RATIO0, 8, 1),
951 DIV(0, "dout_jpg_blk", "aclk166", DIV2_RATIO0, 20, 1),
952
953 /* ISP Block */
954 DIV(0, "dout_isp_sensor0", "mout_isp_sensor", SCLK_DIV_ISP0, 8, 8),
955 DIV(0, "dout_isp_sensor1", "mout_isp_sensor", SCLK_DIV_ISP0, 16, 8),
956 DIV(0, "dout_isp_sensor2", "mout_isp_sensor", SCLK_DIV_ISP0, 24, 8),
957 DIV(0, "dout_pwm_isp", "mout_pwm_isp", SCLK_DIV_ISP1, 28, 4),
958 DIV(0, "dout_uart_isp", "mout_uart_isp", SCLK_DIV_ISP1, 24, 4),
959 DIV(0, "dout_spi0_isp", "mout_spi0_isp", SCLK_DIV_ISP1, 16, 4),
960 DIV(0, "dout_spi1_isp", "mout_spi1_isp", SCLK_DIV_ISP1, 20, 4),
961 DIV_F(0, "dout_spi0_isp_pre", "dout_spi0_isp", SCLK_DIV_ISP1, 0, 8,
962 CLK_SET_RATE_PARENT, 0),
963 DIV_F(0, "dout_spi1_isp_pre", "dout_spi1_isp", SCLK_DIV_ISP1, 8, 8,
964 CLK_SET_RATE_PARENT, 0),
965 };
966
967 static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
968 /* G2D */
969 GATE(CLK_MDMA0, "mdma0", "aclk266_g2d", GATE_IP_G2D, 1, 0, 0),
970 GATE(CLK_SSS, "sss", "aclk266_g2d", GATE_IP_G2D, 2, 0, 0),
971 GATE(CLK_G2D, "g2d", "aclk333_g2d", GATE_IP_G2D, 3, 0, 0),
972 GATE(CLK_SMMU_MDMA0, "smmu_mdma0", "aclk266_g2d", GATE_IP_G2D, 5, 0, 0),
973 GATE(CLK_SMMU_G2D, "smmu_g2d", "aclk333_g2d", GATE_IP_G2D, 7, 0, 0),
974
975 GATE(0, "aclk200_fsys", "mout_user_aclk200_fsys",
976 GATE_BUS_FSYS0, 9, CLK_IS_CRITICAL, 0),
977 GATE(0, "aclk200_fsys2", "mout_user_aclk200_fsys2",
978 GATE_BUS_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
979
980 GATE(0, "aclk333_g2d", "mout_user_aclk333_g2d",
981 GATE_BUS_TOP, 0, CLK_IGNORE_UNUSED, 0),
982 GATE(0, "aclk266_g2d", "mout_user_aclk266_g2d",
983 GATE_BUS_TOP, 1, CLK_IS_CRITICAL, 0),
984 GATE(0, "aclk300_jpeg", "mout_user_aclk300_jpeg",
985 GATE_BUS_TOP, 4, CLK_IGNORE_UNUSED, 0),
986 GATE(0, "aclk333_432_isp0", "mout_user_aclk333_432_isp0",
987 GATE_BUS_TOP, 5, CLK_IS_CRITICAL, 0),
988 GATE(0, "aclk300_gscl", "mout_user_aclk300_gscl",
989 GATE_BUS_TOP, 6, CLK_IS_CRITICAL, 0),
990 GATE(0, "aclk333_432_gscl", "mout_user_aclk333_432_gscl",
991 GATE_BUS_TOP, 7, CLK_IGNORE_UNUSED, 0),
992 GATE(0, "aclk333_432_isp", "mout_user_aclk333_432_isp",
993 GATE_BUS_TOP, 8, CLK_IS_CRITICAL, 0),
994 GATE(CLK_PCLK66_GPIO, "pclk66_gpio", "mout_user_pclk66_gpio",
995 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
996 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
997 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
998 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
999 GATE_BUS_TOP, 13, CLK_IS_CRITICAL, 0),
1000 GATE(0, "aclk166", "mout_user_aclk166",
1001 GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
1002 GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
1003 GATE_BUS_TOP, 15, CLK_IS_CRITICAL, 0),
1004 GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
1005 GATE_BUS_TOP, 16, CLK_IS_CRITICAL, 0),
1006 GATE(0, "aclk400_mscl", "mout_user_aclk400_mscl",
1007 GATE_BUS_TOP, 17, CLK_IS_CRITICAL, 0),
1008 GATE(0, "aclk200_disp1", "mout_user_aclk200_disp1",
1009 GATE_BUS_TOP, 18, CLK_IS_CRITICAL, 0),
1010 GATE(CLK_SCLK_MPHY_IXTAL24, "sclk_mphy_ixtal24", "mphy_refclk_ixtal24",
1011 GATE_BUS_TOP, 28, 0, 0),
1012 GATE(CLK_SCLK_HSIC_12M, "sclk_hsic_12m", "ff_hsic_12m",
1013 GATE_BUS_TOP, 29, 0, 0),
1014
1015 GATE(0, "aclk300_disp1", "mout_user_aclk300_disp1",
1016 SRC_MASK_TOP2, 24, CLK_IS_CRITICAL, 0),
1017
1018 /* sclk */
1019 GATE(CLK_SCLK_UART0, "sclk_uart0", "dout_uart0",
1020 GATE_TOP_SCLK_PERIC, 0, CLK_SET_RATE_PARENT, 0),
1021 GATE(CLK_SCLK_UART1, "sclk_uart1", "dout_uart1",
1022 GATE_TOP_SCLK_PERIC, 1, CLK_SET_RATE_PARENT, 0),
1023 GATE(CLK_SCLK_UART2, "sclk_uart2", "dout_uart2",
1024 GATE_TOP_SCLK_PERIC, 2, CLK_SET_RATE_PARENT, 0),
1025 GATE(CLK_SCLK_UART3, "sclk_uart3", "dout_uart3",
1026 GATE_TOP_SCLK_PERIC, 3, CLK_SET_RATE_PARENT, 0),
1027 GATE(CLK_SCLK_SPI0, "sclk_spi0", "dout_spi0_pre",
1028 GATE_TOP_SCLK_PERIC, 6, CLK_SET_RATE_PARENT, 0),
1029 GATE(CLK_SCLK_SPI1, "sclk_spi1", "dout_spi1_pre",
1030 GATE_TOP_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1031 GATE(CLK_SCLK_SPI2, "sclk_spi2", "dout_spi2_pre",
1032 GATE_TOP_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1033 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "mout_spdif",
1034 GATE_TOP_SCLK_PERIC, 9, CLK_SET_RATE_PARENT, 0),
1035 GATE(CLK_SCLK_PWM, "sclk_pwm", "dout_pwm",
1036 GATE_TOP_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1037 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "dout_pcm1",
1038 GATE_TOP_SCLK_PERIC, 15, CLK_SET_RATE_PARENT, 0),
1039 GATE(CLK_SCLK_PCM2, "sclk_pcm2", "dout_pcm2",
1040 GATE_TOP_SCLK_PERIC, 16, CLK_SET_RATE_PARENT, 0),
1041 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "dout_i2s1",
1042 GATE_TOP_SCLK_PERIC, 17, CLK_SET_RATE_PARENT, 0),
1043 GATE(CLK_SCLK_I2S2, "sclk_i2s2", "dout_i2s2",
1044 GATE_TOP_SCLK_PERIC, 18, CLK_SET_RATE_PARENT, 0),
1045
1046 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "dout_mmc0",
1047 GATE_TOP_SCLK_FSYS, 0, CLK_SET_RATE_PARENT, 0),
1048 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "dout_mmc1",
1049 GATE_TOP_SCLK_FSYS, 1, CLK_SET_RATE_PARENT, 0),
1050 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "dout_mmc2",
1051 GATE_TOP_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
1052 GATE(CLK_SCLK_USBPHY301, "sclk_usbphy301", "dout_usbphy301",
1053 GATE_TOP_SCLK_FSYS, 7, CLK_SET_RATE_PARENT, 0),
1054 GATE(CLK_SCLK_USBPHY300, "sclk_usbphy300", "dout_usbphy300",
1055 GATE_TOP_SCLK_FSYS, 8, CLK_SET_RATE_PARENT, 0),
1056 GATE(CLK_SCLK_USBD300, "sclk_usbd300", "dout_usbd300",
1057 GATE_TOP_SCLK_FSYS, 9, CLK_SET_RATE_PARENT, 0),
1058 GATE(CLK_SCLK_USBD301, "sclk_usbd301", "dout_usbd301",
1059 GATE_TOP_SCLK_FSYS, 10, CLK_SET_RATE_PARENT, 0),
1060
1061 /* Display */
1062 GATE(CLK_SCLK_FIMD1, "sclk_fimd1", "dout_fimd1",
1063 GATE_TOP_SCLK_DISP1, 0, CLK_SET_RATE_PARENT, 0),
1064 GATE(CLK_SCLK_MIPI1, "sclk_mipi1", "dout_mipi1",
1065 GATE_TOP_SCLK_DISP1, 3, CLK_SET_RATE_PARENT, 0),
1066 GATE(CLK_SCLK_HDMI, "sclk_hdmi", "mout_hdmi",
1067 GATE_TOP_SCLK_DISP1, 9, 0, 0),
1068 GATE(CLK_SCLK_PIXEL, "sclk_pixel", "dout_hdmi_pixel",
1069 GATE_TOP_SCLK_DISP1, 10, CLK_SET_RATE_PARENT, 0),
1070 GATE(CLK_SCLK_DP1, "sclk_dp1", "dout_dp1",
1071 GATE_TOP_SCLK_DISP1, 20, CLK_SET_RATE_PARENT, 0),
1072
1073 /* Maudio Block */
1074 GATE(CLK_SCLK_MAUDIO0, "sclk_maudio0", "dout_maudio0",
1075 GATE_TOP_SCLK_MAU, 0, CLK_SET_RATE_PARENT, 0),
1076 GATE(CLK_SCLK_MAUPCM0, "sclk_maupcm0", "dout_maupcm0",
1077 GATE_TOP_SCLK_MAU, 1, CLK_SET_RATE_PARENT, 0),
1078
1079 /* FSYS Block */
1080 GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
1081 GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
1082 GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
1083 GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
1084 GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
1085 GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),
1086 GATE(CLK_MMC1, "mmc1", "aclk200_fsys2", GATE_IP_FSYS, 13, 0, 0),
1087 GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
1088 GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
1089 GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
1090 GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
1091 GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
1092 GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
1093 GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
1094 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
1095
1096 /* PERIC Block */
1097 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
1098 GATE_IP_PERIC, 0, 0, 0),
1099 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1100 GATE_IP_PERIC, 1, 0, 0),
1101 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1102 GATE_IP_PERIC, 2, 0, 0),
1103 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1104 GATE_IP_PERIC, 3, 0, 0),
1105 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1106 GATE_IP_PERIC, 6, 0, 0),
1107 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1108 GATE_IP_PERIC, 7, 0, 0),
1109 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1110 GATE_IP_PERIC, 8, 0, 0),
1111 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1112 GATE_IP_PERIC, 9, 0, 0),
1113 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1114 GATE_IP_PERIC, 10, 0, 0),
1115 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1116 GATE_IP_PERIC, 11, 0, 0),
1117 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1118 GATE_IP_PERIC, 12, 0, 0),
1119 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1120 GATE_IP_PERIC, 13, 0, 0),
1121 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1122 GATE_IP_PERIC, 14, 0, 0),
1123 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1124 GATE_IP_PERIC, 15, 0, 0),
1125 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1126 GATE_IP_PERIC, 16, 0, 0),
1127 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1128 GATE_IP_PERIC, 17, 0, 0),
1129 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1130 GATE_IP_PERIC, 18, 0, 0),
1131 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1132 GATE_IP_PERIC, 20, 0, 0),
1133 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1134 GATE_IP_PERIC, 21, 0, 0),
1135 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1136 GATE_IP_PERIC, 22, 0, 0),
1137 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1138 GATE_IP_PERIC, 23, 0, 0),
1139 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1140 GATE_IP_PERIC, 24, 0, 0),
1141 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1142 GATE_IP_PERIC, 26, 0, 0),
1143 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1144 GATE_IP_PERIC, 28, 0, 0),
1145 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1146 GATE_IP_PERIC, 30, 0, 0),
1147 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1148 GATE_IP_PERIC, 31, 0, 0),
1149
1150 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1151 GATE_BUS_PERIC, 22, 0, 0),
1152
1153 /* PERIS Block */
1154 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
1155 GATE_IP_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1156 GATE(CLK_SYSREG, "sysreg", "aclk66_psgen",
1157 GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1158 GATE(CLK_TZPC0, "tzpc0", "aclk66_psgen", GATE_IP_PERIS, 6, 0, 0),
1159 GATE(CLK_TZPC1, "tzpc1", "aclk66_psgen", GATE_IP_PERIS, 7, 0, 0),
1160 GATE(CLK_TZPC2, "tzpc2", "aclk66_psgen", GATE_IP_PERIS, 8, 0, 0),
1161 GATE(CLK_TZPC3, "tzpc3", "aclk66_psgen", GATE_IP_PERIS, 9, 0, 0),
1162 GATE(CLK_TZPC4, "tzpc4", "aclk66_psgen", GATE_IP_PERIS, 10, 0, 0),
1163 GATE(CLK_TZPC5, "tzpc5", "aclk66_psgen", GATE_IP_PERIS, 11, 0, 0),
1164 GATE(CLK_TZPC6, "tzpc6", "aclk66_psgen", GATE_IP_PERIS, 12, 0, 0),
1165 GATE(CLK_TZPC7, "tzpc7", "aclk66_psgen", GATE_IP_PERIS, 13, 0, 0),
1166 GATE(CLK_TZPC8, "tzpc8", "aclk66_psgen", GATE_IP_PERIS, 14, 0, 0),
1167 GATE(CLK_TZPC9, "tzpc9", "aclk66_psgen", GATE_IP_PERIS, 15, 0, 0),
1168 GATE(CLK_HDMI_CEC, "hdmi_cec", "aclk66_psgen", GATE_IP_PERIS, 16, 0, 0),
1169 GATE(CLK_MCT, "mct", "aclk66_psgen", GATE_IP_PERIS, 18, 0, 0),
1170 GATE(CLK_WDT, "wdt", "aclk66_psgen", GATE_IP_PERIS, 19, 0, 0),
1171 GATE(CLK_RTC, "rtc", "aclk66_psgen", GATE_IP_PERIS, 20, 0, 0),
1172 GATE(CLK_TMU, "tmu", "aclk66_psgen", GATE_IP_PERIS, 21, 0, 0),
1173 GATE(CLK_TMU_GPU, "tmu_gpu", "aclk66_psgen", GATE_IP_PERIS, 22, 0, 0),
1174
1175 /* GEN Block */
1176 GATE(CLK_ROTATOR, "rotator", "mout_user_aclk266", GATE_IP_GEN, 1, 0, 0),
1177 GATE(CLK_JPEG, "jpeg", "aclk300_jpeg", GATE_IP_GEN, 2, 0, 0),
1178 GATE(CLK_JPEG2, "jpeg2", "aclk300_jpeg", GATE_IP_GEN, 3, 0, 0),
1179 GATE(CLK_MDMA1, "mdma1", "mout_user_aclk266", GATE_IP_GEN, 4, 0, 0),
1180 GATE(CLK_TOP_RTC, "top_rtc", "aclk66_psgen", GATE_IP_GEN, 5, 0, 0),
1181 GATE(CLK_SMMU_ROTATOR, "smmu_rotator", "dout_gen_blk",
1182 GATE_IP_GEN, 6, 0, 0),
1183 GATE(CLK_SMMU_JPEG, "smmu_jpeg", "dout_jpg_blk", GATE_IP_GEN, 7, 0, 0),
1184 GATE(CLK_SMMU_MDMA1, "smmu_mdma1", "dout_gen_blk",
1185 GATE_IP_GEN, 9, 0, 0),
1186
1187 /* GATE_IP_GEN doesn't list gates for smmu_jpeg2 and mc */
1188 GATE(CLK_SMMU_JPEG2, "smmu_jpeg2", "dout_jpg_blk",
1189 GATE_BUS_GEN, 28, 0, 0),
1190 GATE(CLK_MC, "mc", "aclk66_psgen", GATE_BUS_GEN, 12, 0, 0),
1191
1192 /* GSCL Block */
1193 GATE(CLK_SCLK_GSCL_WA, "sclk_gscl_wa", "mout_user_aclk333_432_gscl",
1194 GATE_TOP_SCLK_GSCL, 6, 0, 0),
1195 GATE(CLK_SCLK_GSCL_WB, "sclk_gscl_wb", "mout_user_aclk333_432_gscl",
1196 GATE_TOP_SCLK_GSCL, 7, 0, 0),
1197
1198 GATE(CLK_FIMC_3AA, "fimc_3aa", "aclk333_432_gscl",
1199 GATE_IP_GSCL0, 4, 0, 0),
1200 GATE(CLK_FIMC_LITE0, "fimc_lite0", "aclk333_432_gscl",
1201 GATE_IP_GSCL0, 5, 0, 0),
1202 GATE(CLK_FIMC_LITE1, "fimc_lite1", "aclk333_432_gscl",
1203 GATE_IP_GSCL0, 6, 0, 0),
1204
1205 GATE(CLK_SMMU_3AA, "smmu_3aa", "dout_gscl_blk_333",
1206 GATE_IP_GSCL1, 2, 0, 0),
1207 GATE(CLK_SMMU_FIMCL0, "smmu_fimcl0", "dout_gscl_blk_333",
1208 GATE_IP_GSCL1, 3, 0, 0),
1209 GATE(CLK_SMMU_FIMCL1, "smmu_fimcl1", "dout_gscl_blk_333",
1210 GATE_IP_GSCL1, 4, 0, 0),
1211 GATE(CLK_GSCL_WA, "gscl_wa", "sclk_gscl_wa", GATE_IP_GSCL1, 12,
1212 CLK_IS_CRITICAL, 0),
1213 GATE(CLK_GSCL_WB, "gscl_wb", "sclk_gscl_wb", GATE_IP_GSCL1, 13,
1214 CLK_IS_CRITICAL, 0),
1215 GATE(CLK_SMMU_FIMCL3, "smmu_fimcl3,", "dout_gscl_blk_333",
1216 GATE_IP_GSCL1, 16, 0, 0),
1217 GATE(CLK_FIMC_LITE3, "fimc_lite3", "aclk333_432_gscl",
1218 GATE_IP_GSCL1, 17, 0, 0),
1219
1220 /* MSCL Block */
1221 GATE(CLK_MSCL0, "mscl0", "aclk400_mscl", GATE_IP_MSCL, 0, 0, 0),
1222 GATE(CLK_MSCL1, "mscl1", "aclk400_mscl", GATE_IP_MSCL, 1, 0, 0),
1223 GATE(CLK_MSCL2, "mscl2", "aclk400_mscl", GATE_IP_MSCL, 2, 0, 0),
1224 GATE(CLK_SMMU_MSCL0, "smmu_mscl0", "dout_mscl_blk",
1225 GATE_IP_MSCL, 8, 0, 0),
1226 GATE(CLK_SMMU_MSCL1, "smmu_mscl1", "dout_mscl_blk",
1227 GATE_IP_MSCL, 9, 0, 0),
1228 GATE(CLK_SMMU_MSCL2, "smmu_mscl2", "dout_mscl_blk",
1229 GATE_IP_MSCL, 10, 0, 0),
1230
1231 /* ISP */
1232 GATE(CLK_SCLK_UART_ISP, "sclk_uart_isp", "dout_uart_isp",
1233 GATE_TOP_SCLK_ISP, 0, CLK_SET_RATE_PARENT, 0),
1234 GATE(CLK_SCLK_SPI0_ISP, "sclk_spi0_isp", "dout_spi0_isp_pre",
1235 GATE_TOP_SCLK_ISP, 1, CLK_SET_RATE_PARENT, 0),
1236 GATE(CLK_SCLK_SPI1_ISP, "sclk_spi1_isp", "dout_spi1_isp_pre",
1237 GATE_TOP_SCLK_ISP, 2, CLK_SET_RATE_PARENT, 0),
1238 GATE(CLK_SCLK_PWM_ISP, "sclk_pwm_isp", "dout_pwm_isp",
1239 GATE_TOP_SCLK_ISP, 3, CLK_SET_RATE_PARENT, 0),
1240 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "dout_isp_sensor0",
1241 GATE_TOP_SCLK_ISP, 4, CLK_SET_RATE_PARENT, 0),
1242 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "dout_isp_sensor1",
1243 GATE_TOP_SCLK_ISP, 8, CLK_SET_RATE_PARENT, 0),
1244 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "dout_isp_sensor2",
1245 GATE_TOP_SCLK_ISP, 12, CLK_SET_RATE_PARENT, 0),
1246
1247 GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9, 0, 0),
1248 };
1249
1250 static const struct samsung_div_clock exynos5x_disp_div_clks[] __initconst = {
1251 DIV(0, "dout_disp1_blk", "aclk200_disp1", DIV2_RATIO0, 16, 2),
1252 };
1253
1254 static const struct samsung_gate_clock exynos5x_disp_gate_clks[] __initconst = {
1255 GATE(CLK_FIMD1, "fimd1", "aclk300_disp1", GATE_IP_DISP1, 0, 0, 0),
1256 GATE(CLK_DSIM1, "dsim1", "aclk200_disp1", GATE_IP_DISP1, 3, 0, 0),
1257 GATE(CLK_DP1, "dp1", "aclk200_disp1", GATE_IP_DISP1, 4, 0, 0),
1258 GATE(CLK_MIXER, "mixer", "aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
1259 GATE(CLK_HDMI, "hdmi", "aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
1260 GATE(CLK_SMMU_FIMD1M0, "smmu_fimd1m0", "dout_disp1_blk",
1261 GATE_IP_DISP1, 7, 0, 0),
1262 GATE(CLK_SMMU_FIMD1M1, "smmu_fimd1m1", "dout_disp1_blk",
1263 GATE_IP_DISP1, 8, 0, 0),
1264 GATE(CLK_SMMU_MIXER, "smmu_mixer", "aclk200_disp1",
1265 GATE_IP_DISP1, 9, 0, 0),
1266 };
1267
1268 static struct exynos5_subcmu_reg_dump exynos5x_disp_suspend_regs[] = {
1269 { GATE_IP_DISP1, 0xffffffff, 0xffffffff }, /* DISP1 gates */
1270 { SRC_TOP5, 0, BIT(0) }, /* MUX mout_user_aclk400_disp1 */
1271 { SRC_TOP5, 0, BIT(24) }, /* MUX mout_user_aclk300_disp1 */
1272 { SRC_TOP3, 0, BIT(8) }, /* MUX mout_user_aclk200_disp1 */
1273 { DIV2_RATIO0, 0, 0x30000 }, /* DIV dout_disp1_blk */
1274 };
1275
1276 static const struct samsung_div_clock exynos5x_gsc_div_clks[] __initconst = {
1277 DIV(0, "dout_gscl_blk_300", "mout_user_aclk300_gscl",
1278 DIV2_RATIO0, 4, 2),
1279 };
1280
1281 static const struct samsung_gate_clock exynos5x_gsc_gate_clks[] __initconst = {
1282 GATE(CLK_GSCL0, "gscl0", "aclk300_gscl", GATE_IP_GSCL0, 0, 0, 0),
1283 GATE(CLK_GSCL1, "gscl1", "aclk300_gscl", GATE_IP_GSCL0, 1, 0, 0),
1284 GATE(CLK_SMMU_GSCL0, "smmu_gscl0", "dout_gscl_blk_300",
1285 GATE_IP_GSCL1, 6, 0, 0),
1286 GATE(CLK_SMMU_GSCL1, "smmu_gscl1", "dout_gscl_blk_300",
1287 GATE_IP_GSCL1, 7, 0, 0),
1288 };
1289
1290 static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
1291 { GATE_IP_GSCL0, 0x3, 0x3 }, /* GSC gates */
1292 { GATE_IP_GSCL1, 0xc0, 0xc0 }, /* GSC gates */
1293 { SRC_TOP5, 0, BIT(28) }, /* MUX mout_user_aclk300_gscl */
1294 { DIV2_RATIO0, 0, 0x30 }, /* DIV dout_gscl_blk_300 */
1295 };
1296
1297 static const struct samsung_div_clock exynos5x_mfc_div_clks[] __initconst = {
1298 DIV(0, "dout_mfc_blk", "mout_user_aclk333", DIV4_RATIO, 0, 2),
1299 };
1300
1301 static const struct samsung_gate_clock exynos5x_mfc_gate_clks[] __initconst = {
1302 GATE(CLK_MFC, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
1303 GATE(CLK_SMMU_MFCL, "smmu_mfcl", "dout_mfc_blk", GATE_IP_MFC, 1, 0, 0),
1304 GATE(CLK_SMMU_MFCR, "smmu_mfcr", "dout_mfc_blk", GATE_IP_MFC, 2, 0, 0),
1305 };
1306
1307 static struct exynos5_subcmu_reg_dump exynos5x_mfc_suspend_regs[] = {
1308 { GATE_IP_MFC, 0xffffffff, 0xffffffff }, /* MFC gates */
1309 { SRC_TOP4, 0, BIT(28) }, /* MUX mout_user_aclk333 */
1310 { DIV4_RATIO, 0, 0x3 }, /* DIV dout_mfc_blk */
1311 };
1312
1313 static const struct exynos5_subcmu_info exynos5x_subcmus[] = {
1314 {
1315 .div_clks = exynos5x_disp_div_clks,
1316 .nr_div_clks = ARRAY_SIZE(exynos5x_disp_div_clks),
1317 .gate_clks = exynos5x_disp_gate_clks,
1318 .nr_gate_clks = ARRAY_SIZE(exynos5x_disp_gate_clks),
1319 .suspend_regs = exynos5x_disp_suspend_regs,
1320 .nr_suspend_regs = ARRAY_SIZE(exynos5x_disp_suspend_regs),
1321 .pd_name = "DISP",
1322 }, {
1323 .div_clks = exynos5x_gsc_div_clks,
1324 .nr_div_clks = ARRAY_SIZE(exynos5x_gsc_div_clks),
1325 .gate_clks = exynos5x_gsc_gate_clks,
1326 .nr_gate_clks = ARRAY_SIZE(exynos5x_gsc_gate_clks),
1327 .suspend_regs = exynos5x_gsc_suspend_regs,
1328 .nr_suspend_regs = ARRAY_SIZE(exynos5x_gsc_suspend_regs),
1329 .pd_name = "GSC",
1330 }, {
1331 .div_clks = exynos5x_mfc_div_clks,
1332 .nr_div_clks = ARRAY_SIZE(exynos5x_mfc_div_clks),
1333 .gate_clks = exynos5x_mfc_gate_clks,
1334 .nr_gate_clks = ARRAY_SIZE(exynos5x_mfc_gate_clks),
1335 .suspend_regs = exynos5x_mfc_suspend_regs,
1336 .nr_suspend_regs = ARRAY_SIZE(exynos5x_mfc_suspend_regs),
1337 .pd_name = "MFC",
1338 },
1339 };
1340
1341 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
1342 PLL_35XX_RATE(24 * MHZ, 2000000000, 250, 3, 0),
1343 PLL_35XX_RATE(24 * MHZ, 1900000000, 475, 6, 0),
1344 PLL_35XX_RATE(24 * MHZ, 1800000000, 225, 3, 0),
1345 PLL_35XX_RATE(24 * MHZ, 1700000000, 425, 6, 0),
1346 PLL_35XX_RATE(24 * MHZ, 1600000000, 200, 3, 0),
1347 PLL_35XX_RATE(24 * MHZ, 1500000000, 250, 4, 0),
1348 PLL_35XX_RATE(24 * MHZ, 1400000000, 175, 3, 0),
1349 PLL_35XX_RATE(24 * MHZ, 1300000000, 325, 6, 0),
1350 PLL_35XX_RATE(24 * MHZ, 1200000000, 200, 2, 1),
1351 PLL_35XX_RATE(24 * MHZ, 1100000000, 275, 3, 1),
1352 PLL_35XX_RATE(24 * MHZ, 1000000000, 250, 3, 1),
1353 PLL_35XX_RATE(24 * MHZ, 900000000, 150, 2, 1),
1354 PLL_35XX_RATE(24 * MHZ, 800000000, 200, 3, 1),
1355 PLL_35XX_RATE(24 * MHZ, 700000000, 175, 3, 1),
1356 PLL_35XX_RATE(24 * MHZ, 600000000, 200, 2, 2),
1357 PLL_35XX_RATE(24 * MHZ, 500000000, 250, 3, 2),
1358 PLL_35XX_RATE(24 * MHZ, 400000000, 200, 3, 2),
1359 PLL_35XX_RATE(24 * MHZ, 300000000, 200, 2, 3),
1360 PLL_35XX_RATE(24 * MHZ, 200000000, 200, 3, 3),
1361 };
1362
1363 static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = {
1364 PLL_36XX_RATE(24 * MHZ, 600000000U, 100, 2, 1, 0),
1365 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
1366 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
1367 PLL_36XX_RATE(24 * MHZ, 361267218U, 301, 5, 2, 3671),
1368 PLL_36XX_RATE(24 * MHZ, 200000000U, 200, 3, 3, 0),
1369 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
1370 PLL_36XX_RATE(24 * MHZ, 180633609U, 301, 5, 3, 3671),
1371 PLL_36XX_RATE(24 * MHZ, 131072006U, 131, 3, 3, 4719),
1372 PLL_36XX_RATE(24 * MHZ, 100000000U, 200, 3, 4, 0),
1373 PLL_36XX_RATE(24 * MHZ, 73728000U, 98, 2, 4, 19923),
1374 PLL_36XX_RATE(24 * MHZ, 67737602U, 90, 2, 4, 20762),
1375 PLL_36XX_RATE(24 * MHZ, 65536003U, 131, 3, 4, 4719),
1376 PLL_36XX_RATE(24 * MHZ, 49152000U, 197, 3, 5, -25690),
1377 PLL_36XX_RATE(24 * MHZ, 45158401U, 90, 3, 4, 20762),
1378 PLL_36XX_RATE(24 * MHZ, 32768001U, 131, 3, 5, 4719),
1379 };
1380
1381 static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = {
1382 [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK,
1383 APLL_CON0, NULL),
1384 [cpll] = PLL(pll_2550, CLK_FOUT_CPLL, "fout_cpll", "fin_pll", CPLL_LOCK,
1385 CPLL_CON0, NULL),
1386 [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK,
1387 DPLL_CON0, NULL),
1388 [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK,
1389 EPLL_CON0, NULL),
1390 [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK,
1391 RPLL_CON0, NULL),
1392 [ipll] = PLL(pll_2550, CLK_FOUT_IPLL, "fout_ipll", "fin_pll", IPLL_LOCK,
1393 IPLL_CON0, NULL),
1394 [spll] = PLL(pll_2550, CLK_FOUT_SPLL, "fout_spll", "fin_pll", SPLL_LOCK,
1395 SPLL_CON0, NULL),
1396 [vpll] = PLL(pll_2550, CLK_FOUT_VPLL, "fout_vpll", "fin_pll", VPLL_LOCK,
1397 VPLL_CON0, NULL),
1398 [mpll] = PLL(pll_2550, CLK_FOUT_MPLL, "fout_mpll", "fin_pll", MPLL_LOCK,
1399 MPLL_CON0, NULL),
1400 [bpll] = PLL(pll_2550, CLK_FOUT_BPLL, "fout_bpll", "fin_pll", BPLL_LOCK,
1401 BPLL_CON0, NULL),
1402 [kpll] = PLL(pll_2550, CLK_FOUT_KPLL, "fout_kpll", "fin_pll", KPLL_LOCK,
1403 KPLL_CON0, NULL),
1404 };
1405
1406 #define E5420_EGL_DIV0(apll, pclk_dbg, atb, cpud) \
1407 ((((apll) << 24) | ((pclk_dbg) << 20) | ((atb) << 16) | \
1408 ((cpud) << 4)))
1409
1410 static const struct exynos_cpuclk_cfg_data exynos5420_eglclk_d[] __initconst = {
1411 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1412 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1413 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1414 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1415 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1416 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1417 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1418 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1419 { 1000000, E5420_EGL_DIV0(3, 6, 6, 2), },
1420 { 900000, E5420_EGL_DIV0(3, 6, 6, 2), },
1421 { 800000, E5420_EGL_DIV0(3, 5, 5, 2), },
1422 { 700000, E5420_EGL_DIV0(3, 5, 5, 2), },
1423 { 600000, E5420_EGL_DIV0(3, 4, 4, 2), },
1424 { 500000, E5420_EGL_DIV0(3, 3, 3, 2), },
1425 { 400000, E5420_EGL_DIV0(3, 3, 3, 2), },
1426 { 300000, E5420_EGL_DIV0(3, 3, 3, 2), },
1427 { 200000, E5420_EGL_DIV0(3, 3, 3, 2), },
1428 { 0 },
1429 };
1430
1431 static const struct exynos_cpuclk_cfg_data exynos5800_eglclk_d[] __initconst = {
1432 { 2000000, E5420_EGL_DIV0(3, 7, 7, 4), },
1433 { 1900000, E5420_EGL_DIV0(3, 7, 7, 4), },
1434 { 1800000, E5420_EGL_DIV0(3, 7, 7, 4), },
1435 { 1700000, E5420_EGL_DIV0(3, 7, 7, 3), },
1436 { 1600000, E5420_EGL_DIV0(3, 7, 7, 3), },
1437 { 1500000, E5420_EGL_DIV0(3, 7, 7, 3), },
1438 { 1400000, E5420_EGL_DIV0(3, 7, 7, 3), },
1439 { 1300000, E5420_EGL_DIV0(3, 7, 7, 2), },
1440 { 1200000, E5420_EGL_DIV0(3, 7, 7, 2), },
1441 { 1100000, E5420_EGL_DIV0(3, 7, 7, 2), },
1442 { 1000000, E5420_EGL_DIV0(3, 7, 6, 2), },
1443 { 900000, E5420_EGL_DIV0(3, 7, 6, 2), },
1444 { 800000, E5420_EGL_DIV0(3, 7, 5, 2), },
1445 { 700000, E5420_EGL_DIV0(3, 7, 5, 2), },
1446 { 600000, E5420_EGL_DIV0(3, 7, 4, 2), },
1447 { 500000, E5420_EGL_DIV0(3, 7, 3, 2), },
1448 { 400000, E5420_EGL_DIV0(3, 7, 3, 2), },
1449 { 300000, E5420_EGL_DIV0(3, 7, 3, 2), },
1450 { 200000, E5420_EGL_DIV0(3, 7, 3, 2), },
1451 { 0 },
1452 };
1453
1454 #define E5420_KFC_DIV(kpll, pclk, aclk) \
1455 ((((kpll) << 24) | ((pclk) << 20) | ((aclk) << 4)))
1456
1457 static const struct exynos_cpuclk_cfg_data exynos5420_kfcclk_d[] __initconst = {
1458 { 1400000, E5420_KFC_DIV(3, 5, 3), }, /* for Exynos5800 */
1459 { 1300000, E5420_KFC_DIV(3, 5, 2), },
1460 { 1200000, E5420_KFC_DIV(3, 5, 2), },
1461 { 1100000, E5420_KFC_DIV(3, 5, 2), },
1462 { 1000000, E5420_KFC_DIV(3, 5, 2), },
1463 { 900000, E5420_KFC_DIV(3, 5, 2), },
1464 { 800000, E5420_KFC_DIV(3, 5, 2), },
1465 { 700000, E5420_KFC_DIV(3, 4, 2), },
1466 { 600000, E5420_KFC_DIV(3, 4, 2), },
1467 { 500000, E5420_KFC_DIV(3, 4, 2), },
1468 { 400000, E5420_KFC_DIV(3, 3, 2), },
1469 { 300000, E5420_KFC_DIV(3, 3, 2), },
1470 { 200000, E5420_KFC_DIV(3, 3, 2), },
1471 { 0 },
1472 };
1473
1474 static const struct of_device_id ext_clk_match[] __initconst = {
1475 { .compatible = "samsung,exynos5420-oscclk", .data = (void *)0, },
1476 { },
1477 };
1478
1479 /* register exynos5420 clocks */
exynos5x_clk_init(struct device_node * np,enum exynos5x_soc soc)1480 static void __init exynos5x_clk_init(struct device_node *np,
1481 enum exynos5x_soc soc)
1482 {
1483 struct samsung_clk_provider *ctx;
1484
1485 if (np) {
1486 reg_base = of_iomap(np, 0);
1487 if (!reg_base)
1488 panic("%s: failed to map registers\n", __func__);
1489 } else {
1490 panic("%s: unable to determine soc\n", __func__);
1491 }
1492
1493 exynos5x_soc = soc;
1494
1495 ctx = samsung_clk_init(np, reg_base, CLK_NR_CLKS);
1496
1497 samsung_clk_of_register_fixed_ext(ctx, exynos5x_fixed_rate_ext_clks,
1498 ARRAY_SIZE(exynos5x_fixed_rate_ext_clks),
1499 ext_clk_match);
1500
1501 if (_get_rate("fin_pll") == 24 * MHZ) {
1502 exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1503 exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl;
1504 exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1505 exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl;
1506 }
1507
1508 samsung_clk_register_pll(ctx, exynos5x_plls, ARRAY_SIZE(exynos5x_plls),
1509 reg_base);
1510 samsung_clk_register_fixed_rate(ctx, exynos5x_fixed_rate_clks,
1511 ARRAY_SIZE(exynos5x_fixed_rate_clks));
1512 samsung_clk_register_fixed_factor(ctx, exynos5x_fixed_factor_clks,
1513 ARRAY_SIZE(exynos5x_fixed_factor_clks));
1514 samsung_clk_register_mux(ctx, exynos5x_mux_clks,
1515 ARRAY_SIZE(exynos5x_mux_clks));
1516 samsung_clk_register_div(ctx, exynos5x_div_clks,
1517 ARRAY_SIZE(exynos5x_div_clks));
1518 samsung_clk_register_gate(ctx, exynos5x_gate_clks,
1519 ARRAY_SIZE(exynos5x_gate_clks));
1520
1521 if (soc == EXYNOS5420) {
1522 samsung_clk_register_mux(ctx, exynos5420_mux_clks,
1523 ARRAY_SIZE(exynos5420_mux_clks));
1524 samsung_clk_register_div(ctx, exynos5420_div_clks,
1525 ARRAY_SIZE(exynos5420_div_clks));
1526 samsung_clk_register_gate(ctx, exynos5420_gate_clks,
1527 ARRAY_SIZE(exynos5420_gate_clks));
1528 } else {
1529 samsung_clk_register_fixed_factor(
1530 ctx, exynos5800_fixed_factor_clks,
1531 ARRAY_SIZE(exynos5800_fixed_factor_clks));
1532 samsung_clk_register_mux(ctx, exynos5800_mux_clks,
1533 ARRAY_SIZE(exynos5800_mux_clks));
1534 samsung_clk_register_div(ctx, exynos5800_div_clks,
1535 ARRAY_SIZE(exynos5800_div_clks));
1536 samsung_clk_register_gate(ctx, exynos5800_gate_clks,
1537 ARRAY_SIZE(exynos5800_gate_clks));
1538 }
1539
1540 if (soc == EXYNOS5420) {
1541 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1542 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1543 exynos5420_eglclk_d, ARRAY_SIZE(exynos5420_eglclk_d), 0);
1544 } else {
1545 exynos_register_cpu_clock(ctx, CLK_ARM_CLK, "armclk",
1546 mout_cpu_p[0], mout_cpu_p[1], 0x200,
1547 exynos5800_eglclk_d, ARRAY_SIZE(exynos5800_eglclk_d), 0);
1548 }
1549 exynos_register_cpu_clock(ctx, CLK_KFC_CLK, "kfcclk",
1550 mout_kfc_p[0], mout_kfc_p[1], 0x28200,
1551 exynos5420_kfcclk_d, ARRAY_SIZE(exynos5420_kfcclk_d), 0);
1552
1553 exynos5420_clk_sleep_init();
1554 exynos5_subcmus_init(ctx, ARRAY_SIZE(exynos5x_subcmus),
1555 exynos5x_subcmus);
1556
1557 samsung_clk_of_add_provider(np, ctx);
1558 }
1559
exynos5420_clk_init(struct device_node * np)1560 static void __init exynos5420_clk_init(struct device_node *np)
1561 {
1562 exynos5x_clk_init(np, EXYNOS5420);
1563 }
1564 CLK_OF_DECLARE_DRIVER(exynos5420_clk, "samsung,exynos5420-clock",
1565 exynos5420_clk_init);
1566
exynos5800_clk_init(struct device_node * np)1567 static void __init exynos5800_clk_init(struct device_node *np)
1568 {
1569 exynos5x_clk_init(np, EXYNOS5800);
1570 }
1571 CLK_OF_DECLARE_DRIVER(exynos5800_clk, "samsung,exynos5800-clock",
1572 exynos5800_clk_init);
1573