1 /*
2 * Copyright (c) 2014 Samsung Electronics Co., Ltd.
3 * Author: Chanwoo Choi <cw00.choi@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * Common Clock Framework support for Exynos5433 SoC.
10 */
11
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/slab.h>
20
21 #include <dt-bindings/clock/exynos5433.h>
22
23 #include "clk.h"
24 #include "clk-cpu.h"
25 #include "clk-pll.h"
26
27 /*
28 * Register offset definitions for CMU_TOP
29 */
30 #define ISP_PLL_LOCK 0x0000
31 #define AUD_PLL_LOCK 0x0004
32 #define ISP_PLL_CON0 0x0100
33 #define ISP_PLL_CON1 0x0104
34 #define ISP_PLL_FREQ_DET 0x0108
35 #define AUD_PLL_CON0 0x0110
36 #define AUD_PLL_CON1 0x0114
37 #define AUD_PLL_CON2 0x0118
38 #define AUD_PLL_FREQ_DET 0x011c
39 #define MUX_SEL_TOP0 0x0200
40 #define MUX_SEL_TOP1 0x0204
41 #define MUX_SEL_TOP2 0x0208
42 #define MUX_SEL_TOP3 0x020c
43 #define MUX_SEL_TOP4 0x0210
44 #define MUX_SEL_TOP_MSCL 0x0220
45 #define MUX_SEL_TOP_CAM1 0x0224
46 #define MUX_SEL_TOP_DISP 0x0228
47 #define MUX_SEL_TOP_FSYS0 0x0230
48 #define MUX_SEL_TOP_FSYS1 0x0234
49 #define MUX_SEL_TOP_PERIC0 0x0238
50 #define MUX_SEL_TOP_PERIC1 0x023c
51 #define MUX_ENABLE_TOP0 0x0300
52 #define MUX_ENABLE_TOP1 0x0304
53 #define MUX_ENABLE_TOP2 0x0308
54 #define MUX_ENABLE_TOP3 0x030c
55 #define MUX_ENABLE_TOP4 0x0310
56 #define MUX_ENABLE_TOP_MSCL 0x0320
57 #define MUX_ENABLE_TOP_CAM1 0x0324
58 #define MUX_ENABLE_TOP_DISP 0x0328
59 #define MUX_ENABLE_TOP_FSYS0 0x0330
60 #define MUX_ENABLE_TOP_FSYS1 0x0334
61 #define MUX_ENABLE_TOP_PERIC0 0x0338
62 #define MUX_ENABLE_TOP_PERIC1 0x033c
63 #define MUX_STAT_TOP0 0x0400
64 #define MUX_STAT_TOP1 0x0404
65 #define MUX_STAT_TOP2 0x0408
66 #define MUX_STAT_TOP3 0x040c
67 #define MUX_STAT_TOP4 0x0410
68 #define MUX_STAT_TOP_MSCL 0x0420
69 #define MUX_STAT_TOP_CAM1 0x0424
70 #define MUX_STAT_TOP_FSYS0 0x0430
71 #define MUX_STAT_TOP_FSYS1 0x0434
72 #define MUX_STAT_TOP_PERIC0 0x0438
73 #define MUX_STAT_TOP_PERIC1 0x043c
74 #define DIV_TOP0 0x0600
75 #define DIV_TOP1 0x0604
76 #define DIV_TOP2 0x0608
77 #define DIV_TOP3 0x060c
78 #define DIV_TOP4 0x0610
79 #define DIV_TOP_MSCL 0x0618
80 #define DIV_TOP_CAM10 0x061c
81 #define DIV_TOP_CAM11 0x0620
82 #define DIV_TOP_FSYS0 0x062c
83 #define DIV_TOP_FSYS1 0x0630
84 #define DIV_TOP_FSYS2 0x0634
85 #define DIV_TOP_PERIC0 0x0638
86 #define DIV_TOP_PERIC1 0x063c
87 #define DIV_TOP_PERIC2 0x0640
88 #define DIV_TOP_PERIC3 0x0644
89 #define DIV_TOP_PERIC4 0x0648
90 #define DIV_TOP_PLL_FREQ_DET 0x064c
91 #define DIV_STAT_TOP0 0x0700
92 #define DIV_STAT_TOP1 0x0704
93 #define DIV_STAT_TOP2 0x0708
94 #define DIV_STAT_TOP3 0x070c
95 #define DIV_STAT_TOP4 0x0710
96 #define DIV_STAT_TOP_MSCL 0x0718
97 #define DIV_STAT_TOP_CAM10 0x071c
98 #define DIV_STAT_TOP_CAM11 0x0720
99 #define DIV_STAT_TOP_FSYS0 0x072c
100 #define DIV_STAT_TOP_FSYS1 0x0730
101 #define DIV_STAT_TOP_FSYS2 0x0734
102 #define DIV_STAT_TOP_PERIC0 0x0738
103 #define DIV_STAT_TOP_PERIC1 0x073c
104 #define DIV_STAT_TOP_PERIC2 0x0740
105 #define DIV_STAT_TOP_PERIC3 0x0744
106 #define DIV_STAT_TOP_PLL_FREQ_DET 0x074c
107 #define ENABLE_ACLK_TOP 0x0800
108 #define ENABLE_SCLK_TOP 0x0a00
109 #define ENABLE_SCLK_TOP_MSCL 0x0a04
110 #define ENABLE_SCLK_TOP_CAM1 0x0a08
111 #define ENABLE_SCLK_TOP_DISP 0x0a0c
112 #define ENABLE_SCLK_TOP_FSYS 0x0a10
113 #define ENABLE_SCLK_TOP_PERIC 0x0a14
114 #define ENABLE_IP_TOP 0x0b00
115 #define ENABLE_CMU_TOP 0x0c00
116 #define ENABLE_CMU_TOP_DIV_STAT 0x0c04
117
118 static const unsigned long top_clk_regs[] __initconst = {
119 ISP_PLL_LOCK,
120 AUD_PLL_LOCK,
121 ISP_PLL_CON0,
122 ISP_PLL_CON1,
123 ISP_PLL_FREQ_DET,
124 AUD_PLL_CON0,
125 AUD_PLL_CON1,
126 AUD_PLL_CON2,
127 AUD_PLL_FREQ_DET,
128 MUX_SEL_TOP0,
129 MUX_SEL_TOP1,
130 MUX_SEL_TOP2,
131 MUX_SEL_TOP3,
132 MUX_SEL_TOP4,
133 MUX_SEL_TOP_MSCL,
134 MUX_SEL_TOP_CAM1,
135 MUX_SEL_TOP_DISP,
136 MUX_SEL_TOP_FSYS0,
137 MUX_SEL_TOP_FSYS1,
138 MUX_SEL_TOP_PERIC0,
139 MUX_SEL_TOP_PERIC1,
140 MUX_ENABLE_TOP0,
141 MUX_ENABLE_TOP1,
142 MUX_ENABLE_TOP2,
143 MUX_ENABLE_TOP3,
144 MUX_ENABLE_TOP4,
145 MUX_ENABLE_TOP_MSCL,
146 MUX_ENABLE_TOP_CAM1,
147 MUX_ENABLE_TOP_DISP,
148 MUX_ENABLE_TOP_FSYS0,
149 MUX_ENABLE_TOP_FSYS1,
150 MUX_ENABLE_TOP_PERIC0,
151 MUX_ENABLE_TOP_PERIC1,
152 DIV_TOP0,
153 DIV_TOP1,
154 DIV_TOP2,
155 DIV_TOP3,
156 DIV_TOP4,
157 DIV_TOP_MSCL,
158 DIV_TOP_CAM10,
159 DIV_TOP_CAM11,
160 DIV_TOP_FSYS0,
161 DIV_TOP_FSYS1,
162 DIV_TOP_FSYS2,
163 DIV_TOP_PERIC0,
164 DIV_TOP_PERIC1,
165 DIV_TOP_PERIC2,
166 DIV_TOP_PERIC3,
167 DIV_TOP_PERIC4,
168 DIV_TOP_PLL_FREQ_DET,
169 ENABLE_ACLK_TOP,
170 ENABLE_SCLK_TOP,
171 ENABLE_SCLK_TOP_MSCL,
172 ENABLE_SCLK_TOP_CAM1,
173 ENABLE_SCLK_TOP_DISP,
174 ENABLE_SCLK_TOP_FSYS,
175 ENABLE_SCLK_TOP_PERIC,
176 ENABLE_IP_TOP,
177 ENABLE_CMU_TOP,
178 ENABLE_CMU_TOP_DIV_STAT,
179 };
180
181 /* list of all parent clock list */
182 PNAME(mout_aud_pll_p) = { "oscclk", "fout_aud_pll", };
183 PNAME(mout_isp_pll_p) = { "oscclk", "fout_isp_pll", };
184 PNAME(mout_aud_pll_user_p) = { "oscclk", "mout_aud_pll", };
185 PNAME(mout_mphy_pll_user_p) = { "oscclk", "sclk_mphy_pll", };
186 PNAME(mout_mfc_pll_user_p) = { "oscclk", "sclk_mfc_pll", };
187 PNAME(mout_bus_pll_user_p) = { "oscclk", "sclk_bus_pll", };
188 PNAME(mout_bus_pll_user_t_p) = { "oscclk", "mout_bus_pll_user", };
189 PNAME(mout_mphy_pll_user_t_p) = { "oscclk", "mout_mphy_pll_user", };
190
191 PNAME(mout_bus_mfc_pll_user_p) = { "mout_bus_pll_user", "mout_mfc_pll_user",};
192 PNAME(mout_mfc_bus_pll_user_p) = { "mout_mfc_pll_user", "mout_bus_pll_user",};
193 PNAME(mout_aclk_cam1_552_b_p) = { "mout_aclk_cam1_552_a",
194 "mout_mfc_pll_user", };
195 PNAME(mout_aclk_cam1_552_a_p) = { "mout_isp_pll", "mout_bus_pll_user", };
196
197 PNAME(mout_aclk_mfc_400_c_p) = { "mout_aclk_mfc_400_b",
198 "mout_mphy_pll_user", };
199 PNAME(mout_aclk_mfc_400_b_p) = { "mout_aclk_mfc_400_a",
200 "mout_bus_pll_user", };
201 PNAME(mout_aclk_mfc_400_a_p) = { "mout_mfc_pll_user", "mout_isp_pll", };
202
203 PNAME(mout_bus_mphy_pll_user_p) = { "mout_bus_pll_user",
204 "mout_mphy_pll_user", };
205 PNAME(mout_aclk_mscl_b_p) = { "mout_aclk_mscl_400_a",
206 "mout_mphy_pll_user", };
207 PNAME(mout_aclk_g2d_400_b_p) = { "mout_aclk_g2d_400_a",
208 "mout_mphy_pll_user", };
209
210 PNAME(mout_sclk_jpeg_c_p) = { "mout_sclk_jpeg_b", "mout_mphy_pll_user",};
211 PNAME(mout_sclk_jpeg_b_p) = { "mout_sclk_jpeg_a", "mout_mfc_pll_user", };
212
213 PNAME(mout_sclk_mmc2_b_p) = { "mout_sclk_mmc2_a", "mout_mfc_pll_user",};
214 PNAME(mout_sclk_mmc1_b_p) = { "mout_sclk_mmc1_a", "mout_mfc_pll_user",};
215 PNAME(mout_sclk_mmc0_d_p) = { "mout_sclk_mmc0_c", "mout_isp_pll", };
216 PNAME(mout_sclk_mmc0_c_p) = { "mout_sclk_mmc0_b", "mout_mphy_pll_user",};
217 PNAME(mout_sclk_mmc0_b_p) = { "mout_sclk_mmc0_a", "mout_mfc_pll_user", };
218
219 PNAME(mout_sclk_spdif_p) = { "sclk_audio0", "sclk_audio1",
220 "oscclk", "ioclk_spdif_extclk", };
221 PNAME(mout_sclk_audio1_p) = { "ioclk_audiocdclk1", "oscclk",
222 "mout_aud_pll_user_t",};
223 PNAME(mout_sclk_audio0_p) = { "ioclk_audiocdclk0", "oscclk",
224 "mout_aud_pll_user_t",};
225
226 PNAME(mout_sclk_hdmi_spdif_p) = { "sclk_audio1", "ioclk_spdif_extclk", };
227
228 static const struct samsung_fixed_factor_clock top_fixed_factor_clks[] __initconst = {
229 FFACTOR(0, "oscclk_efuse_common", "oscclk", 1, 1, 0),
230 };
231
232 static const struct samsung_fixed_rate_clock top_fixed_clks[] __initconst = {
233 /* Xi2s{0|1}CDCLK input clock for I2S/PCM */
234 FRATE(0, "ioclk_audiocdclk1", NULL, 0, 100000000),
235 FRATE(0, "ioclk_audiocdclk0", NULL, 0, 100000000),
236 /* Xi2s1SDI input clock for SPDIF */
237 FRATE(0, "ioclk_spdif_extclk", NULL, 0, 100000000),
238 /* XspiCLK[4:0] input clock for SPI */
239 FRATE(0, "ioclk_spi4_clk_in", NULL, 0, 50000000),
240 FRATE(0, "ioclk_spi3_clk_in", NULL, 0, 50000000),
241 FRATE(0, "ioclk_spi2_clk_in", NULL, 0, 50000000),
242 FRATE(0, "ioclk_spi1_clk_in", NULL, 0, 50000000),
243 FRATE(0, "ioclk_spi0_clk_in", NULL, 0, 50000000),
244 /* Xi2s1SCLK input clock for I2S1_BCLK */
245 FRATE(0, "ioclk_i2s1_bclk_in", NULL, 0, 12288000),
246 };
247
248 static const struct samsung_mux_clock top_mux_clks[] __initconst = {
249 /* MUX_SEL_TOP0 */
250 MUX(CLK_MOUT_AUD_PLL, "mout_aud_pll", mout_aud_pll_p, MUX_SEL_TOP0,
251 4, 1),
252 MUX(CLK_MOUT_ISP_PLL, "mout_isp_pll", mout_isp_pll_p, MUX_SEL_TOP0,
253 0, 1),
254
255 /* MUX_SEL_TOP1 */
256 MUX(CLK_MOUT_AUD_PLL_USER_T, "mout_aud_pll_user_t",
257 mout_aud_pll_user_p, MUX_SEL_TOP1, 12, 1),
258 MUX(CLK_MOUT_MPHY_PLL_USER, "mout_mphy_pll_user", mout_mphy_pll_user_p,
259 MUX_SEL_TOP1, 8, 1),
260 MUX(CLK_MOUT_MFC_PLL_USER, "mout_mfc_pll_user", mout_mfc_pll_user_p,
261 MUX_SEL_TOP1, 4, 1),
262 MUX(CLK_MOUT_BUS_PLL_USER, "mout_bus_pll_user", mout_bus_pll_user_p,
263 MUX_SEL_TOP1, 0, 1),
264
265 /* MUX_SEL_TOP2 */
266 MUX(CLK_MOUT_ACLK_HEVC_400, "mout_aclk_hevc_400",
267 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 28, 1),
268 MUX(CLK_MOUT_ACLK_CAM1_333, "mout_aclk_cam1_333",
269 mout_mfc_bus_pll_user_p, MUX_SEL_TOP2, 16, 1),
270 MUX(CLK_MOUT_ACLK_CAM1_552_B, "mout_aclk_cam1_552_b",
271 mout_aclk_cam1_552_b_p, MUX_SEL_TOP2, 12, 1),
272 MUX(CLK_MOUT_ACLK_CAM1_552_A, "mout_aclk_cam1_552_a",
273 mout_aclk_cam1_552_a_p, MUX_SEL_TOP2, 8, 1),
274 MUX(CLK_MOUT_ACLK_ISP_DIS_400, "mout_aclk_isp_dis_400",
275 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 4, 1),
276 MUX(CLK_MOUT_ACLK_ISP_400, "mout_aclk_isp_400",
277 mout_bus_mfc_pll_user_p, MUX_SEL_TOP2, 0, 1),
278
279 /* MUX_SEL_TOP3 */
280 MUX(CLK_MOUT_ACLK_BUS0_400, "mout_aclk_bus0_400",
281 mout_bus_mphy_pll_user_p, MUX_SEL_TOP3, 20, 1),
282 MUX(CLK_MOUT_ACLK_MSCL_400_B, "mout_aclk_mscl_400_b",
283 mout_aclk_mscl_b_p, MUX_SEL_TOP3, 16, 1),
284 MUX(CLK_MOUT_ACLK_MSCL_400_A, "mout_aclk_mscl_400_a",
285 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 12, 1),
286 MUX(CLK_MOUT_ACLK_GSCL_333, "mout_aclk_gscl_333",
287 mout_mfc_bus_pll_user_p, MUX_SEL_TOP3, 8, 1),
288 MUX(CLK_MOUT_ACLK_G2D_400_B, "mout_aclk_g2d_400_b",
289 mout_aclk_g2d_400_b_p, MUX_SEL_TOP3, 4, 1),
290 MUX(CLK_MOUT_ACLK_G2D_400_A, "mout_aclk_g2d_400_a",
291 mout_bus_mfc_pll_user_p, MUX_SEL_TOP3, 0, 1),
292
293 /* MUX_SEL_TOP4 */
294 MUX(CLK_MOUT_ACLK_MFC_400_C, "mout_aclk_mfc_400_c",
295 mout_aclk_mfc_400_c_p, MUX_SEL_TOP4, 8, 1),
296 MUX(CLK_MOUT_ACLK_MFC_400_B, "mout_aclk_mfc_400_b",
297 mout_aclk_mfc_400_b_p, MUX_SEL_TOP4, 4, 1),
298 MUX(CLK_MOUT_ACLK_MFC_400_A, "mout_aclk_mfc_400_a",
299 mout_aclk_mfc_400_a_p, MUX_SEL_TOP4, 0, 1),
300
301 /* MUX_SEL_TOP_MSCL */
302 MUX(CLK_MOUT_SCLK_JPEG_C, "mout_sclk_jpeg_c", mout_sclk_jpeg_c_p,
303 MUX_SEL_TOP_MSCL, 8, 1),
304 MUX(CLK_MOUT_SCLK_JPEG_B, "mout_sclk_jpeg_b", mout_sclk_jpeg_b_p,
305 MUX_SEL_TOP_MSCL, 4, 1),
306 MUX(CLK_MOUT_SCLK_JPEG_A, "mout_sclk_jpeg_a", mout_bus_pll_user_t_p,
307 MUX_SEL_TOP_MSCL, 0, 1),
308
309 /* MUX_SEL_TOP_CAM1 */
310 MUX(CLK_MOUT_SCLK_ISP_SENSOR2, "mout_sclk_isp_sensor2",
311 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 24, 1),
312 MUX(CLK_MOUT_SCLK_ISP_SENSOR1, "mout_sclk_isp_sensor1",
313 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 20, 1),
314 MUX(CLK_MOUT_SCLK_ISP_SENSOR0, "mout_sclk_isp_sensor0",
315 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 16, 1),
316 MUX(CLK_MOUT_SCLK_ISP_UART, "mout_sclk_isp_uart",
317 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 8, 1),
318 MUX(CLK_MOUT_SCLK_ISP_SPI1, "mout_sclk_isp_spi1",
319 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 4, 1),
320 MUX(CLK_MOUT_SCLK_ISP_SPI0, "mout_sclk_isp_spi0",
321 mout_bus_pll_user_t_p, MUX_SEL_TOP_CAM1, 0, 1),
322
323 /* MUX_SEL_TOP_FSYS0 */
324 MUX(CLK_MOUT_SCLK_MMC2_B, "mout_sclk_mmc2_b", mout_sclk_mmc2_b_p,
325 MUX_SEL_TOP_FSYS0, 28, 1),
326 MUX(CLK_MOUT_SCLK_MMC2_A, "mout_sclk_mmc2_a", mout_bus_pll_user_t_p,
327 MUX_SEL_TOP_FSYS0, 24, 1),
328 MUX(CLK_MOUT_SCLK_MMC1_B, "mout_sclk_mmc1_b", mout_sclk_mmc1_b_p,
329 MUX_SEL_TOP_FSYS0, 20, 1),
330 MUX(CLK_MOUT_SCLK_MMC1_A, "mout_sclk_mmc1_a", mout_bus_pll_user_t_p,
331 MUX_SEL_TOP_FSYS0, 16, 1),
332 MUX(CLK_MOUT_SCLK_MMC0_D, "mout_sclk_mmc0_d", mout_sclk_mmc0_d_p,
333 MUX_SEL_TOP_FSYS0, 12, 1),
334 MUX(CLK_MOUT_SCLK_MMC0_C, "mout_sclk_mmc0_c", mout_sclk_mmc0_c_p,
335 MUX_SEL_TOP_FSYS0, 8, 1),
336 MUX(CLK_MOUT_SCLK_MMC0_B, "mout_sclk_mmc0_b", mout_sclk_mmc0_b_p,
337 MUX_SEL_TOP_FSYS0, 4, 1),
338 MUX(CLK_MOUT_SCLK_MMC0_A, "mout_sclk_mmc0_a", mout_bus_pll_user_t_p,
339 MUX_SEL_TOP_FSYS0, 0, 1),
340
341 /* MUX_SEL_TOP_FSYS1 */
342 MUX(CLK_MOUT_SCLK_PCIE_100, "mout_sclk_pcie_100", mout_bus_pll_user_t_p,
343 MUX_SEL_TOP_FSYS1, 12, 1),
344 MUX(CLK_MOUT_SCLK_UFSUNIPRO, "mout_sclk_ufsunipro",
345 mout_mphy_pll_user_t_p, MUX_SEL_TOP_FSYS1, 8, 1),
346 MUX(CLK_MOUT_SCLK_USBHOST30, "mout_sclk_usbhost30",
347 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 4, 1),
348 MUX(CLK_MOUT_SCLK_USBDRD30, "mout_sclk_usbdrd30",
349 mout_bus_pll_user_t_p, MUX_SEL_TOP_FSYS1, 0, 1),
350
351 /* MUX_SEL_TOP_PERIC0 */
352 MUX(CLK_MOUT_SCLK_SPI4, "mout_sclk_spi4", mout_bus_pll_user_t_p,
353 MUX_SEL_TOP_PERIC0, 28, 1),
354 MUX(CLK_MOUT_SCLK_SPI3, "mout_sclk_spi3", mout_bus_pll_user_t_p,
355 MUX_SEL_TOP_PERIC0, 24, 1),
356 MUX(CLK_MOUT_SCLK_UART2, "mout_sclk_uart2", mout_bus_pll_user_t_p,
357 MUX_SEL_TOP_PERIC0, 20, 1),
358 MUX(CLK_MOUT_SCLK_UART1, "mout_sclk_uart1", mout_bus_pll_user_t_p,
359 MUX_SEL_TOP_PERIC0, 16, 1),
360 MUX(CLK_MOUT_SCLK_UART0, "mout_sclk_uart0", mout_bus_pll_user_t_p,
361 MUX_SEL_TOP_PERIC0, 12, 1),
362 MUX(CLK_MOUT_SCLK_SPI2, "mout_sclk_spi2", mout_bus_pll_user_t_p,
363 MUX_SEL_TOP_PERIC0, 8, 1),
364 MUX(CLK_MOUT_SCLK_SPI1, "mout_sclk_spi1", mout_bus_pll_user_t_p,
365 MUX_SEL_TOP_PERIC0, 4, 1),
366 MUX(CLK_MOUT_SCLK_SPI0, "mout_sclk_spi0", mout_bus_pll_user_t_p,
367 MUX_SEL_TOP_PERIC0, 0, 1),
368
369 /* MUX_SEL_TOP_PERIC1 */
370 MUX(CLK_MOUT_SCLK_SLIMBUS, "mout_sclk_slimbus", mout_aud_pll_user_p,
371 MUX_SEL_TOP_PERIC1, 16, 1),
372 MUX(CLK_MOUT_SCLK_SPDIF, "mout_sclk_spdif", mout_sclk_spdif_p,
373 MUX_SEL_TOP_PERIC1, 12, 2),
374 MUX(CLK_MOUT_SCLK_AUDIO1, "mout_sclk_audio1", mout_sclk_audio1_p,
375 MUX_SEL_TOP_PERIC1, 4, 2),
376 MUX(CLK_MOUT_SCLK_AUDIO0, "mout_sclk_audio0", mout_sclk_audio0_p,
377 MUX_SEL_TOP_PERIC1, 0, 2),
378
379 /* MUX_SEL_TOP_DISP */
380 MUX(CLK_MOUT_SCLK_HDMI_SPDIF, "mout_sclk_hdmi_spdif",
381 mout_sclk_hdmi_spdif_p, MUX_SEL_TOP_DISP, 0, 1),
382 };
383
384 static const struct samsung_div_clock top_div_clks[] __initconst = {
385 /* DIV_TOP0 */
386 DIV(CLK_DIV_ACLK_CAM1_333, "div_aclk_cam1_333", "mout_aclk_cam1_333",
387 DIV_TOP0, 28, 3),
388 DIV(CLK_DIV_ACLK_CAM1_400, "div_aclk_cam1_400", "mout_bus_pll_user",
389 DIV_TOP0, 24, 3),
390 DIV(CLK_DIV_ACLK_CAM1_552, "div_aclk_cam1_552", "mout_aclk_cam1_552_b",
391 DIV_TOP0, 20, 3),
392 DIV(CLK_DIV_ACLK_CAM0_333, "div_aclk_cam0_333", "mout_mfc_pll_user",
393 DIV_TOP0, 16, 3),
394 DIV(CLK_DIV_ACLK_CAM0_400, "div_aclk_cam0_400", "mout_bus_pll_user",
395 DIV_TOP0, 12, 3),
396 DIV(CLK_DIV_ACLK_CAM0_552, "div_aclk_cam0_552", "mout_isp_pll",
397 DIV_TOP0, 8, 3),
398 DIV(CLK_DIV_ACLK_ISP_DIS_400, "div_aclk_isp_dis_400",
399 "mout_aclk_isp_dis_400", DIV_TOP0, 4, 4),
400 DIV(CLK_DIV_ACLK_ISP_400, "div_aclk_isp_400",
401 "mout_aclk_isp_400", DIV_TOP0, 0, 4),
402
403 /* DIV_TOP1 */
404 DIV(CLK_DIV_ACLK_GSCL_111, "div_aclk_gscl_111", "mout_aclk_gscl_333",
405 DIV_TOP1, 28, 3),
406 DIV(CLK_DIV_ACLK_GSCL_333, "div_aclk_gscl_333", "mout_aclk_gscl_333",
407 DIV_TOP1, 24, 3),
408 DIV(CLK_DIV_ACLK_HEVC_400, "div_aclk_hevc_400", "mout_aclk_hevc_400",
409 DIV_TOP1, 20, 3),
410 DIV(CLK_DIV_ACLK_MFC_400, "div_aclk_mfc_400", "mout_aclk_mfc_400_c",
411 DIV_TOP1, 12, 3),
412 DIV(CLK_DIV_ACLK_G2D_266, "div_aclk_g2d_266", "mout_bus_pll_user",
413 DIV_TOP1, 8, 3),
414 DIV(CLK_DIV_ACLK_G2D_400, "div_aclk_g2d_400", "mout_aclk_g2d_400_b",
415 DIV_TOP1, 0, 3),
416
417 /* DIV_TOP2 */
418 DIV(CLK_DIV_ACLK_MSCL_400, "div_aclk_mscl_400", "mout_aclk_mscl_400_b",
419 DIV_TOP2, 4, 3),
420 DIV(CLK_DIV_ACLK_FSYS_200, "div_aclk_fsys_200", "mout_bus_pll_user",
421 DIV_TOP2, 0, 3),
422
423 /* DIV_TOP3 */
424 DIV(CLK_DIV_ACLK_IMEM_SSSX_266, "div_aclk_imem_sssx_266",
425 "mout_bus_pll_user", DIV_TOP3, 24, 3),
426 DIV(CLK_DIV_ACLK_IMEM_200, "div_aclk_imem_200",
427 "mout_bus_pll_user", DIV_TOP3, 20, 3),
428 DIV(CLK_DIV_ACLK_IMEM_266, "div_aclk_imem_266",
429 "mout_bus_pll_user", DIV_TOP3, 16, 3),
430 DIV(CLK_DIV_ACLK_PERIC_66_B, "div_aclk_peric_66_b",
431 "div_aclk_peric_66_a", DIV_TOP3, 12, 3),
432 DIV(CLK_DIV_ACLK_PERIC_66_A, "div_aclk_peric_66_a",
433 "mout_bus_pll_user", DIV_TOP3, 8, 3),
434 DIV(CLK_DIV_ACLK_PERIS_66_B, "div_aclk_peris_66_b",
435 "div_aclk_peris_66_a", DIV_TOP3, 4, 3),
436 DIV(CLK_DIV_ACLK_PERIS_66_A, "div_aclk_peris_66_a",
437 "mout_bus_pll_user", DIV_TOP3, 0, 3),
438
439 /* DIV_TOP4 */
440 DIV(CLK_DIV_ACLK_G3D_400, "div_aclk_g3d_400", "mout_bus_pll_user",
441 DIV_TOP4, 8, 3),
442 DIV(CLK_DIV_ACLK_BUS0_400, "div_aclk_bus0_400", "mout_aclk_bus0_400",
443 DIV_TOP4, 4, 3),
444 DIV(CLK_DIV_ACLK_BUS1_400, "div_aclk_bus1_400", "mout_bus_pll_user",
445 DIV_TOP4, 0, 3),
446
447 /* DIV_TOP_MSCL */
448 DIV(CLK_DIV_SCLK_JPEG, "div_sclk_jpeg", "mout_sclk_jpeg_c",
449 DIV_TOP_MSCL, 0, 4),
450
451 /* DIV_TOP_CAM10 */
452 DIV(CLK_DIV_SCLK_ISP_UART, "div_sclk_isp_uart", "mout_sclk_isp_uart",
453 DIV_TOP_CAM10, 24, 5),
454 DIV(CLK_DIV_SCLK_ISP_SPI1_B, "div_sclk_isp_spi1_b",
455 "div_sclk_isp_spi1_a", DIV_TOP_CAM10, 16, 8),
456 DIV(CLK_DIV_SCLK_ISP_SPI1_A, "div_sclk_isp_spi1_a",
457 "mout_sclk_isp_spi1", DIV_TOP_CAM10, 12, 4),
458 DIV(CLK_DIV_SCLK_ISP_SPI0_B, "div_sclk_isp_spi0_b",
459 "div_sclk_isp_spi0_a", DIV_TOP_CAM10, 4, 8),
460 DIV(CLK_DIV_SCLK_ISP_SPI0_A, "div_sclk_isp_spi0_a",
461 "mout_sclk_isp_spi0", DIV_TOP_CAM10, 0, 4),
462
463 /* DIV_TOP_CAM11 */
464 DIV(CLK_DIV_SCLK_ISP_SENSOR2_B, "div_sclk_isp_sensor2_b",
465 "div_sclk_isp_sensor2_a", DIV_TOP_CAM11, 20, 4),
466 DIV(CLK_DIV_SCLK_ISP_SENSOR2_A, "div_sclk_isp_sensor2_a",
467 "mout_sclk_isp_sensor2", DIV_TOP_CAM11, 16, 4),
468 DIV(CLK_DIV_SCLK_ISP_SENSOR1_B, "div_sclk_isp_sensor1_b",
469 "div_sclk_isp_sensor1_a", DIV_TOP_CAM11, 12, 4),
470 DIV(CLK_DIV_SCLK_ISP_SENSOR1_A, "div_sclk_isp_sensor1_a",
471 "mout_sclk_isp_sensor1", DIV_TOP_CAM11, 8, 4),
472 DIV(CLK_DIV_SCLK_ISP_SENSOR0_B, "div_sclk_isp_sensor0_b",
473 "div_sclk_isp_sensor0_a", DIV_TOP_CAM11, 4, 4),
474 DIV(CLK_DIV_SCLK_ISP_SENSOR0_A, "div_sclk_isp_sensor0_a",
475 "mout_sclk_isp_sensor0", DIV_TOP_CAM11, 0, 4),
476
477 /* DIV_TOP_FSYS0 */
478 DIV(CLK_DIV_SCLK_MMC1_B, "div_sclk_mmc1_b", "div_sclk_mmc1_a",
479 DIV_TOP_FSYS0, 16, 8),
480 DIV(CLK_DIV_SCLK_MMC1_A, "div_sclk_mmc1_a", "mout_sclk_mmc1_b",
481 DIV_TOP_FSYS0, 12, 4),
482 DIV_F(CLK_DIV_SCLK_MMC0_B, "div_sclk_mmc0_b", "div_sclk_mmc0_a",
483 DIV_TOP_FSYS0, 4, 8, CLK_SET_RATE_PARENT, 0),
484 DIV_F(CLK_DIV_SCLK_MMC0_A, "div_sclk_mmc0_a", "mout_sclk_mmc0_d",
485 DIV_TOP_FSYS0, 0, 4, CLK_SET_RATE_PARENT, 0),
486
487 /* DIV_TOP_FSYS1 */
488 DIV(CLK_DIV_SCLK_MMC2_B, "div_sclk_mmc2_b", "div_sclk_mmc2_a",
489 DIV_TOP_FSYS1, 4, 8),
490 DIV(CLK_DIV_SCLK_MMC2_A, "div_sclk_mmc2_a", "mout_sclk_mmc2_b",
491 DIV_TOP_FSYS1, 0, 4),
492
493 /* DIV_TOP_FSYS2 */
494 DIV(CLK_DIV_SCLK_PCIE_100, "div_sclk_pcie_100", "mout_sclk_pcie_100",
495 DIV_TOP_FSYS2, 12, 3),
496 DIV(CLK_DIV_SCLK_USBHOST30, "div_sclk_usbhost30",
497 "mout_sclk_usbhost30", DIV_TOP_FSYS2, 8, 4),
498 DIV(CLK_DIV_SCLK_UFSUNIPRO, "div_sclk_ufsunipro",
499 "mout_sclk_ufsunipro", DIV_TOP_FSYS2, 4, 4),
500 DIV(CLK_DIV_SCLK_USBDRD30, "div_sclk_usbdrd30", "mout_sclk_usbdrd30",
501 DIV_TOP_FSYS2, 0, 4),
502
503 /* DIV_TOP_PERIC0 */
504 DIV(CLK_DIV_SCLK_SPI1_B, "div_sclk_spi1_b", "div_sclk_spi1_a",
505 DIV_TOP_PERIC0, 16, 8),
506 DIV(CLK_DIV_SCLK_SPI1_A, "div_sclk_spi1_a", "mout_sclk_spi1",
507 DIV_TOP_PERIC0, 12, 4),
508 DIV(CLK_DIV_SCLK_SPI0_B, "div_sclk_spi0_b", "div_sclk_spi0_a",
509 DIV_TOP_PERIC0, 4, 8),
510 DIV(CLK_DIV_SCLK_SPI0_A, "div_sclk_spi0_a", "mout_sclk_spi0",
511 DIV_TOP_PERIC0, 0, 4),
512
513 /* DIV_TOP_PERIC1 */
514 DIV(CLK_DIV_SCLK_SPI2_B, "div_sclk_spi2_b", "div_sclk_spi2_a",
515 DIV_TOP_PERIC1, 4, 8),
516 DIV(CLK_DIV_SCLK_SPI2_A, "div_sclk_spi2_a", "mout_sclk_spi2",
517 DIV_TOP_PERIC1, 0, 4),
518
519 /* DIV_TOP_PERIC2 */
520 DIV(CLK_DIV_SCLK_UART2, "div_sclk_uart2", "mout_sclk_uart2",
521 DIV_TOP_PERIC2, 8, 4),
522 DIV(CLK_DIV_SCLK_UART1, "div_sclk_uart1", "mout_sclk_uart0",
523 DIV_TOP_PERIC2, 4, 4),
524 DIV(CLK_DIV_SCLK_UART0, "div_sclk_uart0", "mout_sclk_uart1",
525 DIV_TOP_PERIC2, 0, 4),
526
527 /* DIV_TOP_PERIC3 */
528 DIV(CLK_DIV_SCLK_I2S1, "div_sclk_i2s1", "sclk_audio1",
529 DIV_TOP_PERIC3, 16, 6),
530 DIV(CLK_DIV_SCLK_PCM1, "div_sclk_pcm1", "sclk_audio1",
531 DIV_TOP_PERIC3, 8, 8),
532 DIV(CLK_DIV_SCLK_AUDIO1, "div_sclk_audio1", "mout_sclk_audio1",
533 DIV_TOP_PERIC3, 4, 4),
534 DIV(CLK_DIV_SCLK_AUDIO0, "div_sclk_audio0", "mout_sclk_audio0",
535 DIV_TOP_PERIC3, 0, 4),
536
537 /* DIV_TOP_PERIC4 */
538 DIV(CLK_DIV_SCLK_SPI4_B, "div_sclk_spi4_b", "div_sclk_spi4_a",
539 DIV_TOP_PERIC4, 16, 8),
540 DIV(CLK_DIV_SCLK_SPI4_A, "div_sclk_spi4_a", "mout_sclk_spi4",
541 DIV_TOP_PERIC4, 12, 4),
542 DIV(CLK_DIV_SCLK_SPI3_B, "div_sclk_spi3_b", "div_sclk_spi3_a",
543 DIV_TOP_PERIC4, 4, 8),
544 DIV(CLK_DIV_SCLK_SPI3_A, "div_sclk_spi3_a", "mout_sclk_spi3",
545 DIV_TOP_PERIC4, 0, 4),
546 };
547
548 static const struct samsung_gate_clock top_gate_clks[] __initconst = {
549 /* ENABLE_ACLK_TOP */
550 GATE(CLK_ACLK_G3D_400, "aclk_g3d_400", "div_aclk_g3d_400",
551 ENABLE_ACLK_TOP, 30, CLK_IS_CRITICAL, 0),
552 GATE(CLK_ACLK_IMEM_SSX_266, "aclk_imem_ssx_266",
553 "div_aclk_imem_sssx_266", ENABLE_ACLK_TOP,
554 29, CLK_IGNORE_UNUSED, 0),
555 GATE(CLK_ACLK_BUS0_400, "aclk_bus0_400", "div_aclk_bus0_400",
556 ENABLE_ACLK_TOP, 26,
557 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
558 GATE(CLK_ACLK_BUS1_400, "aclk_bus1_400", "div_aclk_bus1_400",
559 ENABLE_ACLK_TOP, 25,
560 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
561 GATE(CLK_ACLK_IMEM_200, "aclk_imem_200", "div_aclk_imem_266",
562 ENABLE_ACLK_TOP, 24,
563 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
564 GATE(CLK_ACLK_IMEM_266, "aclk_imem_266", "div_aclk_imem_200",
565 ENABLE_ACLK_TOP, 23,
566 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
567 GATE(CLK_ACLK_PERIC_66, "aclk_peric_66", "div_aclk_peric_66_b",
568 ENABLE_ACLK_TOP, 22,
569 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
570 GATE(CLK_ACLK_PERIS_66, "aclk_peris_66", "div_aclk_peris_66_b",
571 ENABLE_ACLK_TOP, 21,
572 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
573 GATE(CLK_ACLK_MSCL_400, "aclk_mscl_400", "div_aclk_mscl_400",
574 ENABLE_ACLK_TOP, 19,
575 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
576 GATE(CLK_ACLK_FSYS_200, "aclk_fsys_200", "div_aclk_fsys_200",
577 ENABLE_ACLK_TOP, 18,
578 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
579 GATE(CLK_ACLK_GSCL_111, "aclk_gscl_111", "div_aclk_gscl_111",
580 ENABLE_ACLK_TOP, 15,
581 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
582 GATE(CLK_ACLK_GSCL_333, "aclk_gscl_333", "div_aclk_gscl_333",
583 ENABLE_ACLK_TOP, 14,
584 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
585 GATE(CLK_ACLK_CAM1_333, "aclk_cam1_333", "div_aclk_cam1_333",
586 ENABLE_ACLK_TOP, 13,
587 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
588 GATE(CLK_ACLK_CAM1_400, "aclk_cam1_400", "div_aclk_cam1_400",
589 ENABLE_ACLK_TOP, 12,
590 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
591 GATE(CLK_ACLK_CAM1_552, "aclk_cam1_552", "div_aclk_cam1_552",
592 ENABLE_ACLK_TOP, 11,
593 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
594 GATE(CLK_ACLK_CAM0_333, "aclk_cam0_333", "div_aclk_cam0_333",
595 ENABLE_ACLK_TOP, 10,
596 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
597 GATE(CLK_ACLK_CAM0_400, "aclk_cam0_400", "div_aclk_cam0_400",
598 ENABLE_ACLK_TOP, 9,
599 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
600 GATE(CLK_ACLK_CAM0_552, "aclk_cam0_552", "div_aclk_cam0_552",
601 ENABLE_ACLK_TOP, 8,
602 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
603 GATE(CLK_ACLK_ISP_DIS_400, "aclk_isp_dis_400", "div_aclk_isp_dis_400",
604 ENABLE_ACLK_TOP, 7,
605 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
606 GATE(CLK_ACLK_ISP_400, "aclk_isp_400", "div_aclk_isp_400",
607 ENABLE_ACLK_TOP, 6,
608 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
609 GATE(CLK_ACLK_HEVC_400, "aclk_hevc_400", "div_aclk_hevc_400",
610 ENABLE_ACLK_TOP, 5,
611 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
612 GATE(CLK_ACLK_MFC_400, "aclk_mfc_400", "div_aclk_mfc_400",
613 ENABLE_ACLK_TOP, 3,
614 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
615 GATE(CLK_ACLK_G2D_266, "aclk_g2d_266", "div_aclk_g2d_266",
616 ENABLE_ACLK_TOP, 2,
617 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
618 GATE(CLK_ACLK_G2D_400, "aclk_g2d_400", "div_aclk_g2d_400",
619 ENABLE_ACLK_TOP, 0,
620 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0),
621
622 /* ENABLE_SCLK_TOP_MSCL */
623 GATE(CLK_SCLK_JPEG_MSCL, "sclk_jpeg_mscl", "div_sclk_jpeg",
624 ENABLE_SCLK_TOP_MSCL, 0, CLK_SET_RATE_PARENT, 0),
625
626 /* ENABLE_SCLK_TOP_CAM1 */
627 GATE(CLK_SCLK_ISP_SENSOR2, "sclk_isp_sensor2", "div_sclk_isp_sensor2_b",
628 ENABLE_SCLK_TOP_CAM1, 7, 0, 0),
629 GATE(CLK_SCLK_ISP_SENSOR1, "sclk_isp_sensor1", "div_sclk_isp_sensor1_b",
630 ENABLE_SCLK_TOP_CAM1, 6, 0, 0),
631 GATE(CLK_SCLK_ISP_SENSOR0, "sclk_isp_sensor0", "div_sclk_isp_sensor0_b",
632 ENABLE_SCLK_TOP_CAM1, 5, 0, 0),
633 GATE(CLK_SCLK_ISP_MCTADC_CAM1, "sclk_isp_mctadc_cam1", "oscclk",
634 ENABLE_SCLK_TOP_CAM1, 4, 0, 0),
635 GATE(CLK_SCLK_ISP_UART_CAM1, "sclk_isp_uart_cam1", "div_sclk_isp_uart",
636 ENABLE_SCLK_TOP_CAM1, 2, 0, 0),
637 GATE(CLK_SCLK_ISP_SPI1_CAM1, "sclk_isp_spi1_cam1", "div_sclk_isp_spi1_b",
638 ENABLE_SCLK_TOP_CAM1, 1, 0, 0),
639 GATE(CLK_SCLK_ISP_SPI0_CAM1, "sclk_isp_spi0_cam1", "div_sclk_isp_spi0_b",
640 ENABLE_SCLK_TOP_CAM1, 0, 0, 0),
641
642 /* ENABLE_SCLK_TOP_DISP */
643 GATE(CLK_SCLK_HDMI_SPDIF_DISP, "sclk_hdmi_spdif_disp",
644 "mout_sclk_hdmi_spdif", ENABLE_SCLK_TOP_DISP, 0,
645 CLK_IGNORE_UNUSED, 0),
646
647 /* ENABLE_SCLK_TOP_FSYS */
648 GATE(CLK_SCLK_PCIE_100_FSYS, "sclk_pcie_100_fsys", "div_sclk_pcie_100",
649 ENABLE_SCLK_TOP_FSYS, 7, CLK_IGNORE_UNUSED, 0),
650 GATE(CLK_SCLK_MMC2_FSYS, "sclk_mmc2_fsys", "div_sclk_mmc2_b",
651 ENABLE_SCLK_TOP_FSYS, 6, CLK_SET_RATE_PARENT, 0),
652 GATE(CLK_SCLK_MMC1_FSYS, "sclk_mmc1_fsys", "div_sclk_mmc1_b",
653 ENABLE_SCLK_TOP_FSYS, 5, CLK_SET_RATE_PARENT, 0),
654 GATE(CLK_SCLK_MMC0_FSYS, "sclk_mmc0_fsys", "div_sclk_mmc0_b",
655 ENABLE_SCLK_TOP_FSYS, 4, CLK_SET_RATE_PARENT, 0),
656 GATE(CLK_SCLK_UFSUNIPRO_FSYS, "sclk_ufsunipro_fsys",
657 "div_sclk_ufsunipro", ENABLE_SCLK_TOP_FSYS,
658 3, CLK_SET_RATE_PARENT, 0),
659 GATE(CLK_SCLK_USBHOST30_FSYS, "sclk_usbhost30_fsys",
660 "div_sclk_usbhost30", ENABLE_SCLK_TOP_FSYS,
661 1, CLK_SET_RATE_PARENT, 0),
662 GATE(CLK_SCLK_USBDRD30_FSYS, "sclk_usbdrd30_fsys",
663 "div_sclk_usbdrd30", ENABLE_SCLK_TOP_FSYS,
664 0, CLK_SET_RATE_PARENT, 0),
665
666 /* ENABLE_SCLK_TOP_PERIC */
667 GATE(CLK_SCLK_SPI4_PERIC, "sclk_spi4_peric", "div_sclk_spi4_b",
668 ENABLE_SCLK_TOP_PERIC, 12, CLK_SET_RATE_PARENT, 0),
669 GATE(CLK_SCLK_SPI3_PERIC, "sclk_spi3_peric", "div_sclk_spi3_b",
670 ENABLE_SCLK_TOP_PERIC, 11, CLK_SET_RATE_PARENT, 0),
671 GATE(CLK_SCLK_SPDIF_PERIC, "sclk_spdif_peric", "mout_sclk_spdif",
672 ENABLE_SCLK_TOP_PERIC, 9, CLK_SET_RATE_PARENT, 0),
673 GATE(CLK_SCLK_I2S1_PERIC, "sclk_i2s1_peric", "div_sclk_i2s1",
674 ENABLE_SCLK_TOP_PERIC, 8, CLK_SET_RATE_PARENT, 0),
675 GATE(CLK_SCLK_PCM1_PERIC, "sclk_pcm1_peric", "div_sclk_pcm1",
676 ENABLE_SCLK_TOP_PERIC, 7, CLK_SET_RATE_PARENT, 0),
677 GATE(CLK_SCLK_UART2_PERIC, "sclk_uart2_peric", "div_sclk_uart2",
678 ENABLE_SCLK_TOP_PERIC, 5, CLK_SET_RATE_PARENT |
679 CLK_IGNORE_UNUSED, 0),
680 GATE(CLK_SCLK_UART1_PERIC, "sclk_uart1_peric", "div_sclk_uart1",
681 ENABLE_SCLK_TOP_PERIC, 4, CLK_SET_RATE_PARENT |
682 CLK_IGNORE_UNUSED, 0),
683 GATE(CLK_SCLK_UART0_PERIC, "sclk_uart0_peric", "div_sclk_uart0",
684 ENABLE_SCLK_TOP_PERIC, 3, CLK_SET_RATE_PARENT |
685 CLK_IGNORE_UNUSED, 0),
686 GATE(CLK_SCLK_SPI2_PERIC, "sclk_spi2_peric", "div_sclk_spi2_b",
687 ENABLE_SCLK_TOP_PERIC, 2, CLK_SET_RATE_PARENT, 0),
688 GATE(CLK_SCLK_SPI1_PERIC, "sclk_spi1_peric", "div_sclk_spi1_b",
689 ENABLE_SCLK_TOP_PERIC, 1, CLK_SET_RATE_PARENT, 0),
690 GATE(CLK_SCLK_SPI0_PERIC, "sclk_spi0_peric", "div_sclk_spi0_b",
691 ENABLE_SCLK_TOP_PERIC, 0, CLK_SET_RATE_PARENT, 0),
692
693 /* MUX_ENABLE_TOP_PERIC1 */
694 GATE(CLK_SCLK_SLIMBUS, "sclk_slimbus", "mout_sclk_slimbus",
695 MUX_ENABLE_TOP_PERIC1, 16, 0, 0),
696 GATE(CLK_SCLK_AUDIO1, "sclk_audio1", "div_sclk_audio1",
697 MUX_ENABLE_TOP_PERIC1, 4, 0, 0),
698 GATE(CLK_SCLK_AUDIO0, "sclk_audio0", "div_sclk_audio0",
699 MUX_ENABLE_TOP_PERIC1, 0, 0, 0),
700 };
701
702 /*
703 * ATLAS_PLL & APOLLO_PLL & MEM0_PLL & MEM1_PLL & BUS_PLL & MFC_PLL
704 * & MPHY_PLL & G3D_PLL & DISP_PLL & ISP_PLL
705 */
706 static const struct samsung_pll_rate_table exynos5433_pll_rates[] __initconst = {
707 PLL_35XX_RATE(24 * MHZ, 2500000000U, 625, 6, 0),
708 PLL_35XX_RATE(24 * MHZ, 2400000000U, 500, 5, 0),
709 PLL_35XX_RATE(24 * MHZ, 2300000000U, 575, 6, 0),
710 PLL_35XX_RATE(24 * MHZ, 2200000000U, 550, 6, 0),
711 PLL_35XX_RATE(24 * MHZ, 2100000000U, 350, 4, 0),
712 PLL_35XX_RATE(24 * MHZ, 2000000000U, 500, 6, 0),
713 PLL_35XX_RATE(24 * MHZ, 1900000000U, 475, 6, 0),
714 PLL_35XX_RATE(24 * MHZ, 1800000000U, 375, 5, 0),
715 PLL_35XX_RATE(24 * MHZ, 1700000000U, 425, 6, 0),
716 PLL_35XX_RATE(24 * MHZ, 1600000000U, 400, 6, 0),
717 PLL_35XX_RATE(24 * MHZ, 1500000000U, 250, 4, 0),
718 PLL_35XX_RATE(24 * MHZ, 1400000000U, 350, 6, 0),
719 PLL_35XX_RATE(24 * MHZ, 1332000000U, 222, 4, 0),
720 PLL_35XX_RATE(24 * MHZ, 1300000000U, 325, 6, 0),
721 PLL_35XX_RATE(24 * MHZ, 1200000000U, 500, 5, 1),
722 PLL_35XX_RATE(24 * MHZ, 1100000000U, 550, 6, 1),
723 PLL_35XX_RATE(24 * MHZ, 1086000000U, 362, 4, 1),
724 PLL_35XX_RATE(24 * MHZ, 1066000000U, 533, 6, 1),
725 PLL_35XX_RATE(24 * MHZ, 1000000000U, 500, 6, 1),
726 PLL_35XX_RATE(24 * MHZ, 933000000U, 311, 4, 1),
727 PLL_35XX_RATE(24 * MHZ, 921000000U, 307, 4, 1),
728 PLL_35XX_RATE(24 * MHZ, 900000000U, 375, 5, 1),
729 PLL_35XX_RATE(24 * MHZ, 825000000U, 275, 4, 1),
730 PLL_35XX_RATE(24 * MHZ, 800000000U, 400, 6, 1),
731 PLL_35XX_RATE(24 * MHZ, 733000000U, 733, 12, 1),
732 PLL_35XX_RATE(24 * MHZ, 700000000U, 175, 3, 1),
733 PLL_35XX_RATE(24 * MHZ, 666000000U, 222, 4, 1),
734 PLL_35XX_RATE(24 * MHZ, 633000000U, 211, 4, 1),
735 PLL_35XX_RATE(24 * MHZ, 600000000U, 500, 5, 2),
736 PLL_35XX_RATE(24 * MHZ, 552000000U, 460, 5, 2),
737 PLL_35XX_RATE(24 * MHZ, 550000000U, 550, 6, 2),
738 PLL_35XX_RATE(24 * MHZ, 543000000U, 362, 4, 2),
739 PLL_35XX_RATE(24 * MHZ, 533000000U, 533, 6, 2),
740 PLL_35XX_RATE(24 * MHZ, 500000000U, 500, 6, 2),
741 PLL_35XX_RATE(24 * MHZ, 444000000U, 370, 5, 2),
742 PLL_35XX_RATE(24 * MHZ, 420000000U, 350, 5, 2),
743 PLL_35XX_RATE(24 * MHZ, 400000000U, 400, 6, 2),
744 PLL_35XX_RATE(24 * MHZ, 350000000U, 350, 6, 2),
745 PLL_35XX_RATE(24 * MHZ, 333000000U, 222, 4, 2),
746 PLL_35XX_RATE(24 * MHZ, 300000000U, 500, 5, 3),
747 PLL_35XX_RATE(24 * MHZ, 278000000U, 556, 6, 3),
748 PLL_35XX_RATE(24 * MHZ, 266000000U, 532, 6, 3),
749 PLL_35XX_RATE(24 * MHZ, 250000000U, 500, 6, 3),
750 PLL_35XX_RATE(24 * MHZ, 200000000U, 400, 6, 3),
751 PLL_35XX_RATE(24 * MHZ, 166000000U, 332, 6, 3),
752 PLL_35XX_RATE(24 * MHZ, 160000000U, 320, 6, 3),
753 PLL_35XX_RATE(24 * MHZ, 133000000U, 532, 6, 4),
754 PLL_35XX_RATE(24 * MHZ, 100000000U, 400, 6, 4),
755 { /* sentinel */ }
756 };
757
758 /* AUD_PLL */
759 static const struct samsung_pll_rate_table exynos5433_aud_pll_rates[] __initconst = {
760 PLL_36XX_RATE(24 * MHZ, 400000000U, 200, 3, 2, 0),
761 PLL_36XX_RATE(24 * MHZ, 393216003U, 197, 3, 2, -25690),
762 PLL_36XX_RATE(24 * MHZ, 384000000U, 128, 2, 2, 0),
763 PLL_36XX_RATE(24 * MHZ, 368639991U, 246, 4, 2, -15729),
764 PLL_36XX_RATE(24 * MHZ, 361507202U, 181, 3, 2, -16148),
765 PLL_36XX_RATE(24 * MHZ, 338687988U, 113, 2, 2, -6816),
766 PLL_36XX_RATE(24 * MHZ, 294912002U, 98, 1, 3, 19923),
767 PLL_36XX_RATE(24 * MHZ, 288000000U, 96, 1, 3, 0),
768 PLL_36XX_RATE(24 * MHZ, 252000000U, 84, 1, 3, 0),
769 PLL_36XX_RATE(24 * MHZ, 196608001U, 197, 3, 3, -25690),
770 { /* sentinel */ }
771 };
772
773 static const struct samsung_pll_clock top_pll_clks[] __initconst = {
774 PLL(pll_35xx, CLK_FOUT_ISP_PLL, "fout_isp_pll", "oscclk",
775 ISP_PLL_LOCK, ISP_PLL_CON0, exynos5433_pll_rates),
776 PLL(pll_36xx, CLK_FOUT_AUD_PLL, "fout_aud_pll", "oscclk",
777 AUD_PLL_LOCK, AUD_PLL_CON0, exynos5433_aud_pll_rates),
778 };
779
780 static const struct samsung_cmu_info top_cmu_info __initconst = {
781 .pll_clks = top_pll_clks,
782 .nr_pll_clks = ARRAY_SIZE(top_pll_clks),
783 .mux_clks = top_mux_clks,
784 .nr_mux_clks = ARRAY_SIZE(top_mux_clks),
785 .div_clks = top_div_clks,
786 .nr_div_clks = ARRAY_SIZE(top_div_clks),
787 .gate_clks = top_gate_clks,
788 .nr_gate_clks = ARRAY_SIZE(top_gate_clks),
789 .fixed_clks = top_fixed_clks,
790 .nr_fixed_clks = ARRAY_SIZE(top_fixed_clks),
791 .fixed_factor_clks = top_fixed_factor_clks,
792 .nr_fixed_factor_clks = ARRAY_SIZE(top_fixed_factor_clks),
793 .nr_clk_ids = TOP_NR_CLK,
794 .clk_regs = top_clk_regs,
795 .nr_clk_regs = ARRAY_SIZE(top_clk_regs),
796 };
797
exynos5433_cmu_top_init(struct device_node * np)798 static void __init exynos5433_cmu_top_init(struct device_node *np)
799 {
800 samsung_cmu_register_one(np, &top_cmu_info);
801 }
802 CLK_OF_DECLARE(exynos5433_cmu_top, "samsung,exynos5433-cmu-top",
803 exynos5433_cmu_top_init);
804
805 /*
806 * Register offset definitions for CMU_CPIF
807 */
808 #define MPHY_PLL_LOCK 0x0000
809 #define MPHY_PLL_CON0 0x0100
810 #define MPHY_PLL_CON1 0x0104
811 #define MPHY_PLL_FREQ_DET 0x010c
812 #define MUX_SEL_CPIF0 0x0200
813 #define DIV_CPIF 0x0600
814 #define ENABLE_SCLK_CPIF 0x0a00
815
816 static const unsigned long cpif_clk_regs[] __initconst = {
817 MPHY_PLL_LOCK,
818 MPHY_PLL_CON0,
819 MPHY_PLL_CON1,
820 MPHY_PLL_FREQ_DET,
821 MUX_SEL_CPIF0,
822 DIV_CPIF,
823 ENABLE_SCLK_CPIF,
824 };
825
826 /* list of all parent clock list */
827 PNAME(mout_mphy_pll_p) = { "oscclk", "fout_mphy_pll", };
828
829 static const struct samsung_pll_clock cpif_pll_clks[] __initconst = {
830 PLL(pll_35xx, CLK_FOUT_MPHY_PLL, "fout_mphy_pll", "oscclk",
831 MPHY_PLL_LOCK, MPHY_PLL_CON0, exynos5433_pll_rates),
832 };
833
834 static const struct samsung_mux_clock cpif_mux_clks[] __initconst = {
835 /* MUX_SEL_CPIF0 */
836 MUX(CLK_MOUT_MPHY_PLL, "mout_mphy_pll", mout_mphy_pll_p, MUX_SEL_CPIF0,
837 0, 1),
838 };
839
840 static const struct samsung_div_clock cpif_div_clks[] __initconst = {
841 /* DIV_CPIF */
842 DIV(CLK_DIV_SCLK_MPHY, "div_sclk_mphy", "mout_mphy_pll", DIV_CPIF,
843 0, 6),
844 };
845
846 static const struct samsung_gate_clock cpif_gate_clks[] __initconst = {
847 /* ENABLE_SCLK_CPIF */
848 GATE(CLK_SCLK_MPHY_PLL, "sclk_mphy_pll", "mout_mphy_pll",
849 ENABLE_SCLK_CPIF, 9, CLK_IGNORE_UNUSED, 0),
850 GATE(CLK_SCLK_UFS_MPHY, "sclk_ufs_mphy", "div_sclk_mphy",
851 ENABLE_SCLK_CPIF, 4, 0, 0),
852 };
853
854 static const struct samsung_cmu_info cpif_cmu_info __initconst = {
855 .pll_clks = cpif_pll_clks,
856 .nr_pll_clks = ARRAY_SIZE(cpif_pll_clks),
857 .mux_clks = cpif_mux_clks,
858 .nr_mux_clks = ARRAY_SIZE(cpif_mux_clks),
859 .div_clks = cpif_div_clks,
860 .nr_div_clks = ARRAY_SIZE(cpif_div_clks),
861 .gate_clks = cpif_gate_clks,
862 .nr_gate_clks = ARRAY_SIZE(cpif_gate_clks),
863 .nr_clk_ids = CPIF_NR_CLK,
864 .clk_regs = cpif_clk_regs,
865 .nr_clk_regs = ARRAY_SIZE(cpif_clk_regs),
866 };
867
exynos5433_cmu_cpif_init(struct device_node * np)868 static void __init exynos5433_cmu_cpif_init(struct device_node *np)
869 {
870 samsung_cmu_register_one(np, &cpif_cmu_info);
871 }
872 CLK_OF_DECLARE(exynos5433_cmu_cpif, "samsung,exynos5433-cmu-cpif",
873 exynos5433_cmu_cpif_init);
874
875 /*
876 * Register offset definitions for CMU_MIF
877 */
878 #define MEM0_PLL_LOCK 0x0000
879 #define MEM1_PLL_LOCK 0x0004
880 #define BUS_PLL_LOCK 0x0008
881 #define MFC_PLL_LOCK 0x000c
882 #define MEM0_PLL_CON0 0x0100
883 #define MEM0_PLL_CON1 0x0104
884 #define MEM0_PLL_FREQ_DET 0x010c
885 #define MEM1_PLL_CON0 0x0110
886 #define MEM1_PLL_CON1 0x0114
887 #define MEM1_PLL_FREQ_DET 0x011c
888 #define BUS_PLL_CON0 0x0120
889 #define BUS_PLL_CON1 0x0124
890 #define BUS_PLL_FREQ_DET 0x012c
891 #define MFC_PLL_CON0 0x0130
892 #define MFC_PLL_CON1 0x0134
893 #define MFC_PLL_FREQ_DET 0x013c
894 #define MUX_SEL_MIF0 0x0200
895 #define MUX_SEL_MIF1 0x0204
896 #define MUX_SEL_MIF2 0x0208
897 #define MUX_SEL_MIF3 0x020c
898 #define MUX_SEL_MIF4 0x0210
899 #define MUX_SEL_MIF5 0x0214
900 #define MUX_SEL_MIF6 0x0218
901 #define MUX_SEL_MIF7 0x021c
902 #define MUX_ENABLE_MIF0 0x0300
903 #define MUX_ENABLE_MIF1 0x0304
904 #define MUX_ENABLE_MIF2 0x0308
905 #define MUX_ENABLE_MIF3 0x030c
906 #define MUX_ENABLE_MIF4 0x0310
907 #define MUX_ENABLE_MIF5 0x0314
908 #define MUX_ENABLE_MIF6 0x0318
909 #define MUX_ENABLE_MIF7 0x031c
910 #define MUX_STAT_MIF0 0x0400
911 #define MUX_STAT_MIF1 0x0404
912 #define MUX_STAT_MIF2 0x0408
913 #define MUX_STAT_MIF3 0x040c
914 #define MUX_STAT_MIF4 0x0410
915 #define MUX_STAT_MIF5 0x0414
916 #define MUX_STAT_MIF6 0x0418
917 #define MUX_STAT_MIF7 0x041c
918 #define DIV_MIF1 0x0604
919 #define DIV_MIF2 0x0608
920 #define DIV_MIF3 0x060c
921 #define DIV_MIF4 0x0610
922 #define DIV_MIF5 0x0614
923 #define DIV_MIF_PLL_FREQ_DET 0x0618
924 #define DIV_STAT_MIF1 0x0704
925 #define DIV_STAT_MIF2 0x0708
926 #define DIV_STAT_MIF3 0x070c
927 #define DIV_STAT_MIF4 0x0710
928 #define DIV_STAT_MIF5 0x0714
929 #define DIV_STAT_MIF_PLL_FREQ_DET 0x0718
930 #define ENABLE_ACLK_MIF0 0x0800
931 #define ENABLE_ACLK_MIF1 0x0804
932 #define ENABLE_ACLK_MIF2 0x0808
933 #define ENABLE_ACLK_MIF3 0x080c
934 #define ENABLE_PCLK_MIF 0x0900
935 #define ENABLE_PCLK_MIF_SECURE_DREX0_TZ 0x0904
936 #define ENABLE_PCLK_MIF_SECURE_DREX1_TZ 0x0908
937 #define ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT 0x090c
938 #define ENABLE_PCLK_MIF_SECURE_RTC 0x0910
939 #define ENABLE_SCLK_MIF 0x0a00
940 #define ENABLE_IP_MIF0 0x0b00
941 #define ENABLE_IP_MIF1 0x0b04
942 #define ENABLE_IP_MIF2 0x0b08
943 #define ENABLE_IP_MIF3 0x0b0c
944 #define ENABLE_IP_MIF_SECURE_DREX0_TZ 0x0b10
945 #define ENABLE_IP_MIF_SECURE_DREX1_TZ 0x0b14
946 #define ENABLE_IP_MIF_SECURE_MONOTONIC_CNT 0x0b18
947 #define ENABLE_IP_MIF_SECURE_RTC 0x0b1c
948 #define CLKOUT_CMU_MIF 0x0c00
949 #define CLKOUT_CMU_MIF_DIV_STAT 0x0c04
950 #define DREX_FREQ_CTRL0 0x1000
951 #define DREX_FREQ_CTRL1 0x1004
952 #define PAUSE 0x1008
953 #define DDRPHY_LOCK_CTRL 0x100c
954
955 static const unsigned long mif_clk_regs[] __initconst = {
956 MEM0_PLL_LOCK,
957 MEM1_PLL_LOCK,
958 BUS_PLL_LOCK,
959 MFC_PLL_LOCK,
960 MEM0_PLL_CON0,
961 MEM0_PLL_CON1,
962 MEM0_PLL_FREQ_DET,
963 MEM1_PLL_CON0,
964 MEM1_PLL_CON1,
965 MEM1_PLL_FREQ_DET,
966 BUS_PLL_CON0,
967 BUS_PLL_CON1,
968 BUS_PLL_FREQ_DET,
969 MFC_PLL_CON0,
970 MFC_PLL_CON1,
971 MFC_PLL_FREQ_DET,
972 MUX_SEL_MIF0,
973 MUX_SEL_MIF1,
974 MUX_SEL_MIF2,
975 MUX_SEL_MIF3,
976 MUX_SEL_MIF4,
977 MUX_SEL_MIF5,
978 MUX_SEL_MIF6,
979 MUX_SEL_MIF7,
980 MUX_ENABLE_MIF0,
981 MUX_ENABLE_MIF1,
982 MUX_ENABLE_MIF2,
983 MUX_ENABLE_MIF3,
984 MUX_ENABLE_MIF4,
985 MUX_ENABLE_MIF5,
986 MUX_ENABLE_MIF6,
987 MUX_ENABLE_MIF7,
988 DIV_MIF1,
989 DIV_MIF2,
990 DIV_MIF3,
991 DIV_MIF4,
992 DIV_MIF5,
993 DIV_MIF_PLL_FREQ_DET,
994 ENABLE_ACLK_MIF0,
995 ENABLE_ACLK_MIF1,
996 ENABLE_ACLK_MIF2,
997 ENABLE_ACLK_MIF3,
998 ENABLE_PCLK_MIF,
999 ENABLE_PCLK_MIF_SECURE_DREX0_TZ,
1000 ENABLE_PCLK_MIF_SECURE_DREX1_TZ,
1001 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT,
1002 ENABLE_PCLK_MIF_SECURE_RTC,
1003 ENABLE_SCLK_MIF,
1004 ENABLE_IP_MIF0,
1005 ENABLE_IP_MIF1,
1006 ENABLE_IP_MIF2,
1007 ENABLE_IP_MIF3,
1008 ENABLE_IP_MIF_SECURE_DREX0_TZ,
1009 ENABLE_IP_MIF_SECURE_DREX1_TZ,
1010 ENABLE_IP_MIF_SECURE_MONOTONIC_CNT,
1011 ENABLE_IP_MIF_SECURE_RTC,
1012 CLKOUT_CMU_MIF,
1013 CLKOUT_CMU_MIF_DIV_STAT,
1014 DREX_FREQ_CTRL0,
1015 DREX_FREQ_CTRL1,
1016 PAUSE,
1017 DDRPHY_LOCK_CTRL,
1018 };
1019
1020 static const struct samsung_pll_clock mif_pll_clks[] __initconst = {
1021 PLL(pll_35xx, CLK_FOUT_MEM0_PLL, "fout_mem0_pll", "oscclk",
1022 MEM0_PLL_LOCK, MEM0_PLL_CON0, exynos5433_pll_rates),
1023 PLL(pll_35xx, CLK_FOUT_MEM1_PLL, "fout_mem1_pll", "oscclk",
1024 MEM1_PLL_LOCK, MEM1_PLL_CON0, exynos5433_pll_rates),
1025 PLL(pll_35xx, CLK_FOUT_BUS_PLL, "fout_bus_pll", "oscclk",
1026 BUS_PLL_LOCK, BUS_PLL_CON0, exynos5433_pll_rates),
1027 PLL(pll_35xx, CLK_FOUT_MFC_PLL, "fout_mfc_pll", "oscclk",
1028 MFC_PLL_LOCK, MFC_PLL_CON0, exynos5433_pll_rates),
1029 };
1030
1031 /* list of all parent clock list */
1032 PNAME(mout_mfc_pll_div2_p) = { "mout_mfc_pll", "dout_mfc_pll", };
1033 PNAME(mout_bus_pll_div2_p) = { "mout_bus_pll", "dout_bus_pll", };
1034 PNAME(mout_mem1_pll_div2_p) = { "mout_mem1_pll", "dout_mem1_pll", };
1035 PNAME(mout_mem0_pll_div2_p) = { "mout_mem0_pll", "dout_mem0_pll", };
1036 PNAME(mout_mfc_pll_p) = { "oscclk", "fout_mfc_pll", };
1037 PNAME(mout_bus_pll_p) = { "oscclk", "fout_bus_pll", };
1038 PNAME(mout_mem1_pll_p) = { "oscclk", "fout_mem1_pll", };
1039 PNAME(mout_mem0_pll_p) = { "oscclk", "fout_mem0_pll", };
1040
1041 PNAME(mout_clk2x_phy_c_p) = { "mout_mem0_pll_div2", "mout_clkm_phy_b", };
1042 PNAME(mout_clk2x_phy_b_p) = { "mout_bus_pll_div2", "mout_clkm_phy_a", };
1043 PNAME(mout_clk2x_phy_a_p) = { "mout_bus_pll_div2", "mout_mfc_pll_div2", };
1044 PNAME(mout_clkm_phy_b_p) = { "mout_mem1_pll_div2", "mout_clkm_phy_a", };
1045
1046 PNAME(mout_aclk_mifnm_200_p) = { "mout_mem0_pll_div2", "div_mif_pre", };
1047 PNAME(mout_aclk_mifnm_400_p) = { "mout_mem1_pll_div2", "mout_bus_pll_div2",};
1048
1049 PNAME(mout_aclk_disp_333_b_p) = { "mout_aclk_disp_333_a",
1050 "mout_bus_pll_div2", };
1051 PNAME(mout_aclk_disp_333_a_p) = { "mout_mfc_pll_div2", "sclk_mphy_pll", };
1052
1053 PNAME(mout_sclk_decon_vclk_c_p) = { "mout_sclk_decon_vclk_b",
1054 "sclk_mphy_pll", };
1055 PNAME(mout_sclk_decon_vclk_b_p) = { "mout_sclk_decon_vclk_a",
1056 "mout_mfc_pll_div2", };
1057 PNAME(mout_sclk_decon_p) = { "oscclk", "mout_bus_pll_div2", };
1058 PNAME(mout_sclk_decon_eclk_c_p) = { "mout_sclk_decon_eclk_b",
1059 "sclk_mphy_pll", };
1060 PNAME(mout_sclk_decon_eclk_b_p) = { "mout_sclk_decon_eclk_a",
1061 "mout_mfc_pll_div2", };
1062
1063 PNAME(mout_sclk_decon_tv_eclk_c_p) = { "mout_sclk_decon_tv_eclk_b",
1064 "sclk_mphy_pll", };
1065 PNAME(mout_sclk_decon_tv_eclk_b_p) = { "mout_sclk_decon_tv_eclk_a",
1066 "mout_mfc_pll_div2", };
1067 PNAME(mout_sclk_dsd_c_p) = { "mout_sclk_dsd_b", "mout_bus_pll_div2", };
1068 PNAME(mout_sclk_dsd_b_p) = { "mout_sclk_dsd_a", "sclk_mphy_pll", };
1069 PNAME(mout_sclk_dsd_a_p) = { "oscclk", "mout_mfc_pll_div2", };
1070
1071 PNAME(mout_sclk_dsim0_c_p) = { "mout_sclk_dsim0_b", "sclk_mphy_pll", };
1072 PNAME(mout_sclk_dsim0_b_p) = { "mout_sclk_dsim0_a", "mout_mfc_pll_div2" };
1073
1074 PNAME(mout_sclk_decon_tv_vclk_c_p) = { "mout_sclk_decon_tv_vclk_b",
1075 "sclk_mphy_pll", };
1076 PNAME(mout_sclk_decon_tv_vclk_b_p) = { "mout_sclk_decon_tv_vclk_a",
1077 "mout_mfc_pll_div2", };
1078 PNAME(mout_sclk_dsim1_c_p) = { "mout_sclk_dsim1_b", "sclk_mphy_pll", };
1079 PNAME(mout_sclk_dsim1_b_p) = { "mout_sclk_dsim1_a", "mout_mfc_pll_div2",};
1080
1081 static const struct samsung_fixed_factor_clock mif_fixed_factor_clks[] __initconst = {
1082 /* dout_{mfc|bus|mem1|mem0}_pll is half fixed rate from parent mux */
1083 FFACTOR(CLK_DOUT_MFC_PLL, "dout_mfc_pll", "mout_mfc_pll", 1, 1, 0),
1084 FFACTOR(CLK_DOUT_BUS_PLL, "dout_bus_pll", "mout_bus_pll", 1, 1, 0),
1085 FFACTOR(CLK_DOUT_MEM1_PLL, "dout_mem1_pll", "mout_mem1_pll", 1, 1, 0),
1086 FFACTOR(CLK_DOUT_MEM0_PLL, "dout_mem0_pll", "mout_mem0_pll", 1, 1, 0),
1087 };
1088
1089 static const struct samsung_mux_clock mif_mux_clks[] __initconst = {
1090 /* MUX_SEL_MIF0 */
1091 MUX(CLK_MOUT_MFC_PLL_DIV2, "mout_mfc_pll_div2", mout_mfc_pll_div2_p,
1092 MUX_SEL_MIF0, 28, 1),
1093 MUX(CLK_MOUT_BUS_PLL_DIV2, "mout_bus_pll_div2", mout_bus_pll_div2_p,
1094 MUX_SEL_MIF0, 24, 1),
1095 MUX(CLK_MOUT_MEM1_PLL_DIV2, "mout_mem1_pll_div2", mout_mem1_pll_div2_p,
1096 MUX_SEL_MIF0, 20, 1),
1097 MUX(CLK_MOUT_MEM0_PLL_DIV2, "mout_mem0_pll_div2", mout_mem0_pll_div2_p,
1098 MUX_SEL_MIF0, 16, 1),
1099 MUX(CLK_MOUT_MFC_PLL, "mout_mfc_pll", mout_mfc_pll_p, MUX_SEL_MIF0,
1100 12, 1),
1101 MUX(CLK_MOUT_BUS_PLL, "mout_bus_pll", mout_bus_pll_p, MUX_SEL_MIF0,
1102 8, 1),
1103 MUX(CLK_MOUT_MEM1_PLL, "mout_mem1_pll", mout_mem1_pll_p, MUX_SEL_MIF0,
1104 4, 1),
1105 MUX(CLK_MOUT_MEM0_PLL, "mout_mem0_pll", mout_mem0_pll_p, MUX_SEL_MIF0,
1106 0, 1),
1107
1108 /* MUX_SEL_MIF1 */
1109 MUX(CLK_MOUT_CLK2X_PHY_C, "mout_clk2x_phy_c", mout_clk2x_phy_c_p,
1110 MUX_SEL_MIF1, 24, 1),
1111 MUX(CLK_MOUT_CLK2X_PHY_B, "mout_clk2x_phy_b", mout_clk2x_phy_b_p,
1112 MUX_SEL_MIF1, 20, 1),
1113 MUX(CLK_MOUT_CLK2X_PHY_A, "mout_clk2x_phy_a", mout_clk2x_phy_a_p,
1114 MUX_SEL_MIF1, 16, 1),
1115 MUX(CLK_MOUT_CLKM_PHY_C, "mout_clkm_phy_c", mout_clk2x_phy_c_p,
1116 MUX_SEL_MIF1, 12, 1),
1117 MUX(CLK_MOUT_CLKM_PHY_B, "mout_clkm_phy_b", mout_clkm_phy_b_p,
1118 MUX_SEL_MIF1, 8, 1),
1119 MUX(CLK_MOUT_CLKM_PHY_A, "mout_clkm_phy_a", mout_clk2x_phy_a_p,
1120 MUX_SEL_MIF1, 4, 1),
1121
1122 /* MUX_SEL_MIF2 */
1123 MUX(CLK_MOUT_ACLK_MIFNM_200, "mout_aclk_mifnm_200",
1124 mout_aclk_mifnm_200_p, MUX_SEL_MIF2, 8, 1),
1125 MUX(CLK_MOUT_ACLK_MIFNM_400, "mout_aclk_mifnm_400",
1126 mout_aclk_mifnm_400_p, MUX_SEL_MIF2, 0, 1),
1127
1128 /* MUX_SEL_MIF3 */
1129 MUX(CLK_MOUT_ACLK_DISP_333_B, "mout_aclk_disp_333_b",
1130 mout_aclk_disp_333_b_p, MUX_SEL_MIF3, 4, 1),
1131 MUX(CLK_MOUT_ACLK_DISP_333_A, "mout_aclk_disp_333_a",
1132 mout_aclk_disp_333_a_p, MUX_SEL_MIF3, 0, 1),
1133
1134 /* MUX_SEL_MIF4 */
1135 MUX(CLK_MOUT_SCLK_DECON_VCLK_C, "mout_sclk_decon_vclk_c",
1136 mout_sclk_decon_vclk_c_p, MUX_SEL_MIF4, 24, 1),
1137 MUX(CLK_MOUT_SCLK_DECON_VCLK_B, "mout_sclk_decon_vclk_b",
1138 mout_sclk_decon_vclk_b_p, MUX_SEL_MIF4, 20, 1),
1139 MUX(CLK_MOUT_SCLK_DECON_VCLK_A, "mout_sclk_decon_vclk_a",
1140 mout_sclk_decon_p, MUX_SEL_MIF4, 16, 1),
1141 MUX(CLK_MOUT_SCLK_DECON_ECLK_C, "mout_sclk_decon_eclk_c",
1142 mout_sclk_decon_eclk_c_p, MUX_SEL_MIF4, 8, 1),
1143 MUX(CLK_MOUT_SCLK_DECON_ECLK_B, "mout_sclk_decon_eclk_b",
1144 mout_sclk_decon_eclk_b_p, MUX_SEL_MIF4, 4, 1),
1145 MUX(CLK_MOUT_SCLK_DECON_ECLK_A, "mout_sclk_decon_eclk_a",
1146 mout_sclk_decon_p, MUX_SEL_MIF4, 0, 1),
1147
1148 /* MUX_SEL_MIF5 */
1149 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_C, "mout_sclk_decon_tv_eclk_c",
1150 mout_sclk_decon_tv_eclk_c_p, MUX_SEL_MIF5, 24, 1),
1151 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_B, "mout_sclk_decon_tv_eclk_b",
1152 mout_sclk_decon_tv_eclk_b_p, MUX_SEL_MIF5, 20, 1),
1153 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_A, "mout_sclk_decon_tv_eclk_a",
1154 mout_sclk_decon_p, MUX_SEL_MIF5, 16, 1),
1155 MUX(CLK_MOUT_SCLK_DSD_C, "mout_sclk_dsd_c", mout_sclk_dsd_c_p,
1156 MUX_SEL_MIF5, 8, 1),
1157 MUX(CLK_MOUT_SCLK_DSD_B, "mout_sclk_dsd_b", mout_sclk_dsd_b_p,
1158 MUX_SEL_MIF5, 4, 1),
1159 MUX(CLK_MOUT_SCLK_DSD_A, "mout_sclk_dsd_a", mout_sclk_dsd_a_p,
1160 MUX_SEL_MIF5, 0, 1),
1161
1162 /* MUX_SEL_MIF6 */
1163 MUX(CLK_MOUT_SCLK_DSIM0_C, "mout_sclk_dsim0_c", mout_sclk_dsim0_c_p,
1164 MUX_SEL_MIF6, 8, 1),
1165 MUX(CLK_MOUT_SCLK_DSIM0_B, "mout_sclk_dsim0_b", mout_sclk_dsim0_b_p,
1166 MUX_SEL_MIF6, 4, 1),
1167 MUX(CLK_MOUT_SCLK_DSIM0_A, "mout_sclk_dsim0_a", mout_sclk_decon_p,
1168 MUX_SEL_MIF6, 0, 1),
1169
1170 /* MUX_SEL_MIF7 */
1171 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C, "mout_sclk_decon_tv_vclk_c",
1172 mout_sclk_decon_tv_vclk_c_p, MUX_SEL_MIF7, 24, 1),
1173 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B, "mout_sclk_decon_tv_vclk_b",
1174 mout_sclk_decon_tv_vclk_b_p, MUX_SEL_MIF7, 20, 1),
1175 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A, "mout_sclk_decon_tv_vclk_a",
1176 mout_sclk_decon_p, MUX_SEL_MIF7, 16, 1),
1177 MUX(CLK_MOUT_SCLK_DSIM1_C, "mout_sclk_dsim1_c", mout_sclk_dsim1_c_p,
1178 MUX_SEL_MIF7, 8, 1),
1179 MUX(CLK_MOUT_SCLK_DSIM1_B, "mout_sclk_dsim1_b", mout_sclk_dsim1_b_p,
1180 MUX_SEL_MIF7, 4, 1),
1181 MUX(CLK_MOUT_SCLK_DSIM1_A, "mout_sclk_dsim1_a", mout_sclk_decon_p,
1182 MUX_SEL_MIF7, 0, 1),
1183 };
1184
1185 static const struct samsung_div_clock mif_div_clks[] __initconst = {
1186 /* DIV_MIF1 */
1187 DIV(CLK_DIV_SCLK_HPM_MIF, "div_sclk_hpm_mif", "div_clk2x_phy",
1188 DIV_MIF1, 16, 2),
1189 DIV(CLK_DIV_ACLK_DREX1, "div_aclk_drex1", "div_clk2x_phy", DIV_MIF1,
1190 12, 2),
1191 DIV(CLK_DIV_ACLK_DREX0, "div_aclk_drex0", "div_clk2x_phy", DIV_MIF1,
1192 8, 2),
1193 DIV(CLK_DIV_CLK2XPHY, "div_clk2x_phy", "mout_clk2x_phy_c", DIV_MIF1,
1194 4, 4),
1195
1196 /* DIV_MIF2 */
1197 DIV(CLK_DIV_ACLK_MIF_266, "div_aclk_mif_266", "mout_bus_pll_div2",
1198 DIV_MIF2, 20, 3),
1199 DIV(CLK_DIV_ACLK_MIFND_133, "div_aclk_mifnd_133", "div_mif_pre",
1200 DIV_MIF2, 16, 4),
1201 DIV(CLK_DIV_ACLK_MIF_133, "div_aclk_mif_133", "div_mif_pre",
1202 DIV_MIF2, 12, 4),
1203 DIV(CLK_DIV_ACLK_MIFNM_200, "div_aclk_mifnm_200",
1204 "mout_aclk_mifnm_200", DIV_MIF2, 8, 3),
1205 DIV(CLK_DIV_ACLK_MIF_200, "div_aclk_mif_200", "div_aclk_mif_400",
1206 DIV_MIF2, 4, 2),
1207 DIV(CLK_DIV_ACLK_MIF_400, "div_aclk_mif_400", "mout_aclk_mifnm_400",
1208 DIV_MIF2, 0, 3),
1209
1210 /* DIV_MIF3 */
1211 DIV(CLK_DIV_ACLK_BUS2_400, "div_aclk_bus2_400", "div_mif_pre",
1212 DIV_MIF3, 16, 4),
1213 DIV(CLK_DIV_ACLK_DISP_333, "div_aclk_disp_333", "mout_aclk_disp_333_b",
1214 DIV_MIF3, 4, 3),
1215 DIV(CLK_DIV_ACLK_CPIF_200, "div_aclk_cpif_200", "mout_aclk_mifnm_200",
1216 DIV_MIF3, 0, 3),
1217
1218 /* DIV_MIF4 */
1219 DIV(CLK_DIV_SCLK_DSIM1, "div_sclk_dsim1", "mout_sclk_dsim1_c",
1220 DIV_MIF4, 24, 4),
1221 DIV(CLK_DIV_SCLK_DECON_TV_VCLK, "div_sclk_decon_tv_vclk",
1222 "mout_sclk_decon_tv_vclk_c", DIV_MIF4, 20, 4),
1223 DIV(CLK_DIV_SCLK_DSIM0, "div_sclk_dsim0", "mout_sclk_dsim0_c",
1224 DIV_MIF4, 16, 4),
1225 DIV(CLK_DIV_SCLK_DSD, "div_sclk_dsd", "mout_sclk_dsd_c",
1226 DIV_MIF4, 12, 4),
1227 DIV(CLK_DIV_SCLK_DECON_TV_ECLK, "div_sclk_decon_tv_eclk",
1228 "mout_sclk_decon_tv_eclk_c", DIV_MIF4, 8, 4),
1229 DIV(CLK_DIV_SCLK_DECON_VCLK, "div_sclk_decon_vclk",
1230 "mout_sclk_decon_vclk_c", DIV_MIF4, 4, 4),
1231 DIV(CLK_DIV_SCLK_DECON_ECLK, "div_sclk_decon_eclk",
1232 "mout_sclk_decon_eclk_c", DIV_MIF4, 0, 4),
1233
1234 /* DIV_MIF5 */
1235 DIV(CLK_DIV_MIF_PRE, "div_mif_pre", "mout_bus_pll_div2", DIV_MIF5,
1236 0, 3),
1237 };
1238
1239 static const struct samsung_gate_clock mif_gate_clks[] __initconst = {
1240 /* ENABLE_ACLK_MIF0 */
1241 GATE(CLK_CLK2X_PHY1, "clk2k_phy1", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1242 19, CLK_IGNORE_UNUSED, 0),
1243 GATE(CLK_CLK2X_PHY0, "clk2x_phy0", "div_clk2x_phy", ENABLE_ACLK_MIF0,
1244 18, CLK_IGNORE_UNUSED, 0),
1245 GATE(CLK_CLKM_PHY1, "clkm_phy1", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1246 17, CLK_IGNORE_UNUSED, 0),
1247 GATE(CLK_CLKM_PHY0, "clkm_phy0", "mout_clkm_phy_c", ENABLE_ACLK_MIF0,
1248 16, CLK_IGNORE_UNUSED, 0),
1249 GATE(CLK_RCLK_DREX1, "rclk_drex1", "oscclk", ENABLE_ACLK_MIF0,
1250 15, CLK_IGNORE_UNUSED, 0),
1251 GATE(CLK_RCLK_DREX0, "rclk_drex0", "oscclk", ENABLE_ACLK_MIF0,
1252 14, CLK_IGNORE_UNUSED, 0),
1253 GATE(CLK_ACLK_DREX1_TZ, "aclk_drex1_tz", "div_aclk_drex1",
1254 ENABLE_ACLK_MIF0, 13, CLK_IGNORE_UNUSED, 0),
1255 GATE(CLK_ACLK_DREX0_TZ, "aclk_drex0_tz", "div_aclk_drex0",
1256 ENABLE_ACLK_MIF0, 12, CLK_IGNORE_UNUSED, 0),
1257 GATE(CLK_ACLK_DREX1_PEREV, "aclk_drex1_perev", "div_aclk_drex1",
1258 ENABLE_ACLK_MIF0, 11, CLK_IGNORE_UNUSED, 0),
1259 GATE(CLK_ACLK_DREX0_PEREV, "aclk_drex0_perev", "div_aclk_drex0",
1260 ENABLE_ACLK_MIF0, 10, CLK_IGNORE_UNUSED, 0),
1261 GATE(CLK_ACLK_DREX1_MEMIF, "aclk_drex1_memif", "div_aclk_drex1",
1262 ENABLE_ACLK_MIF0, 9, CLK_IGNORE_UNUSED, 0),
1263 GATE(CLK_ACLK_DREX0_MEMIF, "aclk_drex0_memif", "div_aclk_drex0",
1264 ENABLE_ACLK_MIF0, 8, CLK_IGNORE_UNUSED, 0),
1265 GATE(CLK_ACLK_DREX1_SCH, "aclk_drex1_sch", "div_aclk_drex1",
1266 ENABLE_ACLK_MIF0, 7, CLK_IGNORE_UNUSED, 0),
1267 GATE(CLK_ACLK_DREX0_SCH, "aclk_drex0_sch", "div_aclk_drex0",
1268 ENABLE_ACLK_MIF0, 6, CLK_IGNORE_UNUSED, 0),
1269 GATE(CLK_ACLK_DREX1_BUSIF, "aclk_drex1_busif", "div_aclk_drex1",
1270 ENABLE_ACLK_MIF0, 5, CLK_IGNORE_UNUSED, 0),
1271 GATE(CLK_ACLK_DREX0_BUSIF, "aclk_drex0_busif", "div_aclk_drex0",
1272 ENABLE_ACLK_MIF0, 4, CLK_IGNORE_UNUSED, 0),
1273 GATE(CLK_ACLK_DREX1_BUSIF_RD, "aclk_drex1_busif_rd", "div_aclk_drex1",
1274 ENABLE_ACLK_MIF0, 3, CLK_IGNORE_UNUSED, 0),
1275 GATE(CLK_ACLK_DREX0_BUSIF_RD, "aclk_drex0_busif_rd", "div_aclk_drex0",
1276 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1277 GATE(CLK_ACLK_DREX1, "aclk_drex1", "div_aclk_drex1",
1278 ENABLE_ACLK_MIF0, 2, CLK_IGNORE_UNUSED, 0),
1279 GATE(CLK_ACLK_DREX0, "aclk_drex0", "div_aclk_drex0",
1280 ENABLE_ACLK_MIF0, 1, CLK_IGNORE_UNUSED, 0),
1281
1282 /* ENABLE_ACLK_MIF1 */
1283 GATE(CLK_ACLK_ASYNCAXIS_MIF_IMEM, "aclk_asyncaxis_mif_imem",
1284 "div_aclk_mif_200", ENABLE_ACLK_MIF1, 28,
1285 CLK_IGNORE_UNUSED, 0),
1286 GATE(CLK_ACLK_ASYNCAXIS_NOC_P_CCI, "aclk_asyncaxis_noc_p_cci",
1287 "div_aclk_mif_200", ENABLE_ACLK_MIF1,
1288 27, CLK_IGNORE_UNUSED, 0),
1289 GATE(CLK_ACLK_ASYNCAXIM_NOC_P_CCI, "aclk_asyncaxim_noc_p_cci",
1290 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1291 26, CLK_IGNORE_UNUSED, 0),
1292 GATE(CLK_ACLK_ASYNCAXIS_CP1, "aclk_asyncaxis_cp1",
1293 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1294 25, CLK_IGNORE_UNUSED, 0),
1295 GATE(CLK_ACLK_ASYNCAXIM_CP1, "aclk_asyncaxim_cp1",
1296 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1297 24, CLK_IGNORE_UNUSED, 0),
1298 GATE(CLK_ACLK_ASYNCAXIS_CP0, "aclk_asyncaxis_cp0",
1299 "div_aclk_mifnm_200", ENABLE_ACLK_MIF1,
1300 23, CLK_IGNORE_UNUSED, 0),
1301 GATE(CLK_ACLK_ASYNCAXIM_CP0, "aclk_asyncaxim_cp0",
1302 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1303 22, CLK_IGNORE_UNUSED, 0),
1304 GATE(CLK_ACLK_ASYNCAXIS_DREX1_3, "aclk_asyncaxis_drex1_3",
1305 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1306 21, CLK_IGNORE_UNUSED, 0),
1307 GATE(CLK_ACLK_ASYNCAXIM_DREX1_3, "aclk_asyncaxim_drex1_3",
1308 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1309 20, CLK_IGNORE_UNUSED, 0),
1310 GATE(CLK_ACLK_ASYNCAXIS_DREX1_1, "aclk_asyncaxis_drex1_1",
1311 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1312 19, CLK_IGNORE_UNUSED, 0),
1313 GATE(CLK_ACLK_ASYNCAXIM_DREX1_1, "aclk_asyncaxim_drex1_1",
1314 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1315 18, CLK_IGNORE_UNUSED, 0),
1316 GATE(CLK_ACLK_ASYNCAXIS_DREX1_0, "aclk_asyncaxis_drex1_0",
1317 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1318 17, CLK_IGNORE_UNUSED, 0),
1319 GATE(CLK_ACLK_ASYNCAXIM_DREX1_0, "aclk_asyncaxim_drex1_0",
1320 "div_aclk_drex1", ENABLE_ACLK_MIF1,
1321 16, CLK_IGNORE_UNUSED, 0),
1322 GATE(CLK_ACLK_ASYNCAXIS_DREX0_3, "aclk_asyncaxis_drex0_3",
1323 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1324 15, CLK_IGNORE_UNUSED, 0),
1325 GATE(CLK_ACLK_ASYNCAXIM_DREX0_3, "aclk_asyncaxim_drex0_3",
1326 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1327 14, CLK_IGNORE_UNUSED, 0),
1328 GATE(CLK_ACLK_ASYNCAXIS_DREX0_1, "aclk_asyncaxis_drex0_1",
1329 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1330 13, CLK_IGNORE_UNUSED, 0),
1331 GATE(CLK_ACLK_ASYNCAXIM_DREX0_1, "aclk_asyncaxim_drex0_1",
1332 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1333 12, CLK_IGNORE_UNUSED, 0),
1334 GATE(CLK_ACLK_ASYNCAXIS_DREX0_0, "aclk_asyncaxis_drex0_0",
1335 "div_aclk_mif_133", ENABLE_ACLK_MIF1,
1336 11, CLK_IGNORE_UNUSED, 0),
1337 GATE(CLK_ACLK_ASYNCAXIM_DREX0_0, "aclk_asyncaxim_drex0_0",
1338 "div_aclk_drex0", ENABLE_ACLK_MIF1,
1339 10, CLK_IGNORE_UNUSED, 0),
1340 GATE(CLK_ACLK_AHB2APB_MIF2P, "aclk_ahb2apb_mif2p", "div_aclk_mif_133",
1341 ENABLE_ACLK_MIF1, 9, CLK_IGNORE_UNUSED, 0),
1342 GATE(CLK_ACLK_AHB2APB_MIF1P, "aclk_ahb2apb_mif1p", "div_aclk_mif_133",
1343 ENABLE_ACLK_MIF1, 8, CLK_IGNORE_UNUSED, 0),
1344 GATE(CLK_ACLK_AHB2APB_MIF0P, "aclk_ahb2apb_mif0p", "div_aclk_mif_133",
1345 ENABLE_ACLK_MIF1, 7, CLK_IGNORE_UNUSED, 0),
1346 GATE(CLK_ACLK_IXIU_CCI, "aclk_ixiu_cci", "div_aclk_mif_400",
1347 ENABLE_ACLK_MIF1, 6, CLK_IGNORE_UNUSED, 0),
1348 GATE(CLK_ACLK_XIU_MIFSFRX, "aclk_xiu_mifsfrx", "div_aclk_mif_200",
1349 ENABLE_ACLK_MIF1, 5, CLK_IGNORE_UNUSED, 0),
1350 GATE(CLK_ACLK_MIFNP_133, "aclk_mifnp_133", "div_aclk_mif_133",
1351 ENABLE_ACLK_MIF1, 4, CLK_IGNORE_UNUSED, 0),
1352 GATE(CLK_ACLK_MIFNM_200, "aclk_mifnm_200", "div_aclk_mifnm_200",
1353 ENABLE_ACLK_MIF1, 3, CLK_IGNORE_UNUSED, 0),
1354 GATE(CLK_ACLK_MIFND_133, "aclk_mifnd_133", "div_aclk_mifnd_133",
1355 ENABLE_ACLK_MIF1, 2, CLK_IGNORE_UNUSED, 0),
1356 GATE(CLK_ACLK_MIFND_400, "aclk_mifnd_400", "div_aclk_mif_400",
1357 ENABLE_ACLK_MIF1, 1, CLK_IGNORE_UNUSED, 0),
1358 GATE(CLK_ACLK_CCI, "aclk_cci", "div_aclk_mif_400", ENABLE_ACLK_MIF1,
1359 0, CLK_IGNORE_UNUSED, 0),
1360
1361 /* ENABLE_ACLK_MIF2 */
1362 GATE(CLK_ACLK_MIFND_266, "aclk_mifnd_266", "div_aclk_mif_266",
1363 ENABLE_ACLK_MIF2, 20, CLK_IGNORE_UNUSED, 0),
1364 GATE(CLK_ACLK_PPMU_DREX1S3, "aclk_ppmu_drex1s3", "div_aclk_drex1",
1365 ENABLE_ACLK_MIF2, 17, CLK_IGNORE_UNUSED, 0),
1366 GATE(CLK_ACLK_PPMU_DREX1S1, "aclk_ppmu_drex1s1", "div_aclk_drex1",
1367 ENABLE_ACLK_MIF2, 16, CLK_IGNORE_UNUSED, 0),
1368 GATE(CLK_ACLK_PPMU_DREX1S0, "aclk_ppmu_drex1s0", "div_aclk_drex1",
1369 ENABLE_ACLK_MIF2, 15, CLK_IGNORE_UNUSED, 0),
1370 GATE(CLK_ACLK_PPMU_DREX0S3, "aclk_ppmu_drex0s3", "div_aclk_drex0",
1371 ENABLE_ACLK_MIF2, 14, CLK_IGNORE_UNUSED, 0),
1372 GATE(CLK_ACLK_PPMU_DREX0S1, "aclk_ppmu_drex0s1", "div_aclk_drex0",
1373 ENABLE_ACLK_MIF2, 13, CLK_IGNORE_UNUSED, 0),
1374 GATE(CLK_ACLK_PPMU_DREX0S0, "aclk_ppmu_drex0s0", "div_aclk_drex0",
1375 ENABLE_ACLK_MIF2, 12, CLK_IGNORE_UNUSED, 0),
1376 GATE(CLK_ACLK_AXIDS_CCI_MIFSFRX, "aclk_axids_cci_mifsfrx",
1377 "div_aclk_mif_200", ENABLE_ACLK_MIF2, 7,
1378 CLK_IGNORE_UNUSED, 0),
1379 GATE(CLK_ACLK_AXISYNCDNS_CCI, "aclk_axisyncdns_cci",
1380 "div_aclk_mif_400", ENABLE_ACLK_MIF2,
1381 5, CLK_IGNORE_UNUSED, 0),
1382 GATE(CLK_ACLK_AXISYNCDN_CCI, "aclk_axisyncdn_cci", "div_aclk_mif_400",
1383 ENABLE_ACLK_MIF2, 4, CLK_IGNORE_UNUSED, 0),
1384 GATE(CLK_ACLK_AXISYNCDN_NOC_D, "aclk_axisyncdn_noc_d",
1385 "div_aclk_mif_200", ENABLE_ACLK_MIF2,
1386 3, CLK_IGNORE_UNUSED, 0),
1387 GATE(CLK_ACLK_ASYNCAPBS_MIF_CSSYS, "aclk_asyncapbs_mif_cssys",
1388 "div_aclk_mifnd_133", ENABLE_ACLK_MIF2, 0, 0, 0),
1389
1390 /* ENABLE_ACLK_MIF3 */
1391 GATE(CLK_ACLK_BUS2_400, "aclk_bus2_400", "div_aclk_bus2_400",
1392 ENABLE_ACLK_MIF3, 4,
1393 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1394 GATE(CLK_ACLK_DISP_333, "aclk_disp_333", "div_aclk_disp_333",
1395 ENABLE_ACLK_MIF3, 1,
1396 CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, 0),
1397 GATE(CLK_ACLK_CPIF_200, "aclk_cpif_200", "div_aclk_cpif_200",
1398 ENABLE_ACLK_MIF3, 0,
1399 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1400
1401 /* ENABLE_PCLK_MIF */
1402 GATE(CLK_PCLK_PPMU_DREX1S3, "pclk_ppmu_drex1s3", "div_aclk_drex1",
1403 ENABLE_PCLK_MIF, 29, CLK_IGNORE_UNUSED, 0),
1404 GATE(CLK_PCLK_PPMU_DREX1S1, "pclk_ppmu_drex1s1", "div_aclk_drex1",
1405 ENABLE_PCLK_MIF, 28, CLK_IGNORE_UNUSED, 0),
1406 GATE(CLK_PCLK_PPMU_DREX1S0, "pclk_ppmu_drex1s0", "div_aclk_drex1",
1407 ENABLE_PCLK_MIF, 27, CLK_IGNORE_UNUSED, 0),
1408 GATE(CLK_PCLK_PPMU_DREX0S3, "pclk_ppmu_drex0s3", "div_aclk_drex0",
1409 ENABLE_PCLK_MIF, 26, CLK_IGNORE_UNUSED, 0),
1410 GATE(CLK_PCLK_PPMU_DREX0S1, "pclk_ppmu_drex0s1", "div_aclk_drex0",
1411 ENABLE_PCLK_MIF, 25, CLK_IGNORE_UNUSED, 0),
1412 GATE(CLK_PCLK_PPMU_DREX0S0, "pclk_ppmu_drex0s0", "div_aclk_drex0",
1413 ENABLE_PCLK_MIF, 24, CLK_IGNORE_UNUSED, 0),
1414 GATE(CLK_PCLK_ASYNCAXI_NOC_P_CCI, "pclk_asyncaxi_noc_p_cci",
1415 "div_aclk_mif_133", ENABLE_PCLK_MIF, 21,
1416 CLK_IGNORE_UNUSED, 0),
1417 GATE(CLK_PCLK_ASYNCAXI_CP1, "pclk_asyncaxi_cp1", "div_aclk_mif_133",
1418 ENABLE_PCLK_MIF, 19, 0, 0),
1419 GATE(CLK_PCLK_ASYNCAXI_CP0, "pclk_asyncaxi_cp0", "div_aclk_mif_133",
1420 ENABLE_PCLK_MIF, 18, 0, 0),
1421 GATE(CLK_PCLK_ASYNCAXI_DREX1_3, "pclk_asyncaxi_drex1_3",
1422 "div_aclk_mif_133", ENABLE_PCLK_MIF, 17, 0, 0),
1423 GATE(CLK_PCLK_ASYNCAXI_DREX1_1, "pclk_asyncaxi_drex1_1",
1424 "div_aclk_mif_133", ENABLE_PCLK_MIF, 16, 0, 0),
1425 GATE(CLK_PCLK_ASYNCAXI_DREX1_0, "pclk_asyncaxi_drex1_0",
1426 "div_aclk_mif_133", ENABLE_PCLK_MIF, 15, 0, 0),
1427 GATE(CLK_PCLK_ASYNCAXI_DREX0_3, "pclk_asyncaxi_drex0_3",
1428 "div_aclk_mif_133", ENABLE_PCLK_MIF, 14, 0, 0),
1429 GATE(CLK_PCLK_ASYNCAXI_DREX0_1, "pclk_asyncaxi_drex0_1",
1430 "div_aclk_mif_133", ENABLE_PCLK_MIF, 13, 0, 0),
1431 GATE(CLK_PCLK_ASYNCAXI_DREX0_0, "pclk_asyncaxi_drex0_0",
1432 "div_aclk_mif_133", ENABLE_PCLK_MIF, 12, 0, 0),
1433 GATE(CLK_PCLK_MIFSRVND_133, "pclk_mifsrvnd_133", "div_aclk_mif_133",
1434 ENABLE_PCLK_MIF, 11, 0, 0),
1435 GATE(CLK_PCLK_PMU_MIF, "pclk_pmu_mif", "div_aclk_mif_133",
1436 ENABLE_PCLK_MIF, 10, CLK_IGNORE_UNUSED, 0),
1437 GATE(CLK_PCLK_SYSREG_MIF, "pclk_sysreg_mif", "div_aclk_mif_133",
1438 ENABLE_PCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1439 GATE(CLK_PCLK_GPIO_ALIVE, "pclk_gpio_alive", "div_aclk_mif_133",
1440 ENABLE_PCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1441 GATE(CLK_PCLK_ABB, "pclk_abb", "div_aclk_mif_133",
1442 ENABLE_PCLK_MIF, 7, 0, 0),
1443 GATE(CLK_PCLK_PMU_APBIF, "pclk_pmu_apbif", "div_aclk_mif_133",
1444 ENABLE_PCLK_MIF, 6, CLK_IGNORE_UNUSED, 0),
1445 GATE(CLK_PCLK_DDR_PHY1, "pclk_ddr_phy1", "div_aclk_mif_133",
1446 ENABLE_PCLK_MIF, 5, 0, 0),
1447 GATE(CLK_PCLK_DREX1, "pclk_drex1", "div_aclk_mif_133",
1448 ENABLE_PCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1449 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",
1450 ENABLE_PCLK_MIF, 2, 0, 0),
1451 GATE(CLK_PCLK_DREX0, "pclk_drex0", "div_aclk_mif_133",
1452 ENABLE_PCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1453
1454 /* ENABLE_PCLK_MIF_SECURE_DREX0_TZ */
1455 GATE(CLK_PCLK_DREX0_TZ, "pclk_drex0_tz", "div_aclk_mif_133",
1456 ENABLE_PCLK_MIF_SECURE_DREX0_TZ, 0,
1457 CLK_IGNORE_UNUSED, 0),
1458
1459 /* ENABLE_PCLK_MIF_SECURE_DREX1_TZ */
1460 GATE(CLK_PCLK_DREX1_TZ, "pclk_drex1_tz", "div_aclk_mif_133",
1461 ENABLE_PCLK_MIF_SECURE_DREX1_TZ, 0,
1462 CLK_IGNORE_UNUSED, 0),
1463
1464 /* ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT */
1465 GATE(CLK_PCLK_MONOTONIC_CNT, "pclk_monotonic_cnt", "div_aclk_mif_133",
1466 ENABLE_PCLK_MIF_SECURE_MONOTONIC_CNT, 0, 0, 0),
1467
1468 /* ENABLE_PCLK_MIF_SECURE_RTC */
1469 GATE(CLK_PCLK_RTC, "pclk_rtc", "div_aclk_mif_133",
1470 ENABLE_PCLK_MIF_SECURE_RTC, 0, 0, 0),
1471
1472 /* ENABLE_SCLK_MIF */
1473 GATE(CLK_SCLK_DSIM1_DISP, "sclk_dsim1_disp", "div_sclk_dsim1",
1474 ENABLE_SCLK_MIF, 15, CLK_IGNORE_UNUSED, 0),
1475 GATE(CLK_SCLK_DECON_TV_VCLK_DISP, "sclk_decon_tv_vclk_disp",
1476 "div_sclk_decon_tv_vclk", ENABLE_SCLK_MIF,
1477 14, CLK_IGNORE_UNUSED, 0),
1478 GATE(CLK_SCLK_DSIM0_DISP, "sclk_dsim0_disp", "div_sclk_dsim0",
1479 ENABLE_SCLK_MIF, 9, CLK_IGNORE_UNUSED, 0),
1480 GATE(CLK_SCLK_DSD_DISP, "sclk_dsd_disp", "div_sclk_dsd",
1481 ENABLE_SCLK_MIF, 8, CLK_IGNORE_UNUSED, 0),
1482 GATE(CLK_SCLK_DECON_TV_ECLK_DISP, "sclk_decon_tv_eclk_disp",
1483 "div_sclk_decon_tv_eclk", ENABLE_SCLK_MIF,
1484 7, CLK_IGNORE_UNUSED, 0),
1485 GATE(CLK_SCLK_DECON_VCLK_DISP, "sclk_decon_vclk_disp",
1486 "div_sclk_decon_vclk", ENABLE_SCLK_MIF,
1487 6, CLK_IGNORE_UNUSED, 0),
1488 GATE(CLK_SCLK_DECON_ECLK_DISP, "sclk_decon_eclk_disp",
1489 "div_sclk_decon_eclk", ENABLE_SCLK_MIF,
1490 5, CLK_IGNORE_UNUSED, 0),
1491 GATE(CLK_SCLK_HPM_MIF, "sclk_hpm_mif", "div_sclk_hpm_mif",
1492 ENABLE_SCLK_MIF, 4,
1493 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
1494 GATE(CLK_SCLK_MFC_PLL, "sclk_mfc_pll", "mout_mfc_pll_div2",
1495 ENABLE_SCLK_MIF, 3, CLK_IGNORE_UNUSED, 0),
1496 GATE(CLK_SCLK_BUS_PLL, "sclk_bus_pll", "mout_bus_pll_div2",
1497 ENABLE_SCLK_MIF, 2, CLK_IGNORE_UNUSED, 0),
1498 GATE(CLK_SCLK_BUS_PLL_APOLLO, "sclk_bus_pll_apollo", "sclk_bus_pll",
1499 ENABLE_SCLK_MIF, 1, CLK_IGNORE_UNUSED, 0),
1500 GATE(CLK_SCLK_BUS_PLL_ATLAS, "sclk_bus_pll_atlas", "sclk_bus_pll",
1501 ENABLE_SCLK_MIF, 0, CLK_IGNORE_UNUSED, 0),
1502 };
1503
1504 static const struct samsung_cmu_info mif_cmu_info __initconst = {
1505 .pll_clks = mif_pll_clks,
1506 .nr_pll_clks = ARRAY_SIZE(mif_pll_clks),
1507 .mux_clks = mif_mux_clks,
1508 .nr_mux_clks = ARRAY_SIZE(mif_mux_clks),
1509 .div_clks = mif_div_clks,
1510 .nr_div_clks = ARRAY_SIZE(mif_div_clks),
1511 .gate_clks = mif_gate_clks,
1512 .nr_gate_clks = ARRAY_SIZE(mif_gate_clks),
1513 .fixed_factor_clks = mif_fixed_factor_clks,
1514 .nr_fixed_factor_clks = ARRAY_SIZE(mif_fixed_factor_clks),
1515 .nr_clk_ids = MIF_NR_CLK,
1516 .clk_regs = mif_clk_regs,
1517 .nr_clk_regs = ARRAY_SIZE(mif_clk_regs),
1518 };
1519
exynos5433_cmu_mif_init(struct device_node * np)1520 static void __init exynos5433_cmu_mif_init(struct device_node *np)
1521 {
1522 samsung_cmu_register_one(np, &mif_cmu_info);
1523 }
1524 CLK_OF_DECLARE(exynos5433_cmu_mif, "samsung,exynos5433-cmu-mif",
1525 exynos5433_cmu_mif_init);
1526
1527 /*
1528 * Register offset definitions for CMU_PERIC
1529 */
1530 #define DIV_PERIC 0x0600
1531 #define DIV_STAT_PERIC 0x0700
1532 #define ENABLE_ACLK_PERIC 0x0800
1533 #define ENABLE_PCLK_PERIC0 0x0900
1534 #define ENABLE_PCLK_PERIC1 0x0904
1535 #define ENABLE_SCLK_PERIC 0x0A00
1536 #define ENABLE_IP_PERIC0 0x0B00
1537 #define ENABLE_IP_PERIC1 0x0B04
1538 #define ENABLE_IP_PERIC2 0x0B08
1539
1540 static const unsigned long peric_clk_regs[] __initconst = {
1541 DIV_PERIC,
1542 ENABLE_ACLK_PERIC,
1543 ENABLE_PCLK_PERIC0,
1544 ENABLE_PCLK_PERIC1,
1545 ENABLE_SCLK_PERIC,
1546 ENABLE_IP_PERIC0,
1547 ENABLE_IP_PERIC1,
1548 ENABLE_IP_PERIC2,
1549 };
1550
1551 static const struct samsung_div_clock peric_div_clks[] __initconst = {
1552 /* DIV_PERIC */
1553 DIV(CLK_DIV_SCLK_SCI, "div_sclk_sci", "oscclk", DIV_PERIC, 4, 4),
1554 DIV(CLK_DIV_SCLK_SC_IN, "div_sclk_sc_in", "oscclk", DIV_PERIC, 0, 4),
1555 };
1556
1557 static const struct samsung_gate_clock peric_gate_clks[] __initconst = {
1558 /* ENABLE_ACLK_PERIC */
1559 GATE(CLK_ACLK_AHB2APB_PERIC2P, "aclk_ahb2apb_peric2p", "aclk_peric_66",
1560 ENABLE_ACLK_PERIC, 3, CLK_IGNORE_UNUSED, 0),
1561 GATE(CLK_ACLK_AHB2APB_PERIC1P, "aclk_ahb2apb_peric1p", "aclk_peric_66",
1562 ENABLE_ACLK_PERIC, 2, CLK_IGNORE_UNUSED, 0),
1563 GATE(CLK_ACLK_AHB2APB_PERIC0P, "aclk_ahb2apb_peric0p", "aclk_peric_66",
1564 ENABLE_ACLK_PERIC, 1, CLK_IGNORE_UNUSED, 0),
1565 GATE(CLK_ACLK_PERICNP_66, "aclk_pericnp_66", "aclk_peric_66",
1566 ENABLE_ACLK_PERIC, 0, CLK_IGNORE_UNUSED, 0),
1567
1568 /* ENABLE_PCLK_PERIC0 */
1569 GATE(CLK_PCLK_SCI, "pclk_sci", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1570 31, CLK_SET_RATE_PARENT, 0),
1571 GATE(CLK_PCLK_GPIO_FINGER, "pclk_gpio_finger", "aclk_peric_66",
1572 ENABLE_PCLK_PERIC0, 30, CLK_IGNORE_UNUSED, 0),
1573 GATE(CLK_PCLK_GPIO_ESE, "pclk_gpio_ese", "aclk_peric_66",
1574 ENABLE_PCLK_PERIC0, 29, CLK_IGNORE_UNUSED, 0),
1575 GATE(CLK_PCLK_PWM, "pclk_pwm", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1576 28, CLK_SET_RATE_PARENT, 0),
1577 GATE(CLK_PCLK_SPDIF, "pclk_spdif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1578 26, CLK_SET_RATE_PARENT, 0),
1579 GATE(CLK_PCLK_PCM1, "pclk_pcm1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1580 25, CLK_SET_RATE_PARENT, 0),
1581 GATE(CLK_PCLK_I2S1, "pclk_i2s", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1582 24, CLK_SET_RATE_PARENT, 0),
1583 GATE(CLK_PCLK_SPI2, "pclk_spi2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1584 23, CLK_SET_RATE_PARENT, 0),
1585 GATE(CLK_PCLK_SPI1, "pclk_spi1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1586 22, CLK_SET_RATE_PARENT, 0),
1587 GATE(CLK_PCLK_SPI0, "pclk_spi0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1588 21, CLK_SET_RATE_PARENT, 0),
1589 GATE(CLK_PCLK_ADCIF, "pclk_adcif", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1590 20, CLK_SET_RATE_PARENT, 0),
1591 GATE(CLK_PCLK_GPIO_TOUCH, "pclk_gpio_touch", "aclk_peric_66",
1592 ENABLE_PCLK_PERIC0, 19, CLK_IGNORE_UNUSED, 0),
1593 GATE(CLK_PCLK_GPIO_NFC, "pclk_gpio_nfc", "aclk_peric_66",
1594 ENABLE_PCLK_PERIC0, 18, CLK_IGNORE_UNUSED, 0),
1595 GATE(CLK_PCLK_GPIO_PERIC, "pclk_gpio_peric", "aclk_peric_66",
1596 ENABLE_PCLK_PERIC0, 17, CLK_IGNORE_UNUSED, 0),
1597 GATE(CLK_PCLK_PMU_PERIC, "pclk_pmu_peric", "aclk_peric_66",
1598 ENABLE_PCLK_PERIC0, 16, CLK_SET_RATE_PARENT, 0),
1599 GATE(CLK_PCLK_SYSREG_PERIC, "pclk_sysreg_peric", "aclk_peric_66",
1600 ENABLE_PCLK_PERIC0, 15,
1601 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1602 GATE(CLK_PCLK_UART2, "pclk_uart2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1603 14, CLK_SET_RATE_PARENT, 0),
1604 GATE(CLK_PCLK_UART1, "pclk_uart1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1605 13, CLK_SET_RATE_PARENT, 0),
1606 GATE(CLK_PCLK_UART0, "pclk_uart0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1607 12, CLK_SET_RATE_PARENT, 0),
1608 GATE(CLK_PCLK_HSI2C3, "pclk_hsi2c3", "aclk_peric_66",
1609 ENABLE_PCLK_PERIC0, 11, CLK_SET_RATE_PARENT, 0),
1610 GATE(CLK_PCLK_HSI2C2, "pclk_hsi2c2", "aclk_peric_66",
1611 ENABLE_PCLK_PERIC0, 10, CLK_SET_RATE_PARENT, 0),
1612 GATE(CLK_PCLK_HSI2C1, "pclk_hsi2c1", "aclk_peric_66",
1613 ENABLE_PCLK_PERIC0, 9, CLK_SET_RATE_PARENT, 0),
1614 GATE(CLK_PCLK_HSI2C0, "pclk_hsi2c0", "aclk_peric_66",
1615 ENABLE_PCLK_PERIC0, 8, CLK_SET_RATE_PARENT, 0),
1616 GATE(CLK_PCLK_I2C7, "pclk_i2c7", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1617 7, CLK_SET_RATE_PARENT, 0),
1618 GATE(CLK_PCLK_I2C6, "pclk_i2c6", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1619 6, CLK_SET_RATE_PARENT, 0),
1620 GATE(CLK_PCLK_I2C5, "pclk_i2c5", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1621 5, CLK_SET_RATE_PARENT, 0),
1622 GATE(CLK_PCLK_I2C4, "pclk_i2c4", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1623 4, CLK_SET_RATE_PARENT, 0),
1624 GATE(CLK_PCLK_I2C3, "pclk_i2c3", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1625 3, CLK_SET_RATE_PARENT, 0),
1626 GATE(CLK_PCLK_I2C2, "pclk_i2c2", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1627 2, CLK_SET_RATE_PARENT, 0),
1628 GATE(CLK_PCLK_I2C1, "pclk_i2c1", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1629 1, CLK_SET_RATE_PARENT, 0),
1630 GATE(CLK_PCLK_I2C0, "pclk_i2c0", "aclk_peric_66", ENABLE_PCLK_PERIC0,
1631 0, CLK_SET_RATE_PARENT, 0),
1632
1633 /* ENABLE_PCLK_PERIC1 */
1634 GATE(CLK_PCLK_SPI4, "pclk_spi4", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1635 9, CLK_SET_RATE_PARENT, 0),
1636 GATE(CLK_PCLK_SPI3, "pclk_spi3", "aclk_peric_66", ENABLE_PCLK_PERIC1,
1637 8, CLK_SET_RATE_PARENT, 0),
1638 GATE(CLK_PCLK_HSI2C11, "pclk_hsi2c11", "aclk_peric_66",
1639 ENABLE_PCLK_PERIC1, 7, CLK_SET_RATE_PARENT, 0),
1640 GATE(CLK_PCLK_HSI2C10, "pclk_hsi2c10", "aclk_peric_66",
1641 ENABLE_PCLK_PERIC1, 6, CLK_SET_RATE_PARENT, 0),
1642 GATE(CLK_PCLK_HSI2C9, "pclk_hsi2c9", "aclk_peric_66",
1643 ENABLE_PCLK_PERIC1, 5, CLK_SET_RATE_PARENT, 0),
1644 GATE(CLK_PCLK_HSI2C8, "pclk_hsi2c8", "aclk_peric_66",
1645 ENABLE_PCLK_PERIC1, 4, CLK_SET_RATE_PARENT, 0),
1646 GATE(CLK_PCLK_HSI2C7, "pclk_hsi2c7", "aclk_peric_66",
1647 ENABLE_PCLK_PERIC1, 3, CLK_SET_RATE_PARENT, 0),
1648 GATE(CLK_PCLK_HSI2C6, "pclk_hsi2c6", "aclk_peric_66",
1649 ENABLE_PCLK_PERIC1, 2, CLK_SET_RATE_PARENT, 0),
1650 GATE(CLK_PCLK_HSI2C5, "pclk_hsi2c5", "aclk_peric_66",
1651 ENABLE_PCLK_PERIC1, 1, CLK_SET_RATE_PARENT, 0),
1652 GATE(CLK_PCLK_HSI2C4, "pclk_hsi2c4", "aclk_peric_66",
1653 ENABLE_PCLK_PERIC1, 0, CLK_SET_RATE_PARENT, 0),
1654
1655 /* ENABLE_SCLK_PERIC */
1656 GATE(CLK_SCLK_IOCLK_SPI4, "sclk_ioclk_spi4", "ioclk_spi4_clk_in",
1657 ENABLE_SCLK_PERIC, 21, CLK_SET_RATE_PARENT, 0),
1658 GATE(CLK_SCLK_IOCLK_SPI3, "sclk_ioclk_spi3", "ioclk_spi3_clk_in",
1659 ENABLE_SCLK_PERIC, 20, CLK_SET_RATE_PARENT, 0),
1660 GATE(CLK_SCLK_SPI4, "sclk_spi4", "sclk_spi4_peric", ENABLE_SCLK_PERIC,
1661 19, CLK_SET_RATE_PARENT, 0),
1662 GATE(CLK_SCLK_SPI3, "sclk_spi3", "sclk_spi3_peric", ENABLE_SCLK_PERIC,
1663 18, CLK_SET_RATE_PARENT, 0),
1664 GATE(CLK_SCLK_SCI, "sclk_sci", "div_sclk_sci", ENABLE_SCLK_PERIC,
1665 17, 0, 0),
1666 GATE(CLK_SCLK_SC_IN, "sclk_sc_in", "div_sclk_sc_in", ENABLE_SCLK_PERIC,
1667 16, 0, 0),
1668 GATE(CLK_SCLK_PWM, "sclk_pwm", "oscclk", ENABLE_SCLK_PERIC, 15, 0, 0),
1669 GATE(CLK_SCLK_IOCLK_SPI2, "sclk_ioclk_spi2", "ioclk_spi2_clk_in",
1670 ENABLE_SCLK_PERIC, 13, CLK_SET_RATE_PARENT, 0),
1671 GATE(CLK_SCLK_IOCLK_SPI1, "sclk_ioclk_spi1", "ioclk_spi1_clk_in",
1672 ENABLE_SCLK_PERIC, 12, CLK_SET_RATE_PARENT, 0),
1673 GATE(CLK_SCLK_IOCLK_SPI0, "sclk_ioclk_spi0", "ioclk_spi0_clk_in",
1674 ENABLE_SCLK_PERIC, 11, CLK_SET_RATE_PARENT, 0),
1675 GATE(CLK_SCLK_IOCLK_I2S1_BCLK, "sclk_ioclk_i2s1_bclk",
1676 "ioclk_i2s1_bclk_in", ENABLE_SCLK_PERIC, 10,
1677 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1678 GATE(CLK_SCLK_SPDIF, "sclk_spdif", "sclk_spdif_peric",
1679 ENABLE_SCLK_PERIC, 8, CLK_SET_RATE_PARENT, 0),
1680 GATE(CLK_SCLK_PCM1, "sclk_pcm1", "sclk_pcm1_peric",
1681 ENABLE_SCLK_PERIC, 7, CLK_SET_RATE_PARENT, 0),
1682 GATE(CLK_SCLK_I2S1, "sclk_i2s1", "sclk_i2s1_peric",
1683 ENABLE_SCLK_PERIC, 6,
1684 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1685 GATE(CLK_SCLK_SPI2, "sclk_spi2", "sclk_spi2_peric", ENABLE_SCLK_PERIC,
1686 5, CLK_SET_RATE_PARENT, 0),
1687 GATE(CLK_SCLK_SPI1, "sclk_spi1", "sclk_spi1_peric", ENABLE_SCLK_PERIC,
1688 4, CLK_SET_RATE_PARENT, 0),
1689 GATE(CLK_SCLK_SPI0, "sclk_spi0", "sclk_spi0_peric", ENABLE_SCLK_PERIC,
1690 3, CLK_SET_RATE_PARENT, 0),
1691 GATE(CLK_SCLK_UART2, "sclk_uart2", "sclk_uart2_peric",
1692 ENABLE_SCLK_PERIC, 2,
1693 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1694 GATE(CLK_SCLK_UART1, "sclk_uart1", "sclk_uart1_peric",
1695 ENABLE_SCLK_PERIC, 1,
1696 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1697 GATE(CLK_SCLK_UART0, "sclk_uart0", "sclk_uart0_peric",
1698 ENABLE_SCLK_PERIC, 0,
1699 CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, 0),
1700 };
1701
1702 static const struct samsung_cmu_info peric_cmu_info __initconst = {
1703 .div_clks = peric_div_clks,
1704 .nr_div_clks = ARRAY_SIZE(peric_div_clks),
1705 .gate_clks = peric_gate_clks,
1706 .nr_gate_clks = ARRAY_SIZE(peric_gate_clks),
1707 .nr_clk_ids = PERIC_NR_CLK,
1708 .clk_regs = peric_clk_regs,
1709 .nr_clk_regs = ARRAY_SIZE(peric_clk_regs),
1710 };
1711
exynos5433_cmu_peric_init(struct device_node * np)1712 static void __init exynos5433_cmu_peric_init(struct device_node *np)
1713 {
1714 samsung_cmu_register_one(np, &peric_cmu_info);
1715 }
1716
1717 CLK_OF_DECLARE(exynos5433_cmu_peric, "samsung,exynos5433-cmu-peric",
1718 exynos5433_cmu_peric_init);
1719
1720 /*
1721 * Register offset definitions for CMU_PERIS
1722 */
1723 #define ENABLE_ACLK_PERIS 0x0800
1724 #define ENABLE_PCLK_PERIS 0x0900
1725 #define ENABLE_PCLK_PERIS_SECURE_TZPC 0x0904
1726 #define ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF 0x0908
1727 #define ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF 0x090c
1728 #define ENABLE_PCLK_PERIS_SECURE_TOPRTC 0x0910
1729 #define ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF 0x0914
1730 #define ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF 0x0918
1731 #define ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF 0x091c
1732 #define ENABLE_SCLK_PERIS 0x0a00
1733 #define ENABLE_SCLK_PERIS_SECURE_SECKEY 0x0a04
1734 #define ENABLE_SCLK_PERIS_SECURE_CHIPID 0x0a08
1735 #define ENABLE_SCLK_PERIS_SECURE_TOPRTC 0x0a0c
1736 #define ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE 0x0a10
1737 #define ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT 0x0a14
1738 #define ENABLE_SCLK_PERIS_SECURE_OTP_CON 0x0a18
1739 #define ENABLE_IP_PERIS0 0x0b00
1740 #define ENABLE_IP_PERIS1 0x0b04
1741 #define ENABLE_IP_PERIS_SECURE_TZPC 0x0b08
1742 #define ENABLE_IP_PERIS_SECURE_SECKEY 0x0b0c
1743 #define ENABLE_IP_PERIS_SECURE_CHIPID 0x0b10
1744 #define ENABLE_IP_PERIS_SECURE_TOPRTC 0x0b14
1745 #define ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE 0x0b18
1746 #define ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT 0x0b1c
1747 #define ENABLE_IP_PERIS_SECURE_OTP_CON 0x0b20
1748
1749 static const unsigned long peris_clk_regs[] __initconst = {
1750 ENABLE_ACLK_PERIS,
1751 ENABLE_PCLK_PERIS,
1752 ENABLE_PCLK_PERIS_SECURE_TZPC,
1753 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF,
1754 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF,
1755 ENABLE_PCLK_PERIS_SECURE_TOPRTC,
1756 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF,
1757 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF,
1758 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF,
1759 ENABLE_SCLK_PERIS,
1760 ENABLE_SCLK_PERIS_SECURE_SECKEY,
1761 ENABLE_SCLK_PERIS_SECURE_CHIPID,
1762 ENABLE_SCLK_PERIS_SECURE_TOPRTC,
1763 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE,
1764 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT,
1765 ENABLE_SCLK_PERIS_SECURE_OTP_CON,
1766 ENABLE_IP_PERIS0,
1767 ENABLE_IP_PERIS1,
1768 ENABLE_IP_PERIS_SECURE_TZPC,
1769 ENABLE_IP_PERIS_SECURE_SECKEY,
1770 ENABLE_IP_PERIS_SECURE_CHIPID,
1771 ENABLE_IP_PERIS_SECURE_TOPRTC,
1772 ENABLE_IP_PERIS_SECURE_CUSTOM_EFUSE,
1773 ENABLE_IP_PERIS_SECURE_ANTIBRK_CNT,
1774 ENABLE_IP_PERIS_SECURE_OTP_CON,
1775 };
1776
1777 static const struct samsung_gate_clock peris_gate_clks[] __initconst = {
1778 /* ENABLE_ACLK_PERIS */
1779 GATE(CLK_ACLK_AHB2APB_PERIS1P, "aclk_ahb2apb_peris1p", "aclk_peris_66",
1780 ENABLE_ACLK_PERIS, 2, CLK_IGNORE_UNUSED, 0),
1781 GATE(CLK_ACLK_AHB2APB_PERIS0P, "aclk_ahb2apb_peris0p", "aclk_peris_66",
1782 ENABLE_ACLK_PERIS, 1, CLK_IGNORE_UNUSED, 0),
1783 GATE(CLK_ACLK_PERISNP_66, "aclk_perisnp_66", "aclk_peris_66",
1784 ENABLE_ACLK_PERIS, 0, CLK_IGNORE_UNUSED, 0),
1785
1786 /* ENABLE_PCLK_PERIS */
1787 GATE(CLK_PCLK_HPM_APBIF, "pclk_hpm_apbif", "aclk_peris_66",
1788 ENABLE_PCLK_PERIS, 30, CLK_IGNORE_UNUSED, 0),
1789 GATE(CLK_PCLK_TMU1_APBIF, "pclk_tmu1_apbif", "aclk_peris_66",
1790 ENABLE_PCLK_PERIS, 24, CLK_IGNORE_UNUSED, 0),
1791 GATE(CLK_PCLK_TMU0_APBIF, "pclk_tmu0_apbif", "aclk_peris_66",
1792 ENABLE_PCLK_PERIS, 23, CLK_IGNORE_UNUSED, 0),
1793 GATE(CLK_PCLK_PMU_PERIS, "pclk_pmu_peris", "aclk_peris_66",
1794 ENABLE_PCLK_PERIS, 22, CLK_IGNORE_UNUSED, 0),
1795 GATE(CLK_PCLK_SYSREG_PERIS, "pclk_sysreg_peris", "aclk_peris_66",
1796 ENABLE_PCLK_PERIS, 21, CLK_IGNORE_UNUSED, 0),
1797 GATE(CLK_PCLK_CMU_TOP_APBIF, "pclk_cmu_top_apbif", "aclk_peris_66",
1798 ENABLE_PCLK_PERIS, 20, CLK_IGNORE_UNUSED, 0),
1799 GATE(CLK_PCLK_WDT_APOLLO, "pclk_wdt_apollo", "aclk_peris_66",
1800 ENABLE_PCLK_PERIS, 17, CLK_IGNORE_UNUSED, 0),
1801 GATE(CLK_PCLK_WDT_ATLAS, "pclk_wdt_atlas", "aclk_peris_66",
1802 ENABLE_PCLK_PERIS, 16, CLK_IGNORE_UNUSED, 0),
1803 GATE(CLK_PCLK_MCT, "pclk_mct", "aclk_peris_66",
1804 ENABLE_PCLK_PERIS, 15, CLK_IGNORE_UNUSED, 0),
1805 GATE(CLK_PCLK_HDMI_CEC, "pclk_hdmi_cec", "aclk_peris_66",
1806 ENABLE_PCLK_PERIS, 14, CLK_IGNORE_UNUSED, 0),
1807
1808 /* ENABLE_PCLK_PERIS_SECURE_TZPC */
1809 GATE(CLK_PCLK_TZPC12, "pclk_tzpc12", "aclk_peris_66",
1810 ENABLE_PCLK_PERIS_SECURE_TZPC, 12, CLK_IGNORE_UNUSED, 0),
1811 GATE(CLK_PCLK_TZPC11, "pclk_tzpc11", "aclk_peris_66",
1812 ENABLE_PCLK_PERIS_SECURE_TZPC, 11, CLK_IGNORE_UNUSED, 0),
1813 GATE(CLK_PCLK_TZPC10, "pclk_tzpc10", "aclk_peris_66",
1814 ENABLE_PCLK_PERIS_SECURE_TZPC, 10, CLK_IGNORE_UNUSED, 0),
1815 GATE(CLK_PCLK_TZPC9, "pclk_tzpc9", "aclk_peris_66",
1816 ENABLE_PCLK_PERIS_SECURE_TZPC, 9, CLK_IGNORE_UNUSED, 0),
1817 GATE(CLK_PCLK_TZPC8, "pclk_tzpc8", "aclk_peris_66",
1818 ENABLE_PCLK_PERIS_SECURE_TZPC, 8, CLK_IGNORE_UNUSED, 0),
1819 GATE(CLK_PCLK_TZPC7, "pclk_tzpc7", "aclk_peris_66",
1820 ENABLE_PCLK_PERIS_SECURE_TZPC, 7, CLK_IGNORE_UNUSED, 0),
1821 GATE(CLK_PCLK_TZPC6, "pclk_tzpc6", "aclk_peris_66",
1822 ENABLE_PCLK_PERIS_SECURE_TZPC, 6, CLK_IGNORE_UNUSED, 0),
1823 GATE(CLK_PCLK_TZPC5, "pclk_tzpc5", "aclk_peris_66",
1824 ENABLE_PCLK_PERIS_SECURE_TZPC, 5, CLK_IGNORE_UNUSED, 0),
1825 GATE(CLK_PCLK_TZPC4, "pclk_tzpc4", "aclk_peris_66",
1826 ENABLE_PCLK_PERIS_SECURE_TZPC, 4, CLK_IGNORE_UNUSED, 0),
1827 GATE(CLK_PCLK_TZPC3, "pclk_tzpc3", "aclk_peris_66",
1828 ENABLE_PCLK_PERIS_SECURE_TZPC, 3, CLK_IGNORE_UNUSED, 0),
1829 GATE(CLK_PCLK_TZPC2, "pclk_tzpc2", "aclk_peris_66",
1830 ENABLE_PCLK_PERIS_SECURE_TZPC, 2, CLK_IGNORE_UNUSED, 0),
1831 GATE(CLK_PCLK_TZPC1, "pclk_tzpc1", "aclk_peris_66",
1832 ENABLE_PCLK_PERIS_SECURE_TZPC, 1, CLK_IGNORE_UNUSED, 0),
1833 GATE(CLK_PCLK_TZPC0, "pclk_tzpc0", "aclk_peris_66",
1834 ENABLE_PCLK_PERIS_SECURE_TZPC, 0, CLK_IGNORE_UNUSED, 0),
1835
1836 /* ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF */
1837 GATE(CLK_PCLK_SECKEY_APBIF, "pclk_seckey_apbif", "aclk_peris_66",
1838 ENABLE_PCLK_PERIS_SECURE_SECKEY_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1839
1840 /* ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF */
1841 GATE(CLK_PCLK_CHIPID_APBIF, "pclk_chipid_apbif", "aclk_peris_66",
1842 ENABLE_PCLK_PERIS_SECURE_CHIPID_APBIF, 0, CLK_IGNORE_UNUSED, 0),
1843
1844 /* ENABLE_PCLK_PERIS_SECURE_TOPRTC */
1845 GATE(CLK_PCLK_TOPRTC, "pclk_toprtc", "aclk_peris_66",
1846 ENABLE_PCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1847
1848 /* ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF */
1849 GATE(CLK_PCLK_CUSTOM_EFUSE_APBIF, "pclk_custom_efuse_apbif",
1850 "aclk_peris_66",
1851 ENABLE_PCLK_PERIS_SECURE_CUSTOM_EFUSE_APBIF, 0, 0, 0),
1852
1853 /* ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF */
1854 GATE(CLK_PCLK_ANTIRBK_CNT_APBIF, "pclk_antirbk_cnt_apbif",
1855 "aclk_peris_66",
1856 ENABLE_PCLK_PERIS_SECURE_ANTIRBK_CNT_APBIF, 0, 0, 0),
1857
1858 /* ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF */
1859 GATE(CLK_PCLK_OTP_CON_APBIF, "pclk_otp_con_apbif",
1860 "aclk_peris_66",
1861 ENABLE_PCLK_PERIS_SECURE_OTP_CON_APBIF, 0, 0, 0),
1862
1863 /* ENABLE_SCLK_PERIS */
1864 GATE(CLK_SCLK_ASV_TB, "sclk_asv_tb", "oscclk_efuse_common",
1865 ENABLE_SCLK_PERIS, 10, 0, 0),
1866 GATE(CLK_SCLK_TMU1, "sclk_tmu1", "oscclk_efuse_common",
1867 ENABLE_SCLK_PERIS, 4, 0, 0),
1868 GATE(CLK_SCLK_TMU0, "sclk_tmu0", "oscclk_efuse_common",
1869 ENABLE_SCLK_PERIS, 3, 0, 0),
1870
1871 /* ENABLE_SCLK_PERIS_SECURE_SECKEY */
1872 GATE(CLK_SCLK_SECKEY, "sclk_seckey", "oscclk_efuse_common",
1873 ENABLE_SCLK_PERIS_SECURE_SECKEY, 0, CLK_IGNORE_UNUSED, 0),
1874
1875 /* ENABLE_SCLK_PERIS_SECURE_CHIPID */
1876 GATE(CLK_SCLK_CHIPID, "sclk_chipid", "oscclk_efuse_common",
1877 ENABLE_SCLK_PERIS_SECURE_CHIPID, 0, CLK_IGNORE_UNUSED, 0),
1878
1879 /* ENABLE_SCLK_PERIS_SECURE_TOPRTC */
1880 GATE(CLK_SCLK_TOPRTC, "sclk_toprtc", "oscclk_efuse_common",
1881 ENABLE_SCLK_PERIS_SECURE_TOPRTC, 0, 0, 0),
1882
1883 /* ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE */
1884 GATE(CLK_SCLK_CUSTOM_EFUSE, "sclk_custom_efuse", "oscclk_efuse_common",
1885 ENABLE_SCLK_PERIS_SECURE_CUSTOM_EFUSE, 0, 0, 0),
1886
1887 /* ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT */
1888 GATE(CLK_SCLK_ANTIRBK_CNT, "sclk_antirbk_cnt", "oscclk_efuse_common",
1889 ENABLE_SCLK_PERIS_SECURE_ANTIRBK_CNT, 0, 0, 0),
1890
1891 /* ENABLE_SCLK_PERIS_SECURE_OTP_CON */
1892 GATE(CLK_SCLK_OTP_CON, "sclk_otp_con", "oscclk_efuse_common",
1893 ENABLE_SCLK_PERIS_SECURE_OTP_CON, 0, 0, 0),
1894 };
1895
1896 static const struct samsung_cmu_info peris_cmu_info __initconst = {
1897 .gate_clks = peris_gate_clks,
1898 .nr_gate_clks = ARRAY_SIZE(peris_gate_clks),
1899 .nr_clk_ids = PERIS_NR_CLK,
1900 .clk_regs = peris_clk_regs,
1901 .nr_clk_regs = ARRAY_SIZE(peris_clk_regs),
1902 };
1903
exynos5433_cmu_peris_init(struct device_node * np)1904 static void __init exynos5433_cmu_peris_init(struct device_node *np)
1905 {
1906 samsung_cmu_register_one(np, &peris_cmu_info);
1907 }
1908
1909 CLK_OF_DECLARE(exynos5433_cmu_peris, "samsung,exynos5433-cmu-peris",
1910 exynos5433_cmu_peris_init);
1911
1912 /*
1913 * Register offset definitions for CMU_FSYS
1914 */
1915 #define MUX_SEL_FSYS0 0x0200
1916 #define MUX_SEL_FSYS1 0x0204
1917 #define MUX_SEL_FSYS2 0x0208
1918 #define MUX_SEL_FSYS3 0x020c
1919 #define MUX_SEL_FSYS4 0x0210
1920 #define MUX_ENABLE_FSYS0 0x0300
1921 #define MUX_ENABLE_FSYS1 0x0304
1922 #define MUX_ENABLE_FSYS2 0x0308
1923 #define MUX_ENABLE_FSYS3 0x030c
1924 #define MUX_ENABLE_FSYS4 0x0310
1925 #define MUX_STAT_FSYS0 0x0400
1926 #define MUX_STAT_FSYS1 0x0404
1927 #define MUX_STAT_FSYS2 0x0408
1928 #define MUX_STAT_FSYS3 0x040c
1929 #define MUX_STAT_FSYS4 0x0410
1930 #define MUX_IGNORE_FSYS2 0x0508
1931 #define MUX_IGNORE_FSYS3 0x050c
1932 #define ENABLE_ACLK_FSYS0 0x0800
1933 #define ENABLE_ACLK_FSYS1 0x0804
1934 #define ENABLE_PCLK_FSYS 0x0900
1935 #define ENABLE_SCLK_FSYS 0x0a00
1936 #define ENABLE_IP_FSYS0 0x0b00
1937 #define ENABLE_IP_FSYS1 0x0b04
1938
1939 /* list of all parent clock list */
1940 PNAME(mout_sclk_ufs_mphy_user_p) = { "oscclk", "sclk_ufs_mphy", };
1941 PNAME(mout_aclk_fsys_200_user_p) = { "oscclk", "aclk_fsys_200", };
1942 PNAME(mout_sclk_pcie_100_user_p) = { "oscclk", "sclk_pcie_100_fsys",};
1943 PNAME(mout_sclk_ufsunipro_user_p) = { "oscclk", "sclk_ufsunipro_fsys",};
1944 PNAME(mout_sclk_mmc2_user_p) = { "oscclk", "sclk_mmc2_fsys", };
1945 PNAME(mout_sclk_mmc1_user_p) = { "oscclk", "sclk_mmc1_fsys", };
1946 PNAME(mout_sclk_mmc0_user_p) = { "oscclk", "sclk_mmc0_fsys", };
1947 PNAME(mout_sclk_usbhost30_user_p) = { "oscclk", "sclk_usbhost30_fsys",};
1948 PNAME(mout_sclk_usbdrd30_user_p) = { "oscclk", "sclk_usbdrd30_fsys", };
1949
1950 PNAME(mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p)
1951 = { "oscclk", "phyclk_usbhost30_uhost30_pipe_pclk_phy", };
1952 PNAME(mout_phyclk_usbhost30_uhost30_phyclock_user_p)
1953 = { "oscclk", "phyclk_usbhost30_uhost30_phyclock_phy", };
1954 PNAME(mout_phyclk_usbhost20_phy_hsic1_p)
1955 = { "oscclk", "phyclk_usbhost20_phy_hsic1_phy", };
1956 PNAME(mout_phyclk_usbhost20_phy_clk48mohci_user_p)
1957 = { "oscclk", "phyclk_usbhost20_phy_clk48mohci_phy", };
1958 PNAME(mout_phyclk_usbhost20_phy_phyclock_user_p)
1959 = { "oscclk", "phyclk_usbhost20_phy_phyclock_phy", };
1960 PNAME(mout_phyclk_usbhost20_phy_freeclk_user_p)
1961 = { "oscclk", "phyclk_usbhost20_phy_freeclk_phy", };
1962 PNAME(mout_phyclk_usbdrd30_udrd30_pipe_pclk_p)
1963 = { "oscclk", "phyclk_usbdrd30_udrd30_pipe_pclk_phy", };
1964 PNAME(mout_phyclk_usbdrd30_udrd30_phyclock_user_p)
1965 = { "oscclk", "phyclk_usbdrd30_udrd30_phyclock_phy", };
1966 PNAME(mout_phyclk_ufs_rx1_symbol_user_p)
1967 = { "oscclk", "phyclk_ufs_rx1_symbol_phy", };
1968 PNAME(mout_phyclk_ufs_rx0_symbol_user_p)
1969 = { "oscclk", "phyclk_ufs_rx0_symbol_phy", };
1970 PNAME(mout_phyclk_ufs_tx1_symbol_user_p)
1971 = { "oscclk", "phyclk_ufs_tx1_symbol_phy", };
1972 PNAME(mout_phyclk_ufs_tx0_symbol_user_p)
1973 = { "oscclk", "phyclk_ufs_tx0_symbol_phy", };
1974 PNAME(mout_phyclk_lli_mphy_to_ufs_user_p)
1975 = { "oscclk", "phyclk_lli_mphy_to_ufs_phy", };
1976 PNAME(mout_sclk_mphy_p)
1977 = { "mout_sclk_ufs_mphy_user",
1978 "mout_phyclk_lli_mphy_to_ufs_user", };
1979
1980 static const unsigned long fsys_clk_regs[] __initconst = {
1981 MUX_SEL_FSYS0,
1982 MUX_SEL_FSYS1,
1983 MUX_SEL_FSYS2,
1984 MUX_SEL_FSYS3,
1985 MUX_SEL_FSYS4,
1986 MUX_ENABLE_FSYS0,
1987 MUX_ENABLE_FSYS1,
1988 MUX_ENABLE_FSYS2,
1989 MUX_ENABLE_FSYS3,
1990 MUX_ENABLE_FSYS4,
1991 MUX_IGNORE_FSYS2,
1992 MUX_IGNORE_FSYS3,
1993 ENABLE_ACLK_FSYS0,
1994 ENABLE_ACLK_FSYS1,
1995 ENABLE_PCLK_FSYS,
1996 ENABLE_SCLK_FSYS,
1997 ENABLE_IP_FSYS0,
1998 ENABLE_IP_FSYS1,
1999 };
2000
2001 static const struct samsung_clk_reg_dump fsys_suspend_regs[] = {
2002 { MUX_SEL_FSYS0, 0 },
2003 { MUX_SEL_FSYS1, 0 },
2004 { MUX_SEL_FSYS2, 0 },
2005 { MUX_SEL_FSYS3, 0 },
2006 { MUX_SEL_FSYS4, 0 },
2007 };
2008
2009 static const struct samsung_fixed_rate_clock fsys_fixed_clks[] __initconst = {
2010 /* PHY clocks from USBDRD30_PHY */
2011 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_PHY,
2012 "phyclk_usbdrd30_udrd30_phyclock_phy", NULL,
2013 0, 60000000),
2014 FRATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_PHY,
2015 "phyclk_usbdrd30_udrd30_pipe_pclk_phy", NULL,
2016 0, 125000000),
2017 /* PHY clocks from USBHOST30_PHY */
2018 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_PHY,
2019 "phyclk_usbhost30_uhost30_phyclock_phy", NULL,
2020 0, 60000000),
2021 FRATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_PHY,
2022 "phyclk_usbhost30_uhost30_pipe_pclk_phy", NULL,
2023 0, 125000000),
2024 /* PHY clocks from USBHOST20_PHY */
2025 FRATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK_PHY,
2026 "phyclk_usbhost20_phy_freeclk_phy", NULL, 0, 60000000),
2027 FRATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK_PHY,
2028 "phyclk_usbhost20_phy_phyclock_phy", NULL, 0, 60000000),
2029 FRATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI_PHY,
2030 "phyclk_usbhost20_phy_clk48mohci_phy", NULL,
2031 0, 48000000),
2032 FRATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1_PHY,
2033 "phyclk_usbhost20_phy_hsic1_phy", NULL, 0,
2034 60000000),
2035 /* PHY clocks from UFS_PHY */
2036 FRATE(CLK_PHYCLK_UFS_TX0_SYMBOL_PHY, "phyclk_ufs_tx0_symbol_phy",
2037 NULL, 0, 300000000),
2038 FRATE(CLK_PHYCLK_UFS_RX0_SYMBOL_PHY, "phyclk_ufs_rx0_symbol_phy",
2039 NULL, 0, 300000000),
2040 FRATE(CLK_PHYCLK_UFS_TX1_SYMBOL_PHY, "phyclk_ufs_tx1_symbol_phy",
2041 NULL, 0, 300000000),
2042 FRATE(CLK_PHYCLK_UFS_RX1_SYMBOL_PHY, "phyclk_ufs_rx1_symbol_phy",
2043 NULL, 0, 300000000),
2044 /* PHY clocks from LLI_PHY */
2045 FRATE(CLK_PHYCLK_LLI_MPHY_TO_UFS_PHY, "phyclk_lli_mphy_to_ufs_phy",
2046 NULL, 0, 26000000),
2047 };
2048
2049 static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
2050 /* MUX_SEL_FSYS0 */
2051 MUX(CLK_MOUT_SCLK_UFS_MPHY_USER, "mout_sclk_ufs_mphy_user",
2052 mout_sclk_ufs_mphy_user_p, MUX_SEL_FSYS0, 4, 1),
2053 MUX(CLK_MOUT_ACLK_FSYS_200_USER, "mout_aclk_fsys_200_user",
2054 mout_aclk_fsys_200_user_p, MUX_SEL_FSYS0, 0, 1),
2055
2056 /* MUX_SEL_FSYS1 */
2057 MUX(CLK_MOUT_SCLK_PCIE_100_USER, "mout_sclk_pcie_100_user",
2058 mout_sclk_pcie_100_user_p, MUX_SEL_FSYS1, 28, 1),
2059 MUX(CLK_MOUT_SCLK_UFSUNIPRO_USER, "mout_sclk_ufsunipro_user",
2060 mout_sclk_ufsunipro_user_p, MUX_SEL_FSYS1, 24, 1),
2061 MUX(CLK_MOUT_SCLK_MMC2_USER, "mout_sclk_mmc2_user",
2062 mout_sclk_mmc2_user_p, MUX_SEL_FSYS1, 20, 1),
2063 MUX(CLK_MOUT_SCLK_MMC1_USER, "mout_sclk_mmc1_user",
2064 mout_sclk_mmc1_user_p, MUX_SEL_FSYS1, 16, 1),
2065 MUX(CLK_MOUT_SCLK_MMC0_USER, "mout_sclk_mmc0_user",
2066 mout_sclk_mmc0_user_p, MUX_SEL_FSYS1, 12, 1),
2067 MUX(CLK_MOUT_SCLK_USBHOST30_USER, "mout_sclk_usbhost30_user",
2068 mout_sclk_usbhost30_user_p, MUX_SEL_FSYS1, 4, 1),
2069 MUX(CLK_MOUT_SCLK_USBDRD30_USER, "mout_sclk_usbdrd30_user",
2070 mout_sclk_usbdrd30_user_p, MUX_SEL_FSYS1, 0, 1),
2071
2072 /* MUX_SEL_FSYS2 */
2073 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK_USER,
2074 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2075 mout_phyclk_usbhost30_uhost30_pipe_pclk_user_p,
2076 MUX_SEL_FSYS2, 28, 1),
2077 MUX(CLK_MOUT_PHYCLK_USBHOST30_UHOST30_PHYCLOCK_USER,
2078 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2079 mout_phyclk_usbhost30_uhost30_phyclock_user_p,
2080 MUX_SEL_FSYS2, 24, 1),
2081 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_HSIC1_USER,
2082 "mout_phyclk_usbhost20_phy_hsic1",
2083 mout_phyclk_usbhost20_phy_hsic1_p,
2084 MUX_SEL_FSYS2, 20, 1),
2085 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_CLK48MOHCI_USER,
2086 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2087 mout_phyclk_usbhost20_phy_clk48mohci_user_p,
2088 MUX_SEL_FSYS2, 16, 1),
2089 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHYCLOCK_USER,
2090 "mout_phyclk_usbhost20_phy_phyclock_user",
2091 mout_phyclk_usbhost20_phy_phyclock_user_p,
2092 MUX_SEL_FSYS2, 12, 1),
2093 MUX(CLK_MOUT_PHYCLK_USBHOST20_PHY_PHY_FREECLK_USER,
2094 "mout_phyclk_usbhost20_phy_freeclk_user",
2095 mout_phyclk_usbhost20_phy_freeclk_user_p,
2096 MUX_SEL_FSYS2, 8, 1),
2097 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK_USER,
2098 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2099 mout_phyclk_usbdrd30_udrd30_pipe_pclk_p,
2100 MUX_SEL_FSYS2, 4, 1),
2101 MUX(CLK_MOUT_PHYCLK_USBDRD30_UDRD30_PHYCLOCK_USER,
2102 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2103 mout_phyclk_usbdrd30_udrd30_phyclock_user_p,
2104 MUX_SEL_FSYS2, 0, 1),
2105
2106 /* MUX_SEL_FSYS3 */
2107 MUX(CLK_MOUT_PHYCLK_UFS_RX1_SYMBOL_USER,
2108 "mout_phyclk_ufs_rx1_symbol_user",
2109 mout_phyclk_ufs_rx1_symbol_user_p,
2110 MUX_SEL_FSYS3, 16, 1),
2111 MUX(CLK_MOUT_PHYCLK_UFS_RX0_SYMBOL_USER,
2112 "mout_phyclk_ufs_rx0_symbol_user",
2113 mout_phyclk_ufs_rx0_symbol_user_p,
2114 MUX_SEL_FSYS3, 12, 1),
2115 MUX(CLK_MOUT_PHYCLK_UFS_TX1_SYMBOL_USER,
2116 "mout_phyclk_ufs_tx1_symbol_user",
2117 mout_phyclk_ufs_tx1_symbol_user_p,
2118 MUX_SEL_FSYS3, 8, 1),
2119 MUX(CLK_MOUT_PHYCLK_UFS_TX0_SYMBOL_USER,
2120 "mout_phyclk_ufs_tx0_symbol_user",
2121 mout_phyclk_ufs_tx0_symbol_user_p,
2122 MUX_SEL_FSYS3, 4, 1),
2123 MUX(CLK_MOUT_PHYCLK_LLI_MPHY_TO_UFS_USER,
2124 "mout_phyclk_lli_mphy_to_ufs_user",
2125 mout_phyclk_lli_mphy_to_ufs_user_p,
2126 MUX_SEL_FSYS3, 0, 1),
2127
2128 /* MUX_SEL_FSYS4 */
2129 MUX(CLK_MOUT_SCLK_MPHY, "mout_sclk_mphy", mout_sclk_mphy_p,
2130 MUX_SEL_FSYS4, 0, 1),
2131 };
2132
2133 static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
2134 /* ENABLE_ACLK_FSYS0 */
2135 GATE(CLK_ACLK_PCIE, "aclk_pcie", "mout_aclk_fsys_200_user",
2136 ENABLE_ACLK_FSYS0, 13, CLK_IGNORE_UNUSED, 0),
2137 GATE(CLK_ACLK_PDMA1, "aclk_pdma1", "mout_aclk_fsys_200_user",
2138 ENABLE_ACLK_FSYS0, 11, CLK_IGNORE_UNUSED, 0),
2139 GATE(CLK_ACLK_TSI, "aclk_tsi", "mout_aclk_fsys_200_user",
2140 ENABLE_ACLK_FSYS0, 10, CLK_IGNORE_UNUSED, 0),
2141 GATE(CLK_ACLK_MMC2, "aclk_mmc2", "mout_aclk_fsys_200_user",
2142 ENABLE_ACLK_FSYS0, 8, CLK_IGNORE_UNUSED, 0),
2143 GATE(CLK_ACLK_MMC1, "aclk_mmc1", "mout_aclk_fsys_200_user",
2144 ENABLE_ACLK_FSYS0, 7, CLK_IGNORE_UNUSED, 0),
2145 GATE(CLK_ACLK_MMC0, "aclk_mmc0", "mout_aclk_fsys_200_user",
2146 ENABLE_ACLK_FSYS0, 6, CLK_IGNORE_UNUSED, 0),
2147 GATE(CLK_ACLK_UFS, "aclk_ufs", "mout_aclk_fsys_200_user",
2148 ENABLE_ACLK_FSYS0, 5, CLK_IGNORE_UNUSED, 0),
2149 GATE(CLK_ACLK_USBHOST20, "aclk_usbhost20", "mout_aclk_fsys_200_user",
2150 ENABLE_ACLK_FSYS0, 3, CLK_IGNORE_UNUSED, 0),
2151 GATE(CLK_ACLK_USBHOST30, "aclk_usbhost30", "mout_aclk_fsys_200_user",
2152 ENABLE_ACLK_FSYS0, 2, CLK_IGNORE_UNUSED, 0),
2153 GATE(CLK_ACLK_USBDRD30, "aclk_usbdrd30", "mout_aclk_fsys_200_user",
2154 ENABLE_ACLK_FSYS0, 1, CLK_IGNORE_UNUSED, 0),
2155 GATE(CLK_ACLK_PDMA0, "aclk_pdma0", "mout_aclk_fsys_200_user",
2156 ENABLE_ACLK_FSYS0, 0, CLK_IGNORE_UNUSED, 0),
2157
2158 /* ENABLE_ACLK_FSYS1 */
2159 GATE(CLK_ACLK_XIU_FSYSPX, "aclk_xiu_fsyspx", "mout_aclk_fsys_200_user",
2160 ENABLE_ACLK_FSYS1, 27, CLK_IGNORE_UNUSED, 0),
2161 GATE(CLK_ACLK_AHB_USBLINKH1, "aclk_ahb_usblinkh1",
2162 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2163 26, CLK_IGNORE_UNUSED, 0),
2164 GATE(CLK_ACLK_SMMU_PDMA1, "aclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2165 ENABLE_ACLK_FSYS1, 25, CLK_IGNORE_UNUSED, 0),
2166 GATE(CLK_ACLK_BTS_PCIE, "aclk_bts_pcie", "mout_aclk_fsys_200_user",
2167 ENABLE_ACLK_FSYS1, 24, CLK_IGNORE_UNUSED, 0),
2168 GATE(CLK_ACLK_AXIUS_PDMA1, "aclk_axius_pdma1",
2169 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2170 22, CLK_IGNORE_UNUSED, 0),
2171 GATE(CLK_ACLK_SMMU_PDMA0, "aclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2172 ENABLE_ACLK_FSYS1, 17, CLK_IGNORE_UNUSED, 0),
2173 GATE(CLK_ACLK_BTS_UFS, "aclk_bts_ufs", "mout_aclk_fsys_200_user",
2174 ENABLE_ACLK_FSYS1, 14, CLK_IGNORE_UNUSED, 0),
2175 GATE(CLK_ACLK_BTS_USBHOST30, "aclk_bts_usbhost30",
2176 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2177 13, 0, 0),
2178 GATE(CLK_ACLK_BTS_USBDRD30, "aclk_bts_usbdrd30",
2179 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2180 12, 0, 0),
2181 GATE(CLK_ACLK_AXIUS_PDMA0, "aclk_axius_pdma0",
2182 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2183 11, CLK_IGNORE_UNUSED, 0),
2184 GATE(CLK_ACLK_AXIUS_USBHS, "aclk_axius_usbhs",
2185 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2186 10, CLK_IGNORE_UNUSED, 0),
2187 GATE(CLK_ACLK_AXIUS_FSYSSX, "aclk_axius_fsyssx",
2188 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2189 9, CLK_IGNORE_UNUSED, 0),
2190 GATE(CLK_ACLK_AHB2APB_FSYSP, "aclk_ahb2apb_fsysp",
2191 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2192 8, CLK_IGNORE_UNUSED, 0),
2193 GATE(CLK_ACLK_AHB2AXI_USBHS, "aclk_ahb2axi_usbhs",
2194 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2195 7, CLK_IGNORE_UNUSED, 0),
2196 GATE(CLK_ACLK_AHB_USBLINKH0, "aclk_ahb_usblinkh0",
2197 "mout_aclk_fsys_200_user", ENABLE_ACLK_FSYS1,
2198 6, CLK_IGNORE_UNUSED, 0),
2199 GATE(CLK_ACLK_AHB_USBHS, "aclk_ahb_usbhs", "mout_aclk_fsys_200_user",
2200 ENABLE_ACLK_FSYS1, 5, CLK_IGNORE_UNUSED, 0),
2201 GATE(CLK_ACLK_AHB_FSYSH, "aclk_ahb_fsysh", "mout_aclk_fsys_200_user",
2202 ENABLE_ACLK_FSYS1, 4, CLK_IGNORE_UNUSED, 0),
2203 GATE(CLK_ACLK_XIU_FSYSX, "aclk_xiu_fsysx", "mout_aclk_fsys_200_user",
2204 ENABLE_ACLK_FSYS1, 3, CLK_IGNORE_UNUSED, 0),
2205 GATE(CLK_ACLK_XIU_FSYSSX, "aclk_xiu_fsyssx", "mout_aclk_fsys_200_user",
2206 ENABLE_ACLK_FSYS1, 2, CLK_IGNORE_UNUSED, 0),
2207 GATE(CLK_ACLK_FSYSNP_200, "aclk_fsysnp_200", "mout_aclk_fsys_200_user",
2208 ENABLE_ACLK_FSYS1, 1, CLK_IGNORE_UNUSED, 0),
2209 GATE(CLK_ACLK_FSYSND_200, "aclk_fsysnd_200", "mout_aclk_fsys_200_user",
2210 ENABLE_ACLK_FSYS1, 0, CLK_IGNORE_UNUSED, 0),
2211
2212 /* ENABLE_PCLK_FSYS */
2213 GATE(CLK_PCLK_PCIE_CTRL, "pclk_pcie_ctrl", "mout_aclk_fsys_200_user",
2214 ENABLE_PCLK_FSYS, 17, CLK_IGNORE_UNUSED, 0),
2215 GATE(CLK_PCLK_SMMU_PDMA1, "pclk_smmu_pdma1", "mout_aclk_fsys_200_user",
2216 ENABLE_PCLK_FSYS, 16, CLK_IGNORE_UNUSED, 0),
2217 GATE(CLK_PCLK_PCIE_PHY, "pclk_pcie_phy", "mout_aclk_fsys_200_user",
2218 ENABLE_PCLK_FSYS, 14, CLK_IGNORE_UNUSED, 0),
2219 GATE(CLK_PCLK_BTS_PCIE, "pclk_bts_pcie", "mout_aclk_fsys_200_user",
2220 ENABLE_PCLK_FSYS, 13, CLK_IGNORE_UNUSED, 0),
2221 GATE(CLK_PCLK_SMMU_PDMA0, "pclk_smmu_pdma0", "mout_aclk_fsys_200_user",
2222 ENABLE_PCLK_FSYS, 8, CLK_IGNORE_UNUSED, 0),
2223 GATE(CLK_PCLK_BTS_UFS, "pclk_bts_ufs", "mout_aclk_fsys_200_user",
2224 ENABLE_PCLK_FSYS, 5, 0, 0),
2225 GATE(CLK_PCLK_BTS_USBHOST30, "pclk_bts_usbhost30",
2226 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 4, 0, 0),
2227 GATE(CLK_PCLK_BTS_USBDRD30, "pclk_bts_usbdrd30",
2228 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS, 3, 0, 0),
2229 GATE(CLK_PCLK_GPIO_FSYS, "pclk_gpio_fsys", "mout_aclk_fsys_200_user",
2230 ENABLE_PCLK_FSYS, 2, CLK_IGNORE_UNUSED, 0),
2231 GATE(CLK_PCLK_PMU_FSYS, "pclk_pmu_fsys", "mout_aclk_fsys_200_user",
2232 ENABLE_PCLK_FSYS, 1, CLK_IGNORE_UNUSED, 0),
2233 GATE(CLK_PCLK_SYSREG_FSYS, "pclk_sysreg_fsys",
2234 "mout_aclk_fsys_200_user", ENABLE_PCLK_FSYS,
2235 0, CLK_IGNORE_UNUSED, 0),
2236
2237 /* ENABLE_SCLK_FSYS */
2238 GATE(CLK_SCLK_PCIE_100, "sclk_pcie_100", "mout_sclk_pcie_100_user",
2239 ENABLE_SCLK_FSYS, 21, 0, 0),
2240 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PIPE_PCLK,
2241 "phyclk_usbhost30_uhost30_pipe_pclk",
2242 "mout_phyclk_usbhost30_uhost30_pipe_pclk_user",
2243 ENABLE_SCLK_FSYS, 18, 0, 0),
2244 GATE(CLK_PHYCLK_USBHOST30_UHOST30_PHYCLOCK,
2245 "phyclk_usbhost30_uhost30_phyclock",
2246 "mout_phyclk_usbhost30_uhost30_phyclock_user",
2247 ENABLE_SCLK_FSYS, 17, 0, 0),
2248 GATE(CLK_PHYCLK_UFS_RX1_SYMBOL, "phyclk_ufs_rx1_symbol",
2249 "mout_phyclk_ufs_rx1_symbol_user", ENABLE_SCLK_FSYS,
2250 16, 0, 0),
2251 GATE(CLK_PHYCLK_UFS_RX0_SYMBOL, "phyclk_ufs_rx0_symbol",
2252 "mout_phyclk_ufs_rx0_symbol_user", ENABLE_SCLK_FSYS,
2253 15, 0, 0),
2254 GATE(CLK_PHYCLK_UFS_TX1_SYMBOL, "phyclk_ufs_tx1_symbol",
2255 "mout_phyclk_ufs_tx1_symbol_user", ENABLE_SCLK_FSYS,
2256 14, 0, 0),
2257 GATE(CLK_PHYCLK_UFS_TX0_SYMBOL, "phyclk_ufs_tx0_symbol",
2258 "mout_phyclk_ufs_tx0_symbol_user", ENABLE_SCLK_FSYS,
2259 13, 0, 0),
2260 GATE(CLK_PHYCLK_USBHOST20_PHY_HSIC1, "phyclk_usbhost20_phy_hsic1",
2261 "mout_phyclk_usbhost20_phy_hsic1", ENABLE_SCLK_FSYS,
2262 12, 0, 0),
2263 GATE(CLK_PHYCLK_USBHOST20_PHY_CLK48MOHCI,
2264 "phyclk_usbhost20_phy_clk48mohci",
2265 "mout_phyclk_usbhost20_phy_clk48mohci_user",
2266 ENABLE_SCLK_FSYS, 11, 0, 0),
2267 GATE(CLK_PHYCLK_USBHOST20_PHY_PHYCLOCK,
2268 "phyclk_usbhost20_phy_phyclock",
2269 "mout_phyclk_usbhost20_phy_phyclock_user",
2270 ENABLE_SCLK_FSYS, 10, 0, 0),
2271 GATE(CLK_PHYCLK_USBHOST20_PHY_FREECLK,
2272 "phyclk_usbhost20_phy_freeclk",
2273 "mout_phyclk_usbhost20_phy_freeclk_user",
2274 ENABLE_SCLK_FSYS, 9, 0, 0),
2275 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PIPE_PCLK,
2276 "phyclk_usbdrd30_udrd30_pipe_pclk",
2277 "mout_phyclk_usbdrd30_udrd30_pipe_pclk_user",
2278 ENABLE_SCLK_FSYS, 8, 0, 0),
2279 GATE(CLK_PHYCLK_USBDRD30_UDRD30_PHYCLOCK,
2280 "phyclk_usbdrd30_udrd30_phyclock",
2281 "mout_phyclk_usbdrd30_udrd30_phyclock_user",
2282 ENABLE_SCLK_FSYS, 7, 0, 0),
2283 GATE(CLK_SCLK_MPHY, "sclk_mphy", "mout_sclk_mphy",
2284 ENABLE_SCLK_FSYS, 6, 0, 0),
2285 GATE(CLK_SCLK_UFSUNIPRO, "sclk_ufsunipro", "mout_sclk_ufsunipro_user",
2286 ENABLE_SCLK_FSYS, 5, 0, 0),
2287 GATE(CLK_SCLK_MMC2, "sclk_mmc2", "mout_sclk_mmc2_user",
2288 ENABLE_SCLK_FSYS, 4, CLK_SET_RATE_PARENT, 0),
2289 GATE(CLK_SCLK_MMC1, "sclk_mmc1", "mout_sclk_mmc1_user",
2290 ENABLE_SCLK_FSYS, 3, CLK_SET_RATE_PARENT, 0),
2291 GATE(CLK_SCLK_MMC0, "sclk_mmc0", "mout_sclk_mmc0_user",
2292 ENABLE_SCLK_FSYS, 2, CLK_SET_RATE_PARENT, 0),
2293 GATE(CLK_SCLK_USBHOST30, "sclk_usbhost30", "mout_sclk_usbhost30_user",
2294 ENABLE_SCLK_FSYS, 1, 0, 0),
2295 GATE(CLK_SCLK_USBDRD30, "sclk_usbdrd30", "mout_sclk_usbdrd30_user",
2296 ENABLE_SCLK_FSYS, 0, 0, 0),
2297
2298 /* ENABLE_IP_FSYS0 */
2299 GATE(CLK_PCIE, "pcie", "sclk_pcie_100", ENABLE_IP_FSYS0, 17, 0, 0),
2300 GATE(CLK_PDMA1, "pdma1", "aclk_pdma1", ENABLE_IP_FSYS0, 15, 0, 0),
2301 GATE(CLK_PDMA0, "pdma0", "aclk_pdma0", ENABLE_IP_FSYS0, 0, 0, 0),
2302 };
2303
2304 static const struct samsung_cmu_info fsys_cmu_info __initconst = {
2305 .mux_clks = fsys_mux_clks,
2306 .nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
2307 .gate_clks = fsys_gate_clks,
2308 .nr_gate_clks = ARRAY_SIZE(fsys_gate_clks),
2309 .fixed_clks = fsys_fixed_clks,
2310 .nr_fixed_clks = ARRAY_SIZE(fsys_fixed_clks),
2311 .nr_clk_ids = FSYS_NR_CLK,
2312 .clk_regs = fsys_clk_regs,
2313 .nr_clk_regs = ARRAY_SIZE(fsys_clk_regs),
2314 .suspend_regs = fsys_suspend_regs,
2315 .nr_suspend_regs = ARRAY_SIZE(fsys_suspend_regs),
2316 .clk_name = "aclk_fsys_200",
2317 };
2318
2319 /*
2320 * Register offset definitions for CMU_G2D
2321 */
2322 #define MUX_SEL_G2D0 0x0200
2323 #define MUX_SEL_ENABLE_G2D0 0x0300
2324 #define MUX_SEL_STAT_G2D0 0x0400
2325 #define DIV_G2D 0x0600
2326 #define DIV_STAT_G2D 0x0700
2327 #define DIV_ENABLE_ACLK_G2D 0x0800
2328 #define DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D 0x0804
2329 #define DIV_ENABLE_PCLK_G2D 0x0900
2330 #define DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D 0x0904
2331 #define DIV_ENABLE_IP_G2D0 0x0b00
2332 #define DIV_ENABLE_IP_G2D1 0x0b04
2333 #define DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D 0x0b08
2334
2335 static const unsigned long g2d_clk_regs[] __initconst = {
2336 MUX_SEL_G2D0,
2337 MUX_SEL_ENABLE_G2D0,
2338 DIV_G2D,
2339 DIV_ENABLE_ACLK_G2D,
2340 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D,
2341 DIV_ENABLE_PCLK_G2D,
2342 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D,
2343 DIV_ENABLE_IP_G2D0,
2344 DIV_ENABLE_IP_G2D1,
2345 DIV_ENABLE_IP_G2D_SECURE_SMMU_G2D,
2346 };
2347
2348 static const struct samsung_clk_reg_dump g2d_suspend_regs[] = {
2349 { MUX_SEL_G2D0, 0 },
2350 };
2351
2352 /* list of all parent clock list */
2353 PNAME(mout_aclk_g2d_266_user_p) = { "oscclk", "aclk_g2d_266", };
2354 PNAME(mout_aclk_g2d_400_user_p) = { "oscclk", "aclk_g2d_400", };
2355
2356 static const struct samsung_mux_clock g2d_mux_clks[] __initconst = {
2357 /* MUX_SEL_G2D0 */
2358 MUX(CLK_MUX_ACLK_G2D_266_USER, "mout_aclk_g2d_266_user",
2359 mout_aclk_g2d_266_user_p, MUX_SEL_G2D0, 4, 1),
2360 MUX(CLK_MUX_ACLK_G2D_400_USER, "mout_aclk_g2d_400_user",
2361 mout_aclk_g2d_400_user_p, MUX_SEL_G2D0, 0, 1),
2362 };
2363
2364 static const struct samsung_div_clock g2d_div_clks[] __initconst = {
2365 /* DIV_G2D */
2366 DIV(CLK_DIV_PCLK_G2D, "div_pclk_g2d", "mout_aclk_g2d_266_user",
2367 DIV_G2D, 0, 2),
2368 };
2369
2370 static const struct samsung_gate_clock g2d_gate_clks[] __initconst = {
2371 /* DIV_ENABLE_ACLK_G2D */
2372 GATE(CLK_ACLK_SMMU_MDMA1, "aclk_smmu_mdma1", "mout_aclk_g2d_266_user",
2373 DIV_ENABLE_ACLK_G2D, 12, 0, 0),
2374 GATE(CLK_ACLK_BTS_MDMA1, "aclk_bts_mdam1", "mout_aclk_g2d_266_user",
2375 DIV_ENABLE_ACLK_G2D, 11, 0, 0),
2376 GATE(CLK_ACLK_BTS_G2D, "aclk_bts_g2d", "mout_aclk_g2d_400_user",
2377 DIV_ENABLE_ACLK_G2D, 10, 0, 0),
2378 GATE(CLK_ACLK_ALB_G2D, "aclk_alb_g2d", "mout_aclk_g2d_400_user",
2379 DIV_ENABLE_ACLK_G2D, 9, 0, 0),
2380 GATE(CLK_ACLK_AXIUS_G2DX, "aclk_axius_g2dx", "mout_aclk_g2d_400_user",
2381 DIV_ENABLE_ACLK_G2D, 8, 0, 0),
2382 GATE(CLK_ACLK_ASYNCAXI_SYSX, "aclk_asyncaxi_sysx",
2383 "mout_aclk_g2d_400_user", DIV_ENABLE_ACLK_G2D,
2384 7, 0, 0),
2385 GATE(CLK_ACLK_AHB2APB_G2D1P, "aclk_ahb2apb_g2d1p", "div_pclk_g2d",
2386 DIV_ENABLE_ACLK_G2D, 6, CLK_IGNORE_UNUSED, 0),
2387 GATE(CLK_ACLK_AHB2APB_G2D0P, "aclk_ahb2apb_g2d0p", "div_pclk_g2d",
2388 DIV_ENABLE_ACLK_G2D, 5, CLK_IGNORE_UNUSED, 0),
2389 GATE(CLK_ACLK_XIU_G2DX, "aclk_xiu_g2dx", "mout_aclk_g2d_400_user",
2390 DIV_ENABLE_ACLK_G2D, 4, CLK_IGNORE_UNUSED, 0),
2391 GATE(CLK_ACLK_G2DNP_133, "aclk_g2dnp_133", "div_pclk_g2d",
2392 DIV_ENABLE_ACLK_G2D, 3, CLK_IGNORE_UNUSED, 0),
2393 GATE(CLK_ACLK_G2DND_400, "aclk_g2dnd_400", "mout_aclk_g2d_400_user",
2394 DIV_ENABLE_ACLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2395 GATE(CLK_ACLK_MDMA1, "aclk_mdma1", "mout_aclk_g2d_266_user",
2396 DIV_ENABLE_ACLK_G2D, 1, 0, 0),
2397 GATE(CLK_ACLK_G2D, "aclk_g2d", "mout_aclk_g2d_400_user",
2398 DIV_ENABLE_ACLK_G2D, 0, 0, 0),
2399
2400 /* DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D */
2401 GATE(CLK_ACLK_SMMU_G2D, "aclk_smmu_g2d", "mout_aclk_g2d_400_user",
2402 DIV_ENABLE_ACLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2403
2404 /* DIV_ENABLE_PCLK_G2D */
2405 GATE(CLK_PCLK_SMMU_MDMA1, "pclk_smmu_mdma1", "div_pclk_g2d",
2406 DIV_ENABLE_PCLK_G2D, 7, 0, 0),
2407 GATE(CLK_PCLK_BTS_MDMA1, "pclk_bts_mdam1", "div_pclk_g2d",
2408 DIV_ENABLE_PCLK_G2D, 6, 0, 0),
2409 GATE(CLK_PCLK_BTS_G2D, "pclk_bts_g2d", "div_pclk_g2d",
2410 DIV_ENABLE_PCLK_G2D, 5, 0, 0),
2411 GATE(CLK_PCLK_ALB_G2D, "pclk_alb_g2d", "div_pclk_g2d",
2412 DIV_ENABLE_PCLK_G2D, 4, 0, 0),
2413 GATE(CLK_PCLK_ASYNCAXI_SYSX, "pclk_asyncaxi_sysx", "div_pclk_g2d",
2414 DIV_ENABLE_PCLK_G2D, 3, 0, 0),
2415 GATE(CLK_PCLK_PMU_G2D, "pclk_pmu_g2d", "div_pclk_g2d",
2416 DIV_ENABLE_PCLK_G2D, 2, CLK_IGNORE_UNUSED, 0),
2417 GATE(CLK_PCLK_SYSREG_G2D, "pclk_sysreg_g2d", "div_pclk_g2d",
2418 DIV_ENABLE_PCLK_G2D, 1, CLK_IGNORE_UNUSED, 0),
2419 GATE(CLK_PCLK_G2D, "pclk_g2d", "div_pclk_g2d", DIV_ENABLE_PCLK_G2D,
2420 0, 0, 0),
2421
2422 /* DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D */
2423 GATE(CLK_PCLK_SMMU_G2D, "pclk_smmu_g2d", "div_pclk_g2d",
2424 DIV_ENABLE_PCLK_G2D_SECURE_SMMU_G2D, 0, 0, 0),
2425 };
2426
2427 static const struct samsung_cmu_info g2d_cmu_info __initconst = {
2428 .mux_clks = g2d_mux_clks,
2429 .nr_mux_clks = ARRAY_SIZE(g2d_mux_clks),
2430 .div_clks = g2d_div_clks,
2431 .nr_div_clks = ARRAY_SIZE(g2d_div_clks),
2432 .gate_clks = g2d_gate_clks,
2433 .nr_gate_clks = ARRAY_SIZE(g2d_gate_clks),
2434 .nr_clk_ids = G2D_NR_CLK,
2435 .clk_regs = g2d_clk_regs,
2436 .nr_clk_regs = ARRAY_SIZE(g2d_clk_regs),
2437 .suspend_regs = g2d_suspend_regs,
2438 .nr_suspend_regs = ARRAY_SIZE(g2d_suspend_regs),
2439 .clk_name = "aclk_g2d_400",
2440 };
2441
2442 /*
2443 * Register offset definitions for CMU_DISP
2444 */
2445 #define DISP_PLL_LOCK 0x0000
2446 #define DISP_PLL_CON0 0x0100
2447 #define DISP_PLL_CON1 0x0104
2448 #define DISP_PLL_FREQ_DET 0x0108
2449 #define MUX_SEL_DISP0 0x0200
2450 #define MUX_SEL_DISP1 0x0204
2451 #define MUX_SEL_DISP2 0x0208
2452 #define MUX_SEL_DISP3 0x020c
2453 #define MUX_SEL_DISP4 0x0210
2454 #define MUX_ENABLE_DISP0 0x0300
2455 #define MUX_ENABLE_DISP1 0x0304
2456 #define MUX_ENABLE_DISP2 0x0308
2457 #define MUX_ENABLE_DISP3 0x030c
2458 #define MUX_ENABLE_DISP4 0x0310
2459 #define MUX_STAT_DISP0 0x0400
2460 #define MUX_STAT_DISP1 0x0404
2461 #define MUX_STAT_DISP2 0x0408
2462 #define MUX_STAT_DISP3 0x040c
2463 #define MUX_STAT_DISP4 0x0410
2464 #define MUX_IGNORE_DISP2 0x0508
2465 #define DIV_DISP 0x0600
2466 #define DIV_DISP_PLL_FREQ_DET 0x0604
2467 #define DIV_STAT_DISP 0x0700
2468 #define DIV_STAT_DISP_PLL_FREQ_DET 0x0704
2469 #define ENABLE_ACLK_DISP0 0x0800
2470 #define ENABLE_ACLK_DISP1 0x0804
2471 #define ENABLE_PCLK_DISP 0x0900
2472 #define ENABLE_SCLK_DISP 0x0a00
2473 #define ENABLE_IP_DISP0 0x0b00
2474 #define ENABLE_IP_DISP1 0x0b04
2475 #define CLKOUT_CMU_DISP 0x0c00
2476 #define CLKOUT_CMU_DISP_DIV_STAT 0x0c04
2477
2478 static const unsigned long disp_clk_regs[] __initconst = {
2479 DISP_PLL_LOCK,
2480 DISP_PLL_CON0,
2481 DISP_PLL_CON1,
2482 DISP_PLL_FREQ_DET,
2483 MUX_SEL_DISP0,
2484 MUX_SEL_DISP1,
2485 MUX_SEL_DISP2,
2486 MUX_SEL_DISP3,
2487 MUX_SEL_DISP4,
2488 MUX_ENABLE_DISP0,
2489 MUX_ENABLE_DISP1,
2490 MUX_ENABLE_DISP2,
2491 MUX_ENABLE_DISP3,
2492 MUX_ENABLE_DISP4,
2493 MUX_IGNORE_DISP2,
2494 DIV_DISP,
2495 DIV_DISP_PLL_FREQ_DET,
2496 ENABLE_ACLK_DISP0,
2497 ENABLE_ACLK_DISP1,
2498 ENABLE_PCLK_DISP,
2499 ENABLE_SCLK_DISP,
2500 ENABLE_IP_DISP0,
2501 ENABLE_IP_DISP1,
2502 CLKOUT_CMU_DISP,
2503 CLKOUT_CMU_DISP_DIV_STAT,
2504 };
2505
2506 static const struct samsung_clk_reg_dump disp_suspend_regs[] = {
2507 /* PLL has to be enabled for suspend */
2508 { DISP_PLL_CON0, 0x85f40502 },
2509 /* ignore status of external PHY muxes during suspend to avoid hangs */
2510 { MUX_IGNORE_DISP2, 0x00111111 },
2511 { MUX_SEL_DISP0, 0 },
2512 { MUX_SEL_DISP1, 0 },
2513 { MUX_SEL_DISP2, 0 },
2514 { MUX_SEL_DISP3, 0 },
2515 { MUX_SEL_DISP4, 0 },
2516 };
2517
2518 /* list of all parent clock list */
2519 PNAME(mout_disp_pll_p) = { "oscclk", "fout_disp_pll", };
2520 PNAME(mout_sclk_dsim1_user_p) = { "oscclk", "sclk_dsim1_disp", };
2521 PNAME(mout_sclk_dsim0_user_p) = { "oscclk", "sclk_dsim0_disp", };
2522 PNAME(mout_sclk_dsd_user_p) = { "oscclk", "sclk_dsd_disp", };
2523 PNAME(mout_sclk_decon_tv_eclk_user_p) = { "oscclk",
2524 "sclk_decon_tv_eclk_disp", };
2525 PNAME(mout_sclk_decon_vclk_user_p) = { "oscclk",
2526 "sclk_decon_vclk_disp", };
2527 PNAME(mout_sclk_decon_eclk_user_p) = { "oscclk",
2528 "sclk_decon_eclk_disp", };
2529 PNAME(mout_sclk_decon_tv_vlkc_user_p) = { "oscclk",
2530 "sclk_decon_tv_vclk_disp", };
2531 PNAME(mout_aclk_disp_333_user_p) = { "oscclk", "aclk_disp_333", };
2532
2533 PNAME(mout_phyclk_mipidphy1_bitclkdiv8_user_p) = { "oscclk",
2534 "phyclk_mipidphy1_bitclkdiv8_phy", };
2535 PNAME(mout_phyclk_mipidphy1_rxclkesc0_user_p) = { "oscclk",
2536 "phyclk_mipidphy1_rxclkesc0_phy", };
2537 PNAME(mout_phyclk_mipidphy0_bitclkdiv8_user_p) = { "oscclk",
2538 "phyclk_mipidphy0_bitclkdiv8_phy", };
2539 PNAME(mout_phyclk_mipidphy0_rxclkesc0_user_p) = { "oscclk",
2540 "phyclk_mipidphy0_rxclkesc0_phy", };
2541 PNAME(mout_phyclk_hdmiphy_tmds_clko_user_p) = { "oscclk",
2542 "phyclk_hdmiphy_tmds_clko_phy", };
2543 PNAME(mout_phyclk_hdmiphy_pixel_clko_user_p) = { "oscclk",
2544 "phyclk_hdmiphy_pixel_clko_phy", };
2545
2546 PNAME(mout_sclk_dsim0_p) = { "mout_disp_pll",
2547 "mout_sclk_dsim0_user", };
2548 PNAME(mout_sclk_decon_tv_eclk_p) = { "mout_disp_pll",
2549 "mout_sclk_decon_tv_eclk_user", };
2550 PNAME(mout_sclk_decon_vclk_p) = { "mout_disp_pll",
2551 "mout_sclk_decon_vclk_user", };
2552 PNAME(mout_sclk_decon_eclk_p) = { "mout_disp_pll",
2553 "mout_sclk_decon_eclk_user", };
2554
2555 PNAME(mout_sclk_dsim1_b_disp_p) = { "mout_sclk_dsim1_a_disp",
2556 "mout_sclk_dsim1_user", };
2557 PNAME(mout_sclk_decon_tv_vclk_c_disp_p) = {
2558 "mout_phyclk_hdmiphy_pixel_clko_user",
2559 "mout_sclk_decon_tv_vclk_b_disp", };
2560 PNAME(mout_sclk_decon_tv_vclk_b_disp_p) = { "mout_sclk_decon_tv_vclk_a_disp",
2561 "mout_sclk_decon_tv_vclk_user", };
2562
2563 static const struct samsung_pll_clock disp_pll_clks[] __initconst = {
2564 PLL(pll_35xx, CLK_FOUT_DISP_PLL, "fout_disp_pll", "oscclk",
2565 DISP_PLL_LOCK, DISP_PLL_CON0, exynos5433_pll_rates),
2566 };
2567
2568 static const struct samsung_fixed_factor_clock disp_fixed_factor_clks[] __initconst = {
2569 /*
2570 * sclk_rgb_{vclk|tv_vclk} is half clock of sclk_decon_{vclk|tv_vclk}.
2571 * The divider has fixed value (2) between sclk_rgb_{vclk|tv_vclk}
2572 * and sclk_decon_{vclk|tv_vclk}.
2573 */
2574 FFACTOR(CLK_SCLK_RGB_VCLK, "sclk_rgb_vclk", "sclk_decon_vclk",
2575 1, 2, 0),
2576 FFACTOR(CLK_SCLK_RGB_TV_VCLK, "sclk_rgb_tv_vclk", "sclk_decon_tv_vclk",
2577 1, 2, 0),
2578 };
2579
2580 static const struct samsung_fixed_rate_clock disp_fixed_clks[] __initconst = {
2581 /* PHY clocks from MIPI_DPHY1 */
2582 FRATE(0, "phyclk_mipidphy1_bitclkdiv8_phy", NULL, 0, 188000000),
2583 FRATE(0, "phyclk_mipidphy1_rxclkesc0_phy", NULL, 0, 100000000),
2584 /* PHY clocks from MIPI_DPHY0 */
2585 FRATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8_PHY, "phyclk_mipidphy0_bitclkdiv8_phy",
2586 NULL, 0, 188000000),
2587 FRATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0_PHY, "phyclk_mipidphy0_rxclkesc0_phy",
2588 NULL, 0, 100000000),
2589 /* PHY clocks from HDMI_PHY */
2590 FRATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO_PHY, "phyclk_hdmiphy_tmds_clko_phy",
2591 NULL, 0, 300000000),
2592 FRATE(CLK_PHYCLK_HDMIPHY_PIXEL_CLKO_PHY, "phyclk_hdmiphy_pixel_clko_phy",
2593 NULL, 0, 166000000),
2594 };
2595
2596 static const struct samsung_mux_clock disp_mux_clks[] __initconst = {
2597 /* MUX_SEL_DISP0 */
2598 MUX(CLK_MOUT_DISP_PLL, "mout_disp_pll", mout_disp_pll_p, MUX_SEL_DISP0,
2599 0, 1),
2600
2601 /* MUX_SEL_DISP1 */
2602 MUX(CLK_MOUT_SCLK_DSIM1_USER, "mout_sclk_dsim1_user",
2603 mout_sclk_dsim1_user_p, MUX_SEL_DISP1, 28, 1),
2604 MUX(CLK_MOUT_SCLK_DSIM0_USER, "mout_sclk_dsim0_user",
2605 mout_sclk_dsim0_user_p, MUX_SEL_DISP1, 24, 1),
2606 MUX(CLK_MOUT_SCLK_DSD_USER, "mout_sclk_dsd_user", mout_sclk_dsd_user_p,
2607 MUX_SEL_DISP1, 20, 1),
2608 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK_USER, "mout_sclk_decon_tv_eclk_user",
2609 mout_sclk_decon_tv_eclk_user_p, MUX_SEL_DISP1, 16, 1),
2610 MUX(CLK_MOUT_SCLK_DECON_VCLK_USER, "mout_sclk_decon_vclk_user",
2611 mout_sclk_decon_vclk_user_p, MUX_SEL_DISP1, 12, 1),
2612 MUX(CLK_MOUT_SCLK_DECON_ECLK_USER, "mout_sclk_decon_eclk_user",
2613 mout_sclk_decon_eclk_user_p, MUX_SEL_DISP1, 8, 1),
2614 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_USER, "mout_sclk_decon_tv_vclk_user",
2615 mout_sclk_decon_tv_vlkc_user_p, MUX_SEL_DISP1, 4, 1),
2616 MUX(CLK_MOUT_ACLK_DISP_333_USER, "mout_aclk_disp_333_user",
2617 mout_aclk_disp_333_user_p, MUX_SEL_DISP1, 0, 1),
2618
2619 /* MUX_SEL_DISP2 */
2620 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_BITCLKDIV8_USER,
2621 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2622 mout_phyclk_mipidphy1_bitclkdiv8_user_p, MUX_SEL_DISP2,
2623 20, 1),
2624 MUX(CLK_MOUT_PHYCLK_MIPIDPHY1_RXCLKESC0_USER,
2625 "mout_phyclk_mipidphy1_rxclkesc0_user",
2626 mout_phyclk_mipidphy1_rxclkesc0_user_p, MUX_SEL_DISP2,
2627 16, 1),
2628 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_BITCLKDIV8_USER,
2629 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2630 mout_phyclk_mipidphy0_bitclkdiv8_user_p, MUX_SEL_DISP2,
2631 12, 1),
2632 MUX(CLK_MOUT_PHYCLK_MIPIDPHY0_RXCLKESC0_USER,
2633 "mout_phyclk_mipidphy0_rxclkesc0_user",
2634 mout_phyclk_mipidphy0_rxclkesc0_user_p, MUX_SEL_DISP2,
2635 8, 1),
2636 MUX(CLK_MOUT_PHYCLK_HDMIPHY_TMDS_CLKO_USER,
2637 "mout_phyclk_hdmiphy_tmds_clko_user",
2638 mout_phyclk_hdmiphy_tmds_clko_user_p, MUX_SEL_DISP2,
2639 4, 1),
2640 MUX(CLK_MOUT_PHYCLK_HDMIPHY_PIXEL_CLKO_USER,
2641 "mout_phyclk_hdmiphy_pixel_clko_user",
2642 mout_phyclk_hdmiphy_pixel_clko_user_p, MUX_SEL_DISP2,
2643 0, 1),
2644
2645 /* MUX_SEL_DISP3 */
2646 MUX(CLK_MOUT_SCLK_DSIM0, "mout_sclk_dsim0", mout_sclk_dsim0_p,
2647 MUX_SEL_DISP3, 12, 1),
2648 MUX(CLK_MOUT_SCLK_DECON_TV_ECLK, "mout_sclk_decon_tv_eclk",
2649 mout_sclk_decon_tv_eclk_p, MUX_SEL_DISP3, 8, 1),
2650 MUX(CLK_MOUT_SCLK_DECON_VCLK, "mout_sclk_decon_vclk",
2651 mout_sclk_decon_vclk_p, MUX_SEL_DISP3, 4, 1),
2652 MUX(CLK_MOUT_SCLK_DECON_ECLK, "mout_sclk_decon_eclk",
2653 mout_sclk_decon_eclk_p, MUX_SEL_DISP3, 0, 1),
2654
2655 /* MUX_SEL_DISP4 */
2656 MUX(CLK_MOUT_SCLK_DSIM1_B_DISP, "mout_sclk_dsim1_b_disp",
2657 mout_sclk_dsim1_b_disp_p, MUX_SEL_DISP4, 16, 1),
2658 MUX(CLK_MOUT_SCLK_DSIM1_A_DISP, "mout_sclk_dsim1_a_disp",
2659 mout_sclk_dsim0_p, MUX_SEL_DISP4, 12, 1),
2660 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_C_DISP,
2661 "mout_sclk_decon_tv_vclk_c_disp",
2662 mout_sclk_decon_tv_vclk_c_disp_p, MUX_SEL_DISP4, 8, 1),
2663 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_B_DISP,
2664 "mout_sclk_decon_tv_vclk_b_disp",
2665 mout_sclk_decon_tv_vclk_b_disp_p, MUX_SEL_DISP4, 4, 1),
2666 MUX(CLK_MOUT_SCLK_DECON_TV_VCLK_A_DISP,
2667 "mout_sclk_decon_tv_vclk_a_disp",
2668 mout_sclk_decon_vclk_p, MUX_SEL_DISP4, 0, 1),
2669 };
2670
2671 static const struct samsung_div_clock disp_div_clks[] __initconst = {
2672 /* DIV_DISP */
2673 DIV(CLK_DIV_SCLK_DSIM1_DISP, "div_sclk_dsim1_disp",
2674 "mout_sclk_dsim1_b_disp", DIV_DISP, 24, 3),
2675 DIV(CLK_DIV_SCLK_DECON_TV_VCLK_DISP, "div_sclk_decon_tv_vclk_disp",
2676 "mout_sclk_decon_tv_vclk_c_disp", DIV_DISP, 20, 3),
2677 DIV(CLK_DIV_SCLK_DSIM0_DISP, "div_sclk_dsim0_disp", "mout_sclk_dsim0",
2678 DIV_DISP, 16, 3),
2679 DIV(CLK_DIV_SCLK_DECON_TV_ECLK_DISP, "div_sclk_decon_tv_eclk_disp",
2680 "mout_sclk_decon_tv_eclk", DIV_DISP, 12, 3),
2681 DIV(CLK_DIV_SCLK_DECON_VCLK_DISP, "div_sclk_decon_vclk_disp",
2682 "mout_sclk_decon_vclk", DIV_DISP, 8, 3),
2683 DIV(CLK_DIV_SCLK_DECON_ECLK_DISP, "div_sclk_decon_eclk_disp",
2684 "mout_sclk_decon_eclk", DIV_DISP, 4, 3),
2685 DIV(CLK_DIV_PCLK_DISP, "div_pclk_disp", "mout_aclk_disp_333_user",
2686 DIV_DISP, 0, 2),
2687 };
2688
2689 static const struct samsung_gate_clock disp_gate_clks[] __initconst = {
2690 /* ENABLE_ACLK_DISP0 */
2691 GATE(CLK_ACLK_DECON_TV, "aclk_decon_tv", "mout_aclk_disp_333_user",
2692 ENABLE_ACLK_DISP0, 2, 0, 0),
2693 GATE(CLK_ACLK_DECON, "aclk_decon", "mout_aclk_disp_333_user",
2694 ENABLE_ACLK_DISP0, 0, 0, 0),
2695
2696 /* ENABLE_ACLK_DISP1 */
2697 GATE(CLK_ACLK_SMMU_TV1X, "aclk_smmu_tv1x", "mout_aclk_disp_333_user",
2698 ENABLE_ACLK_DISP1, 25, 0, 0),
2699 GATE(CLK_ACLK_SMMU_TV0X, "aclk_smmu_tv0x", "mout_aclk_disp_333_user",
2700 ENABLE_ACLK_DISP1, 24, 0, 0),
2701 GATE(CLK_ACLK_SMMU_DECON1X, "aclk_smmu_decon1x",
2702 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 23, 0, 0),
2703 GATE(CLK_ACLK_SMMU_DECON0X, "aclk_smmu_decon0x",
2704 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 22, 0, 0),
2705 GATE(CLK_ACLK_BTS_DECON_TV_M3, "aclk_bts_decon_tv_m3",
2706 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 21, 0, 0),
2707 GATE(CLK_ACLK_BTS_DECON_TV_M2, "aclk_bts_decon_tv_m2",
2708 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 20, 0, 0),
2709 GATE(CLK_ACLK_BTS_DECON_TV_M1, "aclk_bts_decon_tv_m1",
2710 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 19, 0, 0),
2711 GATE(CLK_ACLK_BTS_DECON_TV_M0, "aclk-bts_decon_tv_m0",
2712 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 18, 0, 0),
2713 GATE(CLK_ACLK_BTS_DECON_NM4, "aclk_bts_decon_nm4",
2714 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 17, 0, 0),
2715 GATE(CLK_ACLK_BTS_DECON_NM3, "aclk_bts_decon_nm3",
2716 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 16, 0, 0),
2717 GATE(CLK_ACLK_BTS_DECON_NM2, "aclk_bts_decon_nm2",
2718 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 15, 0, 0),
2719 GATE(CLK_ACLK_BTS_DECON_NM1, "aclk_bts_decon_nm1",
2720 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 14, 0, 0),
2721 GATE(CLK_ACLK_BTS_DECON_NM0, "aclk_bts_decon_nm0",
2722 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 13, 0, 0),
2723 GATE(CLK_ACLK_AHB2APB_DISPSFR2P, "aclk_ahb2apb_dispsfr2p",
2724 "div_pclk_disp", ENABLE_ACLK_DISP1,
2725 12, CLK_IGNORE_UNUSED, 0),
2726 GATE(CLK_ACLK_AHB2APB_DISPSFR1P, "aclk_ahb2apb_dispsfr1p",
2727 "div_pclk_disp", ENABLE_ACLK_DISP1,
2728 11, CLK_IGNORE_UNUSED, 0),
2729 GATE(CLK_ACLK_AHB2APB_DISPSFR0P, "aclk_ahb2apb_dispsfr0p",
2730 "div_pclk_disp", ENABLE_ACLK_DISP1,
2731 10, CLK_IGNORE_UNUSED, 0),
2732 GATE(CLK_ACLK_AHB_DISPH, "aclk_ahb_disph", "div_pclk_disp",
2733 ENABLE_ACLK_DISP1, 8, CLK_IGNORE_UNUSED, 0),
2734 GATE(CLK_ACLK_XIU_TV1X, "aclk_xiu_tv1x", "mout_aclk_disp_333_user",
2735 ENABLE_ACLK_DISP1, 7, 0, 0),
2736 GATE(CLK_ACLK_XIU_TV0X, "aclk_xiu_tv0x", "mout_aclk_disp_333_user",
2737 ENABLE_ACLK_DISP1, 6, 0, 0),
2738 GATE(CLK_ACLK_XIU_DECON1X, "aclk_xiu_decon1x",
2739 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 5, 0, 0),
2740 GATE(CLK_ACLK_XIU_DECON0X, "aclk_xiu_decon0x",
2741 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 4, 0, 0),
2742 GATE(CLK_ACLK_XIU_DISP1X, "aclk_xiu_disp1x", "mout_aclk_disp_333_user",
2743 ENABLE_ACLK_DISP1, 3, CLK_IGNORE_UNUSED, 0),
2744 GATE(CLK_ACLK_XIU_DISPNP_100, "aclk_xiu_dispnp_100", "div_pclk_disp",
2745 ENABLE_ACLK_DISP1, 2, CLK_IGNORE_UNUSED, 0),
2746 GATE(CLK_ACLK_DISP1ND_333, "aclk_disp1nd_333",
2747 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1, 1,
2748 CLK_IGNORE_UNUSED, 0),
2749 GATE(CLK_ACLK_DISP0ND_333, "aclk_disp0nd_333",
2750 "mout_aclk_disp_333_user", ENABLE_ACLK_DISP1,
2751 0, CLK_IGNORE_UNUSED, 0),
2752
2753 /* ENABLE_PCLK_DISP */
2754 GATE(CLK_PCLK_SMMU_TV1X, "pclk_smmu_tv1x", "div_pclk_disp",
2755 ENABLE_PCLK_DISP, 23, 0, 0),
2756 GATE(CLK_PCLK_SMMU_TV0X, "pclk_smmu_tv0x", "div_pclk_disp",
2757 ENABLE_PCLK_DISP, 22, 0, 0),
2758 GATE(CLK_PCLK_SMMU_DECON1X, "pclk_smmu_decon1x", "div_pclk_disp",
2759 ENABLE_PCLK_DISP, 21, 0, 0),
2760 GATE(CLK_PCLK_SMMU_DECON0X, "pclk_smmu_decon0x", "div_pclk_disp",
2761 ENABLE_PCLK_DISP, 20, 0, 0),
2762 GATE(CLK_PCLK_BTS_DECON_TV_M3, "pclk_bts_decon_tv_m3", "div_pclk_disp",
2763 ENABLE_PCLK_DISP, 19, 0, 0),
2764 GATE(CLK_PCLK_BTS_DECON_TV_M2, "pclk_bts_decon_tv_m2", "div_pclk_disp",
2765 ENABLE_PCLK_DISP, 18, 0, 0),
2766 GATE(CLK_PCLK_BTS_DECON_TV_M1, "pclk_bts_decon_tv_m1", "div_pclk_disp",
2767 ENABLE_PCLK_DISP, 17, 0, 0),
2768 GATE(CLK_PCLK_BTS_DECON_TV_M0, "pclk_bts_decon_tv_m0", "div_pclk_disp",
2769 ENABLE_PCLK_DISP, 16, 0, 0),
2770 GATE(CLK_PCLK_BTS_DECONM4, "pclk_bts_deconm4", "div_pclk_disp",
2771 ENABLE_PCLK_DISP, 15, 0, 0),
2772 GATE(CLK_PCLK_BTS_DECONM3, "pclk_bts_deconm3", "div_pclk_disp",
2773 ENABLE_PCLK_DISP, 14, 0, 0),
2774 GATE(CLK_PCLK_BTS_DECONM2, "pclk_bts_deconm2", "div_pclk_disp",
2775 ENABLE_PCLK_DISP, 13, 0, 0),
2776 GATE(CLK_PCLK_BTS_DECONM1, "pclk_bts_deconm1", "div_pclk_disp",
2777 ENABLE_PCLK_DISP, 12, 0, 0),
2778 GATE(CLK_PCLK_BTS_DECONM0, "pclk_bts_deconm0", "div_pclk_disp",
2779 ENABLE_PCLK_DISP, 11, 0, 0),
2780 GATE(CLK_PCLK_MIC1, "pclk_mic1", "div_pclk_disp",
2781 ENABLE_PCLK_DISP, 10, 0, 0),
2782 GATE(CLK_PCLK_PMU_DISP, "pclk_pmu_disp", "div_pclk_disp",
2783 ENABLE_PCLK_DISP, 9, CLK_IGNORE_UNUSED, 0),
2784 GATE(CLK_PCLK_SYSREG_DISP, "pclk_sysreg_disp", "div_pclk_disp",
2785 ENABLE_PCLK_DISP, 8, CLK_IGNORE_UNUSED, 0),
2786 GATE(CLK_PCLK_HDMIPHY, "pclk_hdmiphy", "div_pclk_disp",
2787 ENABLE_PCLK_DISP, 7, 0, 0),
2788 GATE(CLK_PCLK_HDMI, "pclk_hdmi", "div_pclk_disp",
2789 ENABLE_PCLK_DISP, 6, 0, 0),
2790 GATE(CLK_PCLK_MIC0, "pclk_mic0", "div_pclk_disp",
2791 ENABLE_PCLK_DISP, 5, 0, 0),
2792 GATE(CLK_PCLK_DSIM1, "pclk_dsim1", "div_pclk_disp",
2793 ENABLE_PCLK_DISP, 3, 0, 0),
2794 GATE(CLK_PCLK_DSIM0, "pclk_dsim0", "div_pclk_disp",
2795 ENABLE_PCLK_DISP, 2, 0, 0),
2796 GATE(CLK_PCLK_DECON_TV, "pclk_decon_tv", "div_pclk_disp",
2797 ENABLE_PCLK_DISP, 1, 0, 0),
2798 GATE(CLK_PCLK_DECON, "pclk_decon", "div_pclk_disp",
2799 ENABLE_PCLK_DISP, 0, 0, 0),
2800
2801 /* ENABLE_SCLK_DISP */
2802 GATE(CLK_PHYCLK_MIPIDPHY1_BITCLKDIV8, "phyclk_mipidphy1_bitclkdiv8",
2803 "mout_phyclk_mipidphy1_bitclkdiv8_user",
2804 ENABLE_SCLK_DISP, 26, 0, 0),
2805 GATE(CLK_PHYCLK_MIPIDPHY1_RXCLKESC0, "phyclk_mipidphy1_rxclkesc0",
2806 "mout_phyclk_mipidphy1_rxclkesc0_user",
2807 ENABLE_SCLK_DISP, 25, 0, 0),
2808 GATE(CLK_SCLK_RGB_TV_VCLK_TO_DSIM1, "sclk_rgb_tv_vclk_to_dsim1",
2809 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 24, 0, 0),
2810 GATE(CLK_SCLK_RGB_TV_VCLK_TO_MIC1, "sclk_rgb_tv_vclk_to_mic1",
2811 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 23, 0, 0),
2812 GATE(CLK_SCLK_DSIM1, "sclk_dsim1", "div_sclk_dsim1_disp",
2813 ENABLE_SCLK_DISP, 22, 0, 0),
2814 GATE(CLK_SCLK_DECON_TV_VCLK, "sclk_decon_tv_vclk",
2815 "div_sclk_decon_tv_vclk_disp",
2816 ENABLE_SCLK_DISP, 21, 0, 0),
2817 GATE(CLK_PHYCLK_MIPIDPHY0_BITCLKDIV8, "phyclk_mipidphy0_bitclkdiv8",
2818 "mout_phyclk_mipidphy0_bitclkdiv8_user",
2819 ENABLE_SCLK_DISP, 15, 0, 0),
2820 GATE(CLK_PHYCLK_MIPIDPHY0_RXCLKESC0, "phyclk_mipidphy0_rxclkesc0",
2821 "mout_phyclk_mipidphy0_rxclkesc0_user",
2822 ENABLE_SCLK_DISP, 14, 0, 0),
2823 GATE(CLK_PHYCLK_HDMIPHY_TMDS_CLKO, "phyclk_hdmiphy_tmds_clko",
2824 "mout_phyclk_hdmiphy_tmds_clko_user",
2825 ENABLE_SCLK_DISP, 13, 0, 0),
2826 GATE(CLK_PHYCLK_HDMI_PIXEL, "phyclk_hdmi_pixel",
2827 "sclk_rgb_tv_vclk", ENABLE_SCLK_DISP, 12, 0, 0),
2828 GATE(CLK_SCLK_RGB_VCLK_TO_SMIES, "sclk_rgb_vclk_to_smies",
2829 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 11, 0, 0),
2830 GATE(CLK_SCLK_RGB_VCLK_TO_DSIM0, "sclk_rgb_vclk_to_dsim0",
2831 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 9, 0, 0),
2832 GATE(CLK_SCLK_RGB_VCLK_TO_MIC0, "sclk_rgb_vclk_to_mic0",
2833 "sclk_rgb_vclk", ENABLE_SCLK_DISP, 8, 0, 0),
2834 GATE(CLK_SCLK_DSD, "sclk_dsd", "mout_sclk_dsd_user",
2835 ENABLE_SCLK_DISP, 7, 0, 0),
2836 GATE(CLK_SCLK_HDMI_SPDIF, "sclk_hdmi_spdif", "sclk_hdmi_spdif_disp",
2837 ENABLE_SCLK_DISP, 6, 0, 0),
2838 GATE(CLK_SCLK_DSIM0, "sclk_dsim0", "div_sclk_dsim0_disp",
2839 ENABLE_SCLK_DISP, 5, 0, 0),
2840 GATE(CLK_SCLK_DECON_TV_ECLK, "sclk_decon_tv_eclk",
2841 "div_sclk_decon_tv_eclk_disp",
2842 ENABLE_SCLK_DISP, 4, 0, 0),
2843 GATE(CLK_SCLK_DECON_VCLK, "sclk_decon_vclk",
2844 "div_sclk_decon_vclk_disp", ENABLE_SCLK_DISP, 3, 0, 0),
2845 GATE(CLK_SCLK_DECON_ECLK, "sclk_decon_eclk",
2846 "div_sclk_decon_eclk_disp", ENABLE_SCLK_DISP, 2, 0, 0),
2847 };
2848
2849 static const struct samsung_cmu_info disp_cmu_info __initconst = {
2850 .pll_clks = disp_pll_clks,
2851 .nr_pll_clks = ARRAY_SIZE(disp_pll_clks),
2852 .mux_clks = disp_mux_clks,
2853 .nr_mux_clks = ARRAY_SIZE(disp_mux_clks),
2854 .div_clks = disp_div_clks,
2855 .nr_div_clks = ARRAY_SIZE(disp_div_clks),
2856 .gate_clks = disp_gate_clks,
2857 .nr_gate_clks = ARRAY_SIZE(disp_gate_clks),
2858 .fixed_clks = disp_fixed_clks,
2859 .nr_fixed_clks = ARRAY_SIZE(disp_fixed_clks),
2860 .fixed_factor_clks = disp_fixed_factor_clks,
2861 .nr_fixed_factor_clks = ARRAY_SIZE(disp_fixed_factor_clks),
2862 .nr_clk_ids = DISP_NR_CLK,
2863 .clk_regs = disp_clk_regs,
2864 .nr_clk_regs = ARRAY_SIZE(disp_clk_regs),
2865 .suspend_regs = disp_suspend_regs,
2866 .nr_suspend_regs = ARRAY_SIZE(disp_suspend_regs),
2867 .clk_name = "aclk_disp_333",
2868 };
2869
2870 /*
2871 * Register offset definitions for CMU_AUD
2872 */
2873 #define MUX_SEL_AUD0 0x0200
2874 #define MUX_SEL_AUD1 0x0204
2875 #define MUX_ENABLE_AUD0 0x0300
2876 #define MUX_ENABLE_AUD1 0x0304
2877 #define MUX_STAT_AUD0 0x0400
2878 #define DIV_AUD0 0x0600
2879 #define DIV_AUD1 0x0604
2880 #define DIV_STAT_AUD0 0x0700
2881 #define DIV_STAT_AUD1 0x0704
2882 #define ENABLE_ACLK_AUD 0x0800
2883 #define ENABLE_PCLK_AUD 0x0900
2884 #define ENABLE_SCLK_AUD0 0x0a00
2885 #define ENABLE_SCLK_AUD1 0x0a04
2886 #define ENABLE_IP_AUD0 0x0b00
2887 #define ENABLE_IP_AUD1 0x0b04
2888
2889 static const unsigned long aud_clk_regs[] __initconst = {
2890 MUX_SEL_AUD0,
2891 MUX_SEL_AUD1,
2892 MUX_ENABLE_AUD0,
2893 MUX_ENABLE_AUD1,
2894 DIV_AUD0,
2895 DIV_AUD1,
2896 ENABLE_ACLK_AUD,
2897 ENABLE_PCLK_AUD,
2898 ENABLE_SCLK_AUD0,
2899 ENABLE_SCLK_AUD1,
2900 ENABLE_IP_AUD0,
2901 ENABLE_IP_AUD1,
2902 };
2903
2904 static const struct samsung_clk_reg_dump aud_suspend_regs[] = {
2905 { MUX_SEL_AUD0, 0 },
2906 { MUX_SEL_AUD1, 0 },
2907 };
2908
2909 /* list of all parent clock list */
2910 PNAME(mout_aud_pll_user_aud_p) = { "oscclk", "fout_aud_pll", };
2911 PNAME(mout_sclk_aud_pcm_p) = { "mout_aud_pll_user", "ioclk_audiocdclk0",};
2912
2913 static const struct samsung_fixed_rate_clock aud_fixed_clks[] __initconst = {
2914 FRATE(0, "ioclk_jtag_tclk", NULL, 0, 33000000),
2915 FRATE(0, "ioclk_slimbus_clk", NULL, 0, 25000000),
2916 FRATE(0, "ioclk_i2s_bclk", NULL, 0, 50000000),
2917 };
2918
2919 static const struct samsung_mux_clock aud_mux_clks[] __initconst = {
2920 /* MUX_SEL_AUD0 */
2921 MUX(CLK_MOUT_AUD_PLL_USER, "mout_aud_pll_user",
2922 mout_aud_pll_user_aud_p, MUX_SEL_AUD0, 0, 1),
2923
2924 /* MUX_SEL_AUD1 */
2925 MUX(CLK_MOUT_SCLK_AUD_PCM, "mout_sclk_aud_pcm", mout_sclk_aud_pcm_p,
2926 MUX_SEL_AUD1, 8, 1),
2927 MUX(CLK_MOUT_SCLK_AUD_I2S, "mout_sclk_aud_i2s", mout_sclk_aud_pcm_p,
2928 MUX_SEL_AUD1, 0, 1),
2929 };
2930
2931 static const struct samsung_div_clock aud_div_clks[] __initconst = {
2932 /* DIV_AUD0 */
2933 DIV(CLK_DIV_ATCLK_AUD, "div_atclk_aud", "div_aud_ca5", DIV_AUD0,
2934 12, 4),
2935 DIV(CLK_DIV_PCLK_DBG_AUD, "div_pclk_dbg_aud", "div_aud_ca5", DIV_AUD0,
2936 8, 4),
2937 DIV(CLK_DIV_ACLK_AUD, "div_aclk_aud", "div_aud_ca5", DIV_AUD0,
2938 4, 4),
2939 DIV(CLK_DIV_AUD_CA5, "div_aud_ca5", "mout_aud_pll_user", DIV_AUD0,
2940 0, 4),
2941
2942 /* DIV_AUD1 */
2943 DIV(CLK_DIV_SCLK_AUD_SLIMBUS, "div_sclk_aud_slimbus",
2944 "mout_aud_pll_user", DIV_AUD1, 16, 5),
2945 DIV(CLK_DIV_SCLK_AUD_UART, "div_sclk_aud_uart", "mout_aud_pll_user",
2946 DIV_AUD1, 12, 4),
2947 DIV(CLK_DIV_SCLK_AUD_PCM, "div_sclk_aud_pcm", "mout_sclk_aud_pcm",
2948 DIV_AUD1, 4, 8),
2949 DIV(CLK_DIV_SCLK_AUD_I2S, "div_sclk_aud_i2s", "mout_sclk_aud_i2s",
2950 DIV_AUD1, 0, 4),
2951 };
2952
2953 static const struct samsung_gate_clock aud_gate_clks[] __initconst = {
2954 /* ENABLE_ACLK_AUD */
2955 GATE(CLK_ACLK_INTR_CTRL, "aclk_intr_ctrl", "div_aclk_aud",
2956 ENABLE_ACLK_AUD, 12, 0, 0),
2957 GATE(CLK_ACLK_SMMU_LPASSX, "aclk_smmu_lpassx", "div_aclk_aud",
2958 ENABLE_ACLK_AUD, 7, 0, 0),
2959 GATE(CLK_ACLK_XIU_LPASSX, "aclk_xiu_lpassx", "div_aclk_aud",
2960 ENABLE_ACLK_AUD, 0, 4, 0),
2961 GATE(CLK_ACLK_AUDNP_133, "aclk_audnp_133", "div_aclk_aud",
2962 ENABLE_ACLK_AUD, 0, 3, 0),
2963 GATE(CLK_ACLK_AUDND_133, "aclk_audnd_133", "div_aclk_aud",
2964 ENABLE_ACLK_AUD, 0, 2, 0),
2965 GATE(CLK_ACLK_SRAMC, "aclk_sramc", "div_aclk_aud", ENABLE_ACLK_AUD,
2966 0, 1, 0),
2967 GATE(CLK_ACLK_DMAC, "aclk_dmac", "div_aclk_aud", ENABLE_ACLK_AUD,
2968 0, CLK_IGNORE_UNUSED, 0),
2969
2970 /* ENABLE_PCLK_AUD */
2971 GATE(CLK_PCLK_WDT1, "pclk_wdt1", "div_aclk_aud", ENABLE_PCLK_AUD,
2972 13, 0, 0),
2973 GATE(CLK_PCLK_WDT0, "pclk_wdt0", "div_aclk_aud", ENABLE_PCLK_AUD,
2974 12, 0, 0),
2975 GATE(CLK_PCLK_SFR1, "pclk_sfr1", "div_aclk_aud", ENABLE_PCLK_AUD,
2976 11, 0, 0),
2977 GATE(CLK_PCLK_SMMU_LPASSX, "pclk_smmu_lpassx", "div_aclk_aud",
2978 ENABLE_PCLK_AUD, 10, 0, 0),
2979 GATE(CLK_PCLK_GPIO_AUD, "pclk_gpio_aud", "div_aclk_aud",
2980 ENABLE_PCLK_AUD, 9, CLK_IGNORE_UNUSED, 0),
2981 GATE(CLK_PCLK_PMU_AUD, "pclk_pmu_aud", "div_aclk_aud",
2982 ENABLE_PCLK_AUD, 8, CLK_IGNORE_UNUSED, 0),
2983 GATE(CLK_PCLK_SYSREG_AUD, "pclk_sysreg_aud", "div_aclk_aud",
2984 ENABLE_PCLK_AUD, 7, CLK_IGNORE_UNUSED, 0),
2985 GATE(CLK_PCLK_AUD_SLIMBUS, "pclk_aud_slimbus", "div_aclk_aud",
2986 ENABLE_PCLK_AUD, 6, 0, 0),
2987 GATE(CLK_PCLK_AUD_UART, "pclk_aud_uart", "div_aclk_aud",
2988 ENABLE_PCLK_AUD, 5, 0, 0),
2989 GATE(CLK_PCLK_AUD_PCM, "pclk_aud_pcm", "div_aclk_aud",
2990 ENABLE_PCLK_AUD, 4, 0, 0),
2991 GATE(CLK_PCLK_AUD_I2S, "pclk_aud_i2s", "div_aclk_aud",
2992 ENABLE_PCLK_AUD, 3, 0, 0),
2993 GATE(CLK_PCLK_TIMER, "pclk_timer", "div_aclk_aud", ENABLE_PCLK_AUD,
2994 2, 0, 0),
2995 GATE(CLK_PCLK_SFR0_CTRL, "pclk_sfr0_ctrl", "div_aclk_aud",
2996 ENABLE_PCLK_AUD, 0, 0, 0),
2997
2998 /* ENABLE_SCLK_AUD0 */
2999 GATE(CLK_ATCLK_AUD, "atclk_aud", "div_atclk_aud", ENABLE_SCLK_AUD0,
3000 2, CLK_IGNORE_UNUSED, 0),
3001 GATE(CLK_PCLK_DBG_AUD, "pclk_dbg_aud", "div_pclk_dbg_aud",
3002 ENABLE_SCLK_AUD0, 1, 0, 0),
3003 GATE(CLK_SCLK_AUD_CA5, "sclk_aud_ca5", "div_aud_ca5", ENABLE_SCLK_AUD0,
3004 0, 0, 0),
3005
3006 /* ENABLE_SCLK_AUD1 */
3007 GATE(CLK_SCLK_JTAG_TCK, "sclk_jtag_tck", "ioclk_jtag_tclk",
3008 ENABLE_SCLK_AUD1, 6, 0, 0),
3009 GATE(CLK_SCLK_SLIMBUS_CLKIN, "sclk_slimbus_clkin", "ioclk_slimbus_clk",
3010 ENABLE_SCLK_AUD1, 5, 0, 0),
3011 GATE(CLK_SCLK_AUD_SLIMBUS, "sclk_aud_slimbus", "div_sclk_aud_slimbus",
3012 ENABLE_SCLK_AUD1, 4, 0, 0),
3013 GATE(CLK_SCLK_AUD_UART, "sclk_aud_uart", "div_sclk_aud_uart",
3014 ENABLE_SCLK_AUD1, 3, CLK_IGNORE_UNUSED, 0),
3015 GATE(CLK_SCLK_AUD_PCM, "sclk_aud_pcm", "div_sclk_aud_pcm",
3016 ENABLE_SCLK_AUD1, 2, 0, 0),
3017 GATE(CLK_SCLK_I2S_BCLK, "sclk_i2s_bclk", "ioclk_i2s_bclk",
3018 ENABLE_SCLK_AUD1, 1, CLK_IGNORE_UNUSED, 0),
3019 GATE(CLK_SCLK_AUD_I2S, "sclk_aud_i2s", "div_sclk_aud_i2s",
3020 ENABLE_SCLK_AUD1, 0, CLK_IGNORE_UNUSED, 0),
3021 };
3022
3023 static const struct samsung_cmu_info aud_cmu_info __initconst = {
3024 .mux_clks = aud_mux_clks,
3025 .nr_mux_clks = ARRAY_SIZE(aud_mux_clks),
3026 .div_clks = aud_div_clks,
3027 .nr_div_clks = ARRAY_SIZE(aud_div_clks),
3028 .gate_clks = aud_gate_clks,
3029 .nr_gate_clks = ARRAY_SIZE(aud_gate_clks),
3030 .fixed_clks = aud_fixed_clks,
3031 .nr_fixed_clks = ARRAY_SIZE(aud_fixed_clks),
3032 .nr_clk_ids = AUD_NR_CLK,
3033 .clk_regs = aud_clk_regs,
3034 .nr_clk_regs = ARRAY_SIZE(aud_clk_regs),
3035 .suspend_regs = aud_suspend_regs,
3036 .nr_suspend_regs = ARRAY_SIZE(aud_suspend_regs),
3037 .clk_name = "fout_aud_pll",
3038 };
3039
3040 /*
3041 * Register offset definitions for CMU_BUS{0|1|2}
3042 */
3043 #define DIV_BUS 0x0600
3044 #define DIV_STAT_BUS 0x0700
3045 #define ENABLE_ACLK_BUS 0x0800
3046 #define ENABLE_PCLK_BUS 0x0900
3047 #define ENABLE_IP_BUS0 0x0b00
3048 #define ENABLE_IP_BUS1 0x0b04
3049
3050 #define MUX_SEL_BUS2 0x0200 /* Only for CMU_BUS2 */
3051 #define MUX_ENABLE_BUS2 0x0300 /* Only for CMU_BUS2 */
3052 #define MUX_STAT_BUS2 0x0400 /* Only for CMU_BUS2 */
3053
3054 /* list of all parent clock list */
3055 PNAME(mout_aclk_bus2_400_p) = { "oscclk", "aclk_bus2_400", };
3056
3057 #define CMU_BUS_COMMON_CLK_REGS \
3058 DIV_BUS, \
3059 ENABLE_ACLK_BUS, \
3060 ENABLE_PCLK_BUS, \
3061 ENABLE_IP_BUS0, \
3062 ENABLE_IP_BUS1
3063
3064 static const unsigned long bus01_clk_regs[] __initconst = {
3065 CMU_BUS_COMMON_CLK_REGS,
3066 };
3067
3068 static const unsigned long bus2_clk_regs[] __initconst = {
3069 MUX_SEL_BUS2,
3070 MUX_ENABLE_BUS2,
3071 CMU_BUS_COMMON_CLK_REGS,
3072 };
3073
3074 static const struct samsung_div_clock bus0_div_clks[] __initconst = {
3075 /* DIV_BUS0 */
3076 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus0_133", "aclk_bus0_400",
3077 DIV_BUS, 0, 3),
3078 };
3079
3080 /* CMU_BUS0 clocks */
3081 static const struct samsung_gate_clock bus0_gate_clks[] __initconst = {
3082 /* ENABLE_ACLK_BUS0 */
3083 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus0p", "div_pclk_bus0_133",
3084 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3085 GATE(CLK_ACLK_BUSNP_133, "aclk_bus0np_133", "div_pclk_bus0_133",
3086 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3087 GATE(CLK_ACLK_BUSND_400, "aclk_bus0nd_400", "aclk_bus0_400",
3088 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3089
3090 /* ENABLE_PCLK_BUS0 */
3091 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus0srvnd_133", "div_pclk_bus0_133",
3092 ENABLE_PCLK_BUS, 2, 0, 0),
3093 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus0", "div_pclk_bus0_133",
3094 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3095 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus0", "div_pclk_bus0_133",
3096 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3097 };
3098
3099 /* CMU_BUS1 clocks */
3100 static const struct samsung_div_clock bus1_div_clks[] __initconst = {
3101 /* DIV_BUS1 */
3102 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus1_133", "aclk_bus1_400",
3103 DIV_BUS, 0, 3),
3104 };
3105
3106 static const struct samsung_gate_clock bus1_gate_clks[] __initconst = {
3107 /* ENABLE_ACLK_BUS1 */
3108 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus1p", "div_pclk_bus1_133",
3109 ENABLE_ACLK_BUS, 4, CLK_IGNORE_UNUSED, 0),
3110 GATE(CLK_ACLK_BUSNP_133, "aclk_bus1np_133", "div_pclk_bus1_133",
3111 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3112 GATE(CLK_ACLK_BUSND_400, "aclk_bus1nd_400", "aclk_bus1_400",
3113 ENABLE_ACLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3114
3115 /* ENABLE_PCLK_BUS1 */
3116 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus1srvnd_133", "div_pclk_bus1_133",
3117 ENABLE_PCLK_BUS, 2, 0, 0),
3118 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus1", "div_pclk_bus1_133",
3119 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3120 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus1", "div_pclk_bus1_133",
3121 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3122 };
3123
3124 /* CMU_BUS2 clocks */
3125 static const struct samsung_mux_clock bus2_mux_clks[] __initconst = {
3126 /* MUX_SEL_BUS2 */
3127 MUX(CLK_MOUT_ACLK_BUS2_400_USER, "mout_aclk_bus2_400_user",
3128 mout_aclk_bus2_400_p, MUX_SEL_BUS2, 0, 1),
3129 };
3130
3131 static const struct samsung_div_clock bus2_div_clks[] __initconst = {
3132 /* DIV_BUS2 */
3133 DIV(CLK_DIV_PCLK_BUS_133, "div_pclk_bus2_133",
3134 "mout_aclk_bus2_400_user", DIV_BUS, 0, 3),
3135 };
3136
3137 static const struct samsung_gate_clock bus2_gate_clks[] __initconst = {
3138 /* ENABLE_ACLK_BUS2 */
3139 GATE(CLK_ACLK_AHB2APB_BUSP, "aclk_ahb2apb_bus2p", "div_pclk_bus2_133",
3140 ENABLE_ACLK_BUS, 3, CLK_IGNORE_UNUSED, 0),
3141 GATE(CLK_ACLK_BUSNP_133, "aclk_bus2np_133", "div_pclk_bus2_133",
3142 ENABLE_ACLK_BUS, 2, CLK_IGNORE_UNUSED, 0),
3143 GATE(CLK_ACLK_BUS2BEND_400, "aclk_bus2bend_400",
3144 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3145 1, CLK_IGNORE_UNUSED, 0),
3146 GATE(CLK_ACLK_BUS2RTND_400, "aclk_bus2rtnd_400",
3147 "mout_aclk_bus2_400_user", ENABLE_ACLK_BUS,
3148 0, CLK_IGNORE_UNUSED, 0),
3149
3150 /* ENABLE_PCLK_BUS2 */
3151 GATE(CLK_PCLK_BUSSRVND_133, "pclk_bus2srvnd_133", "div_pclk_bus2_133",
3152 ENABLE_PCLK_BUS, 2, 0, 0),
3153 GATE(CLK_PCLK_PMU_BUS, "pclk_pmu_bus2", "div_pclk_bus2_133",
3154 ENABLE_PCLK_BUS, 1, CLK_IGNORE_UNUSED, 0),
3155 GATE(CLK_PCLK_SYSREG_BUS, "pclk_sysreg_bus2", "div_pclk_bus2_133",
3156 ENABLE_PCLK_BUS, 0, CLK_IGNORE_UNUSED, 0),
3157 };
3158
3159 #define CMU_BUS_INFO_CLKS(id) \
3160 .div_clks = bus##id##_div_clks, \
3161 .nr_div_clks = ARRAY_SIZE(bus##id##_div_clks), \
3162 .gate_clks = bus##id##_gate_clks, \
3163 .nr_gate_clks = ARRAY_SIZE(bus##id##_gate_clks), \
3164 .nr_clk_ids = BUSx_NR_CLK
3165
3166 static const struct samsung_cmu_info bus0_cmu_info __initconst = {
3167 CMU_BUS_INFO_CLKS(0),
3168 .clk_regs = bus01_clk_regs,
3169 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3170 };
3171
3172 static const struct samsung_cmu_info bus1_cmu_info __initconst = {
3173 CMU_BUS_INFO_CLKS(1),
3174 .clk_regs = bus01_clk_regs,
3175 .nr_clk_regs = ARRAY_SIZE(bus01_clk_regs),
3176 };
3177
3178 static const struct samsung_cmu_info bus2_cmu_info __initconst = {
3179 CMU_BUS_INFO_CLKS(2),
3180 .mux_clks = bus2_mux_clks,
3181 .nr_mux_clks = ARRAY_SIZE(bus2_mux_clks),
3182 .clk_regs = bus2_clk_regs,
3183 .nr_clk_regs = ARRAY_SIZE(bus2_clk_regs),
3184 };
3185
3186 #define exynos5433_cmu_bus_init(id) \
3187 static void __init exynos5433_cmu_bus##id##_init(struct device_node *np)\
3188 { \
3189 samsung_cmu_register_one(np, &bus##id##_cmu_info); \
3190 } \
3191 CLK_OF_DECLARE(exynos5433_cmu_bus##id, \
3192 "samsung,exynos5433-cmu-bus"#id, \
3193 exynos5433_cmu_bus##id##_init)
3194
3195 exynos5433_cmu_bus_init(0);
3196 exynos5433_cmu_bus_init(1);
3197 exynos5433_cmu_bus_init(2);
3198
3199 /*
3200 * Register offset definitions for CMU_G3D
3201 */
3202 #define G3D_PLL_LOCK 0x0000
3203 #define G3D_PLL_CON0 0x0100
3204 #define G3D_PLL_CON1 0x0104
3205 #define G3D_PLL_FREQ_DET 0x010c
3206 #define MUX_SEL_G3D 0x0200
3207 #define MUX_ENABLE_G3D 0x0300
3208 #define MUX_STAT_G3D 0x0400
3209 #define DIV_G3D 0x0600
3210 #define DIV_G3D_PLL_FREQ_DET 0x0604
3211 #define DIV_STAT_G3D 0x0700
3212 #define DIV_STAT_G3D_PLL_FREQ_DET 0x0704
3213 #define ENABLE_ACLK_G3D 0x0800
3214 #define ENABLE_PCLK_G3D 0x0900
3215 #define ENABLE_SCLK_G3D 0x0a00
3216 #define ENABLE_IP_G3D0 0x0b00
3217 #define ENABLE_IP_G3D1 0x0b04
3218 #define CLKOUT_CMU_G3D 0x0c00
3219 #define CLKOUT_CMU_G3D_DIV_STAT 0x0c04
3220 #define CLK_STOPCTRL 0x1000
3221
3222 static const unsigned long g3d_clk_regs[] __initconst = {
3223 G3D_PLL_LOCK,
3224 G3D_PLL_CON0,
3225 G3D_PLL_CON1,
3226 G3D_PLL_FREQ_DET,
3227 MUX_SEL_G3D,
3228 MUX_ENABLE_G3D,
3229 DIV_G3D,
3230 DIV_G3D_PLL_FREQ_DET,
3231 ENABLE_ACLK_G3D,
3232 ENABLE_PCLK_G3D,
3233 ENABLE_SCLK_G3D,
3234 ENABLE_IP_G3D0,
3235 ENABLE_IP_G3D1,
3236 CLKOUT_CMU_G3D,
3237 CLKOUT_CMU_G3D_DIV_STAT,
3238 CLK_STOPCTRL,
3239 };
3240
3241 static const struct samsung_clk_reg_dump g3d_suspend_regs[] = {
3242 { MUX_SEL_G3D, 0 },
3243 };
3244
3245 /* list of all parent clock list */
3246 PNAME(mout_aclk_g3d_400_p) = { "mout_g3d_pll", "aclk_g3d_400", };
3247 PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll", };
3248
3249 static const struct samsung_pll_clock g3d_pll_clks[] __initconst = {
3250 PLL(pll_35xx, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk",
3251 G3D_PLL_LOCK, G3D_PLL_CON0, exynos5433_pll_rates),
3252 };
3253
3254 static const struct samsung_mux_clock g3d_mux_clks[] __initconst = {
3255 /* MUX_SEL_G3D */
3256 MUX_F(CLK_MOUT_ACLK_G3D_400, "mout_aclk_g3d_400", mout_aclk_g3d_400_p,
3257 MUX_SEL_G3D, 8, 1, CLK_SET_RATE_PARENT, 0),
3258 MUX_F(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p,
3259 MUX_SEL_G3D, 0, 1, CLK_SET_RATE_PARENT, 0),
3260 };
3261
3262 static const struct samsung_div_clock g3d_div_clks[] __initconst = {
3263 /* DIV_G3D */
3264 DIV(CLK_DIV_SCLK_HPM_G3D, "div_sclk_hpm_g3d", "mout_g3d_pll", DIV_G3D,
3265 8, 2),
3266 DIV(CLK_DIV_PCLK_G3D, "div_pclk_g3d", "div_aclk_g3d", DIV_G3D,
3267 4, 3),
3268 DIV_F(CLK_DIV_ACLK_G3D, "div_aclk_g3d", "mout_aclk_g3d_400", DIV_G3D,
3269 0, 3, CLK_SET_RATE_PARENT, 0),
3270 };
3271
3272 static const struct samsung_gate_clock g3d_gate_clks[] __initconst = {
3273 /* ENABLE_ACLK_G3D */
3274 GATE(CLK_ACLK_BTS_G3D1, "aclk_bts_g3d1", "div_aclk_g3d",
3275 ENABLE_ACLK_G3D, 7, 0, 0),
3276 GATE(CLK_ACLK_BTS_G3D0, "aclk_bts_g3d0", "div_aclk_g3d",
3277 ENABLE_ACLK_G3D, 6, 0, 0),
3278 GATE(CLK_ACLK_ASYNCAPBS_G3D, "aclk_asyncapbs_g3d", "div_pclk_g3d",
3279 ENABLE_ACLK_G3D, 5, CLK_IGNORE_UNUSED, 0),
3280 GATE(CLK_ACLK_ASYNCAPBM_G3D, "aclk_asyncapbm_g3d", "div_aclk_g3d",
3281 ENABLE_ACLK_G3D, 4, CLK_IGNORE_UNUSED, 0),
3282 GATE(CLK_ACLK_AHB2APB_G3DP, "aclk_ahb2apb_g3dp", "div_pclk_g3d",
3283 ENABLE_ACLK_G3D, 3, CLK_IGNORE_UNUSED, 0),
3284 GATE(CLK_ACLK_G3DNP_150, "aclk_g3dnp_150", "div_pclk_g3d",
3285 ENABLE_ACLK_G3D, 2, CLK_IGNORE_UNUSED, 0),
3286 GATE(CLK_ACLK_G3DND_600, "aclk_g3dnd_600", "div_aclk_g3d",
3287 ENABLE_ACLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3288 GATE(CLK_ACLK_G3D, "aclk_g3d", "div_aclk_g3d",
3289 ENABLE_ACLK_G3D, 0, CLK_SET_RATE_PARENT, 0),
3290
3291 /* ENABLE_PCLK_G3D */
3292 GATE(CLK_PCLK_BTS_G3D1, "pclk_bts_g3d1", "div_pclk_g3d",
3293 ENABLE_PCLK_G3D, 3, 0, 0),
3294 GATE(CLK_PCLK_BTS_G3D0, "pclk_bts_g3d0", "div_pclk_g3d",
3295 ENABLE_PCLK_G3D, 2, 0, 0),
3296 GATE(CLK_PCLK_PMU_G3D, "pclk_pmu_g3d", "div_pclk_g3d",
3297 ENABLE_PCLK_G3D, 1, CLK_IGNORE_UNUSED, 0),
3298 GATE(CLK_PCLK_SYSREG_G3D, "pclk_sysreg_g3d", "div_pclk_g3d",
3299 ENABLE_PCLK_G3D, 0, CLK_IGNORE_UNUSED, 0),
3300
3301 /* ENABLE_SCLK_G3D */
3302 GATE(CLK_SCLK_HPM_G3D, "sclk_hpm_g3d", "div_sclk_hpm_g3d",
3303 ENABLE_SCLK_G3D, 0, 0, 0),
3304 };
3305
3306 static const struct samsung_cmu_info g3d_cmu_info __initconst = {
3307 .pll_clks = g3d_pll_clks,
3308 .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks),
3309 .mux_clks = g3d_mux_clks,
3310 .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks),
3311 .div_clks = g3d_div_clks,
3312 .nr_div_clks = ARRAY_SIZE(g3d_div_clks),
3313 .gate_clks = g3d_gate_clks,
3314 .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks),
3315 .nr_clk_ids = G3D_NR_CLK,
3316 .clk_regs = g3d_clk_regs,
3317 .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs),
3318 .suspend_regs = g3d_suspend_regs,
3319 .nr_suspend_regs = ARRAY_SIZE(g3d_suspend_regs),
3320 .clk_name = "aclk_g3d_400",
3321 };
3322
3323 /*
3324 * Register offset definitions for CMU_GSCL
3325 */
3326 #define MUX_SEL_GSCL 0x0200
3327 #define MUX_ENABLE_GSCL 0x0300
3328 #define MUX_STAT_GSCL 0x0400
3329 #define ENABLE_ACLK_GSCL 0x0800
3330 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 0x0804
3331 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 0x0808
3332 #define ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 0x080c
3333 #define ENABLE_PCLK_GSCL 0x0900
3334 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 0x0904
3335 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 0x0908
3336 #define ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 0x090c
3337 #define ENABLE_IP_GSCL0 0x0b00
3338 #define ENABLE_IP_GSCL1 0x0b04
3339 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL0 0x0b08
3340 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL1 0x0b0c
3341 #define ENABLE_IP_GSCL_SECURE_SMMU_GSCL2 0x0b10
3342
3343 static const unsigned long gscl_clk_regs[] __initconst = {
3344 MUX_SEL_GSCL,
3345 MUX_ENABLE_GSCL,
3346 ENABLE_ACLK_GSCL,
3347 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0,
3348 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1,
3349 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2,
3350 ENABLE_PCLK_GSCL,
3351 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0,
3352 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1,
3353 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2,
3354 ENABLE_IP_GSCL0,
3355 ENABLE_IP_GSCL1,
3356 ENABLE_IP_GSCL_SECURE_SMMU_GSCL0,
3357 ENABLE_IP_GSCL_SECURE_SMMU_GSCL1,
3358 ENABLE_IP_GSCL_SECURE_SMMU_GSCL2,
3359 };
3360
3361 static const struct samsung_clk_reg_dump gscl_suspend_regs[] = {
3362 { MUX_SEL_GSCL, 0 },
3363 { ENABLE_ACLK_GSCL, 0xfff },
3364 { ENABLE_PCLK_GSCL, 0xff },
3365 };
3366
3367 /* list of all parent clock list */
3368 PNAME(aclk_gscl_111_user_p) = { "oscclk", "aclk_gscl_111", };
3369 PNAME(aclk_gscl_333_user_p) = { "oscclk", "aclk_gscl_333", };
3370
3371 static const struct samsung_mux_clock gscl_mux_clks[] __initconst = {
3372 /* MUX_SEL_GSCL */
3373 MUX(CLK_MOUT_ACLK_GSCL_111_USER, "mout_aclk_gscl_111_user",
3374 aclk_gscl_111_user_p, MUX_SEL_GSCL, 4, 1),
3375 MUX(CLK_MOUT_ACLK_GSCL_333_USER, "mout_aclk_gscl_333_user",
3376 aclk_gscl_333_user_p, MUX_SEL_GSCL, 0, 1),
3377 };
3378
3379 static const struct samsung_gate_clock gscl_gate_clks[] __initconst = {
3380 /* ENABLE_ACLK_GSCL */
3381 GATE(CLK_ACLK_BTS_GSCL2, "aclk_bts_gscl2", "mout_aclk_gscl_333_user",
3382 ENABLE_ACLK_GSCL, 11, 0, 0),
3383 GATE(CLK_ACLK_BTS_GSCL1, "aclk_bts_gscl1", "mout_aclk_gscl_333_user",
3384 ENABLE_ACLK_GSCL, 10, 0, 0),
3385 GATE(CLK_ACLK_BTS_GSCL0, "aclk_bts_gscl0", "mout_aclk_gscl_333_user",
3386 ENABLE_ACLK_GSCL, 9, 0, 0),
3387 GATE(CLK_ACLK_AHB2APB_GSCLP, "aclk_ahb2apb_gsclp",
3388 "mout_aclk_gscl_111_user", ENABLE_ACLK_GSCL,
3389 8, CLK_IGNORE_UNUSED, 0),
3390 GATE(CLK_ACLK_XIU_GSCLX, "aclk_xiu_gsclx", "mout_aclk_gscl_333_user",
3391 ENABLE_ACLK_GSCL, 7, 0, 0),
3392 GATE(CLK_ACLK_GSCLNP_111, "aclk_gsclnp_111", "mout_aclk_gscl_111_user",
3393 ENABLE_ACLK_GSCL, 6, CLK_IGNORE_UNUSED, 0),
3394 GATE(CLK_ACLK_GSCLRTND_333, "aclk_gsclrtnd_333",
3395 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 5,
3396 CLK_IGNORE_UNUSED, 0),
3397 GATE(CLK_ACLK_GSCLBEND_333, "aclk_gsclbend_333",
3398 "mout_aclk_gscl_333_user", ENABLE_ACLK_GSCL, 4,
3399 CLK_IGNORE_UNUSED, 0),
3400 GATE(CLK_ACLK_GSD, "aclk_gsd", "mout_aclk_gscl_333_user",
3401 ENABLE_ACLK_GSCL, 3, 0, 0),
3402 GATE(CLK_ACLK_GSCL2, "aclk_gscl2", "mout_aclk_gscl_333_user",
3403 ENABLE_ACLK_GSCL, 2, 0, 0),
3404 GATE(CLK_ACLK_GSCL1, "aclk_gscl1", "mout_aclk_gscl_333_user",
3405 ENABLE_ACLK_GSCL, 1, 0, 0),
3406 GATE(CLK_ACLK_GSCL0, "aclk_gscl0", "mout_aclk_gscl_333_user",
3407 ENABLE_ACLK_GSCL, 0, 0, 0),
3408
3409 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0 */
3410 GATE(CLK_ACLK_SMMU_GSCL0, "aclk_smmu_gscl0", "mout_aclk_gscl_333_user",
3411 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3412
3413 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1 */
3414 GATE(CLK_ACLK_SMMU_GSCL1, "aclk_smmu_gscl1", "mout_aclk_gscl_333_user",
3415 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3416
3417 /* ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2 */
3418 GATE(CLK_ACLK_SMMU_GSCL2, "aclk_smmu_gscl2", "mout_aclk_gscl_333_user",
3419 ENABLE_ACLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3420
3421 /* ENABLE_PCLK_GSCL */
3422 GATE(CLK_PCLK_BTS_GSCL2, "pclk_bts_gscl2", "mout_aclk_gscl_111_user",
3423 ENABLE_PCLK_GSCL, 7, 0, 0),
3424 GATE(CLK_PCLK_BTS_GSCL1, "pclk_bts_gscl1", "mout_aclk_gscl_111_user",
3425 ENABLE_PCLK_GSCL, 6, 0, 0),
3426 GATE(CLK_PCLK_BTS_GSCL0, "pclk_bts_gscl0", "mout_aclk_gscl_111_user",
3427 ENABLE_PCLK_GSCL, 5, 0, 0),
3428 GATE(CLK_PCLK_PMU_GSCL, "pclk_pmu_gscl", "mout_aclk_gscl_111_user",
3429 ENABLE_PCLK_GSCL, 4, CLK_IGNORE_UNUSED, 0),
3430 GATE(CLK_PCLK_SYSREG_GSCL, "pclk_sysreg_gscl",
3431 "mout_aclk_gscl_111_user", ENABLE_PCLK_GSCL,
3432 3, CLK_IGNORE_UNUSED, 0),
3433 GATE(CLK_PCLK_GSCL2, "pclk_gscl2", "mout_aclk_gscl_111_user",
3434 ENABLE_PCLK_GSCL, 2, 0, 0),
3435 GATE(CLK_PCLK_GSCL1, "pclk_gscl1", "mout_aclk_gscl_111_user",
3436 ENABLE_PCLK_GSCL, 1, 0, 0),
3437 GATE(CLK_PCLK_GSCL0, "pclk_gscl0", "mout_aclk_gscl_111_user",
3438 ENABLE_PCLK_GSCL, 0, 0, 0),
3439
3440 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0 */
3441 GATE(CLK_PCLK_SMMU_GSCL0, "pclk_smmu_gscl0", "mout_aclk_gscl_111_user",
3442 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL0, 0, 0, 0),
3443
3444 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1 */
3445 GATE(CLK_PCLK_SMMU_GSCL1, "pclk_smmu_gscl1", "mout_aclk_gscl_111_user",
3446 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL1, 0, 0, 0),
3447
3448 /* ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2 */
3449 GATE(CLK_PCLK_SMMU_GSCL2, "pclk_smmu_gscl2", "mout_aclk_gscl_111_user",
3450 ENABLE_PCLK_GSCL_SECURE_SMMU_GSCL2, 0, 0, 0),
3451 };
3452
3453 static const struct samsung_cmu_info gscl_cmu_info __initconst = {
3454 .mux_clks = gscl_mux_clks,
3455 .nr_mux_clks = ARRAY_SIZE(gscl_mux_clks),
3456 .gate_clks = gscl_gate_clks,
3457 .nr_gate_clks = ARRAY_SIZE(gscl_gate_clks),
3458 .nr_clk_ids = GSCL_NR_CLK,
3459 .clk_regs = gscl_clk_regs,
3460 .nr_clk_regs = ARRAY_SIZE(gscl_clk_regs),
3461 .suspend_regs = gscl_suspend_regs,
3462 .nr_suspend_regs = ARRAY_SIZE(gscl_suspend_regs),
3463 .clk_name = "aclk_gscl_111",
3464 };
3465
3466 /*
3467 * Register offset definitions for CMU_APOLLO
3468 */
3469 #define APOLLO_PLL_LOCK 0x0000
3470 #define APOLLO_PLL_CON0 0x0100
3471 #define APOLLO_PLL_CON1 0x0104
3472 #define APOLLO_PLL_FREQ_DET 0x010c
3473 #define MUX_SEL_APOLLO0 0x0200
3474 #define MUX_SEL_APOLLO1 0x0204
3475 #define MUX_SEL_APOLLO2 0x0208
3476 #define MUX_ENABLE_APOLLO0 0x0300
3477 #define MUX_ENABLE_APOLLO1 0x0304
3478 #define MUX_ENABLE_APOLLO2 0x0308
3479 #define MUX_STAT_APOLLO0 0x0400
3480 #define MUX_STAT_APOLLO1 0x0404
3481 #define MUX_STAT_APOLLO2 0x0408
3482 #define DIV_APOLLO0 0x0600
3483 #define DIV_APOLLO1 0x0604
3484 #define DIV_APOLLO_PLL_FREQ_DET 0x0608
3485 #define DIV_STAT_APOLLO0 0x0700
3486 #define DIV_STAT_APOLLO1 0x0704
3487 #define DIV_STAT_APOLLO_PLL_FREQ_DET 0x0708
3488 #define ENABLE_ACLK_APOLLO 0x0800
3489 #define ENABLE_PCLK_APOLLO 0x0900
3490 #define ENABLE_SCLK_APOLLO 0x0a00
3491 #define ENABLE_IP_APOLLO0 0x0b00
3492 #define ENABLE_IP_APOLLO1 0x0b04
3493 #define CLKOUT_CMU_APOLLO 0x0c00
3494 #define CLKOUT_CMU_APOLLO_DIV_STAT 0x0c04
3495 #define ARMCLK_STOPCTRL 0x1000
3496 #define APOLLO_PWR_CTRL 0x1020
3497 #define APOLLO_PWR_CTRL2 0x1024
3498 #define APOLLO_INTR_SPREAD_ENABLE 0x1080
3499 #define APOLLO_INTR_SPREAD_USE_STANDBYWFI 0x1084
3500 #define APOLLO_INTR_SPREAD_BLOCKING_DURATION 0x1088
3501
3502 static const unsigned long apollo_clk_regs[] __initconst = {
3503 APOLLO_PLL_LOCK,
3504 APOLLO_PLL_CON0,
3505 APOLLO_PLL_CON1,
3506 APOLLO_PLL_FREQ_DET,
3507 MUX_SEL_APOLLO0,
3508 MUX_SEL_APOLLO1,
3509 MUX_SEL_APOLLO2,
3510 MUX_ENABLE_APOLLO0,
3511 MUX_ENABLE_APOLLO1,
3512 MUX_ENABLE_APOLLO2,
3513 DIV_APOLLO0,
3514 DIV_APOLLO1,
3515 DIV_APOLLO_PLL_FREQ_DET,
3516 ENABLE_ACLK_APOLLO,
3517 ENABLE_PCLK_APOLLO,
3518 ENABLE_SCLK_APOLLO,
3519 ENABLE_IP_APOLLO0,
3520 ENABLE_IP_APOLLO1,
3521 CLKOUT_CMU_APOLLO,
3522 CLKOUT_CMU_APOLLO_DIV_STAT,
3523 ARMCLK_STOPCTRL,
3524 APOLLO_PWR_CTRL,
3525 APOLLO_PWR_CTRL2,
3526 APOLLO_INTR_SPREAD_ENABLE,
3527 APOLLO_INTR_SPREAD_USE_STANDBYWFI,
3528 APOLLO_INTR_SPREAD_BLOCKING_DURATION,
3529 };
3530
3531 /* list of all parent clock list */
3532 PNAME(mout_apollo_pll_p) = { "oscclk", "fout_apollo_pll", };
3533 PNAME(mout_bus_pll_apollo_user_p) = { "oscclk", "sclk_bus_pll_apollo", };
3534 PNAME(mout_apollo_p) = { "mout_apollo_pll",
3535 "mout_bus_pll_apollo_user", };
3536
3537 static const struct samsung_pll_clock apollo_pll_clks[] __initconst = {
3538 PLL(pll_35xx, CLK_FOUT_APOLLO_PLL, "fout_apollo_pll", "oscclk",
3539 APOLLO_PLL_LOCK, APOLLO_PLL_CON0, exynos5433_pll_rates),
3540 };
3541
3542 static const struct samsung_mux_clock apollo_mux_clks[] __initconst = {
3543 /* MUX_SEL_APOLLO0 */
3544 MUX_F(CLK_MOUT_APOLLO_PLL, "mout_apollo_pll", mout_apollo_pll_p,
3545 MUX_SEL_APOLLO0, 0, 1, CLK_SET_RATE_PARENT |
3546 CLK_RECALC_NEW_RATES, 0),
3547
3548 /* MUX_SEL_APOLLO1 */
3549 MUX(CLK_MOUT_BUS_PLL_APOLLO_USER, "mout_bus_pll_apollo_user",
3550 mout_bus_pll_apollo_user_p, MUX_SEL_APOLLO1, 0, 1),
3551
3552 /* MUX_SEL_APOLLO2 */
3553 MUX_F(CLK_MOUT_APOLLO, "mout_apollo", mout_apollo_p, MUX_SEL_APOLLO2,
3554 0, 1, CLK_SET_RATE_PARENT, 0),
3555 };
3556
3557 static const struct samsung_div_clock apollo_div_clks[] __initconst = {
3558 /* DIV_APOLLO0 */
3559 DIV_F(CLK_DIV_CNTCLK_APOLLO, "div_cntclk_apollo", "div_apollo2",
3560 DIV_APOLLO0, 24, 3, CLK_GET_RATE_NOCACHE,
3561 CLK_DIVIDER_READ_ONLY),
3562 DIV_F(CLK_DIV_PCLK_DBG_APOLLO, "div_pclk_dbg_apollo", "div_apollo2",
3563 DIV_APOLLO0, 20, 3, CLK_GET_RATE_NOCACHE,
3564 CLK_DIVIDER_READ_ONLY),
3565 DIV_F(CLK_DIV_ATCLK_APOLLO, "div_atclk_apollo", "div_apollo2",
3566 DIV_APOLLO0, 16, 3, CLK_GET_RATE_NOCACHE,
3567 CLK_DIVIDER_READ_ONLY),
3568 DIV_F(CLK_DIV_PCLK_APOLLO, "div_pclk_apollo", "div_apollo2",
3569 DIV_APOLLO0, 12, 3, CLK_GET_RATE_NOCACHE,
3570 CLK_DIVIDER_READ_ONLY),
3571 DIV_F(CLK_DIV_ACLK_APOLLO, "div_aclk_apollo", "div_apollo2",
3572 DIV_APOLLO0, 8, 3, CLK_GET_RATE_NOCACHE,
3573 CLK_DIVIDER_READ_ONLY),
3574 DIV_F(CLK_DIV_APOLLO2, "div_apollo2", "div_apollo1",
3575 DIV_APOLLO0, 4, 3, CLK_SET_RATE_PARENT, 0),
3576 DIV_F(CLK_DIV_APOLLO1, "div_apollo1", "mout_apollo",
3577 DIV_APOLLO0, 0, 3, CLK_SET_RATE_PARENT, 0),
3578
3579 /* DIV_APOLLO1 */
3580 DIV_F(CLK_DIV_SCLK_HPM_APOLLO, "div_sclk_hpm_apollo", "mout_apollo",
3581 DIV_APOLLO1, 4, 3, CLK_GET_RATE_NOCACHE,
3582 CLK_DIVIDER_READ_ONLY),
3583 DIV_F(CLK_DIV_APOLLO_PLL, "div_apollo_pll", "mout_apollo",
3584 DIV_APOLLO1, 0, 3, CLK_GET_RATE_NOCACHE,
3585 CLK_DIVIDER_READ_ONLY),
3586 };
3587
3588 static const struct samsung_gate_clock apollo_gate_clks[] __initconst = {
3589 /* ENABLE_ACLK_APOLLO */
3590 GATE(CLK_ACLK_ASATBSLV_APOLLO_3_CSSYS, "aclk_asatbslv_apollo_3_cssys",
3591 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3592 6, CLK_IGNORE_UNUSED, 0),
3593 GATE(CLK_ACLK_ASATBSLV_APOLLO_2_CSSYS, "aclk_asatbslv_apollo_2_cssys",
3594 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3595 5, CLK_IGNORE_UNUSED, 0),
3596 GATE(CLK_ACLK_ASATBSLV_APOLLO_1_CSSYS, "aclk_asatbslv_apollo_1_cssys",
3597 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3598 4, CLK_IGNORE_UNUSED, 0),
3599 GATE(CLK_ACLK_ASATBSLV_APOLLO_0_CSSYS, "aclk_asatbslv_apollo_0_cssys",
3600 "div_atclk_apollo", ENABLE_ACLK_APOLLO,
3601 3, CLK_IGNORE_UNUSED, 0),
3602 GATE(CLK_ACLK_ASYNCACES_APOLLO_CCI, "aclk_asyncaces_apollo_cci",
3603 "div_aclk_apollo", ENABLE_ACLK_APOLLO,
3604 2, CLK_IGNORE_UNUSED, 0),
3605 GATE(CLK_ACLK_AHB2APB_APOLLOP, "aclk_ahb2apb_apollop",
3606 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3607 1, CLK_IGNORE_UNUSED, 0),
3608 GATE(CLK_ACLK_APOLLONP_200, "aclk_apollonp_200",
3609 "div_pclk_apollo", ENABLE_ACLK_APOLLO,
3610 0, CLK_IGNORE_UNUSED, 0),
3611
3612 /* ENABLE_PCLK_APOLLO */
3613 GATE(CLK_PCLK_ASAPBMST_CSSYS_APOLLO, "pclk_asapbmst_cssys_apollo",
3614 "div_pclk_dbg_apollo", ENABLE_PCLK_APOLLO,
3615 2, CLK_IGNORE_UNUSED, 0),
3616 GATE(CLK_PCLK_PMU_APOLLO, "pclk_pmu_apollo", "div_pclk_apollo",
3617 ENABLE_PCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3618 GATE(CLK_PCLK_SYSREG_APOLLO, "pclk_sysreg_apollo",
3619 "div_pclk_apollo", ENABLE_PCLK_APOLLO,
3620 0, CLK_IGNORE_UNUSED, 0),
3621
3622 /* ENABLE_SCLK_APOLLO */
3623 GATE(CLK_CNTCLK_APOLLO, "cntclk_apollo", "div_cntclk_apollo",
3624 ENABLE_SCLK_APOLLO, 3, CLK_IGNORE_UNUSED, 0),
3625 GATE(CLK_SCLK_HPM_APOLLO, "sclk_hpm_apollo", "div_sclk_hpm_apollo",
3626 ENABLE_SCLK_APOLLO, 1, CLK_IGNORE_UNUSED, 0),
3627 };
3628
3629 #define E5433_APOLLO_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3630 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3631 ((pclk) << 12) | ((aclk) << 8))
3632
3633 #define E5433_APOLLO_DIV1(hpm, copy) \
3634 (((hpm) << 4) | ((copy) << 0))
3635
3636 static const struct exynos_cpuclk_cfg_data exynos5433_apolloclk_d[] __initconst = {
3637 { 1300000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3638 { 1200000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3639 { 1100000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3640 { 1000000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3641 { 900000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3642 { 800000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3643 { 700000, E5433_APOLLO_DIV0(3, 7, 7, 7, 2), E5433_APOLLO_DIV1(7, 1), },
3644 { 600000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3645 { 500000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3646 { 400000, E5433_APOLLO_DIV0(3, 7, 7, 7, 1), E5433_APOLLO_DIV1(7, 1), },
3647 { 0 },
3648 };
3649
exynos5433_cmu_apollo_init(struct device_node * np)3650 static void __init exynos5433_cmu_apollo_init(struct device_node *np)
3651 {
3652 void __iomem *reg_base;
3653 struct samsung_clk_provider *ctx;
3654
3655 reg_base = of_iomap(np, 0);
3656 if (!reg_base) {
3657 panic("%s: failed to map registers\n", __func__);
3658 return;
3659 }
3660
3661 ctx = samsung_clk_init(np, reg_base, APOLLO_NR_CLK);
3662 if (!ctx) {
3663 panic("%s: unable to allocate ctx\n", __func__);
3664 return;
3665 }
3666
3667 samsung_clk_register_pll(ctx, apollo_pll_clks,
3668 ARRAY_SIZE(apollo_pll_clks), reg_base);
3669 samsung_clk_register_mux(ctx, apollo_mux_clks,
3670 ARRAY_SIZE(apollo_mux_clks));
3671 samsung_clk_register_div(ctx, apollo_div_clks,
3672 ARRAY_SIZE(apollo_div_clks));
3673 samsung_clk_register_gate(ctx, apollo_gate_clks,
3674 ARRAY_SIZE(apollo_gate_clks));
3675
3676 exynos_register_cpu_clock(ctx, CLK_SCLK_APOLLO, "apolloclk",
3677 mout_apollo_p[0], mout_apollo_p[1], 0x200,
3678 exynos5433_apolloclk_d, ARRAY_SIZE(exynos5433_apolloclk_d),
3679 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3680
3681 samsung_clk_sleep_init(reg_base, apollo_clk_regs,
3682 ARRAY_SIZE(apollo_clk_regs));
3683
3684 samsung_clk_of_add_provider(np, ctx);
3685 }
3686 CLK_OF_DECLARE(exynos5433_cmu_apollo, "samsung,exynos5433-cmu-apollo",
3687 exynos5433_cmu_apollo_init);
3688
3689 /*
3690 * Register offset definitions for CMU_ATLAS
3691 */
3692 #define ATLAS_PLL_LOCK 0x0000
3693 #define ATLAS_PLL_CON0 0x0100
3694 #define ATLAS_PLL_CON1 0x0104
3695 #define ATLAS_PLL_FREQ_DET 0x010c
3696 #define MUX_SEL_ATLAS0 0x0200
3697 #define MUX_SEL_ATLAS1 0x0204
3698 #define MUX_SEL_ATLAS2 0x0208
3699 #define MUX_ENABLE_ATLAS0 0x0300
3700 #define MUX_ENABLE_ATLAS1 0x0304
3701 #define MUX_ENABLE_ATLAS2 0x0308
3702 #define MUX_STAT_ATLAS0 0x0400
3703 #define MUX_STAT_ATLAS1 0x0404
3704 #define MUX_STAT_ATLAS2 0x0408
3705 #define DIV_ATLAS0 0x0600
3706 #define DIV_ATLAS1 0x0604
3707 #define DIV_ATLAS_PLL_FREQ_DET 0x0608
3708 #define DIV_STAT_ATLAS0 0x0700
3709 #define DIV_STAT_ATLAS1 0x0704
3710 #define DIV_STAT_ATLAS_PLL_FREQ_DET 0x0708
3711 #define ENABLE_ACLK_ATLAS 0x0800
3712 #define ENABLE_PCLK_ATLAS 0x0900
3713 #define ENABLE_SCLK_ATLAS 0x0a00
3714 #define ENABLE_IP_ATLAS0 0x0b00
3715 #define ENABLE_IP_ATLAS1 0x0b04
3716 #define CLKOUT_CMU_ATLAS 0x0c00
3717 #define CLKOUT_CMU_ATLAS_DIV_STAT 0x0c04
3718 #define ARMCLK_STOPCTRL 0x1000
3719 #define ATLAS_PWR_CTRL 0x1020
3720 #define ATLAS_PWR_CTRL2 0x1024
3721 #define ATLAS_INTR_SPREAD_ENABLE 0x1080
3722 #define ATLAS_INTR_SPREAD_USE_STANDBYWFI 0x1084
3723 #define ATLAS_INTR_SPREAD_BLOCKING_DURATION 0x1088
3724
3725 static const unsigned long atlas_clk_regs[] __initconst = {
3726 ATLAS_PLL_LOCK,
3727 ATLAS_PLL_CON0,
3728 ATLAS_PLL_CON1,
3729 ATLAS_PLL_FREQ_DET,
3730 MUX_SEL_ATLAS0,
3731 MUX_SEL_ATLAS1,
3732 MUX_SEL_ATLAS2,
3733 MUX_ENABLE_ATLAS0,
3734 MUX_ENABLE_ATLAS1,
3735 MUX_ENABLE_ATLAS2,
3736 DIV_ATLAS0,
3737 DIV_ATLAS1,
3738 DIV_ATLAS_PLL_FREQ_DET,
3739 ENABLE_ACLK_ATLAS,
3740 ENABLE_PCLK_ATLAS,
3741 ENABLE_SCLK_ATLAS,
3742 ENABLE_IP_ATLAS0,
3743 ENABLE_IP_ATLAS1,
3744 CLKOUT_CMU_ATLAS,
3745 CLKOUT_CMU_ATLAS_DIV_STAT,
3746 ARMCLK_STOPCTRL,
3747 ATLAS_PWR_CTRL,
3748 ATLAS_PWR_CTRL2,
3749 ATLAS_INTR_SPREAD_ENABLE,
3750 ATLAS_INTR_SPREAD_USE_STANDBYWFI,
3751 ATLAS_INTR_SPREAD_BLOCKING_DURATION,
3752 };
3753
3754 /* list of all parent clock list */
3755 PNAME(mout_atlas_pll_p) = { "oscclk", "fout_atlas_pll", };
3756 PNAME(mout_bus_pll_atlas_user_p) = { "oscclk", "sclk_bus_pll_atlas", };
3757 PNAME(mout_atlas_p) = { "mout_atlas_pll",
3758 "mout_bus_pll_atlas_user", };
3759
3760 static const struct samsung_pll_clock atlas_pll_clks[] __initconst = {
3761 PLL(pll_35xx, CLK_FOUT_ATLAS_PLL, "fout_atlas_pll", "oscclk",
3762 ATLAS_PLL_LOCK, ATLAS_PLL_CON0, exynos5433_pll_rates),
3763 };
3764
3765 static const struct samsung_mux_clock atlas_mux_clks[] __initconst = {
3766 /* MUX_SEL_ATLAS0 */
3767 MUX_F(CLK_MOUT_ATLAS_PLL, "mout_atlas_pll", mout_atlas_pll_p,
3768 MUX_SEL_ATLAS0, 0, 1, CLK_SET_RATE_PARENT |
3769 CLK_RECALC_NEW_RATES, 0),
3770
3771 /* MUX_SEL_ATLAS1 */
3772 MUX(CLK_MOUT_BUS_PLL_ATLAS_USER, "mout_bus_pll_atlas_user",
3773 mout_bus_pll_atlas_user_p, MUX_SEL_ATLAS1, 0, 1),
3774
3775 /* MUX_SEL_ATLAS2 */
3776 MUX_F(CLK_MOUT_ATLAS, "mout_atlas", mout_atlas_p, MUX_SEL_ATLAS2,
3777 0, 1, CLK_SET_RATE_PARENT, 0),
3778 };
3779
3780 static const struct samsung_div_clock atlas_div_clks[] __initconst = {
3781 /* DIV_ATLAS0 */
3782 DIV_F(CLK_DIV_CNTCLK_ATLAS, "div_cntclk_atlas", "div_atlas2",
3783 DIV_ATLAS0, 24, 3, CLK_GET_RATE_NOCACHE,
3784 CLK_DIVIDER_READ_ONLY),
3785 DIV_F(CLK_DIV_PCLK_DBG_ATLAS, "div_pclk_dbg_atlas", "div_atclk_atlas",
3786 DIV_ATLAS0, 20, 3, CLK_GET_RATE_NOCACHE,
3787 CLK_DIVIDER_READ_ONLY),
3788 DIV_F(CLK_DIV_ATCLK_ATLASO, "div_atclk_atlas", "div_atlas2",
3789 DIV_ATLAS0, 16, 3, CLK_GET_RATE_NOCACHE,
3790 CLK_DIVIDER_READ_ONLY),
3791 DIV_F(CLK_DIV_PCLK_ATLAS, "div_pclk_atlas", "div_atlas2",
3792 DIV_ATLAS0, 12, 3, CLK_GET_RATE_NOCACHE,
3793 CLK_DIVIDER_READ_ONLY),
3794 DIV_F(CLK_DIV_ACLK_ATLAS, "div_aclk_atlas", "div_atlas2",
3795 DIV_ATLAS0, 8, 3, CLK_GET_RATE_NOCACHE,
3796 CLK_DIVIDER_READ_ONLY),
3797 DIV_F(CLK_DIV_ATLAS2, "div_atlas2", "div_atlas1",
3798 DIV_ATLAS0, 4, 3, CLK_SET_RATE_PARENT, 0),
3799 DIV_F(CLK_DIV_ATLAS1, "div_atlas1", "mout_atlas",
3800 DIV_ATLAS0, 0, 3, CLK_SET_RATE_PARENT, 0),
3801
3802 /* DIV_ATLAS1 */
3803 DIV_F(CLK_DIV_SCLK_HPM_ATLAS, "div_sclk_hpm_atlas", "mout_atlas",
3804 DIV_ATLAS1, 4, 3, CLK_GET_RATE_NOCACHE,
3805 CLK_DIVIDER_READ_ONLY),
3806 DIV_F(CLK_DIV_ATLAS_PLL, "div_atlas_pll", "mout_atlas",
3807 DIV_ATLAS1, 0, 3, CLK_GET_RATE_NOCACHE,
3808 CLK_DIVIDER_READ_ONLY),
3809 };
3810
3811 static const struct samsung_gate_clock atlas_gate_clks[] __initconst = {
3812 /* ENABLE_ACLK_ATLAS */
3813 GATE(CLK_ACLK_ATB_AUD_CSSYS, "aclk_atb_aud_cssys",
3814 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3815 9, CLK_IGNORE_UNUSED, 0),
3816 GATE(CLK_ACLK_ATB_APOLLO3_CSSYS, "aclk_atb_apollo3_cssys",
3817 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3818 8, CLK_IGNORE_UNUSED, 0),
3819 GATE(CLK_ACLK_ATB_APOLLO2_CSSYS, "aclk_atb_apollo2_cssys",
3820 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3821 7, CLK_IGNORE_UNUSED, 0),
3822 GATE(CLK_ACLK_ATB_APOLLO1_CSSYS, "aclk_atb_apollo1_cssys",
3823 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3824 6, CLK_IGNORE_UNUSED, 0),
3825 GATE(CLK_ACLK_ATB_APOLLO0_CSSYS, "aclk_atb_apollo0_cssys",
3826 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3827 5, CLK_IGNORE_UNUSED, 0),
3828 GATE(CLK_ACLK_ASYNCAHBS_CSSYS_SSS, "aclk_asyncahbs_cssys_sss",
3829 "div_atclk_atlas", ENABLE_ACLK_ATLAS,
3830 4, CLK_IGNORE_UNUSED, 0),
3831 GATE(CLK_ACLK_ASYNCAXIS_CSSYS_CCIX, "aclk_asyncaxis_cssys_ccix",
3832 "div_pclk_dbg_atlas", ENABLE_ACLK_ATLAS,
3833 3, CLK_IGNORE_UNUSED, 0),
3834 GATE(CLK_ACLK_ASYNCACES_ATLAS_CCI, "aclk_asyncaces_atlas_cci",
3835 "div_aclk_atlas", ENABLE_ACLK_ATLAS,
3836 2, CLK_IGNORE_UNUSED, 0),
3837 GATE(CLK_ACLK_AHB2APB_ATLASP, "aclk_ahb2apb_atlasp", "div_pclk_atlas",
3838 ENABLE_ACLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3839 GATE(CLK_ACLK_ATLASNP_200, "aclk_atlasnp_200", "div_pclk_atlas",
3840 ENABLE_ACLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3841
3842 /* ENABLE_PCLK_ATLAS */
3843 GATE(CLK_PCLK_ASYNCAPB_AUD_CSSYS, "pclk_asyncapb_aud_cssys",
3844 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3845 5, CLK_IGNORE_UNUSED, 0),
3846 GATE(CLK_PCLK_ASYNCAPB_ISP_CSSYS, "pclk_asyncapb_isp_cssys",
3847 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3848 4, CLK_IGNORE_UNUSED, 0),
3849 GATE(CLK_PCLK_ASYNCAPB_APOLLO_CSSYS, "pclk_asyncapb_apollo_cssys",
3850 "div_pclk_dbg_atlas", ENABLE_PCLK_ATLAS,
3851 3, CLK_IGNORE_UNUSED, 0),
3852 GATE(CLK_PCLK_PMU_ATLAS, "pclk_pmu_atlas", "div_pclk_atlas",
3853 ENABLE_PCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3854 GATE(CLK_PCLK_SYSREG_ATLAS, "pclk_sysreg_atlas", "div_pclk_atlas",
3855 ENABLE_PCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3856 GATE(CLK_PCLK_SECJTAG, "pclk_secjtag", "div_pclk_dbg_atlas",
3857 ENABLE_PCLK_ATLAS, 0, CLK_IGNORE_UNUSED, 0),
3858
3859 /* ENABLE_SCLK_ATLAS */
3860 GATE(CLK_CNTCLK_ATLAS, "cntclk_atlas", "div_cntclk_atlas",
3861 ENABLE_SCLK_ATLAS, 10, CLK_IGNORE_UNUSED, 0),
3862 GATE(CLK_SCLK_HPM_ATLAS, "sclk_hpm_atlas", "div_sclk_hpm_atlas",
3863 ENABLE_SCLK_ATLAS, 7, CLK_IGNORE_UNUSED, 0),
3864 GATE(CLK_TRACECLK, "traceclk", "div_atclk_atlas",
3865 ENABLE_SCLK_ATLAS, 6, CLK_IGNORE_UNUSED, 0),
3866 GATE(CLK_CTMCLK, "ctmclk", "div_atclk_atlas",
3867 ENABLE_SCLK_ATLAS, 5, CLK_IGNORE_UNUSED, 0),
3868 GATE(CLK_HCLK_CSSYS, "hclk_cssys", "div_atclk_atlas",
3869 ENABLE_SCLK_ATLAS, 4, CLK_IGNORE_UNUSED, 0),
3870 GATE(CLK_PCLK_DBG_CSSYS, "pclk_dbg_cssys", "div_pclk_dbg_atlas",
3871 ENABLE_SCLK_ATLAS, 3, CLK_IGNORE_UNUSED, 0),
3872 GATE(CLK_PCLK_DBG, "pclk_dbg", "div_pclk_dbg_atlas",
3873 ENABLE_SCLK_ATLAS, 2, CLK_IGNORE_UNUSED, 0),
3874 GATE(CLK_ATCLK, "atclk", "div_atclk_atlas",
3875 ENABLE_SCLK_ATLAS, 1, CLK_IGNORE_UNUSED, 0),
3876 };
3877
3878 #define E5433_ATLAS_DIV0(cntclk, pclk_dbg, atclk, pclk, aclk) \
3879 (((cntclk) << 24) | ((pclk_dbg) << 20) | ((atclk) << 16) | \
3880 ((pclk) << 12) | ((aclk) << 8))
3881
3882 #define E5433_ATLAS_DIV1(hpm, copy) \
3883 (((hpm) << 4) | ((copy) << 0))
3884
3885 static const struct exynos_cpuclk_cfg_data exynos5433_atlasclk_d[] __initconst = {
3886 { 1900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3887 { 1800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3888 { 1700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3889 { 1600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 4), E5433_ATLAS_DIV1(7, 1), },
3890 { 1500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3891 { 1400000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3892 { 1300000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3893 { 1200000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3894 { 1100000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3895 { 1000000, E5433_ATLAS_DIV0(7, 7, 7, 7, 3), E5433_ATLAS_DIV1(7, 1), },
3896 { 900000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3897 { 800000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3898 { 700000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3899 { 600000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3900 { 500000, E5433_ATLAS_DIV0(7, 7, 7, 7, 2), E5433_ATLAS_DIV1(7, 1), },
3901 { 0 },
3902 };
3903
exynos5433_cmu_atlas_init(struct device_node * np)3904 static void __init exynos5433_cmu_atlas_init(struct device_node *np)
3905 {
3906 void __iomem *reg_base;
3907 struct samsung_clk_provider *ctx;
3908
3909 reg_base = of_iomap(np, 0);
3910 if (!reg_base) {
3911 panic("%s: failed to map registers\n", __func__);
3912 return;
3913 }
3914
3915 ctx = samsung_clk_init(np, reg_base, ATLAS_NR_CLK);
3916 if (!ctx) {
3917 panic("%s: unable to allocate ctx\n", __func__);
3918 return;
3919 }
3920
3921 samsung_clk_register_pll(ctx, atlas_pll_clks,
3922 ARRAY_SIZE(atlas_pll_clks), reg_base);
3923 samsung_clk_register_mux(ctx, atlas_mux_clks,
3924 ARRAY_SIZE(atlas_mux_clks));
3925 samsung_clk_register_div(ctx, atlas_div_clks,
3926 ARRAY_SIZE(atlas_div_clks));
3927 samsung_clk_register_gate(ctx, atlas_gate_clks,
3928 ARRAY_SIZE(atlas_gate_clks));
3929
3930 exynos_register_cpu_clock(ctx, CLK_SCLK_ATLAS, "atlasclk",
3931 mout_atlas_p[0], mout_atlas_p[1], 0x200,
3932 exynos5433_atlasclk_d, ARRAY_SIZE(exynos5433_atlasclk_d),
3933 CLK_CPU_HAS_E5433_REGS_LAYOUT);
3934
3935 samsung_clk_sleep_init(reg_base, atlas_clk_regs,
3936 ARRAY_SIZE(atlas_clk_regs));
3937
3938 samsung_clk_of_add_provider(np, ctx);
3939 }
3940 CLK_OF_DECLARE(exynos5433_cmu_atlas, "samsung,exynos5433-cmu-atlas",
3941 exynos5433_cmu_atlas_init);
3942
3943 /*
3944 * Register offset definitions for CMU_MSCL
3945 */
3946 #define MUX_SEL_MSCL0 0x0200
3947 #define MUX_SEL_MSCL1 0x0204
3948 #define MUX_ENABLE_MSCL0 0x0300
3949 #define MUX_ENABLE_MSCL1 0x0304
3950 #define MUX_STAT_MSCL0 0x0400
3951 #define MUX_STAT_MSCL1 0x0404
3952 #define DIV_MSCL 0x0600
3953 #define DIV_STAT_MSCL 0x0700
3954 #define ENABLE_ACLK_MSCL 0x0800
3955 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0804
3956 #define ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0808
3957 #define ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG 0x080c
3958 #define ENABLE_PCLK_MSCL 0x0900
3959 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 0x0904
3960 #define ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 0x0908
3961 #define ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG 0x090c
3962 #define ENABLE_SCLK_MSCL 0x0a00
3963 #define ENABLE_IP_MSCL0 0x0b00
3964 #define ENABLE_IP_MSCL1 0x0b04
3965 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0 0x0b08
3966 #define ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1 0x0b0c
3967 #define ENABLE_IP_MSCL_SECURE_SMMU_JPEG 0x0b10
3968
3969 static const unsigned long mscl_clk_regs[] __initconst = {
3970 MUX_SEL_MSCL0,
3971 MUX_SEL_MSCL1,
3972 MUX_ENABLE_MSCL0,
3973 MUX_ENABLE_MSCL1,
3974 DIV_MSCL,
3975 ENABLE_ACLK_MSCL,
3976 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
3977 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
3978 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
3979 ENABLE_PCLK_MSCL,
3980 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
3981 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
3982 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
3983 ENABLE_SCLK_MSCL,
3984 ENABLE_IP_MSCL0,
3985 ENABLE_IP_MSCL1,
3986 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER0,
3987 ENABLE_IP_MSCL_SECURE_SMMU_M2MSCALER1,
3988 ENABLE_IP_MSCL_SECURE_SMMU_JPEG,
3989 };
3990
3991 static const struct samsung_clk_reg_dump mscl_suspend_regs[] = {
3992 { MUX_SEL_MSCL0, 0 },
3993 { MUX_SEL_MSCL1, 0 },
3994 };
3995
3996 /* list of all parent clock list */
3997 PNAME(mout_sclk_jpeg_user_p) = { "oscclk", "sclk_jpeg_mscl", };
3998 PNAME(mout_aclk_mscl_400_user_p) = { "oscclk", "aclk_mscl_400", };
3999 PNAME(mout_sclk_jpeg_p) = { "mout_sclk_jpeg_user",
4000 "mout_aclk_mscl_400_user", };
4001
4002 static const struct samsung_mux_clock mscl_mux_clks[] __initconst = {
4003 /* MUX_SEL_MSCL0 */
4004 MUX(CLK_MOUT_SCLK_JPEG_USER, "mout_sclk_jpeg_user",
4005 mout_sclk_jpeg_user_p, MUX_SEL_MSCL0, 4, 1),
4006 MUX(CLK_MOUT_ACLK_MSCL_400_USER, "mout_aclk_mscl_400_user",
4007 mout_aclk_mscl_400_user_p, MUX_SEL_MSCL0, 0, 1),
4008
4009 /* MUX_SEL_MSCL1 */
4010 MUX(CLK_MOUT_SCLK_JPEG, "mout_sclk_jpeg", mout_sclk_jpeg_p,
4011 MUX_SEL_MSCL1, 0, 1),
4012 };
4013
4014 static const struct samsung_div_clock mscl_div_clks[] __initconst = {
4015 /* DIV_MSCL */
4016 DIV(CLK_DIV_PCLK_MSCL, "div_pclk_mscl", "mout_aclk_mscl_400_user",
4017 DIV_MSCL, 0, 3),
4018 };
4019
4020 static const struct samsung_gate_clock mscl_gate_clks[] __initconst = {
4021 /* ENABLE_ACLK_MSCL */
4022 GATE(CLK_ACLK_BTS_JPEG, "aclk_bts_jpeg", "mout_aclk_mscl_400_user",
4023 ENABLE_ACLK_MSCL, 9, 0, 0),
4024 GATE(CLK_ACLK_BTS_M2MSCALER1, "aclk_bts_m2mscaler1",
4025 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 8, 0, 0),
4026 GATE(CLK_ACLK_BTS_M2MSCALER0, "aclk_bts_m2mscaler0",
4027 "mout_aclk_mscl_400_user", ENABLE_ACLK_MSCL, 7, 0, 0),
4028 GATE(CLK_ACLK_AHB2APB_MSCL0P, "aclk_abh2apb_mscl0p", "div_pclk_mscl",
4029 ENABLE_ACLK_MSCL, 6, CLK_IGNORE_UNUSED, 0),
4030 GATE(CLK_ACLK_XIU_MSCLX, "aclk_xiu_msclx", "mout_aclk_mscl_400_user",
4031 ENABLE_ACLK_MSCL, 5, CLK_IGNORE_UNUSED, 0),
4032 GATE(CLK_ACLK_MSCLNP_100, "aclk_msclnp_100", "div_pclk_mscl",
4033 ENABLE_ACLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4034 GATE(CLK_ACLK_MSCLND_400, "aclk_msclnd_400", "mout_aclk_mscl_400_user",
4035 ENABLE_ACLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4036 GATE(CLK_ACLK_JPEG, "aclk_jpeg", "mout_aclk_mscl_400_user",
4037 ENABLE_ACLK_MSCL, 2, 0, 0),
4038 GATE(CLK_ACLK_M2MSCALER1, "aclk_m2mscaler1", "mout_aclk_mscl_400_user",
4039 ENABLE_ACLK_MSCL, 1, 0, 0),
4040 GATE(CLK_ACLK_M2MSCALER0, "aclk_m2mscaler0", "mout_aclk_mscl_400_user",
4041 ENABLE_ACLK_MSCL, 0, 0, 0),
4042
4043 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4044 GATE(CLK_ACLK_SMMU_M2MSCALER0, "aclk_smmu_m2mscaler0",
4045 "mout_aclk_mscl_400_user",
4046 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER0,
4047 0, CLK_IGNORE_UNUSED, 0),
4048
4049 /* ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4050 GATE(CLK_ACLK_SMMU_M2MSCALER1, "aclk_smmu_m2mscaler1",
4051 "mout_aclk_mscl_400_user",
4052 ENABLE_ACLK_MSCL_SECURE_SMMU_M2MSCALER1,
4053 0, CLK_IGNORE_UNUSED, 0),
4054
4055 /* ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG */
4056 GATE(CLK_ACLK_SMMU_JPEG, "aclk_smmu_jpeg", "mout_aclk_mscl_400_user",
4057 ENABLE_ACLK_MSCL_SECURE_SMMU_JPEG,
4058 0, CLK_IGNORE_UNUSED, 0),
4059
4060 /* ENABLE_PCLK_MSCL */
4061 GATE(CLK_PCLK_BTS_JPEG, "pclk_bts_jpeg", "div_pclk_mscl",
4062 ENABLE_PCLK_MSCL, 7, 0, 0),
4063 GATE(CLK_PCLK_BTS_M2MSCALER1, "pclk_bts_m2mscaler1", "div_pclk_mscl",
4064 ENABLE_PCLK_MSCL, 6, 0, 0),
4065 GATE(CLK_PCLK_BTS_M2MSCALER0, "pclk_bts_m2mscaler0", "div_pclk_mscl",
4066 ENABLE_PCLK_MSCL, 5, 0, 0),
4067 GATE(CLK_PCLK_PMU_MSCL, "pclk_pmu_mscl", "div_pclk_mscl",
4068 ENABLE_PCLK_MSCL, 4, CLK_IGNORE_UNUSED, 0),
4069 GATE(CLK_PCLK_SYSREG_MSCL, "pclk_sysreg_mscl", "div_pclk_mscl",
4070 ENABLE_PCLK_MSCL, 3, CLK_IGNORE_UNUSED, 0),
4071 GATE(CLK_PCLK_JPEG, "pclk_jpeg", "div_pclk_mscl",
4072 ENABLE_PCLK_MSCL, 2, 0, 0),
4073 GATE(CLK_PCLK_M2MSCALER1, "pclk_m2mscaler1", "div_pclk_mscl",
4074 ENABLE_PCLK_MSCL, 1, 0, 0),
4075 GATE(CLK_PCLK_M2MSCALER0, "pclk_m2mscaler0", "div_pclk_mscl",
4076 ENABLE_PCLK_MSCL, 0, 0, 0),
4077
4078 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0 */
4079 GATE(CLK_PCLK_SMMU_M2MSCALER0, "pclk_smmu_m2mscaler0", "div_pclk_mscl",
4080 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER0,
4081 0, CLK_IGNORE_UNUSED, 0),
4082
4083 /* ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1 */
4084 GATE(CLK_PCLK_SMMU_M2MSCALER1, "pclk_smmu_m2mscaler1", "div_pclk_mscl",
4085 ENABLE_PCLK_MSCL_SECURE_SMMU_M2MSCALER1,
4086 0, CLK_IGNORE_UNUSED, 0),
4087
4088 /* ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG */
4089 GATE(CLK_PCLK_SMMU_JPEG, "pclk_smmu_jpeg", "div_pclk_mscl",
4090 ENABLE_PCLK_MSCL_SECURE_SMMU_JPEG,
4091 0, CLK_IGNORE_UNUSED, 0),
4092
4093 /* ENABLE_SCLK_MSCL */
4094 GATE(CLK_SCLK_JPEG, "sclk_jpeg", "mout_sclk_jpeg", ENABLE_SCLK_MSCL, 0,
4095 CLK_IGNORE_UNUSED | CLK_SET_RATE_PARENT, 0),
4096 };
4097
4098 static const struct samsung_cmu_info mscl_cmu_info __initconst = {
4099 .mux_clks = mscl_mux_clks,
4100 .nr_mux_clks = ARRAY_SIZE(mscl_mux_clks),
4101 .div_clks = mscl_div_clks,
4102 .nr_div_clks = ARRAY_SIZE(mscl_div_clks),
4103 .gate_clks = mscl_gate_clks,
4104 .nr_gate_clks = ARRAY_SIZE(mscl_gate_clks),
4105 .nr_clk_ids = MSCL_NR_CLK,
4106 .clk_regs = mscl_clk_regs,
4107 .nr_clk_regs = ARRAY_SIZE(mscl_clk_regs),
4108 .suspend_regs = mscl_suspend_regs,
4109 .nr_suspend_regs = ARRAY_SIZE(mscl_suspend_regs),
4110 .clk_name = "aclk_mscl_400",
4111 };
4112
4113 /*
4114 * Register offset definitions for CMU_MFC
4115 */
4116 #define MUX_SEL_MFC 0x0200
4117 #define MUX_ENABLE_MFC 0x0300
4118 #define MUX_STAT_MFC 0x0400
4119 #define DIV_MFC 0x0600
4120 #define DIV_STAT_MFC 0x0700
4121 #define ENABLE_ACLK_MFC 0x0800
4122 #define ENABLE_ACLK_MFC_SECURE_SMMU_MFC 0x0804
4123 #define ENABLE_PCLK_MFC 0x0900
4124 #define ENABLE_PCLK_MFC_SECURE_SMMU_MFC 0x0904
4125 #define ENABLE_IP_MFC0 0x0b00
4126 #define ENABLE_IP_MFC1 0x0b04
4127 #define ENABLE_IP_MFC_SECURE_SMMU_MFC 0x0b08
4128
4129 static const unsigned long mfc_clk_regs[] __initconst = {
4130 MUX_SEL_MFC,
4131 MUX_ENABLE_MFC,
4132 DIV_MFC,
4133 ENABLE_ACLK_MFC,
4134 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4135 ENABLE_PCLK_MFC,
4136 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4137 ENABLE_IP_MFC0,
4138 ENABLE_IP_MFC1,
4139 ENABLE_IP_MFC_SECURE_SMMU_MFC,
4140 };
4141
4142 static const struct samsung_clk_reg_dump mfc_suspend_regs[] = {
4143 { MUX_SEL_MFC, 0 },
4144 };
4145
4146 PNAME(mout_aclk_mfc_400_user_p) = { "oscclk", "aclk_mfc_400", };
4147
4148 static const struct samsung_mux_clock mfc_mux_clks[] __initconst = {
4149 /* MUX_SEL_MFC */
4150 MUX(CLK_MOUT_ACLK_MFC_400_USER, "mout_aclk_mfc_400_user",
4151 mout_aclk_mfc_400_user_p, MUX_SEL_MFC, 0, 0),
4152 };
4153
4154 static const struct samsung_div_clock mfc_div_clks[] __initconst = {
4155 /* DIV_MFC */
4156 DIV(CLK_DIV_PCLK_MFC, "div_pclk_mfc", "mout_aclk_mfc_400_user",
4157 DIV_MFC, 0, 2),
4158 };
4159
4160 static const struct samsung_gate_clock mfc_gate_clks[] __initconst = {
4161 /* ENABLE_ACLK_MFC */
4162 GATE(CLK_ACLK_BTS_MFC_1, "aclk_bts_mfc_1", "mout_aclk_mfc_400_user",
4163 ENABLE_ACLK_MFC, 6, 0, 0),
4164 GATE(CLK_ACLK_BTS_MFC_0, "aclk_bts_mfc_0", "mout_aclk_mfc_400_user",
4165 ENABLE_ACLK_MFC, 5, 0, 0),
4166 GATE(CLK_ACLK_AHB2APB_MFCP, "aclk_ahb2apb_mfcp", "div_pclk_mfc",
4167 ENABLE_ACLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4168 GATE(CLK_ACLK_XIU_MFCX, "aclk_xiu_mfcx", "mout_aclk_mfc_400_user",
4169 ENABLE_ACLK_MFC, 3, CLK_IGNORE_UNUSED, 0),
4170 GATE(CLK_ACLK_MFCNP_100, "aclk_mfcnp_100", "div_pclk_mfc",
4171 ENABLE_ACLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4172 GATE(CLK_ACLK_MFCND_400, "aclk_mfcnd_400", "mout_aclk_mfc_400_user",
4173 ENABLE_ACLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4174 GATE(CLK_ACLK_MFC, "aclk_mfc", "mout_aclk_mfc_400_user",
4175 ENABLE_ACLK_MFC, 0, 0, 0),
4176
4177 /* ENABLE_ACLK_MFC_SECURE_SMMU_MFC */
4178 GATE(CLK_ACLK_SMMU_MFC_1, "aclk_smmu_mfc_1", "mout_aclk_mfc_400_user",
4179 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4180 1, CLK_IGNORE_UNUSED, 0),
4181 GATE(CLK_ACLK_SMMU_MFC_0, "aclk_smmu_mfc_0", "mout_aclk_mfc_400_user",
4182 ENABLE_ACLK_MFC_SECURE_SMMU_MFC,
4183 0, CLK_IGNORE_UNUSED, 0),
4184
4185 /* ENABLE_PCLK_MFC */
4186 GATE(CLK_PCLK_BTS_MFC_1, "pclk_bts_mfc_1", "div_pclk_mfc",
4187 ENABLE_PCLK_MFC, 4, 0, 0),
4188 GATE(CLK_PCLK_BTS_MFC_0, "pclk_bts_mfc_0", "div_pclk_mfc",
4189 ENABLE_PCLK_MFC, 3, 0, 0),
4190 GATE(CLK_PCLK_PMU_MFC, "pclk_pmu_mfc", "div_pclk_mfc",
4191 ENABLE_PCLK_MFC, 2, CLK_IGNORE_UNUSED, 0),
4192 GATE(CLK_PCLK_SYSREG_MFC, "pclk_sysreg_mfc", "div_pclk_mfc",
4193 ENABLE_PCLK_MFC, 1, CLK_IGNORE_UNUSED, 0),
4194 GATE(CLK_PCLK_MFC, "pclk_mfc", "div_pclk_mfc",
4195 ENABLE_PCLK_MFC, 4, CLK_IGNORE_UNUSED, 0),
4196
4197 /* ENABLE_PCLK_MFC_SECURE_SMMU_MFC */
4198 GATE(CLK_PCLK_SMMU_MFC_1, "pclk_smmu_mfc_1", "div_pclk_mfc",
4199 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4200 1, CLK_IGNORE_UNUSED, 0),
4201 GATE(CLK_PCLK_SMMU_MFC_0, "pclk_smmu_mfc_0", "div_pclk_mfc",
4202 ENABLE_PCLK_MFC_SECURE_SMMU_MFC,
4203 0, CLK_IGNORE_UNUSED, 0),
4204 };
4205
4206 static const struct samsung_cmu_info mfc_cmu_info __initconst = {
4207 .mux_clks = mfc_mux_clks,
4208 .nr_mux_clks = ARRAY_SIZE(mfc_mux_clks),
4209 .div_clks = mfc_div_clks,
4210 .nr_div_clks = ARRAY_SIZE(mfc_div_clks),
4211 .gate_clks = mfc_gate_clks,
4212 .nr_gate_clks = ARRAY_SIZE(mfc_gate_clks),
4213 .nr_clk_ids = MFC_NR_CLK,
4214 .clk_regs = mfc_clk_regs,
4215 .nr_clk_regs = ARRAY_SIZE(mfc_clk_regs),
4216 .suspend_regs = mfc_suspend_regs,
4217 .nr_suspend_regs = ARRAY_SIZE(mfc_suspend_regs),
4218 .clk_name = "aclk_mfc_400",
4219 };
4220
4221 /*
4222 * Register offset definitions for CMU_HEVC
4223 */
4224 #define MUX_SEL_HEVC 0x0200
4225 #define MUX_ENABLE_HEVC 0x0300
4226 #define MUX_STAT_HEVC 0x0400
4227 #define DIV_HEVC 0x0600
4228 #define DIV_STAT_HEVC 0x0700
4229 #define ENABLE_ACLK_HEVC 0x0800
4230 #define ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC 0x0804
4231 #define ENABLE_PCLK_HEVC 0x0900
4232 #define ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC 0x0904
4233 #define ENABLE_IP_HEVC0 0x0b00
4234 #define ENABLE_IP_HEVC1 0x0b04
4235 #define ENABLE_IP_HEVC_SECURE_SMMU_HEVC 0x0b08
4236
4237 static const unsigned long hevc_clk_regs[] __initconst = {
4238 MUX_SEL_HEVC,
4239 MUX_ENABLE_HEVC,
4240 DIV_HEVC,
4241 ENABLE_ACLK_HEVC,
4242 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4243 ENABLE_PCLK_HEVC,
4244 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4245 ENABLE_IP_HEVC0,
4246 ENABLE_IP_HEVC1,
4247 ENABLE_IP_HEVC_SECURE_SMMU_HEVC,
4248 };
4249
4250 static const struct samsung_clk_reg_dump hevc_suspend_regs[] = {
4251 { MUX_SEL_HEVC, 0 },
4252 };
4253
4254 PNAME(mout_aclk_hevc_400_user_p) = { "oscclk", "aclk_hevc_400", };
4255
4256 static const struct samsung_mux_clock hevc_mux_clks[] __initconst = {
4257 /* MUX_SEL_HEVC */
4258 MUX(CLK_MOUT_ACLK_HEVC_400_USER, "mout_aclk_hevc_400_user",
4259 mout_aclk_hevc_400_user_p, MUX_SEL_HEVC, 0, 0),
4260 };
4261
4262 static const struct samsung_div_clock hevc_div_clks[] __initconst = {
4263 /* DIV_HEVC */
4264 DIV(CLK_DIV_PCLK_HEVC, "div_pclk_hevc", "mout_aclk_hevc_400_user",
4265 DIV_HEVC, 0, 2),
4266 };
4267
4268 static const struct samsung_gate_clock hevc_gate_clks[] __initconst = {
4269 /* ENABLE_ACLK_HEVC */
4270 GATE(CLK_ACLK_BTS_HEVC_1, "aclk_bts_hevc_1", "mout_aclk_hevc_400_user",
4271 ENABLE_ACLK_HEVC, 6, 0, 0),
4272 GATE(CLK_ACLK_BTS_HEVC_0, "aclk_bts_hevc_0", "mout_aclk_hevc_400_user",
4273 ENABLE_ACLK_HEVC, 5, 0, 0),
4274 GATE(CLK_ACLK_AHB2APB_HEVCP, "aclk_ahb2apb_hevcp", "div_pclk_hevc",
4275 ENABLE_ACLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4276 GATE(CLK_ACLK_XIU_HEVCX, "aclk_xiu_hevcx", "mout_aclk_hevc_400_user",
4277 ENABLE_ACLK_HEVC, 3, CLK_IGNORE_UNUSED, 0),
4278 GATE(CLK_ACLK_HEVCNP_100, "aclk_hevcnp_100", "div_pclk_hevc",
4279 ENABLE_ACLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4280 GATE(CLK_ACLK_HEVCND_400, "aclk_hevcnd_400", "mout_aclk_hevc_400_user",
4281 ENABLE_ACLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4282 GATE(CLK_ACLK_HEVC, "aclk_hevc", "mout_aclk_hevc_400_user",
4283 ENABLE_ACLK_HEVC, 0, 0, 0),
4284
4285 /* ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC */
4286 GATE(CLK_ACLK_SMMU_HEVC_1, "aclk_smmu_hevc_1",
4287 "mout_aclk_hevc_400_user",
4288 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4289 1, CLK_IGNORE_UNUSED, 0),
4290 GATE(CLK_ACLK_SMMU_HEVC_0, "aclk_smmu_hevc_0",
4291 "mout_aclk_hevc_400_user",
4292 ENABLE_ACLK_HEVC_SECURE_SMMU_HEVC,
4293 0, CLK_IGNORE_UNUSED, 0),
4294
4295 /* ENABLE_PCLK_HEVC */
4296 GATE(CLK_PCLK_BTS_HEVC_1, "pclk_bts_hevc_1", "div_pclk_hevc",
4297 ENABLE_PCLK_HEVC, 4, 0, 0),
4298 GATE(CLK_PCLK_BTS_HEVC_0, "pclk_bts_hevc_0", "div_pclk_hevc",
4299 ENABLE_PCLK_HEVC, 3, 0, 0),
4300 GATE(CLK_PCLK_PMU_HEVC, "pclk_pmu_hevc", "div_pclk_hevc",
4301 ENABLE_PCLK_HEVC, 2, CLK_IGNORE_UNUSED, 0),
4302 GATE(CLK_PCLK_SYSREG_HEVC, "pclk_sysreg_hevc", "div_pclk_hevc",
4303 ENABLE_PCLK_HEVC, 1, CLK_IGNORE_UNUSED, 0),
4304 GATE(CLK_PCLK_HEVC, "pclk_hevc", "div_pclk_hevc",
4305 ENABLE_PCLK_HEVC, 4, CLK_IGNORE_UNUSED, 0),
4306
4307 /* ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC */
4308 GATE(CLK_PCLK_SMMU_HEVC_1, "pclk_smmu_hevc_1", "div_pclk_hevc",
4309 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4310 1, CLK_IGNORE_UNUSED, 0),
4311 GATE(CLK_PCLK_SMMU_HEVC_0, "pclk_smmu_hevc_0", "div_pclk_hevc",
4312 ENABLE_PCLK_HEVC_SECURE_SMMU_HEVC,
4313 0, CLK_IGNORE_UNUSED, 0),
4314 };
4315
4316 static const struct samsung_cmu_info hevc_cmu_info __initconst = {
4317 .mux_clks = hevc_mux_clks,
4318 .nr_mux_clks = ARRAY_SIZE(hevc_mux_clks),
4319 .div_clks = hevc_div_clks,
4320 .nr_div_clks = ARRAY_SIZE(hevc_div_clks),
4321 .gate_clks = hevc_gate_clks,
4322 .nr_gate_clks = ARRAY_SIZE(hevc_gate_clks),
4323 .nr_clk_ids = HEVC_NR_CLK,
4324 .clk_regs = hevc_clk_regs,
4325 .nr_clk_regs = ARRAY_SIZE(hevc_clk_regs),
4326 .suspend_regs = hevc_suspend_regs,
4327 .nr_suspend_regs = ARRAY_SIZE(hevc_suspend_regs),
4328 .clk_name = "aclk_hevc_400",
4329 };
4330
4331 /*
4332 * Register offset definitions for CMU_ISP
4333 */
4334 #define MUX_SEL_ISP 0x0200
4335 #define MUX_ENABLE_ISP 0x0300
4336 #define MUX_STAT_ISP 0x0400
4337 #define DIV_ISP 0x0600
4338 #define DIV_STAT_ISP 0x0700
4339 #define ENABLE_ACLK_ISP0 0x0800
4340 #define ENABLE_ACLK_ISP1 0x0804
4341 #define ENABLE_ACLK_ISP2 0x0808
4342 #define ENABLE_PCLK_ISP 0x0900
4343 #define ENABLE_SCLK_ISP 0x0a00
4344 #define ENABLE_IP_ISP0 0x0b00
4345 #define ENABLE_IP_ISP1 0x0b04
4346 #define ENABLE_IP_ISP2 0x0b08
4347 #define ENABLE_IP_ISP3 0x0b0c
4348
4349 static const unsigned long isp_clk_regs[] __initconst = {
4350 MUX_SEL_ISP,
4351 MUX_ENABLE_ISP,
4352 DIV_ISP,
4353 ENABLE_ACLK_ISP0,
4354 ENABLE_ACLK_ISP1,
4355 ENABLE_ACLK_ISP2,
4356 ENABLE_PCLK_ISP,
4357 ENABLE_SCLK_ISP,
4358 ENABLE_IP_ISP0,
4359 ENABLE_IP_ISP1,
4360 ENABLE_IP_ISP2,
4361 ENABLE_IP_ISP3,
4362 };
4363
4364 static const struct samsung_clk_reg_dump isp_suspend_regs[] = {
4365 { MUX_SEL_ISP, 0 },
4366 };
4367
4368 PNAME(mout_aclk_isp_dis_400_user_p) = { "oscclk", "aclk_isp_dis_400", };
4369 PNAME(mout_aclk_isp_400_user_p) = { "oscclk", "aclk_isp_400", };
4370
4371 static const struct samsung_mux_clock isp_mux_clks[] __initconst = {
4372 /* MUX_SEL_ISP */
4373 MUX(CLK_MOUT_ACLK_ISP_DIS_400_USER, "mout_aclk_isp_dis_400_user",
4374 mout_aclk_isp_dis_400_user_p, MUX_SEL_ISP, 4, 0),
4375 MUX(CLK_MOUT_ACLK_ISP_400_USER, "mout_aclk_isp_400_user",
4376 mout_aclk_isp_400_user_p, MUX_SEL_ISP, 0, 0),
4377 };
4378
4379 static const struct samsung_div_clock isp_div_clks[] __initconst = {
4380 /* DIV_ISP */
4381 DIV(CLK_DIV_PCLK_ISP_DIS, "div_pclk_isp_dis",
4382 "mout_aclk_isp_dis_400_user", DIV_ISP, 12, 3),
4383 DIV(CLK_DIV_PCLK_ISP, "div_pclk_isp", "mout_aclk_isp_400_user",
4384 DIV_ISP, 8, 3),
4385 DIV(CLK_DIV_ACLK_ISP_D_200, "div_aclk_isp_d_200",
4386 "mout_aclk_isp_400_user", DIV_ISP, 4, 3),
4387 DIV(CLK_DIV_ACLK_ISP_C_200, "div_aclk_isp_c_200",
4388 "mout_aclk_isp_400_user", DIV_ISP, 0, 3),
4389 };
4390
4391 static const struct samsung_gate_clock isp_gate_clks[] __initconst = {
4392 /* ENABLE_ACLK_ISP0 */
4393 GATE(CLK_ACLK_ISP_D_GLUE, "aclk_isp_d_glue", "mout_aclk_isp_400_user",
4394 ENABLE_ACLK_ISP0, 6, CLK_IGNORE_UNUSED, 0),
4395 GATE(CLK_ACLK_SCALERP, "aclk_scalerp", "mout_aclk_isp_400_user",
4396 ENABLE_ACLK_ISP0, 5, 0, 0),
4397 GATE(CLK_ACLK_3DNR, "aclk_3dnr", "mout_aclk_isp_400_user",
4398 ENABLE_ACLK_ISP0, 4, 0, 0),
4399 GATE(CLK_ACLK_DIS, "aclk_dis", "mout_aclk_isp_dis_400_user",
4400 ENABLE_ACLK_ISP0, 3, 0, 0),
4401 GATE(CLK_ACLK_SCALERC, "aclk_scalerc", "mout_aclk_isp_400_user",
4402 ENABLE_ACLK_ISP0, 2, 0, 0),
4403 GATE(CLK_ACLK_DRC, "aclk_drc", "mout_aclk_isp_400_user",
4404 ENABLE_ACLK_ISP0, 1, 0, 0),
4405 GATE(CLK_ACLK_ISP, "aclk_isp", "mout_aclk_isp_400_user",
4406 ENABLE_ACLK_ISP0, 0, 0, 0),
4407
4408 /* ENABLE_ACLK_ISP1 */
4409 GATE(CLK_ACLK_AXIUS_SCALERP, "aclk_axius_scalerp",
4410 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4411 17, CLK_IGNORE_UNUSED, 0),
4412 GATE(CLK_ACLK_AXIUS_SCALERC, "aclk_axius_scalerc",
4413 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4414 16, CLK_IGNORE_UNUSED, 0),
4415 GATE(CLK_ACLK_AXIUS_DRC, "aclk_axius_drc",
4416 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4417 15, CLK_IGNORE_UNUSED, 0),
4418 GATE(CLK_ACLK_ASYNCAHBM_ISP2P, "aclk_asyncahbm_isp2p",
4419 "div_pclk_isp", ENABLE_ACLK_ISP1,
4420 14, CLK_IGNORE_UNUSED, 0),
4421 GATE(CLK_ACLK_ASYNCAHBM_ISP1P, "aclk_asyncahbm_isp1p",
4422 "div_pclk_isp", ENABLE_ACLK_ISP1,
4423 13, CLK_IGNORE_UNUSED, 0),
4424 GATE(CLK_ACLK_ASYNCAXIS_DIS1, "aclk_asyncaxis_dis1",
4425 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4426 12, CLK_IGNORE_UNUSED, 0),
4427 GATE(CLK_ACLK_ASYNCAXIS_DIS0, "aclk_asyncaxis_dis0",
4428 "mout_aclk_isp_dis_400_user", ENABLE_ACLK_ISP1,
4429 11, CLK_IGNORE_UNUSED, 0),
4430 GATE(CLK_ACLK_ASYNCAXIM_DIS1, "aclk_asyncaxim_dis1",
4431 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4432 10, CLK_IGNORE_UNUSED, 0),
4433 GATE(CLK_ACLK_ASYNCAXIM_DIS0, "aclk_asyncaxim_dis0",
4434 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP1,
4435 9, CLK_IGNORE_UNUSED, 0),
4436 GATE(CLK_ACLK_ASYNCAXIM_ISP2P, "aclk_asyncaxim_isp2p",
4437 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4438 8, CLK_IGNORE_UNUSED, 0),
4439 GATE(CLK_ACLK_ASYNCAXIM_ISP1P, "aclk_asyncaxim_isp1p",
4440 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4441 7, CLK_IGNORE_UNUSED, 0),
4442 GATE(CLK_ACLK_AHB2APB_ISP2P, "aclk_ahb2apb_isp2p", "div_pclk_isp",
4443 ENABLE_ACLK_ISP1, 6, CLK_IGNORE_UNUSED, 0),
4444 GATE(CLK_ACLK_AHB2APB_ISP1P, "aclk_ahb2apb_isp1p", "div_pclk_isp",
4445 ENABLE_ACLK_ISP1, 5, CLK_IGNORE_UNUSED, 0),
4446 GATE(CLK_ACLK_AXI2APB_ISP2P, "aclk_axi2apb_isp2p",
4447 "div_aclk_isp_d_200", ENABLE_ACLK_ISP1,
4448 4, CLK_IGNORE_UNUSED, 0),
4449 GATE(CLK_ACLK_AXI2APB_ISP1P, "aclk_axi2apb_isp1p",
4450 "div_aclk_isp_c_200", ENABLE_ACLK_ISP1,
4451 3, CLK_IGNORE_UNUSED, 0),
4452 GATE(CLK_ACLK_XIU_ISPEX1, "aclk_xiu_ispex1", "mout_aclk_isp_400_user",
4453 ENABLE_ACLK_ISP1, 2, CLK_IGNORE_UNUSED, 0),
4454 GATE(CLK_ACLK_XIU_ISPEX0, "aclk_xiu_ispex0", "mout_aclk_isp_400_user",
4455 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4456 GATE(CLK_ACLK_ISPND_400, "aclk_ispnd_400", "mout_aclk_isp_400_user",
4457 ENABLE_ACLK_ISP1, 1, CLK_IGNORE_UNUSED, 0),
4458
4459 /* ENABLE_ACLK_ISP2 */
4460 GATE(CLK_ACLK_SMMU_SCALERP, "aclk_smmu_scalerp",
4461 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4462 13, CLK_IGNORE_UNUSED, 0),
4463 GATE(CLK_ACLK_SMMU_3DNR, "aclk_smmu_3dnr", "mout_aclk_isp_400_user",
4464 ENABLE_ACLK_ISP2, 12, CLK_IGNORE_UNUSED, 0),
4465 GATE(CLK_ACLK_SMMU_DIS1, "aclk_smmu_dis1", "mout_aclk_isp_400_user",
4466 ENABLE_ACLK_ISP2, 11, CLK_IGNORE_UNUSED, 0),
4467 GATE(CLK_ACLK_SMMU_DIS0, "aclk_smmu_dis0", "mout_aclk_isp_400_user",
4468 ENABLE_ACLK_ISP2, 10, CLK_IGNORE_UNUSED, 0),
4469 GATE(CLK_ACLK_SMMU_SCALERC, "aclk_smmu_scalerc",
4470 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4471 9, CLK_IGNORE_UNUSED, 0),
4472 GATE(CLK_ACLK_SMMU_DRC, "aclk_smmu_drc", "mout_aclk_isp_400_user",
4473 ENABLE_ACLK_ISP2, 8, CLK_IGNORE_UNUSED, 0),
4474 GATE(CLK_ACLK_SMMU_ISP, "aclk_smmu_isp", "mout_aclk_isp_400_user",
4475 ENABLE_ACLK_ISP2, 7, CLK_IGNORE_UNUSED, 0),
4476 GATE(CLK_ACLK_BTS_SCALERP, "aclk_bts_scalerp",
4477 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4478 6, CLK_IGNORE_UNUSED, 0),
4479 GATE(CLK_ACLK_BTS_3DR, "aclk_bts_3dnr", "mout_aclk_isp_400_user",
4480 ENABLE_ACLK_ISP2, 5, CLK_IGNORE_UNUSED, 0),
4481 GATE(CLK_ACLK_BTS_DIS1, "aclk_bts_dis1", "mout_aclk_isp_400_user",
4482 ENABLE_ACLK_ISP2, 4, CLK_IGNORE_UNUSED, 0),
4483 GATE(CLK_ACLK_BTS_DIS0, "aclk_bts_dis0", "mout_aclk_isp_400_user",
4484 ENABLE_ACLK_ISP2, 3, CLK_IGNORE_UNUSED, 0),
4485 GATE(CLK_ACLK_BTS_SCALERC, "aclk_bts_scalerc",
4486 "mout_aclk_isp_400_user", ENABLE_ACLK_ISP2,
4487 2, CLK_IGNORE_UNUSED, 0),
4488 GATE(CLK_ACLK_BTS_DRC, "aclk_bts_drc", "mout_aclk_isp_400_user",
4489 ENABLE_ACLK_ISP2, 1, CLK_IGNORE_UNUSED, 0),
4490 GATE(CLK_ACLK_BTS_ISP, "aclk_bts_isp", "mout_aclk_isp_400_user",
4491 ENABLE_ACLK_ISP2, 0, CLK_IGNORE_UNUSED, 0),
4492
4493 /* ENABLE_PCLK_ISP */
4494 GATE(CLK_PCLK_SMMU_SCALERP, "pclk_smmu_scalerp", "div_aclk_isp_d_200",
4495 ENABLE_PCLK_ISP, 25, CLK_IGNORE_UNUSED, 0),
4496 GATE(CLK_PCLK_SMMU_3DNR, "pclk_smmu_3dnr", "div_aclk_isp_d_200",
4497 ENABLE_PCLK_ISP, 24, CLK_IGNORE_UNUSED, 0),
4498 GATE(CLK_PCLK_SMMU_DIS1, "pclk_smmu_dis1", "div_aclk_isp_d_200",
4499 ENABLE_PCLK_ISP, 23, CLK_IGNORE_UNUSED, 0),
4500 GATE(CLK_PCLK_SMMU_DIS0, "pclk_smmu_dis0", "div_aclk_isp_d_200",
4501 ENABLE_PCLK_ISP, 22, CLK_IGNORE_UNUSED, 0),
4502 GATE(CLK_PCLK_SMMU_SCALERC, "pclk_smmu_scalerc", "div_aclk_isp_c_200",
4503 ENABLE_PCLK_ISP, 21, CLK_IGNORE_UNUSED, 0),
4504 GATE(CLK_PCLK_SMMU_DRC, "pclk_smmu_drc", "div_aclk_isp_c_200",
4505 ENABLE_PCLK_ISP, 20, CLK_IGNORE_UNUSED, 0),
4506 GATE(CLK_PCLK_SMMU_ISP, "pclk_smmu_isp", "div_aclk_isp_c_200",
4507 ENABLE_PCLK_ISP, 19, CLK_IGNORE_UNUSED, 0),
4508 GATE(CLK_PCLK_BTS_SCALERP, "pclk_bts_scalerp", "div_pclk_isp",
4509 ENABLE_PCLK_ISP, 18, CLK_IGNORE_UNUSED, 0),
4510 GATE(CLK_PCLK_BTS_3DNR, "pclk_bts_3dnr", "div_pclk_isp",
4511 ENABLE_PCLK_ISP, 17, CLK_IGNORE_UNUSED, 0),
4512 GATE(CLK_PCLK_BTS_DIS1, "pclk_bts_dis1", "div_pclk_isp",
4513 ENABLE_PCLK_ISP, 16, CLK_IGNORE_UNUSED, 0),
4514 GATE(CLK_PCLK_BTS_DIS0, "pclk_bts_dis0", "div_pclk_isp",
4515 ENABLE_PCLK_ISP, 15, CLK_IGNORE_UNUSED, 0),
4516 GATE(CLK_PCLK_BTS_SCALERC, "pclk_bts_scalerc", "div_pclk_isp",
4517 ENABLE_PCLK_ISP, 14, CLK_IGNORE_UNUSED, 0),
4518 GATE(CLK_PCLK_BTS_DRC, "pclk_bts_drc", "div_pclk_isp",
4519 ENABLE_PCLK_ISP, 13, CLK_IGNORE_UNUSED, 0),
4520 GATE(CLK_PCLK_BTS_ISP, "pclk_bts_isp", "div_pclk_isp",
4521 ENABLE_PCLK_ISP, 12, CLK_IGNORE_UNUSED, 0),
4522 GATE(CLK_PCLK_ASYNCAXI_DIS1, "pclk_asyncaxi_dis1", "div_pclk_isp",
4523 ENABLE_PCLK_ISP, 11, CLK_IGNORE_UNUSED, 0),
4524 GATE(CLK_PCLK_ASYNCAXI_DIS0, "pclk_asyncaxi_dis0", "div_pclk_isp",
4525 ENABLE_PCLK_ISP, 10, CLK_IGNORE_UNUSED, 0),
4526 GATE(CLK_PCLK_PMU_ISP, "pclk_pmu_isp", "div_pclk_isp",
4527 ENABLE_PCLK_ISP, 9, CLK_IGNORE_UNUSED, 0),
4528 GATE(CLK_PCLK_SYSREG_ISP, "pclk_sysreg_isp", "div_pclk_isp",
4529 ENABLE_PCLK_ISP, 8, CLK_IGNORE_UNUSED, 0),
4530 GATE(CLK_PCLK_CMU_ISP_LOCAL, "pclk_cmu_isp_local",
4531 "div_aclk_isp_c_200", ENABLE_PCLK_ISP,
4532 7, CLK_IGNORE_UNUSED, 0),
4533 GATE(CLK_PCLK_SCALERP, "pclk_scalerp", "div_aclk_isp_d_200",
4534 ENABLE_PCLK_ISP, 6, CLK_IGNORE_UNUSED, 0),
4535 GATE(CLK_PCLK_3DNR, "pclk_3dnr", "div_aclk_isp_d_200",
4536 ENABLE_PCLK_ISP, 5, CLK_IGNORE_UNUSED, 0),
4537 GATE(CLK_PCLK_DIS_CORE, "pclk_dis_core", "div_pclk_isp_dis",
4538 ENABLE_PCLK_ISP, 4, CLK_IGNORE_UNUSED, 0),
4539 GATE(CLK_PCLK_DIS, "pclk_dis", "div_aclk_isp_d_200",
4540 ENABLE_PCLK_ISP, 3, CLK_IGNORE_UNUSED, 0),
4541 GATE(CLK_PCLK_SCALERC, "pclk_scalerc", "div_aclk_isp_c_200",
4542 ENABLE_PCLK_ISP, 2, CLK_IGNORE_UNUSED, 0),
4543 GATE(CLK_PCLK_DRC, "pclk_drc", "div_aclk_isp_c_200",
4544 ENABLE_PCLK_ISP, 1, CLK_IGNORE_UNUSED, 0),
4545 GATE(CLK_PCLK_ISP, "pclk_isp", "div_aclk_isp_c_200",
4546 ENABLE_PCLK_ISP, 0, CLK_IGNORE_UNUSED, 0),
4547
4548 /* ENABLE_SCLK_ISP */
4549 GATE(CLK_SCLK_PIXELASYNCS_DIS, "sclk_pixelasyncs_dis",
4550 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4551 5, CLK_IGNORE_UNUSED, 0),
4552 GATE(CLK_SCLK_PIXELASYNCM_DIS, "sclk_pixelasyncm_dis",
4553 "mout_aclk_isp_dis_400_user", ENABLE_SCLK_ISP,
4554 4, CLK_IGNORE_UNUSED, 0),
4555 GATE(CLK_SCLK_PIXELASYNCS_SCALERP, "sclk_pixelasyncs_scalerp",
4556 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4557 3, CLK_IGNORE_UNUSED, 0),
4558 GATE(CLK_SCLK_PIXELASYNCM_ISPD, "sclk_pixelasyncm_ispd",
4559 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4560 2, CLK_IGNORE_UNUSED, 0),
4561 GATE(CLK_SCLK_PIXELASYNCS_ISPC, "sclk_pixelasyncs_ispc",
4562 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4563 1, CLK_IGNORE_UNUSED, 0),
4564 GATE(CLK_SCLK_PIXELASYNCM_ISPC, "sclk_pixelasyncm_ispc",
4565 "mout_aclk_isp_400_user", ENABLE_SCLK_ISP,
4566 0, CLK_IGNORE_UNUSED, 0),
4567 };
4568
4569 static const struct samsung_cmu_info isp_cmu_info __initconst = {
4570 .mux_clks = isp_mux_clks,
4571 .nr_mux_clks = ARRAY_SIZE(isp_mux_clks),
4572 .div_clks = isp_div_clks,
4573 .nr_div_clks = ARRAY_SIZE(isp_div_clks),
4574 .gate_clks = isp_gate_clks,
4575 .nr_gate_clks = ARRAY_SIZE(isp_gate_clks),
4576 .nr_clk_ids = ISP_NR_CLK,
4577 .clk_regs = isp_clk_regs,
4578 .nr_clk_regs = ARRAY_SIZE(isp_clk_regs),
4579 .suspend_regs = isp_suspend_regs,
4580 .nr_suspend_regs = ARRAY_SIZE(isp_suspend_regs),
4581 .clk_name = "aclk_isp_400",
4582 };
4583
4584 /*
4585 * Register offset definitions for CMU_CAM0
4586 */
4587 #define MUX_SEL_CAM00 0x0200
4588 #define MUX_SEL_CAM01 0x0204
4589 #define MUX_SEL_CAM02 0x0208
4590 #define MUX_SEL_CAM03 0x020c
4591 #define MUX_SEL_CAM04 0x0210
4592 #define MUX_ENABLE_CAM00 0x0300
4593 #define MUX_ENABLE_CAM01 0x0304
4594 #define MUX_ENABLE_CAM02 0x0308
4595 #define MUX_ENABLE_CAM03 0x030c
4596 #define MUX_ENABLE_CAM04 0x0310
4597 #define MUX_STAT_CAM00 0x0400
4598 #define MUX_STAT_CAM01 0x0404
4599 #define MUX_STAT_CAM02 0x0408
4600 #define MUX_STAT_CAM03 0x040c
4601 #define MUX_STAT_CAM04 0x0410
4602 #define MUX_IGNORE_CAM01 0x0504
4603 #define DIV_CAM00 0x0600
4604 #define DIV_CAM01 0x0604
4605 #define DIV_CAM02 0x0608
4606 #define DIV_CAM03 0x060c
4607 #define DIV_STAT_CAM00 0x0700
4608 #define DIV_STAT_CAM01 0x0704
4609 #define DIV_STAT_CAM02 0x0708
4610 #define DIV_STAT_CAM03 0x070c
4611 #define ENABLE_ACLK_CAM00 0X0800
4612 #define ENABLE_ACLK_CAM01 0X0804
4613 #define ENABLE_ACLK_CAM02 0X0808
4614 #define ENABLE_PCLK_CAM0 0X0900
4615 #define ENABLE_SCLK_CAM0 0X0a00
4616 #define ENABLE_IP_CAM00 0X0b00
4617 #define ENABLE_IP_CAM01 0X0b04
4618 #define ENABLE_IP_CAM02 0X0b08
4619 #define ENABLE_IP_CAM03 0X0b0C
4620
4621 static const unsigned long cam0_clk_regs[] __initconst = {
4622 MUX_SEL_CAM00,
4623 MUX_SEL_CAM01,
4624 MUX_SEL_CAM02,
4625 MUX_SEL_CAM03,
4626 MUX_SEL_CAM04,
4627 MUX_ENABLE_CAM00,
4628 MUX_ENABLE_CAM01,
4629 MUX_ENABLE_CAM02,
4630 MUX_ENABLE_CAM03,
4631 MUX_ENABLE_CAM04,
4632 MUX_IGNORE_CAM01,
4633 DIV_CAM00,
4634 DIV_CAM01,
4635 DIV_CAM02,
4636 DIV_CAM03,
4637 ENABLE_ACLK_CAM00,
4638 ENABLE_ACLK_CAM01,
4639 ENABLE_ACLK_CAM02,
4640 ENABLE_PCLK_CAM0,
4641 ENABLE_SCLK_CAM0,
4642 ENABLE_IP_CAM00,
4643 ENABLE_IP_CAM01,
4644 ENABLE_IP_CAM02,
4645 ENABLE_IP_CAM03,
4646 };
4647
4648 static const struct samsung_clk_reg_dump cam0_suspend_regs[] = {
4649 { MUX_SEL_CAM00, 0 },
4650 { MUX_SEL_CAM01, 0 },
4651 { MUX_SEL_CAM02, 0 },
4652 { MUX_SEL_CAM03, 0 },
4653 { MUX_SEL_CAM04, 0 },
4654 };
4655
4656 PNAME(mout_aclk_cam0_333_user_p) = { "oscclk", "aclk_cam0_333", };
4657 PNAME(mout_aclk_cam0_400_user_p) = { "oscclk", "aclk_cam0_400", };
4658 PNAME(mout_aclk_cam0_552_user_p) = { "oscclk", "aclk_cam0_552", };
4659
4660 PNAME(mout_phyclk_rxbyteclkhs0_s4_user_p) = { "oscclk",
4661 "phyclk_rxbyteclkhs0_s4_phy", };
4662 PNAME(mout_phyclk_rxbyteclkhs0_s2a_user_p) = { "oscclk",
4663 "phyclk_rxbyteclkhs0_s2a_phy", };
4664
4665 PNAME(mout_aclk_lite_d_b_p) = { "mout_aclk_lite_d_a",
4666 "mout_aclk_cam0_333_user", };
4667 PNAME(mout_aclk_lite_d_a_p) = { "mout_aclk_cam0_552_user",
4668 "mout_aclk_cam0_400_user", };
4669 PNAME(mout_aclk_lite_b_b_p) = { "mout_aclk_lite_b_a",
4670 "mout_aclk_cam0_333_user", };
4671 PNAME(mout_aclk_lite_b_a_p) = { "mout_aclk_cam0_552_user",
4672 "mout_aclk_cam0_400_user", };
4673 PNAME(mout_aclk_lite_a_b_p) = { "mout_aclk_lite_a_a",
4674 "mout_aclk_cam0_333_user", };
4675 PNAME(mout_aclk_lite_a_a_p) = { "mout_aclk_cam0_552_user",
4676 "mout_aclk_cam0_400_user", };
4677 PNAME(mout_aclk_cam0_400_p) = { "mout_aclk_cam0_400_user",
4678 "mout_aclk_cam0_333_user", };
4679
4680 PNAME(mout_aclk_csis1_b_p) = { "mout_aclk_csis1_a",
4681 "mout_aclk_cam0_333_user" };
4682 PNAME(mout_aclk_csis1_a_p) = { "mout_aclk_cam0_552_user",
4683 "mout_aclk_cam0_400_user", };
4684 PNAME(mout_aclk_csis0_b_p) = { "mout_aclk_csis0_a",
4685 "mout_aclk_cam0_333_user", };
4686 PNAME(mout_aclk_csis0_a_p) = { "mout_aclk_cam0_552_user",
4687 "mout_aclk-cam0_400_user", };
4688 PNAME(mout_aclk_3aa1_b_p) = { "mout_aclk_3aa1_a",
4689 "mout_aclk_cam0_333_user", };
4690 PNAME(mout_aclk_3aa1_a_p) = { "mout_aclk_cam0_552_user",
4691 "mout_aclk_cam0_400_user", };
4692 PNAME(mout_aclk_3aa0_b_p) = { "mout_aclk_3aa0_a",
4693 "mout_aclk_cam0_333_user", };
4694 PNAME(mout_aclk_3aa0_a_p) = { "mout_aclk_cam0_552_user",
4695 "mout_aclk_cam0_400_user", };
4696
4697 PNAME(mout_sclk_lite_freecnt_c_p) = { "mout_sclk_lite_freecnt_b",
4698 "div_pclk_lite_d", };
4699 PNAME(mout_sclk_lite_freecnt_b_p) = { "mout_sclk_lite_freecnt_a",
4700 "div_pclk_pixelasync_lite_c", };
4701 PNAME(mout_sclk_lite_freecnt_a_p) = { "div_pclk_lite_a",
4702 "div_pclk_lite_b", };
4703 PNAME(mout_sclk_pixelasync_lite_c_b_p) = { "mout_sclk_pixelasync_lite_c_a",
4704 "mout_aclk_cam0_333_user", };
4705 PNAME(mout_sclk_pixelasync_lite_c_a_p) = { "mout_aclk_cam0_552_user",
4706 "mout_aclk_cam0_400_user", };
4707 PNAME(mout_sclk_pixelasync_lite_c_init_b_p) = {
4708 "mout_sclk_pixelasync_lite_c_init_a",
4709 "mout_aclk_cam0_400_user", };
4710 PNAME(mout_sclk_pixelasync_lite_c_init_a_p) = {
4711 "mout_aclk_cam0_552_user",
4712 "mout_aclk_cam0_400_user", };
4713
4714 static const struct samsung_fixed_rate_clock cam0_fixed_clks[] __initconst = {
4715 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S4_PHY, "phyclk_rxbyteclkhs0_s4_phy",
4716 NULL, 0, 100000000),
4717 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2A_PHY, "phyclk_rxbyteclkhs0_s2a_phy",
4718 NULL, 0, 100000000),
4719 };
4720
4721 static const struct samsung_mux_clock cam0_mux_clks[] __initconst = {
4722 /* MUX_SEL_CAM00 */
4723 MUX(CLK_MOUT_ACLK_CAM0_333_USER, "mout_aclk_cam0_333_user",
4724 mout_aclk_cam0_333_user_p, MUX_SEL_CAM00, 8, 1),
4725 MUX(CLK_MOUT_ACLK_CAM0_400_USER, "mout_aclk_cam0_400_user",
4726 mout_aclk_cam0_400_user_p, MUX_SEL_CAM00, 4, 1),
4727 MUX(CLK_MOUT_ACLK_CAM0_552_USER, "mout_aclk_cam0_552_user",
4728 mout_aclk_cam0_552_user_p, MUX_SEL_CAM00, 0, 1),
4729
4730 /* MUX_SEL_CAM01 */
4731 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S4_USER,
4732 "mout_phyclk_rxbyteclkhs0_s4_user",
4733 mout_phyclk_rxbyteclkhs0_s4_user_p,
4734 MUX_SEL_CAM01, 4, 1),
4735 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2A_USER,
4736 "mout_phyclk_rxbyteclkhs0_s2a_user",
4737 mout_phyclk_rxbyteclkhs0_s2a_user_p,
4738 MUX_SEL_CAM01, 0, 1),
4739
4740 /* MUX_SEL_CAM02 */
4741 MUX(CLK_MOUT_ACLK_LITE_D_B, "mout_aclk_lite_d_b", mout_aclk_lite_d_b_p,
4742 MUX_SEL_CAM02, 24, 1),
4743 MUX(CLK_MOUT_ACLK_LITE_D_A, "mout_aclk_lite_d_a", mout_aclk_lite_d_a_p,
4744 MUX_SEL_CAM02, 20, 1),
4745 MUX(CLK_MOUT_ACLK_LITE_B_B, "mout_aclk_lite_b_b", mout_aclk_lite_b_b_p,
4746 MUX_SEL_CAM02, 16, 1),
4747 MUX(CLK_MOUT_ACLK_LITE_B_A, "mout_aclk_lite_b_a", mout_aclk_lite_b_a_p,
4748 MUX_SEL_CAM02, 12, 1),
4749 MUX(CLK_MOUT_ACLK_LITE_A_B, "mout_aclk_lite_a_b", mout_aclk_lite_a_b_p,
4750 MUX_SEL_CAM02, 8, 1),
4751 MUX(CLK_MOUT_ACLK_LITE_A_A, "mout_aclk_lite_a_a", mout_aclk_lite_a_a_p,
4752 MUX_SEL_CAM02, 4, 1),
4753 MUX(CLK_MOUT_ACLK_CAM0_400, "mout_aclk_cam0_400", mout_aclk_cam0_400_p,
4754 MUX_SEL_CAM02, 0, 1),
4755
4756 /* MUX_SEL_CAM03 */
4757 MUX(CLK_MOUT_ACLK_CSIS1_B, "mout_aclk_csis1_b", mout_aclk_csis1_b_p,
4758 MUX_SEL_CAM03, 28, 1),
4759 MUX(CLK_MOUT_ACLK_CSIS1_A, "mout_aclk_csis1_a", mout_aclk_csis1_a_p,
4760 MUX_SEL_CAM03, 24, 1),
4761 MUX(CLK_MOUT_ACLK_CSIS0_B, "mout_aclk_csis0_b", mout_aclk_csis0_b_p,
4762 MUX_SEL_CAM03, 20, 1),
4763 MUX(CLK_MOUT_ACLK_CSIS0_A, "mout_aclk_csis0_a", mout_aclk_csis0_a_p,
4764 MUX_SEL_CAM03, 16, 1),
4765 MUX(CLK_MOUT_ACLK_3AA1_B, "mout_aclk_3aa1_b", mout_aclk_3aa1_b_p,
4766 MUX_SEL_CAM03, 12, 1),
4767 MUX(CLK_MOUT_ACLK_3AA1_A, "mout_aclk_3aa1_a", mout_aclk_3aa1_a_p,
4768 MUX_SEL_CAM03, 8, 1),
4769 MUX(CLK_MOUT_ACLK_3AA0_B, "mout_aclk_3aa0_b", mout_aclk_3aa0_b_p,
4770 MUX_SEL_CAM03, 4, 1),
4771 MUX(CLK_MOUT_ACLK_3AA0_A, "mout_aclk_3aa0_a", mout_aclk_3aa0_a_p,
4772 MUX_SEL_CAM03, 0, 1),
4773
4774 /* MUX_SEL_CAM04 */
4775 MUX(CLK_MOUT_SCLK_LITE_FREECNT_C, "mout_sclk_lite_freecnt_c",
4776 mout_sclk_lite_freecnt_c_p, MUX_SEL_CAM04, 24, 1),
4777 MUX(CLK_MOUT_SCLK_LITE_FREECNT_B, "mout_sclk_lite_freecnt_b",
4778 mout_sclk_lite_freecnt_b_p, MUX_SEL_CAM04, 20, 1),
4779 MUX(CLK_MOUT_SCLK_LITE_FREECNT_A, "mout_sclk_lite_freecnt_a",
4780 mout_sclk_lite_freecnt_a_p, MUX_SEL_CAM04, 16, 1),
4781 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_B, "mout_sclk_pixelasync_lite_c_b",
4782 mout_sclk_pixelasync_lite_c_b_p, MUX_SEL_CAM04, 12, 1),
4783 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_A, "mout_sclk_pixelasync_lite_c_a",
4784 mout_sclk_pixelasync_lite_c_a_p, MUX_SEL_CAM04, 8, 1),
4785 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_B,
4786 "mout_sclk_pixelasync_lite_c_init_b",
4787 mout_sclk_pixelasync_lite_c_init_b_p,
4788 MUX_SEL_CAM04, 4, 1),
4789 MUX(CLK_MOUT_SCLK_PIXELASYNC_LITE_C_INIT_A,
4790 "mout_sclk_pixelasync_lite_c_init_a",
4791 mout_sclk_pixelasync_lite_c_init_a_p,
4792 MUX_SEL_CAM04, 0, 1),
4793 };
4794
4795 static const struct samsung_div_clock cam0_div_clks[] __initconst = {
4796 /* DIV_CAM00 */
4797 DIV(CLK_DIV_PCLK_CAM0_50, "div_pclk_cam0_50", "div_aclk_cam0_200",
4798 DIV_CAM00, 8, 2),
4799 DIV(CLK_DIV_ACLK_CAM0_200, "div_aclk_cam0_200", "mout_aclk_cam0_400",
4800 DIV_CAM00, 4, 3),
4801 DIV(CLK_DIV_ACLK_CAM0_BUS_400, "div_aclk_cam0_bus_400",
4802 "mout_aclk_cam0_400", DIV_CAM00, 0, 3),
4803
4804 /* DIV_CAM01 */
4805 DIV(CLK_DIV_PCLK_LITE_D, "div_pclk_lite_d", "div_aclk_lite_d",
4806 DIV_CAM01, 20, 2),
4807 DIV(CLK_DIV_ACLK_LITE_D, "div_aclk_lite_d", "mout_aclk_lite_d_b",
4808 DIV_CAM01, 16, 3),
4809 DIV(CLK_DIV_PCLK_LITE_B, "div_pclk_lite_b", "div_aclk_lite_b",
4810 DIV_CAM01, 12, 2),
4811 DIV(CLK_DIV_ACLK_LITE_B, "div_aclk_lite_b", "mout_aclk_lite_b_b",
4812 DIV_CAM01, 8, 3),
4813 DIV(CLK_DIV_PCLK_LITE_A, "div_pclk_lite_a", "div_aclk_lite_a",
4814 DIV_CAM01, 4, 2),
4815 DIV(CLK_DIV_ACLK_LITE_A, "div_aclk_lite_a", "mout_aclk_lite_a_b",
4816 DIV_CAM01, 0, 3),
4817
4818 /* DIV_CAM02 */
4819 DIV(CLK_DIV_ACLK_CSIS1, "div_aclk_csis1", "mout_aclk_csis1_b",
4820 DIV_CAM02, 20, 3),
4821 DIV(CLK_DIV_ACLK_CSIS0, "div_aclk_csis0", "mout_aclk_csis0_b",
4822 DIV_CAM02, 16, 3),
4823 DIV(CLK_DIV_PCLK_3AA1, "div_pclk_3aa1", "div_aclk_3aa1",
4824 DIV_CAM02, 12, 2),
4825 DIV(CLK_DIV_ACLK_3AA1, "div_aclk_3aa1", "mout_aclk_3aa1_b",
4826 DIV_CAM02, 8, 3),
4827 DIV(CLK_DIV_PCLK_3AA0, "div_pclk_3aa0", "div_aclk_3aa0",
4828 DIV_CAM02, 4, 2),
4829 DIV(CLK_DIV_ACLK_3AA0, "div_aclk_3aa0", "mout_aclk_3aa0_b",
4830 DIV_CAM02, 0, 3),
4831
4832 /* DIV_CAM03 */
4833 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C, "div_sclk_pixelasync_lite_c",
4834 "mout_sclk_pixelasync_lite_c_b", DIV_CAM03, 8, 3),
4835 DIV(CLK_DIV_PCLK_PIXELASYNC_LITE_C, "div_pclk_pixelasync_lite_c",
4836 "div_sclk_pixelasync_lite_c_init", DIV_CAM03, 4, 2),
4837 DIV(CLK_DIV_SCLK_PIXELASYNC_LITE_C_INIT,
4838 "div_sclk_pixelasync_lite_c_init",
4839 "mout_sclk_pixelasync_lite_c_init_b", DIV_CAM03, 0, 3),
4840 };
4841
4842 static const struct samsung_gate_clock cam0_gate_clks[] __initconst = {
4843 /* ENABLE_ACLK_CAM00 */
4844 GATE(CLK_ACLK_CSIS1, "aclk_csis1", "div_aclk_csis1", ENABLE_ACLK_CAM00,
4845 6, 0, 0),
4846 GATE(CLK_ACLK_CSIS0, "aclk_csis0", "div_aclk_csis0", ENABLE_ACLK_CAM00,
4847 5, 0, 0),
4848 GATE(CLK_ACLK_3AA1, "aclk_3aa1", "div_aclk_3aa1", ENABLE_ACLK_CAM00,
4849 4, 0, 0),
4850 GATE(CLK_ACLK_3AA0, "aclk_3aa0", "div_aclk_3aa0", ENABLE_ACLK_CAM00,
4851 3, 0, 0),
4852 GATE(CLK_ACLK_LITE_D, "aclk_lite_d", "div_aclk_lite_d",
4853 ENABLE_ACLK_CAM00, 2, 0, 0),
4854 GATE(CLK_ACLK_LITE_B, "aclk_lite_b", "div_aclk_lite_b",
4855 ENABLE_ACLK_CAM00, 1, 0, 0),
4856 GATE(CLK_ACLK_LITE_A, "aclk_lite_a", "div_aclk_lite_a",
4857 ENABLE_ACLK_CAM00, 0, 0, 0),
4858
4859 /* ENABLE_ACLK_CAM01 */
4860 GATE(CLK_ACLK_AHBSYNCDN, "aclk_ahbsyncdn", "div_aclk_cam0_200",
4861 ENABLE_ACLK_CAM01, 31, CLK_IGNORE_UNUSED, 0),
4862 GATE(CLK_ACLK_AXIUS_LITE_D, "aclk_axius_lite_d", "div_aclk_cam0_bus_400",
4863 ENABLE_ACLK_CAM01, 30, CLK_IGNORE_UNUSED, 0),
4864 GATE(CLK_ACLK_AXIUS_LITE_B, "aclk_axius_lite_b", "div_aclk_cam0_bus_400",
4865 ENABLE_ACLK_CAM01, 29, CLK_IGNORE_UNUSED, 0),
4866 GATE(CLK_ACLK_AXIUS_LITE_A, "aclk_axius_lite_a", "div_aclk_cam0_bus_400",
4867 ENABLE_ACLK_CAM01, 28, CLK_IGNORE_UNUSED, 0),
4868 GATE(CLK_ACLK_ASYNCAPBM_3AA1, "aclk_asyncapbm_3aa1", "div_pclk_3aa1",
4869 ENABLE_ACLK_CAM01, 27, CLK_IGNORE_UNUSED, 0),
4870 GATE(CLK_ACLK_ASYNCAPBS_3AA1, "aclk_asyncapbs_3aa1", "div_aclk_3aa1",
4871 ENABLE_ACLK_CAM01, 26, CLK_IGNORE_UNUSED, 0),
4872 GATE(CLK_ACLK_ASYNCAPBM_3AA0, "aclk_asyncapbm_3aa0", "div_pclk_3aa0",
4873 ENABLE_ACLK_CAM01, 25, CLK_IGNORE_UNUSED, 0),
4874 GATE(CLK_ACLK_ASYNCAPBS_3AA0, "aclk_asyncapbs_3aa0", "div_aclk_3aa0",
4875 ENABLE_ACLK_CAM01, 24, CLK_IGNORE_UNUSED, 0),
4876 GATE(CLK_ACLK_ASYNCAPBM_LITE_D, "aclk_asyncapbm_lite_d",
4877 "div_pclk_lite_d", ENABLE_ACLK_CAM01,
4878 23, CLK_IGNORE_UNUSED, 0),
4879 GATE(CLK_ACLK_ASYNCAPBS_LITE_D, "aclk_asyncapbs_lite_d",
4880 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4881 22, CLK_IGNORE_UNUSED, 0),
4882 GATE(CLK_ACLK_ASYNCAPBM_LITE_B, "aclk_asyncapbm_lite_b",
4883 "div_pclk_lite_b", ENABLE_ACLK_CAM01,
4884 21, CLK_IGNORE_UNUSED, 0),
4885 GATE(CLK_ACLK_ASYNCAPBS_LITE_B, "aclk_asyncapbs_lite_b",
4886 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4887 20, CLK_IGNORE_UNUSED, 0),
4888 GATE(CLK_ACLK_ASYNCAPBM_LITE_A, "aclk_asyncapbm_lite_a",
4889 "div_pclk_lite_a", ENABLE_ACLK_CAM01,
4890 19, CLK_IGNORE_UNUSED, 0),
4891 GATE(CLK_ACLK_ASYNCAPBS_LITE_A, "aclk_asyncapbs_lite_a",
4892 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4893 18, CLK_IGNORE_UNUSED, 0),
4894 GATE(CLK_ACLK_ASYNCAXIM_ISP0P, "aclk_asyncaxim_isp0p",
4895 "div_aclk_cam0_200", ENABLE_ACLK_CAM01,
4896 17, CLK_IGNORE_UNUSED, 0),
4897 GATE(CLK_ACLK_ASYNCAXIM_3AA1, "aclk_asyncaxim_3aa1",
4898 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4899 16, CLK_IGNORE_UNUSED, 0),
4900 GATE(CLK_ACLK_ASYNCAXIS_3AA1, "aclk_asyncaxis_3aa1",
4901 "div_aclk_3aa1", ENABLE_ACLK_CAM01,
4902 15, CLK_IGNORE_UNUSED, 0),
4903 GATE(CLK_ACLK_ASYNCAXIM_3AA0, "aclk_asyncaxim_3aa0",
4904 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4905 14, CLK_IGNORE_UNUSED, 0),
4906 GATE(CLK_ACLK_ASYNCAXIS_3AA0, "aclk_asyncaxis_3aa0",
4907 "div_aclk_3aa0", ENABLE_ACLK_CAM01,
4908 13, CLK_IGNORE_UNUSED, 0),
4909 GATE(CLK_ACLK_ASYNCAXIM_LITE_D, "aclk_asyncaxim_lite_d",
4910 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4911 12, CLK_IGNORE_UNUSED, 0),
4912 GATE(CLK_ACLK_ASYNCAXIS_LITE_D, "aclk_asyncaxis_lite_d",
4913 "div_aclk_lite_d", ENABLE_ACLK_CAM01,
4914 11, CLK_IGNORE_UNUSED, 0),
4915 GATE(CLK_ACLK_ASYNCAXIM_LITE_B, "aclk_asyncaxim_lite_b",
4916 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4917 10, CLK_IGNORE_UNUSED, 0),
4918 GATE(CLK_ACLK_ASYNCAXIS_LITE_B, "aclk_asyncaxis_lite_b",
4919 "div_aclk_lite_b", ENABLE_ACLK_CAM01,
4920 9, CLK_IGNORE_UNUSED, 0),
4921 GATE(CLK_ACLK_ASYNCAXIM_LITE_A, "aclk_asyncaxim_lite_a",
4922 "div_aclk_cam0_bus_400", ENABLE_ACLK_CAM01,
4923 8, CLK_IGNORE_UNUSED, 0),
4924 GATE(CLK_ACLK_ASYNCAXIS_LITE_A, "aclk_asyncaxis_lite_a",
4925 "div_aclk_lite_a", ENABLE_ACLK_CAM01,
4926 7, CLK_IGNORE_UNUSED, 0),
4927 GATE(CLK_ACLK_AHB2APB_ISPSFRP, "aclk_ahb2apb_ispsfrp",
4928 "div_pclk_cam0_50", ENABLE_ACLK_CAM01,
4929 6, CLK_IGNORE_UNUSED, 0),
4930 GATE(CLK_ACLK_AXI2APB_ISP0P, "aclk_axi2apb_isp0p", "div_aclk_cam0_200",
4931 ENABLE_ACLK_CAM01, 5, CLK_IGNORE_UNUSED, 0),
4932 GATE(CLK_ACLK_AXI2AHB_ISP0P, "aclk_axi2ahb_isp0p", "div_aclk_cam0_200",
4933 ENABLE_ACLK_CAM01, 4, CLK_IGNORE_UNUSED, 0),
4934 GATE(CLK_ACLK_XIU_IS0X, "aclk_xiu_is0x", "div_aclk_cam0_200",
4935 ENABLE_ACLK_CAM01, 3, CLK_IGNORE_UNUSED, 0),
4936 GATE(CLK_ACLK_XIU_ISP0EX, "aclk_xiu_isp0ex", "div_aclk_cam0_bus_400",
4937 ENABLE_ACLK_CAM01, 2, CLK_IGNORE_UNUSED, 0),
4938 GATE(CLK_ACLK_CAM0NP_276, "aclk_cam0np_276", "div_aclk_cam0_200",
4939 ENABLE_ACLK_CAM01, 1, CLK_IGNORE_UNUSED, 0),
4940 GATE(CLK_ACLK_CAM0ND_400, "aclk_cam0nd_400", "div_aclk_cam0_bus_400",
4941 ENABLE_ACLK_CAM01, 0, CLK_IGNORE_UNUSED, 0),
4942
4943 /* ENABLE_ACLK_CAM02 */
4944 GATE(CLK_ACLK_SMMU_3AA1, "aclk_smmu_3aa1", "div_aclk_cam0_bus_400",
4945 ENABLE_ACLK_CAM02, 9, CLK_IGNORE_UNUSED, 0),
4946 GATE(CLK_ACLK_SMMU_3AA0, "aclk_smmu_3aa0", "div_aclk_cam0_bus_400",
4947 ENABLE_ACLK_CAM02, 8, CLK_IGNORE_UNUSED, 0),
4948 GATE(CLK_ACLK_SMMU_LITE_D, "aclk_smmu_lite_d", "div_aclk_cam0_bus_400",
4949 ENABLE_ACLK_CAM02, 7, CLK_IGNORE_UNUSED, 0),
4950 GATE(CLK_ACLK_SMMU_LITE_B, "aclk_smmu_lite_b", "div_aclk_cam0_bus_400",
4951 ENABLE_ACLK_CAM02, 6, CLK_IGNORE_UNUSED, 0),
4952 GATE(CLK_ACLK_SMMU_LITE_A, "aclk_smmu_lite_a", "div_aclk_cam0_bus_400",
4953 ENABLE_ACLK_CAM02, 5, CLK_IGNORE_UNUSED, 0),
4954 GATE(CLK_ACLK_BTS_3AA1, "aclk_bts_3aa1", "div_aclk_cam0_bus_400",
4955 ENABLE_ACLK_CAM02, 4, CLK_IGNORE_UNUSED, 0),
4956 GATE(CLK_ACLK_BTS_3AA0, "aclk_bts_3aa0", "div_aclk_cam0_bus_400",
4957 ENABLE_ACLK_CAM02, 3, CLK_IGNORE_UNUSED, 0),
4958 GATE(CLK_ACLK_BTS_LITE_D, "aclk_bts_lite_d", "div_aclk_cam0_bus_400",
4959 ENABLE_ACLK_CAM02, 2, CLK_IGNORE_UNUSED, 0),
4960 GATE(CLK_ACLK_BTS_LITE_B, "aclk_bts_lite_b", "div_aclk_cam0_bus_400",
4961 ENABLE_ACLK_CAM02, 1, CLK_IGNORE_UNUSED, 0),
4962 GATE(CLK_ACLK_BTS_LITE_A, "aclk_bts_lite_a", "div_aclk_cam0_bus_400",
4963 ENABLE_ACLK_CAM02, 0, CLK_IGNORE_UNUSED, 0),
4964
4965 /* ENABLE_PCLK_CAM0 */
4966 GATE(CLK_PCLK_SMMU_3AA1, "pclk_smmu_3aa1", "div_aclk_cam0_200",
4967 ENABLE_PCLK_CAM0, 25, CLK_IGNORE_UNUSED, 0),
4968 GATE(CLK_PCLK_SMMU_3AA0, "pclk_smmu_3aa0", "div_aclk_cam0_200",
4969 ENABLE_PCLK_CAM0, 24, CLK_IGNORE_UNUSED, 0),
4970 GATE(CLK_PCLK_SMMU_LITE_D, "pclk_smmu_lite_d", "div_aclk_cam0_200",
4971 ENABLE_PCLK_CAM0, 23, CLK_IGNORE_UNUSED, 0),
4972 GATE(CLK_PCLK_SMMU_LITE_B, "pclk_smmu_lite_b", "div_aclk_cam0_200",
4973 ENABLE_PCLK_CAM0, 22, CLK_IGNORE_UNUSED, 0),
4974 GATE(CLK_PCLK_SMMU_LITE_A, "pclk_smmu_lite_a", "div_aclk_cam0_200",
4975 ENABLE_PCLK_CAM0, 21, CLK_IGNORE_UNUSED, 0),
4976 GATE(CLK_PCLK_BTS_3AA1, "pclk_bts_3aa1", "div_pclk_cam0_50",
4977 ENABLE_PCLK_CAM0, 20, CLK_IGNORE_UNUSED, 0),
4978 GATE(CLK_PCLK_BTS_3AA0, "pclk_bts_3aa0", "div_pclk_cam0_50",
4979 ENABLE_PCLK_CAM0, 19, CLK_IGNORE_UNUSED, 0),
4980 GATE(CLK_PCLK_BTS_LITE_D, "pclk_bts_lite_d", "div_pclk_cam0_50",
4981 ENABLE_PCLK_CAM0, 18, CLK_IGNORE_UNUSED, 0),
4982 GATE(CLK_PCLK_BTS_LITE_B, "pclk_bts_lite_b", "div_pclk_cam0_50",
4983 ENABLE_PCLK_CAM0, 17, CLK_IGNORE_UNUSED, 0),
4984 GATE(CLK_PCLK_BTS_LITE_A, "pclk_bts_lite_a", "div_pclk_cam0_50",
4985 ENABLE_PCLK_CAM0, 16, CLK_IGNORE_UNUSED, 0),
4986 GATE(CLK_PCLK_ASYNCAXI_CAM1, "pclk_asyncaxi_cam1", "div_pclk_cam0_50",
4987 ENABLE_PCLK_CAM0, 15, CLK_IGNORE_UNUSED, 0),
4988 GATE(CLK_PCLK_ASYNCAXI_3AA1, "pclk_asyncaxi_3aa1", "div_pclk_cam0_50",
4989 ENABLE_PCLK_CAM0, 14, CLK_IGNORE_UNUSED, 0),
4990 GATE(CLK_PCLK_ASYNCAXI_3AA0, "pclk_asyncaxi_3aa0", "div_pclk_cam0_50",
4991 ENABLE_PCLK_CAM0, 13, CLK_IGNORE_UNUSED, 0),
4992 GATE(CLK_PCLK_ASYNCAXI_LITE_D, "pclk_asyncaxi_lite_d",
4993 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4994 12, CLK_IGNORE_UNUSED, 0),
4995 GATE(CLK_PCLK_ASYNCAXI_LITE_B, "pclk_asyncaxi_lite_b",
4996 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
4997 11, CLK_IGNORE_UNUSED, 0),
4998 GATE(CLK_PCLK_ASYNCAXI_LITE_A, "pclk_asyncaxi_lite_a",
4999 "div_pclk_cam0_50", ENABLE_PCLK_CAM0,
5000 10, CLK_IGNORE_UNUSED, 0),
5001 GATE(CLK_PCLK_PMU_CAM0, "pclk_pmu_cam0", "div_pclk_cam0_50",
5002 ENABLE_PCLK_CAM0, 9, CLK_IGNORE_UNUSED, 0),
5003 GATE(CLK_PCLK_SYSREG_CAM0, "pclk_sysreg_cam0", "div_pclk_cam0_50",
5004 ENABLE_PCLK_CAM0, 8, CLK_IGNORE_UNUSED, 0),
5005 GATE(CLK_PCLK_CMU_CAM0_LOCAL, "pclk_cmu_cam0_local",
5006 "div_aclk_cam0_200", ENABLE_PCLK_CAM0,
5007 7, CLK_IGNORE_UNUSED, 0),
5008 GATE(CLK_PCLK_CSIS1, "pclk_csis1", "div_aclk_cam0_200",
5009 ENABLE_PCLK_CAM0, 6, CLK_IGNORE_UNUSED, 0),
5010 GATE(CLK_PCLK_CSIS0, "pclk_csis0", "div_aclk_cam0_200",
5011 ENABLE_PCLK_CAM0, 5, CLK_IGNORE_UNUSED, 0),
5012 GATE(CLK_PCLK_3AA1, "pclk_3aa1", "div_pclk_3aa1",
5013 ENABLE_PCLK_CAM0, 4, CLK_IGNORE_UNUSED, 0),
5014 GATE(CLK_PCLK_3AA0, "pclk_3aa0", "div_pclk_3aa0",
5015 ENABLE_PCLK_CAM0, 3, CLK_IGNORE_UNUSED, 0),
5016 GATE(CLK_PCLK_LITE_D, "pclk_lite_d", "div_pclk_lite_d",
5017 ENABLE_PCLK_CAM0, 2, CLK_IGNORE_UNUSED, 0),
5018 GATE(CLK_PCLK_LITE_B, "pclk_lite_b", "div_pclk_lite_b",
5019 ENABLE_PCLK_CAM0, 1, CLK_IGNORE_UNUSED, 0),
5020 GATE(CLK_PCLK_LITE_A, "pclk_lite_a", "div_pclk_lite_a",
5021 ENABLE_PCLK_CAM0, 0, CLK_IGNORE_UNUSED, 0),
5022
5023 /* ENABLE_SCLK_CAM0 */
5024 GATE(CLK_PHYCLK_RXBYTECLKHS0_S4, "phyclk_rxbyteclkhs0_s4",
5025 "mout_phyclk_rxbyteclkhs0_s4_user",
5026 ENABLE_SCLK_CAM0, 8, 0, 0),
5027 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2A, "phyclk_rxbyteclkhs0_s2a",
5028 "mout_phyclk_rxbyteclkhs0_s2a_user",
5029 ENABLE_SCLK_CAM0, 7, 0, 0),
5030 GATE(CLK_SCLK_LITE_FREECNT, "sclk_lite_freecnt",
5031 "mout_sclk_lite_freecnt_c", ENABLE_SCLK_CAM0, 6, 0, 0),
5032 GATE(CLK_SCLK_PIXELASYNCM_3AA1, "sclk_pixelasycm_3aa1",
5033 "div_aclk_3aa1", ENABLE_SCLK_CAM0, 5, 0, 0),
5034 GATE(CLK_SCLK_PIXELASYNCM_3AA0, "sclk_pixelasycm_3aa0",
5035 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 4, 0, 0),
5036 GATE(CLK_SCLK_PIXELASYNCS_3AA0, "sclk_pixelasycs_3aa0",
5037 "div_aclk_3aa0", ENABLE_SCLK_CAM0, 3, 0, 0),
5038 GATE(CLK_SCLK_PIXELASYNCM_LITE_C, "sclk_pixelasyncm_lite_c",
5039 "div_sclk_pixelasync_lite_c",
5040 ENABLE_SCLK_CAM0, 2, 0, 0),
5041 GATE(CLK_SCLK_PIXELASYNCM_LITE_C_INIT, "sclk_pixelasyncm_lite_c_init",
5042 "div_sclk_pixelasync_lite_c_init",
5043 ENABLE_SCLK_CAM0, 1, 0, 0),
5044 GATE(CLK_SCLK_PIXELASYNCS_LITE_C_INIT, "sclk_pixelasyncs_lite_c_init",
5045 "div_sclk_pixelasync_lite_c",
5046 ENABLE_SCLK_CAM0, 0, 0, 0),
5047 };
5048
5049 static const struct samsung_cmu_info cam0_cmu_info __initconst = {
5050 .mux_clks = cam0_mux_clks,
5051 .nr_mux_clks = ARRAY_SIZE(cam0_mux_clks),
5052 .div_clks = cam0_div_clks,
5053 .nr_div_clks = ARRAY_SIZE(cam0_div_clks),
5054 .gate_clks = cam0_gate_clks,
5055 .nr_gate_clks = ARRAY_SIZE(cam0_gate_clks),
5056 .fixed_clks = cam0_fixed_clks,
5057 .nr_fixed_clks = ARRAY_SIZE(cam0_fixed_clks),
5058 .nr_clk_ids = CAM0_NR_CLK,
5059 .clk_regs = cam0_clk_regs,
5060 .nr_clk_regs = ARRAY_SIZE(cam0_clk_regs),
5061 .suspend_regs = cam0_suspend_regs,
5062 .nr_suspend_regs = ARRAY_SIZE(cam0_suspend_regs),
5063 .clk_name = "aclk_cam0_400",
5064 };
5065
5066 /*
5067 * Register offset definitions for CMU_CAM1
5068 */
5069 #define MUX_SEL_CAM10 0x0200
5070 #define MUX_SEL_CAM11 0x0204
5071 #define MUX_SEL_CAM12 0x0208
5072 #define MUX_ENABLE_CAM10 0x0300
5073 #define MUX_ENABLE_CAM11 0x0304
5074 #define MUX_ENABLE_CAM12 0x0308
5075 #define MUX_STAT_CAM10 0x0400
5076 #define MUX_STAT_CAM11 0x0404
5077 #define MUX_STAT_CAM12 0x0408
5078 #define MUX_IGNORE_CAM11 0x0504
5079 #define DIV_CAM10 0x0600
5080 #define DIV_CAM11 0x0604
5081 #define DIV_STAT_CAM10 0x0700
5082 #define DIV_STAT_CAM11 0x0704
5083 #define ENABLE_ACLK_CAM10 0X0800
5084 #define ENABLE_ACLK_CAM11 0X0804
5085 #define ENABLE_ACLK_CAM12 0X0808
5086 #define ENABLE_PCLK_CAM1 0X0900
5087 #define ENABLE_SCLK_CAM1 0X0a00
5088 #define ENABLE_IP_CAM10 0X0b00
5089 #define ENABLE_IP_CAM11 0X0b04
5090 #define ENABLE_IP_CAM12 0X0b08
5091
5092 static const unsigned long cam1_clk_regs[] __initconst = {
5093 MUX_SEL_CAM10,
5094 MUX_SEL_CAM11,
5095 MUX_SEL_CAM12,
5096 MUX_ENABLE_CAM10,
5097 MUX_ENABLE_CAM11,
5098 MUX_ENABLE_CAM12,
5099 MUX_IGNORE_CAM11,
5100 DIV_CAM10,
5101 DIV_CAM11,
5102 ENABLE_ACLK_CAM10,
5103 ENABLE_ACLK_CAM11,
5104 ENABLE_ACLK_CAM12,
5105 ENABLE_PCLK_CAM1,
5106 ENABLE_SCLK_CAM1,
5107 ENABLE_IP_CAM10,
5108 ENABLE_IP_CAM11,
5109 ENABLE_IP_CAM12,
5110 };
5111
5112 static const struct samsung_clk_reg_dump cam1_suspend_regs[] = {
5113 { MUX_SEL_CAM10, 0 },
5114 { MUX_SEL_CAM11, 0 },
5115 { MUX_SEL_CAM12, 0 },
5116 };
5117
5118 PNAME(mout_sclk_isp_uart_user_p) = { "oscclk", "sclk_isp_uart_cam1", };
5119 PNAME(mout_sclk_isp_spi1_user_p) = { "oscclk", "sclk_isp_spi1_cam1", };
5120 PNAME(mout_sclk_isp_spi0_user_p) = { "oscclk", "sclk_isp_spi0_cam1", };
5121
5122 PNAME(mout_aclk_cam1_333_user_p) = { "oscclk", "aclk_cam1_333", };
5123 PNAME(mout_aclk_cam1_400_user_p) = { "oscclk", "aclk_cam1_400", };
5124 PNAME(mout_aclk_cam1_552_user_p) = { "oscclk", "aclk_cam1_552", };
5125
5126 PNAME(mout_phyclk_rxbyteclkhs0_s2b_user_p) = { "oscclk",
5127 "phyclk_rxbyteclkhs0_s2b_phy", };
5128
5129 PNAME(mout_aclk_csis2_b_p) = { "mout_aclk_csis2_a",
5130 "mout_aclk_cam1_333_user", };
5131 PNAME(mout_aclk_csis2_a_p) = { "mout_aclk_cam1_552_user",
5132 "mout_aclk_cam1_400_user", };
5133
5134 PNAME(mout_aclk_fd_b_p) = { "mout_aclk_fd_a",
5135 "mout_aclk_cam1_333_user", };
5136 PNAME(mout_aclk_fd_a_p) = { "mout_aclk_cam1_552_user",
5137 "mout_aclk_cam1_400_user", };
5138
5139 PNAME(mout_aclk_lite_c_b_p) = { "mout_aclk_lite_c_a",
5140 "mout_aclk_cam1_333_user", };
5141 PNAME(mout_aclk_lite_c_a_p) = { "mout_aclk_cam1_552_user",
5142 "mout_aclk_cam1_400_user", };
5143
5144 static const struct samsung_fixed_rate_clock cam1_fixed_clks[] __initconst = {
5145 FRATE(CLK_PHYCLK_RXBYTEECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b_phy", NULL,
5146 0, 100000000),
5147 };
5148
5149 static const struct samsung_mux_clock cam1_mux_clks[] __initconst = {
5150 /* MUX_SEL_CAM10 */
5151 MUX(CLK_MOUT_SCLK_ISP_UART_USER, "mout_sclk_isp_uart_user",
5152 mout_sclk_isp_uart_user_p, MUX_SEL_CAM10, 20, 1),
5153 MUX(CLK_MOUT_SCLK_ISP_SPI1_USER, "mout_sclk_isp_spi1_user",
5154 mout_sclk_isp_spi1_user_p, MUX_SEL_CAM10, 16, 1),
5155 MUX(CLK_MOUT_SCLK_ISP_SPI0_USER, "mout_sclk_isp_spi0_user",
5156 mout_sclk_isp_spi0_user_p, MUX_SEL_CAM10, 12, 1),
5157 MUX(CLK_MOUT_ACLK_CAM1_333_USER, "mout_aclk_cam1_333_user",
5158 mout_aclk_cam1_333_user_p, MUX_SEL_CAM10, 8, 1),
5159 MUX(CLK_MOUT_ACLK_CAM1_400_USER, "mout_aclk_cam1_400_user",
5160 mout_aclk_cam1_400_user_p, MUX_SEL_CAM10, 4, 1),
5161 MUX(CLK_MOUT_ACLK_CAM1_552_USER, "mout_aclk_cam1_552_user",
5162 mout_aclk_cam1_552_user_p, MUX_SEL_CAM10, 0, 1),
5163
5164 /* MUX_SEL_CAM11 */
5165 MUX(CLK_MOUT_PHYCLK_RXBYTECLKHS0_S2B_USER,
5166 "mout_phyclk_rxbyteclkhs0_s2b_user",
5167 mout_phyclk_rxbyteclkhs0_s2b_user_p,
5168 MUX_SEL_CAM11, 0, 1),
5169
5170 /* MUX_SEL_CAM12 */
5171 MUX(CLK_MOUT_ACLK_CSIS2_B, "mout_aclk_csis2_b", mout_aclk_csis2_b_p,
5172 MUX_SEL_CAM12, 20, 1),
5173 MUX(CLK_MOUT_ACLK_CSIS2_A, "mout_aclk_csis2_a", mout_aclk_csis2_a_p,
5174 MUX_SEL_CAM12, 16, 1),
5175 MUX(CLK_MOUT_ACLK_FD_B, "mout_aclk_fd_b", mout_aclk_fd_b_p,
5176 MUX_SEL_CAM12, 12, 1),
5177 MUX(CLK_MOUT_ACLK_FD_A, "mout_aclk_fd_a", mout_aclk_fd_a_p,
5178 MUX_SEL_CAM12, 8, 1),
5179 MUX(CLK_MOUT_ACLK_LITE_C_B, "mout_aclk_lite_c_b", mout_aclk_lite_c_b_p,
5180 MUX_SEL_CAM12, 4, 1),
5181 MUX(CLK_MOUT_ACLK_LITE_C_A, "mout_aclk_lite_c_a", mout_aclk_lite_c_a_p,
5182 MUX_SEL_CAM12, 0, 1),
5183 };
5184
5185 static const struct samsung_div_clock cam1_div_clks[] __initconst = {
5186 /* DIV_CAM10 */
5187 DIV(CLK_DIV_SCLK_ISP_MPWM, "div_sclk_isp_mpwm",
5188 "div_pclk_cam1_83", DIV_CAM10, 16, 2),
5189 DIV(CLK_DIV_PCLK_CAM1_83, "div_pclk_cam1_83",
5190 "mout_aclk_cam1_333_user", DIV_CAM10, 12, 2),
5191 DIV(CLK_DIV_PCLK_CAM1_166, "div_pclk_cam1_166",
5192 "mout_aclk_cam1_333_user", DIV_CAM10, 8, 2),
5193 DIV(CLK_DIV_PCLK_DBG_CAM1, "div_pclk_dbg_cam1",
5194 "mout_aclk_cam1_552_user", DIV_CAM10, 4, 3),
5195 DIV(CLK_DIV_ATCLK_CAM1, "div_atclk_cam1", "mout_aclk_cam1_552_user",
5196 DIV_CAM10, 0, 3),
5197
5198 /* DIV_CAM11 */
5199 DIV(CLK_DIV_ACLK_CSIS2, "div_aclk_csis2", "mout_aclk_csis2_b",
5200 DIV_CAM11, 16, 3),
5201 DIV(CLK_DIV_PCLK_FD, "div_pclk_fd", "div_aclk_fd", DIV_CAM11, 12, 2),
5202 DIV(CLK_DIV_ACLK_FD, "div_aclk_fd", "mout_aclk_fd_b", DIV_CAM11, 8, 3),
5203 DIV(CLK_DIV_PCLK_LITE_C, "div_pclk_lite_c", "div_aclk_lite_c",
5204 DIV_CAM11, 4, 2),
5205 DIV(CLK_DIV_ACLK_LITE_C, "div_aclk_lite_c", "mout_aclk_lite_c_b",
5206 DIV_CAM11, 0, 3),
5207 };
5208
5209 static const struct samsung_gate_clock cam1_gate_clks[] __initconst = {
5210 /* ENABLE_ACLK_CAM10 */
5211 GATE(CLK_ACLK_ISP_GIC, "aclk_isp_gic", "mout_aclk_cam1_333_user",
5212 ENABLE_ACLK_CAM10, 4, 0, 0),
5213 GATE(CLK_ACLK_FD, "aclk_fd", "div_aclk_fd",
5214 ENABLE_ACLK_CAM10, 3, 0, 0),
5215 GATE(CLK_ACLK_LITE_C, "aclk_lite_c", "div_aclk_lite_c",
5216 ENABLE_ACLK_CAM10, 1, 0, 0),
5217 GATE(CLK_ACLK_CSIS2, "aclk_csis2", "div_aclk_csis2",
5218 ENABLE_ACLK_CAM10, 0, 0, 0),
5219
5220 /* ENABLE_ACLK_CAM11 */
5221 GATE(CLK_ACLK_ASYNCAPBM_FD, "aclk_asyncapbm_fd", "div_pclk_fd",
5222 ENABLE_ACLK_CAM11, 29, CLK_IGNORE_UNUSED, 0),
5223 GATE(CLK_ACLK_ASYNCAPBS_FD, "aclk_asyncapbs_fd", "div_pclk_cam1_166",
5224 ENABLE_ACLK_CAM11, 28, CLK_IGNORE_UNUSED, 0),
5225 GATE(CLK_ACLK_ASYNCAPBM_LITE_C, "aclk_asyncapbm_lite_c",
5226 "div_pclk_lite_c", ENABLE_ACLK_CAM11,
5227 27, CLK_IGNORE_UNUSED, 0),
5228 GATE(CLK_ACLK_ASYNCAPBS_LITE_C, "aclk_asyncapbs_lite_c",
5229 "div_pclk_cam1_166", ENABLE_ACLK_CAM11,
5230 26, CLK_IGNORE_UNUSED, 0),
5231 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H2, "aclk_asyncahbs_sfrisp2h2",
5232 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5233 25, CLK_IGNORE_UNUSED, 0),
5234 GATE(CLK_ACLK_ASYNCAHBS_SFRISP2H1, "aclk_asyncahbs_sfrisp2h1",
5235 "div_pclk_cam1_83", ENABLE_ACLK_CAM11,
5236 24, CLK_IGNORE_UNUSED, 0),
5237 GATE(CLK_ACLK_ASYNCAXIM_CA5, "aclk_asyncaxim_ca5",
5238 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5239 23, CLK_IGNORE_UNUSED, 0),
5240 GATE(CLK_ACLK_ASYNCAXIS_CA5, "aclk_asyncaxis_ca5",
5241 "mout_aclk_cam1_552_user", ENABLE_ACLK_CAM11,
5242 22, CLK_IGNORE_UNUSED, 0),
5243 GATE(CLK_ACLK_ASYNCAXIS_ISPX2, "aclk_asyncaxis_ispx2",
5244 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5245 21, CLK_IGNORE_UNUSED, 0),
5246 GATE(CLK_ACLK_ASYNCAXIS_ISPX1, "aclk_asyncaxis_ispx1",
5247 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5248 20, CLK_IGNORE_UNUSED, 0),
5249 GATE(CLK_ACLK_ASYNCAXIS_ISPX0, "aclk_asyncaxis_ispx0",
5250 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5251 19, CLK_IGNORE_UNUSED, 0),
5252 GATE(CLK_ACLK_ASYNCAXIM_ISPEX, "aclk_asyncaxim_ispex",
5253 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5254 18, CLK_IGNORE_UNUSED, 0),
5255 GATE(CLK_ACLK_ASYNCAXIM_ISP3P, "aclk_asyncaxim_isp3p",
5256 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5257 17, CLK_IGNORE_UNUSED, 0),
5258 GATE(CLK_ACLK_ASYNCAXIS_ISP3P, "aclk_asyncaxis_isp3p",
5259 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5260 16, CLK_IGNORE_UNUSED, 0),
5261 GATE(CLK_ACLK_ASYNCAXIM_FD, "aclk_asyncaxim_fd",
5262 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5263 15, CLK_IGNORE_UNUSED, 0),
5264 GATE(CLK_ACLK_ASYNCAXIS_FD, "aclk_asyncaxis_fd", "div_aclk_fd",
5265 ENABLE_ACLK_CAM11, 14, CLK_IGNORE_UNUSED, 0),
5266 GATE(CLK_ACLK_ASYNCAXIM_LITE_C, "aclk_asyncaxim_lite_c",
5267 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM11,
5268 13, CLK_IGNORE_UNUSED, 0),
5269 GATE(CLK_ACLK_ASYNCAXIS_LITE_C, "aclk_asyncaxis_lite_c",
5270 "div_aclk_lite_c", ENABLE_ACLK_CAM11,
5271 12, CLK_IGNORE_UNUSED, 0),
5272 GATE(CLK_ACLK_AHB2APB_ISP5P, "aclk_ahb2apb_isp5p", "div_pclk_cam1_83",
5273 ENABLE_ACLK_CAM11, 11, CLK_IGNORE_UNUSED, 0),
5274 GATE(CLK_ACLK_AHB2APB_ISP3P, "aclk_ahb2apb_isp3p", "div_pclk_cam1_83",
5275 ENABLE_ACLK_CAM11, 10, CLK_IGNORE_UNUSED, 0),
5276 GATE(CLK_ACLK_AXI2APB_ISP3P, "aclk_axi2apb_isp3p",
5277 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM11,
5278 9, CLK_IGNORE_UNUSED, 0),
5279 GATE(CLK_ACLK_AHB_SFRISP2H, "aclk_ahb_sfrisp2h", "div_pclk_cam1_83",
5280 ENABLE_ACLK_CAM11, 8, CLK_IGNORE_UNUSED, 0),
5281 GATE(CLK_ACLK_AXI_ISP_HX_R, "aclk_axi_isp_hx_r", "div_pclk_cam1_166",
5282 ENABLE_ACLK_CAM11, 7, CLK_IGNORE_UNUSED, 0),
5283 GATE(CLK_ACLK_AXI_ISP_CX_R, "aclk_axi_isp_cx_r", "div_pclk_cam1_166",
5284 ENABLE_ACLK_CAM11, 6, CLK_IGNORE_UNUSED, 0),
5285 GATE(CLK_ACLK_AXI_ISP_HX, "aclk_axi_isp_hx", "mout_aclk_cam1_333_user",
5286 ENABLE_ACLK_CAM11, 5, CLK_IGNORE_UNUSED, 0),
5287 GATE(CLK_ACLK_AXI_ISP_CX, "aclk_axi_isp_cx", "mout_aclk_cam1_333_user",
5288 ENABLE_ACLK_CAM11, 4, CLK_IGNORE_UNUSED, 0),
5289 GATE(CLK_ACLK_XIU_ISPX, "aclk_xiu_ispx", "mout_aclk_cam1_333_user",
5290 ENABLE_ACLK_CAM11, 3, CLK_IGNORE_UNUSED, 0),
5291 GATE(CLK_ACLK_XIU_ISPEX, "aclk_xiu_ispex", "mout_aclk_cam1_400_user",
5292 ENABLE_ACLK_CAM11, 2, CLK_IGNORE_UNUSED, 0),
5293 GATE(CLK_ACLK_CAM1NP_333, "aclk_cam1np_333", "mout_aclk_cam1_333_user",
5294 ENABLE_ACLK_CAM11, 1, CLK_IGNORE_UNUSED, 0),
5295 GATE(CLK_ACLK_CAM1ND_400, "aclk_cam1nd_400", "mout_aclk_cam1_400_user",
5296 ENABLE_ACLK_CAM11, 0, CLK_IGNORE_UNUSED, 0),
5297
5298 /* ENABLE_ACLK_CAM12 */
5299 GATE(CLK_ACLK_SMMU_ISPCPU, "aclk_smmu_ispcpu",
5300 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5301 10, CLK_IGNORE_UNUSED, 0),
5302 GATE(CLK_ACLK_SMMU_FD, "aclk_smmu_fd", "mout_aclk_cam1_400_user",
5303 ENABLE_ACLK_CAM12, 9, CLK_IGNORE_UNUSED, 0),
5304 GATE(CLK_ACLK_SMMU_LITE_C, "aclk_smmu_lite_c",
5305 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5306 8, CLK_IGNORE_UNUSED, 0),
5307 GATE(CLK_ACLK_BTS_ISP3P, "aclk_bts_isp3p", "mout_aclk_cam1_400_user",
5308 ENABLE_ACLK_CAM12, 7, CLK_IGNORE_UNUSED, 0),
5309 GATE(CLK_ACLK_BTS_FD, "aclk_bts_fd", "mout_aclk_cam1_400_user",
5310 ENABLE_ACLK_CAM12, 6, CLK_IGNORE_UNUSED, 0),
5311 GATE(CLK_ACLK_BTS_LITE_C, "aclk_bts_lite_c", "mout_aclk_cam1_400_user",
5312 ENABLE_ACLK_CAM12, 5, CLK_IGNORE_UNUSED, 0),
5313 GATE(CLK_ACLK_AHBDN_SFRISP2H, "aclk_ahbdn_sfrisp2h",
5314 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5315 4, CLK_IGNORE_UNUSED, 0),
5316 GATE(CLK_ACLK_AHBDN_ISP5P, "aclk_aclk-shbdn_isp5p",
5317 "mout_aclk_cam1_333_user", ENABLE_ACLK_CAM12,
5318 3, CLK_IGNORE_UNUSED, 0),
5319 GATE(CLK_ACLK_AXIUS_ISP3P, "aclk_axius_isp3p",
5320 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5321 2, CLK_IGNORE_UNUSED, 0),
5322 GATE(CLK_ACLK_AXIUS_FD, "aclk_axius_fd", "mout_aclk_cam1_400_user",
5323 ENABLE_ACLK_CAM12, 1, CLK_IGNORE_UNUSED, 0),
5324 GATE(CLK_ACLK_AXIUS_LITE_C, "aclk_axius_lite_c",
5325 "mout_aclk_cam1_400_user", ENABLE_ACLK_CAM12,
5326 0, CLK_IGNORE_UNUSED, 0),
5327
5328 /* ENABLE_PCLK_CAM1 */
5329 GATE(CLK_PCLK_SMMU_ISPCPU, "pclk_smmu_ispcpu", "div_pclk_cam1_166",
5330 ENABLE_PCLK_CAM1, 27, CLK_IGNORE_UNUSED, 0),
5331 GATE(CLK_PCLK_SMMU_FD, "pclk_smmu_fd", "div_pclk_cam1_166",
5332 ENABLE_PCLK_CAM1, 26, CLK_IGNORE_UNUSED, 0),
5333 GATE(CLK_PCLK_SMMU_LITE_C, "pclk_smmu_lite_c", "div_pclk_cam1_166",
5334 ENABLE_PCLK_CAM1, 25, CLK_IGNORE_UNUSED, 0),
5335 GATE(CLK_PCLK_BTS_ISP3P, "pclk_bts_isp3p", "div_pclk_cam1_83",
5336 ENABLE_PCLK_CAM1, 24, CLK_IGNORE_UNUSED, 0),
5337 GATE(CLK_PCLK_BTS_FD, "pclk_bts_fd", "div_pclk_cam1_83",
5338 ENABLE_PCLK_CAM1, 23, CLK_IGNORE_UNUSED, 0),
5339 GATE(CLK_PCLK_BTS_LITE_C, "pclk_bts_lite_c", "div_pclk_cam1_83",
5340 ENABLE_PCLK_CAM1, 22, CLK_IGNORE_UNUSED, 0),
5341 GATE(CLK_PCLK_ASYNCAXIM_CA5, "pclk_asyncaxim_ca5", "div_pclk_cam1_166",
5342 ENABLE_PCLK_CAM1, 21, CLK_IGNORE_UNUSED, 0),
5343 GATE(CLK_PCLK_ASYNCAXIM_ISPEX, "pclk_asyncaxim_ispex",
5344 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5345 20, CLK_IGNORE_UNUSED, 0),
5346 GATE(CLK_PCLK_ASYNCAXIM_ISP3P, "pclk_asyncaxim_isp3p",
5347 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5348 19, CLK_IGNORE_UNUSED, 0),
5349 GATE(CLK_PCLK_ASYNCAXIM_FD, "pclk_asyncaxim_fd", "div_pclk_cam1_83",
5350 ENABLE_PCLK_CAM1, 18, CLK_IGNORE_UNUSED, 0),
5351 GATE(CLK_PCLK_ASYNCAXIM_LITE_C, "pclk_asyncaxim_lite_c",
5352 "div_pclk_cam1_83", ENABLE_PCLK_CAM1,
5353 17, CLK_IGNORE_UNUSED, 0),
5354 GATE(CLK_PCLK_PMU_CAM1, "pclk_pmu_cam1", "div_pclk_cam1_83",
5355 ENABLE_PCLK_CAM1, 16, CLK_IGNORE_UNUSED, 0),
5356 GATE(CLK_PCLK_SYSREG_CAM1, "pclk_sysreg_cam1", "div_pclk_cam1_83",
5357 ENABLE_PCLK_CAM1, 15, CLK_IGNORE_UNUSED, 0),
5358 GATE(CLK_PCLK_CMU_CAM1_LOCAL, "pclk_cmu_cam1_local",
5359 "div_pclk_cam1_166", ENABLE_PCLK_CAM1,
5360 14, CLK_IGNORE_UNUSED, 0),
5361 GATE(CLK_PCLK_ISP_MCTADC, "pclk_isp_mctadc", "div_pclk_cam1_83",
5362 ENABLE_PCLK_CAM1, 13, CLK_IGNORE_UNUSED, 0),
5363 GATE(CLK_PCLK_ISP_WDT, "pclk_isp_wdt", "div_pclk_cam1_83",
5364 ENABLE_PCLK_CAM1, 12, CLK_IGNORE_UNUSED, 0),
5365 GATE(CLK_PCLK_ISP_PWM, "pclk_isp_pwm", "div_pclk_cam1_83",
5366 ENABLE_PCLK_CAM1, 11, CLK_IGNORE_UNUSED, 0),
5367 GATE(CLK_PCLK_ISP_UART, "pclk_isp_uart", "div_pclk_cam1_83",
5368 ENABLE_PCLK_CAM1, 10, CLK_IGNORE_UNUSED, 0),
5369 GATE(CLK_PCLK_ISP_MCUCTL, "pclk_isp_mcuctl", "div_pclk_cam1_83",
5370 ENABLE_PCLK_CAM1, 9, CLK_IGNORE_UNUSED, 0),
5371 GATE(CLK_PCLK_ISP_SPI1, "pclk_isp_spi1", "div_pclk_cam1_83",
5372 ENABLE_PCLK_CAM1, 8, CLK_IGNORE_UNUSED, 0),
5373 GATE(CLK_PCLK_ISP_SPI0, "pclk_isp_spi0", "div_pclk_cam1_83",
5374 ENABLE_PCLK_CAM1, 7, CLK_IGNORE_UNUSED, 0),
5375 GATE(CLK_PCLK_ISP_I2C2, "pclk_isp_i2c2", "div_pclk_cam1_83",
5376 ENABLE_PCLK_CAM1, 6, CLK_IGNORE_UNUSED, 0),
5377 GATE(CLK_PCLK_ISP_I2C1, "pclk_isp_i2c1", "div_pclk_cam1_83",
5378 ENABLE_PCLK_CAM1, 5, CLK_IGNORE_UNUSED, 0),
5379 GATE(CLK_PCLK_ISP_I2C0, "pclk_isp_i2c0", "div_pclk_cam1_83",
5380 ENABLE_PCLK_CAM1, 4, CLK_IGNORE_UNUSED, 0),
5381 GATE(CLK_PCLK_ISP_MPWM, "pclk_isp_mpwm", "div_pclk_cam1_83",
5382 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5383 GATE(CLK_PCLK_FD, "pclk_fd", "div_pclk_fd",
5384 ENABLE_PCLK_CAM1, 3, CLK_IGNORE_UNUSED, 0),
5385 GATE(CLK_PCLK_LITE_C, "pclk_lite_c", "div_pclk_lite_c",
5386 ENABLE_PCLK_CAM1, 1, CLK_IGNORE_UNUSED, 0),
5387 GATE(CLK_PCLK_CSIS2, "pclk_csis2", "div_pclk_cam1_166",
5388 ENABLE_PCLK_CAM1, 0, CLK_IGNORE_UNUSED, 0),
5389
5390 /* ENABLE_SCLK_CAM1 */
5391 GATE(CLK_SCLK_ISP_I2C2, "sclk_isp_i2c2", "oscclk", ENABLE_SCLK_CAM1,
5392 15, 0, 0),
5393 GATE(CLK_SCLK_ISP_I2C1, "sclk_isp_i2c1", "oscclk", ENABLE_SCLK_CAM1,
5394 14, 0, 0),
5395 GATE(CLK_SCLK_ISP_I2C0, "sclk_isp_i2c0", "oscclk", ENABLE_SCLK_CAM1,
5396 13, 0, 0),
5397 GATE(CLK_SCLK_ISP_PWM, "sclk_isp_pwm", "oscclk", ENABLE_SCLK_CAM1,
5398 12, 0, 0),
5399 GATE(CLK_PHYCLK_RXBYTECLKHS0_S2B, "phyclk_rxbyteclkhs0_s2b",
5400 "mout_phyclk_rxbyteclkhs0_s2b_user",
5401 ENABLE_SCLK_CAM1, 11, 0, 0),
5402 GATE(CLK_SCLK_LITE_C_FREECNT, "sclk_lite_c_freecnt", "div_pclk_lite_c",
5403 ENABLE_SCLK_CAM1, 10, 0, 0),
5404 GATE(CLK_SCLK_PIXELASYNCM_FD, "sclk_pixelasyncm_fd", "div_aclk_fd",
5405 ENABLE_SCLK_CAM1, 9, 0, 0),
5406 GATE(CLK_SCLK_ISP_MCTADC, "sclk_isp_mctadc", "sclk_isp_mctadc_cam1",
5407 ENABLE_SCLK_CAM1, 7, 0, 0),
5408 GATE(CLK_SCLK_ISP_UART, "sclk_isp_uart", "mout_sclk_isp_uart_user",
5409 ENABLE_SCLK_CAM1, 6, 0, 0),
5410 GATE(CLK_SCLK_ISP_SPI1, "sclk_isp_spi1", "mout_sclk_isp_spi1_user",
5411 ENABLE_SCLK_CAM1, 5, 0, 0),
5412 GATE(CLK_SCLK_ISP_SPI0, "sclk_isp_spi0", "mout_sclk_isp_spi0_user",
5413 ENABLE_SCLK_CAM1, 4, 0, 0),
5414 GATE(CLK_SCLK_ISP_MPWM, "sclk_isp_mpwm", "div_sclk_isp_mpwm",
5415 ENABLE_SCLK_CAM1, 3, 0, 0),
5416 GATE(CLK_PCLK_DBG_ISP, "sclk_dbg_isp", "div_pclk_dbg_cam1",
5417 ENABLE_SCLK_CAM1, 2, 0, 0),
5418 GATE(CLK_ATCLK_ISP, "atclk_isp", "div_atclk_cam1",
5419 ENABLE_SCLK_CAM1, 1, 0, 0),
5420 GATE(CLK_SCLK_ISP_CA5, "sclk_isp_ca5", "mout_aclk_cam1_552_user",
5421 ENABLE_SCLK_CAM1, 0, 0, 0),
5422 };
5423
5424 static const struct samsung_cmu_info cam1_cmu_info __initconst = {
5425 .mux_clks = cam1_mux_clks,
5426 .nr_mux_clks = ARRAY_SIZE(cam1_mux_clks),
5427 .div_clks = cam1_div_clks,
5428 .nr_div_clks = ARRAY_SIZE(cam1_div_clks),
5429 .gate_clks = cam1_gate_clks,
5430 .nr_gate_clks = ARRAY_SIZE(cam1_gate_clks),
5431 .fixed_clks = cam1_fixed_clks,
5432 .nr_fixed_clks = ARRAY_SIZE(cam1_fixed_clks),
5433 .nr_clk_ids = CAM1_NR_CLK,
5434 .clk_regs = cam1_clk_regs,
5435 .nr_clk_regs = ARRAY_SIZE(cam1_clk_regs),
5436 .suspend_regs = cam1_suspend_regs,
5437 .nr_suspend_regs = ARRAY_SIZE(cam1_suspend_regs),
5438 .clk_name = "aclk_cam1_400",
5439 };
5440
5441
5442 struct exynos5433_cmu_data {
5443 struct samsung_clk_reg_dump *clk_save;
5444 unsigned int nr_clk_save;
5445 const struct samsung_clk_reg_dump *clk_suspend;
5446 unsigned int nr_clk_suspend;
5447
5448 struct clk *clk;
5449 struct clk **pclks;
5450 int nr_pclks;
5451
5452 /* must be the last entry */
5453 struct samsung_clk_provider ctx;
5454 };
5455
exynos5433_cmu_suspend(struct device * dev)5456 static int __maybe_unused exynos5433_cmu_suspend(struct device *dev)
5457 {
5458 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5459 int i;
5460
5461 samsung_clk_save(data->ctx.reg_base, data->clk_save,
5462 data->nr_clk_save);
5463
5464 for (i = 0; i < data->nr_pclks; i++)
5465 clk_prepare_enable(data->pclks[i]);
5466
5467 /* for suspend some registers have to be set to certain values */
5468 samsung_clk_restore(data->ctx.reg_base, data->clk_suspend,
5469 data->nr_clk_suspend);
5470
5471 for (i = 0; i < data->nr_pclks; i++)
5472 clk_disable_unprepare(data->pclks[i]);
5473
5474 clk_disable_unprepare(data->clk);
5475
5476 return 0;
5477 }
5478
exynos5433_cmu_resume(struct device * dev)5479 static int __maybe_unused exynos5433_cmu_resume(struct device *dev)
5480 {
5481 struct exynos5433_cmu_data *data = dev_get_drvdata(dev);
5482 int i;
5483
5484 clk_prepare_enable(data->clk);
5485
5486 for (i = 0; i < data->nr_pclks; i++)
5487 clk_prepare_enable(data->pclks[i]);
5488
5489 samsung_clk_restore(data->ctx.reg_base, data->clk_save,
5490 data->nr_clk_save);
5491
5492 for (i = 0; i < data->nr_pclks; i++)
5493 clk_disable_unprepare(data->pclks[i]);
5494
5495 return 0;
5496 }
5497
exynos5433_cmu_probe(struct platform_device * pdev)5498 static int __init exynos5433_cmu_probe(struct platform_device *pdev)
5499 {
5500 const struct samsung_cmu_info *info;
5501 struct exynos5433_cmu_data *data;
5502 struct samsung_clk_provider *ctx;
5503 struct device *dev = &pdev->dev;
5504 struct resource *res;
5505 void __iomem *reg_base;
5506 int i;
5507
5508 info = of_device_get_match_data(dev);
5509
5510 data = devm_kzalloc(dev,
5511 struct_size(data, ctx.clk_data.hws, info->nr_clk_ids),
5512 GFP_KERNEL);
5513 if (!data)
5514 return -ENOMEM;
5515 ctx = &data->ctx;
5516
5517 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
5518 reg_base = devm_ioremap_resource(dev, res);
5519 if (IS_ERR(reg_base))
5520 return PTR_ERR(reg_base);
5521
5522 for (i = 0; i < info->nr_clk_ids; ++i)
5523 ctx->clk_data.hws[i] = ERR_PTR(-ENOENT);
5524
5525 ctx->clk_data.num = info->nr_clk_ids;
5526 ctx->reg_base = reg_base;
5527 ctx->dev = dev;
5528 spin_lock_init(&ctx->lock);
5529
5530 data->clk_save = samsung_clk_alloc_reg_dump(info->clk_regs,
5531 info->nr_clk_regs);
5532 if (!data->clk_save)
5533 return -ENOMEM;
5534 data->nr_clk_save = info->nr_clk_regs;
5535 data->clk_suspend = info->suspend_regs;
5536 data->nr_clk_suspend = info->nr_suspend_regs;
5537 data->nr_pclks = of_count_phandle_with_args(dev->of_node, "clocks",
5538 "#clock-cells");
5539 if (data->nr_pclks > 0) {
5540 data->pclks = devm_kcalloc(dev, sizeof(struct clk *),
5541 data->nr_pclks, GFP_KERNEL);
5542 if (!data->pclks) {
5543 kfree(data->clk_save);
5544 return -ENOMEM;
5545 }
5546 for (i = 0; i < data->nr_pclks; i++) {
5547 struct clk *clk = of_clk_get(dev->of_node, i);
5548
5549 if (IS_ERR(clk)) {
5550 kfree(data->clk_save);
5551 while (--i >= 0)
5552 clk_put(data->pclks[i]);
5553 return PTR_ERR(clk);
5554 }
5555 data->pclks[i] = clk;
5556 }
5557 }
5558
5559 if (info->clk_name)
5560 data->clk = clk_get(dev, info->clk_name);
5561 clk_prepare_enable(data->clk);
5562
5563 platform_set_drvdata(pdev, data);
5564
5565 /*
5566 * Enable runtime PM here to allow the clock core using runtime PM
5567 * for the registered clocks. Additionally, we increase the runtime
5568 * PM usage count before registering the clocks, to prevent the
5569 * clock core from runtime suspending the device.
5570 */
5571 pm_runtime_get_noresume(dev);
5572 pm_runtime_set_active(dev);
5573 pm_runtime_enable(dev);
5574
5575 if (info->pll_clks)
5576 samsung_clk_register_pll(ctx, info->pll_clks, info->nr_pll_clks,
5577 reg_base);
5578 if (info->mux_clks)
5579 samsung_clk_register_mux(ctx, info->mux_clks,
5580 info->nr_mux_clks);
5581 if (info->div_clks)
5582 samsung_clk_register_div(ctx, info->div_clks,
5583 info->nr_div_clks);
5584 if (info->gate_clks)
5585 samsung_clk_register_gate(ctx, info->gate_clks,
5586 info->nr_gate_clks);
5587 if (info->fixed_clks)
5588 samsung_clk_register_fixed_rate(ctx, info->fixed_clks,
5589 info->nr_fixed_clks);
5590 if (info->fixed_factor_clks)
5591 samsung_clk_register_fixed_factor(ctx, info->fixed_factor_clks,
5592 info->nr_fixed_factor_clks);
5593
5594 samsung_clk_of_add_provider(dev->of_node, ctx);
5595 pm_runtime_put_sync(dev);
5596
5597 return 0;
5598 }
5599
5600 static const struct of_device_id exynos5433_cmu_of_match[] = {
5601 {
5602 .compatible = "samsung,exynos5433-cmu-aud",
5603 .data = &aud_cmu_info,
5604 }, {
5605 .compatible = "samsung,exynos5433-cmu-cam0",
5606 .data = &cam0_cmu_info,
5607 }, {
5608 .compatible = "samsung,exynos5433-cmu-cam1",
5609 .data = &cam1_cmu_info,
5610 }, {
5611 .compatible = "samsung,exynos5433-cmu-disp",
5612 .data = &disp_cmu_info,
5613 }, {
5614 .compatible = "samsung,exynos5433-cmu-g2d",
5615 .data = &g2d_cmu_info,
5616 }, {
5617 .compatible = "samsung,exynos5433-cmu-g3d",
5618 .data = &g3d_cmu_info,
5619 }, {
5620 .compatible = "samsung,exynos5433-cmu-fsys",
5621 .data = &fsys_cmu_info,
5622 }, {
5623 .compatible = "samsung,exynos5433-cmu-gscl",
5624 .data = &gscl_cmu_info,
5625 }, {
5626 .compatible = "samsung,exynos5433-cmu-mfc",
5627 .data = &mfc_cmu_info,
5628 }, {
5629 .compatible = "samsung,exynos5433-cmu-hevc",
5630 .data = &hevc_cmu_info,
5631 }, {
5632 .compatible = "samsung,exynos5433-cmu-isp",
5633 .data = &isp_cmu_info,
5634 }, {
5635 .compatible = "samsung,exynos5433-cmu-mscl",
5636 .data = &mscl_cmu_info,
5637 }, {
5638 },
5639 };
5640
5641 static const struct dev_pm_ops exynos5433_cmu_pm_ops = {
5642 SET_RUNTIME_PM_OPS(exynos5433_cmu_suspend, exynos5433_cmu_resume,
5643 NULL)
5644 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
5645 pm_runtime_force_resume)
5646 };
5647
5648 static struct platform_driver exynos5433_cmu_driver __refdata = {
5649 .driver = {
5650 .name = "exynos5433-cmu",
5651 .of_match_table = exynos5433_cmu_of_match,
5652 .suppress_bind_attrs = true,
5653 .pm = &exynos5433_cmu_pm_ops,
5654 },
5655 .probe = exynos5433_cmu_probe,
5656 };
5657
exynos5433_cmu_init(void)5658 static int __init exynos5433_cmu_init(void)
5659 {
5660 return platform_driver_register(&exynos5433_cmu_driver);
5661 }
5662 core_initcall(exynos5433_cmu_init);
5663