1# 2# FPGA framework configuration 3# 4 5menuconfig FPGA 6 tristate "FPGA Configuration Framework" 7 help 8 Say Y here if you want support for configuring FPGAs from the 9 kernel. The FPGA framework adds a FPGA manager class and FPGA 10 manager drivers. 11 12if FPGA 13 14config FPGA_MGR_SOCFPGA 15 tristate "Altera SOCFPGA FPGA Manager" 16 depends on ARCH_SOCFPGA || COMPILE_TEST 17 help 18 FPGA manager driver support for Altera SOCFPGA. 19 20config FPGA_MGR_SOCFPGA_A10 21 tristate "Altera SoCFPGA Arria10" 22 depends on ARCH_SOCFPGA || COMPILE_TEST 23 select REGMAP_MMIO 24 help 25 FPGA manager driver support for Altera Arria10 SoCFPGA. 26 27config ALTERA_PR_IP_CORE 28 tristate "Altera Partial Reconfiguration IP Core" 29 help 30 Core driver support for Altera Partial Reconfiguration IP component 31 32config ALTERA_PR_IP_CORE_PLAT 33 tristate "Platform support of Altera Partial Reconfiguration IP Core" 34 depends on ALTERA_PR_IP_CORE && OF && HAS_IOMEM 35 help 36 Platform driver support for Altera Partial Reconfiguration IP 37 component 38 39config FPGA_MGR_ALTERA_PS_SPI 40 tristate "Altera FPGA Passive Serial over SPI" 41 depends on SPI 42 select BITREVERSE 43 help 44 FPGA manager driver support for Altera Arria/Cyclone/Stratix 45 using the passive serial interface over SPI. 46 47config FPGA_MGR_ALTERA_CVP 48 tristate "Altera Arria-V/Cyclone-V/Stratix-V CvP FPGA Manager" 49 depends on PCI 50 help 51 FPGA manager driver support for Arria-V, Cyclone-V, Stratix-V 52 and Arria 10 Altera FPGAs using the CvP interface over PCIe. 53 54config FPGA_MGR_ZYNQ_FPGA 55 tristate "Xilinx Zynq FPGA" 56 depends on ARCH_ZYNQ || COMPILE_TEST 57 help 58 FPGA manager driver support for Xilinx Zynq FPGAs. 59 60config FPGA_MGR_XILINX_SPI 61 tristate "Xilinx Configuration over Slave Serial (SPI)" 62 depends on SPI 63 help 64 FPGA manager driver support for Xilinx FPGA configuration 65 over slave serial interface. 66 67config FPGA_MGR_ICE40_SPI 68 tristate "Lattice iCE40 SPI" 69 depends on OF && SPI 70 help 71 FPGA manager driver support for Lattice iCE40 FPGAs over SPI. 72 73config FPGA_MGR_MACHXO2_SPI 74 tristate "Lattice MachXO2 SPI" 75 depends on SPI 76 help 77 FPGA manager driver support for Lattice MachXO2 configuration 78 over slave SPI interface. 79 80config FPGA_MGR_TS73XX 81 tristate "Technologic Systems TS-73xx SBC FPGA Manager" 82 depends on ARCH_EP93XX && MACH_TS72XX 83 help 84 FPGA manager driver support for the Altera Cyclone II FPGA 85 present on the TS-73xx SBC boards. 86 87config FPGA_BRIDGE 88 tristate "FPGA Bridge Framework" 89 help 90 Say Y here if you want to support bridges connected between host 91 processors and FPGAs or between FPGAs. 92 93config SOCFPGA_FPGA_BRIDGE 94 tristate "Altera SoCFPGA FPGA Bridges" 95 depends on ARCH_SOCFPGA && FPGA_BRIDGE 96 help 97 Say Y to enable drivers for FPGA bridges for Altera SOCFPGA 98 devices. 99 100config ALTERA_FREEZE_BRIDGE 101 tristate "Altera FPGA Freeze Bridge" 102 depends on ARCH_SOCFPGA && FPGA_BRIDGE 103 help 104 Say Y to enable drivers for Altera FPGA Freeze bridges. A 105 freeze bridge is a bridge that exists in the FPGA fabric to 106 isolate one region of the FPGA from the busses while that 107 region is being reprogrammed. 108 109config XILINX_PR_DECOUPLER 110 tristate "Xilinx LogiCORE PR Decoupler" 111 depends on FPGA_BRIDGE 112 depends on HAS_IOMEM 113 help 114 Say Y to enable drivers for Xilinx LogiCORE PR Decoupler. 115 The PR Decoupler exists in the FPGA fabric to isolate one 116 region of the FPGA from the busses while that region is 117 being reprogrammed during partial reconfig. 118 119config FPGA_REGION 120 tristate "FPGA Region" 121 depends on FPGA_BRIDGE 122 help 123 FPGA Region common code. A FPGA Region controls a FPGA Manager 124 and the FPGA Bridges associated with either a reconfigurable 125 region of an FPGA or a whole FPGA. 126 127config OF_FPGA_REGION 128 tristate "FPGA Region Device Tree Overlay Support" 129 depends on OF && FPGA_REGION 130 help 131 Support for loading FPGA images by applying a Device Tree 132 overlay. 133 134config FPGA_DFL 135 tristate "FPGA Device Feature List (DFL) support" 136 select FPGA_BRIDGE 137 select FPGA_REGION 138 help 139 Device Feature List (DFL) defines a feature list structure that 140 creates a linked list of feature headers within the MMIO space 141 to provide an extensible way of adding features for FPGA. 142 Driver can walk through the feature headers to enumerate feature 143 devices (e.g. FPGA Management Engine, Port and Accelerator 144 Function Unit) and their private features for target FPGA devices. 145 146 Select this option to enable common support for Field-Programmable 147 Gate Array (FPGA) solutions which implement Device Feature List. 148 It provides enumeration APIs and feature device infrastructure. 149 150config FPGA_DFL_FME 151 tristate "FPGA DFL FME Driver" 152 depends on FPGA_DFL 153 help 154 The FPGA Management Engine (FME) is a feature device implemented 155 under Device Feature List (DFL) framework. Select this option to 156 enable the platform device driver for FME which implements all 157 FPGA platform level management features. There shall be one FME 158 per DFL based FPGA device. 159 160config FPGA_DFL_FME_MGR 161 tristate "FPGA DFL FME Manager Driver" 162 depends on FPGA_DFL_FME && HAS_IOMEM 163 help 164 Say Y to enable FPGA Manager driver for FPGA Management Engine. 165 166config FPGA_DFL_FME_BRIDGE 167 tristate "FPGA DFL FME Bridge Driver" 168 depends on FPGA_DFL_FME && HAS_IOMEM 169 help 170 Say Y to enable FPGA Bridge driver for FPGA Management Engine. 171 172config FPGA_DFL_FME_REGION 173 tristate "FPGA DFL FME Region Driver" 174 depends on FPGA_DFL_FME && HAS_IOMEM 175 help 176 Say Y to enable FPGA Region driver for FPGA Management Engine. 177 178config FPGA_DFL_AFU 179 tristate "FPGA DFL AFU Driver" 180 depends on FPGA_DFL 181 help 182 This is the driver for FPGA Accelerated Function Unit (AFU) which 183 implements AFU and Port management features. A User AFU connects 184 to the FPGA infrastructure via a Port. There may be more than one 185 Port/AFU per DFL based FPGA device. 186 187config FPGA_DFL_PCI 188 tristate "FPGA DFL PCIe Device Driver" 189 depends on PCI && FPGA_DFL 190 help 191 Select this option to enable PCIe driver for PCIe-based 192 Field-Programmable Gate Array (FPGA) solutions which implement 193 the Device Feature List (DFL). This driver provides interfaces 194 for userspace applications to configure, enumerate, open and access 195 FPGA accelerators on the FPGA DFL devices, enables system level 196 management functions such as FPGA partial reconfiguration, power 197 management and virtualization with DFL framework and DFL feature 198 device drivers. 199 200 To compile this as a module, choose M here. 201 202endif # FPGA 203