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1  /*
2   * Copyright (c) 2017, National Instruments Corp.
3   * Copyright (c) 2017, Xilix Inc
4   *
5   * FPGA Bridge Driver for the Xilinx LogiCORE Partial Reconfiguration
6   * Decoupler IP Core.
7   *
8   * This program is free software; you can redistribute it and/or modify
9   * it under the terms of the GNU General Public License as published by
10   * the Free Software Foundation; version 2 of the License.
11   *
12   * This program is distributed in the hope that it will be useful,
13   * but WITHOUT ANY WARRANTY; without even the implied warranty of
14   * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15   * GNU General Public License for more details.
16   */
17  
18  #include <linux/clk.h>
19  #include <linux/io.h>
20  #include <linux/kernel.h>
21  #include <linux/of_device.h>
22  #include <linux/module.h>
23  #include <linux/fpga/fpga-bridge.h>
24  
25  #define CTRL_CMD_DECOUPLE	BIT(0)
26  #define CTRL_CMD_COUPLE		0
27  #define CTRL_OFFSET		0
28  
29  struct xlnx_pr_decoupler_data {
30  	void __iomem *io_base;
31  	struct clk *clk;
32  };
33  
xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data * d,u32 offset,u32 val)34  static inline void xlnx_pr_decoupler_write(struct xlnx_pr_decoupler_data *d,
35  					   u32 offset, u32 val)
36  {
37  	writel(val, d->io_base + offset);
38  }
39  
xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data * d,u32 offset)40  static inline u32 xlnx_pr_decouple_read(const struct xlnx_pr_decoupler_data *d,
41  					u32 offset)
42  {
43  	return readl(d->io_base + offset);
44  }
45  
xlnx_pr_decoupler_enable_set(struct fpga_bridge * bridge,bool enable)46  static int xlnx_pr_decoupler_enable_set(struct fpga_bridge *bridge, bool enable)
47  {
48  	int err;
49  	struct xlnx_pr_decoupler_data *priv = bridge->priv;
50  
51  	err = clk_enable(priv->clk);
52  	if (err)
53  		return err;
54  
55  	if (enable)
56  		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_COUPLE);
57  	else
58  		xlnx_pr_decoupler_write(priv, CTRL_OFFSET, CTRL_CMD_DECOUPLE);
59  
60  	clk_disable(priv->clk);
61  
62  	return 0;
63  }
64  
xlnx_pr_decoupler_enable_show(struct fpga_bridge * bridge)65  static int xlnx_pr_decoupler_enable_show(struct fpga_bridge *bridge)
66  {
67  	const struct xlnx_pr_decoupler_data *priv = bridge->priv;
68  	u32 status;
69  	int err;
70  
71  	err = clk_enable(priv->clk);
72  	if (err)
73  		return err;
74  
75  	status = readl(priv->io_base);
76  
77  	clk_disable(priv->clk);
78  
79  	return !status;
80  }
81  
82  static const struct fpga_bridge_ops xlnx_pr_decoupler_br_ops = {
83  	.enable_set = xlnx_pr_decoupler_enable_set,
84  	.enable_show = xlnx_pr_decoupler_enable_show,
85  };
86  
87  static const struct of_device_id xlnx_pr_decoupler_of_match[] = {
88  	{ .compatible = "xlnx,pr-decoupler-1.00", },
89  	{ .compatible = "xlnx,pr-decoupler", },
90  	{},
91  };
92  MODULE_DEVICE_TABLE(of, xlnx_pr_decoupler_of_match);
93  
xlnx_pr_decoupler_probe(struct platform_device * pdev)94  static int xlnx_pr_decoupler_probe(struct platform_device *pdev)
95  {
96  	struct xlnx_pr_decoupler_data *priv;
97  	struct fpga_bridge *br;
98  	int err;
99  	struct resource *res;
100  
101  	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
102  	if (!priv)
103  		return -ENOMEM;
104  
105  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
106  	priv->io_base = devm_ioremap_resource(&pdev->dev, res);
107  	if (IS_ERR(priv->io_base))
108  		return PTR_ERR(priv->io_base);
109  
110  	priv->clk = devm_clk_get(&pdev->dev, "aclk");
111  	if (IS_ERR(priv->clk)) {
112  		dev_err(&pdev->dev, "input clock not found\n");
113  		return PTR_ERR(priv->clk);
114  	}
115  
116  	err = clk_prepare_enable(priv->clk);
117  	if (err) {
118  		dev_err(&pdev->dev, "unable to enable clock\n");
119  		return err;
120  	}
121  
122  	clk_disable(priv->clk);
123  
124  	br = fpga_bridge_create(&pdev->dev, "Xilinx PR Decoupler",
125  				&xlnx_pr_decoupler_br_ops, priv);
126  	if (!br) {
127  		err = -ENOMEM;
128  		goto err_clk;
129  	}
130  
131  	platform_set_drvdata(pdev, br);
132  
133  	err = fpga_bridge_register(br);
134  	if (err) {
135  		dev_err(&pdev->dev, "unable to register Xilinx PR Decoupler");
136  		goto err_clk;
137  	}
138  
139  	return 0;
140  
141  err_clk:
142  	clk_unprepare(priv->clk);
143  
144  	return err;
145  }
146  
xlnx_pr_decoupler_remove(struct platform_device * pdev)147  static int xlnx_pr_decoupler_remove(struct platform_device *pdev)
148  {
149  	struct fpga_bridge *bridge = platform_get_drvdata(pdev);
150  	struct xlnx_pr_decoupler_data *p = bridge->priv;
151  
152  	fpga_bridge_unregister(bridge);
153  
154  	clk_unprepare(p->clk);
155  
156  	return 0;
157  }
158  
159  static struct platform_driver xlnx_pr_decoupler_driver = {
160  	.probe = xlnx_pr_decoupler_probe,
161  	.remove = xlnx_pr_decoupler_remove,
162  	.driver = {
163  		.name = "xlnx_pr_decoupler",
164  		.of_match_table = of_match_ptr(xlnx_pr_decoupler_of_match),
165  	},
166  };
167  
168  module_platform_driver(xlnx_pr_decoupler_driver);
169  
170  MODULE_DESCRIPTION("Xilinx Partial Reconfiguration Decoupler");
171  MODULE_AUTHOR("Moritz Fischer <mdf@kernel.org>");
172  MODULE_AUTHOR("Michal Simek <michal.simek@xilinx.com>");
173  MODULE_LICENSE("GPL v2");
174