1 /*
2 * arch/arm/mach-tegra/gpio.c
3 *
4 * Copyright (c) 2010 Google, Inc
5 *
6 * Author:
7 * Erik Gilling <konkers@google.com>
8 *
9 * This software is licensed under the terms of the GNU General Public
10 * License version 2, as published by the Free Software Foundation, and
11 * may be copied, distributed, and modified under those terms.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 */
19
20 #include <linux/err.h>
21 #include <linux/init.h>
22 #include <linux/irq.h>
23 #include <linux/interrupt.h>
24 #include <linux/io.h>
25 #include <linux/gpio/driver.h>
26 #include <linux/of_device.h>
27 #include <linux/platform_device.h>
28 #include <linux/module.h>
29 #include <linux/irqdomain.h>
30 #include <linux/irqchip/chained_irq.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm.h>
33
34 #define GPIO_BANK(x) ((x) >> 5)
35 #define GPIO_PORT(x) (((x) >> 3) & 0x3)
36 #define GPIO_BIT(x) ((x) & 0x7)
37
38 #define GPIO_REG(tgi, x) (GPIO_BANK(x) * tgi->soc->bank_stride + \
39 GPIO_PORT(x) * 4)
40
41 #define GPIO_CNF(t, x) (GPIO_REG(t, x) + 0x00)
42 #define GPIO_OE(t, x) (GPIO_REG(t, x) + 0x10)
43 #define GPIO_OUT(t, x) (GPIO_REG(t, x) + 0X20)
44 #define GPIO_IN(t, x) (GPIO_REG(t, x) + 0x30)
45 #define GPIO_INT_STA(t, x) (GPIO_REG(t, x) + 0x40)
46 #define GPIO_INT_ENB(t, x) (GPIO_REG(t, x) + 0x50)
47 #define GPIO_INT_LVL(t, x) (GPIO_REG(t, x) + 0x60)
48 #define GPIO_INT_CLR(t, x) (GPIO_REG(t, x) + 0x70)
49 #define GPIO_DBC_CNT(t, x) (GPIO_REG(t, x) + 0xF0)
50
51
52 #define GPIO_MSK_CNF(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x00)
53 #define GPIO_MSK_OE(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x10)
54 #define GPIO_MSK_OUT(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0X20)
55 #define GPIO_MSK_DBC_EN(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x30)
56 #define GPIO_MSK_INT_STA(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x40)
57 #define GPIO_MSK_INT_ENB(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x50)
58 #define GPIO_MSK_INT_LVL(t, x) (GPIO_REG(t, x) + t->soc->upper_offset + 0x60)
59
60 #define GPIO_INT_LVL_MASK 0x010101
61 #define GPIO_INT_LVL_EDGE_RISING 0x000101
62 #define GPIO_INT_LVL_EDGE_FALLING 0x000100
63 #define GPIO_INT_LVL_EDGE_BOTH 0x010100
64 #define GPIO_INT_LVL_LEVEL_HIGH 0x000001
65 #define GPIO_INT_LVL_LEVEL_LOW 0x000000
66
67 struct tegra_gpio_info;
68
69 struct tegra_gpio_bank {
70 unsigned int bank;
71 unsigned int irq;
72 spinlock_t lvl_lock[4];
73 spinlock_t dbc_lock[4]; /* Lock for updating debounce count register */
74 #ifdef CONFIG_PM_SLEEP
75 u32 cnf[4];
76 u32 out[4];
77 u32 oe[4];
78 u32 int_enb[4];
79 u32 int_lvl[4];
80 u32 wake_enb[4];
81 u32 dbc_enb[4];
82 #endif
83 u32 dbc_cnt[4];
84 struct tegra_gpio_info *tgi;
85 };
86
87 struct tegra_gpio_soc_config {
88 bool debounce_supported;
89 u32 bank_stride;
90 u32 upper_offset;
91 };
92
93 struct tegra_gpio_info {
94 struct device *dev;
95 void __iomem *regs;
96 struct irq_domain *irq_domain;
97 struct tegra_gpio_bank *bank_info;
98 const struct tegra_gpio_soc_config *soc;
99 struct gpio_chip gc;
100 struct irq_chip ic;
101 u32 bank_count;
102 };
103
tegra_gpio_writel(struct tegra_gpio_info * tgi,u32 val,u32 reg)104 static inline void tegra_gpio_writel(struct tegra_gpio_info *tgi,
105 u32 val, u32 reg)
106 {
107 __raw_writel(val, tgi->regs + reg);
108 }
109
tegra_gpio_readl(struct tegra_gpio_info * tgi,u32 reg)110 static inline u32 tegra_gpio_readl(struct tegra_gpio_info *tgi, u32 reg)
111 {
112 return __raw_readl(tgi->regs + reg);
113 }
114
tegra_gpio_compose(unsigned int bank,unsigned int port,unsigned int bit)115 static unsigned int tegra_gpio_compose(unsigned int bank, unsigned int port,
116 unsigned int bit)
117 {
118 return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7);
119 }
120
tegra_gpio_mask_write(struct tegra_gpio_info * tgi,u32 reg,unsigned int gpio,u32 value)121 static void tegra_gpio_mask_write(struct tegra_gpio_info *tgi, u32 reg,
122 unsigned int gpio, u32 value)
123 {
124 u32 val;
125
126 val = 0x100 << GPIO_BIT(gpio);
127 if (value)
128 val |= 1 << GPIO_BIT(gpio);
129 tegra_gpio_writel(tgi, val, reg);
130 }
131
tegra_gpio_enable(struct tegra_gpio_info * tgi,unsigned int gpio)132 static void tegra_gpio_enable(struct tegra_gpio_info *tgi, unsigned int gpio)
133 {
134 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 1);
135 }
136
tegra_gpio_disable(struct tegra_gpio_info * tgi,unsigned int gpio)137 static void tegra_gpio_disable(struct tegra_gpio_info *tgi, unsigned int gpio)
138 {
139 tegra_gpio_mask_write(tgi, GPIO_MSK_CNF(tgi, gpio), gpio, 0);
140 }
141
tegra_gpio_request(struct gpio_chip * chip,unsigned int offset)142 static int tegra_gpio_request(struct gpio_chip *chip, unsigned int offset)
143 {
144 return pinctrl_gpio_request(offset);
145 }
146
tegra_gpio_free(struct gpio_chip * chip,unsigned int offset)147 static void tegra_gpio_free(struct gpio_chip *chip, unsigned int offset)
148 {
149 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
150
151 pinctrl_gpio_free(offset);
152 tegra_gpio_disable(tgi, offset);
153 }
154
tegra_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)155 static void tegra_gpio_set(struct gpio_chip *chip, unsigned int offset,
156 int value)
157 {
158 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
159
160 tegra_gpio_mask_write(tgi, GPIO_MSK_OUT(tgi, offset), offset, value);
161 }
162
tegra_gpio_get(struct gpio_chip * chip,unsigned int offset)163 static int tegra_gpio_get(struct gpio_chip *chip, unsigned int offset)
164 {
165 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
166 unsigned int bval = BIT(GPIO_BIT(offset));
167
168 /* If gpio is in output mode then read from the out value */
169 if (tegra_gpio_readl(tgi, GPIO_OE(tgi, offset)) & bval)
170 return !!(tegra_gpio_readl(tgi, GPIO_OUT(tgi, offset)) & bval);
171
172 return !!(tegra_gpio_readl(tgi, GPIO_IN(tgi, offset)) & bval);
173 }
174
tegra_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)175 static int tegra_gpio_direction_input(struct gpio_chip *chip,
176 unsigned int offset)
177 {
178 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
179
180 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 0);
181 tegra_gpio_enable(tgi, offset);
182 return 0;
183 }
184
tegra_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)185 static int tegra_gpio_direction_output(struct gpio_chip *chip,
186 unsigned int offset,
187 int value)
188 {
189 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
190
191 tegra_gpio_set(chip, offset, value);
192 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, offset), offset, 1);
193 tegra_gpio_enable(tgi, offset);
194 return 0;
195 }
196
tegra_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)197 static int tegra_gpio_get_direction(struct gpio_chip *chip,
198 unsigned int offset)
199 {
200 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
201 u32 pin_mask = BIT(GPIO_BIT(offset));
202 u32 cnf, oe;
203
204 cnf = tegra_gpio_readl(tgi, GPIO_CNF(tgi, offset));
205 if (!(cnf & pin_mask))
206 return -EINVAL;
207
208 oe = tegra_gpio_readl(tgi, GPIO_OE(tgi, offset));
209
210 return !(oe & pin_mask);
211 }
212
tegra_gpio_set_debounce(struct gpio_chip * chip,unsigned int offset,unsigned int debounce)213 static int tegra_gpio_set_debounce(struct gpio_chip *chip, unsigned int offset,
214 unsigned int debounce)
215 {
216 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
217 struct tegra_gpio_bank *bank = &tgi->bank_info[GPIO_BANK(offset)];
218 unsigned int debounce_ms = DIV_ROUND_UP(debounce, 1000);
219 unsigned long flags;
220 unsigned int port;
221
222 if (!debounce_ms) {
223 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset),
224 offset, 0);
225 return 0;
226 }
227
228 debounce_ms = min(debounce_ms, 255U);
229 port = GPIO_PORT(offset);
230
231 /* There is only one debounce count register per port and hence
232 * set the maximum of current and requested debounce time.
233 */
234 spin_lock_irqsave(&bank->dbc_lock[port], flags);
235 if (bank->dbc_cnt[port] < debounce_ms) {
236 tegra_gpio_writel(tgi, debounce_ms, GPIO_DBC_CNT(tgi, offset));
237 bank->dbc_cnt[port] = debounce_ms;
238 }
239 spin_unlock_irqrestore(&bank->dbc_lock[port], flags);
240
241 tegra_gpio_mask_write(tgi, GPIO_MSK_DBC_EN(tgi, offset), offset, 1);
242
243 return 0;
244 }
245
tegra_gpio_set_config(struct gpio_chip * chip,unsigned int offset,unsigned long config)246 static int tegra_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
247 unsigned long config)
248 {
249 u32 debounce;
250
251 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
252 return -ENOTSUPP;
253
254 debounce = pinconf_to_config_argument(config);
255 return tegra_gpio_set_debounce(chip, offset, debounce);
256 }
257
tegra_gpio_to_irq(struct gpio_chip * chip,unsigned int offset)258 static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
259 {
260 struct tegra_gpio_info *tgi = gpiochip_get_data(chip);
261
262 return irq_find_mapping(tgi->irq_domain, offset);
263 }
264
tegra_gpio_irq_ack(struct irq_data * d)265 static void tegra_gpio_irq_ack(struct irq_data *d)
266 {
267 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
268 struct tegra_gpio_info *tgi = bank->tgi;
269 unsigned int gpio = d->hwirq;
270
271 tegra_gpio_writel(tgi, 1 << GPIO_BIT(gpio), GPIO_INT_CLR(tgi, gpio));
272 }
273
tegra_gpio_irq_mask(struct irq_data * d)274 static void tegra_gpio_irq_mask(struct irq_data *d)
275 {
276 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
277 struct tegra_gpio_info *tgi = bank->tgi;
278 unsigned int gpio = d->hwirq;
279
280 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 0);
281 }
282
tegra_gpio_irq_unmask(struct irq_data * d)283 static void tegra_gpio_irq_unmask(struct irq_data *d)
284 {
285 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
286 struct tegra_gpio_info *tgi = bank->tgi;
287 unsigned int gpio = d->hwirq;
288
289 tegra_gpio_mask_write(tgi, GPIO_MSK_INT_ENB(tgi, gpio), gpio, 1);
290 }
291
tegra_gpio_irq_set_type(struct irq_data * d,unsigned int type)292 static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type)
293 {
294 unsigned int gpio = d->hwirq, port = GPIO_PORT(gpio), lvl_type;
295 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
296 struct tegra_gpio_info *tgi = bank->tgi;
297 unsigned long flags;
298 u32 val;
299 int ret;
300
301 switch (type & IRQ_TYPE_SENSE_MASK) {
302 case IRQ_TYPE_EDGE_RISING:
303 lvl_type = GPIO_INT_LVL_EDGE_RISING;
304 break;
305
306 case IRQ_TYPE_EDGE_FALLING:
307 lvl_type = GPIO_INT_LVL_EDGE_FALLING;
308 break;
309
310 case IRQ_TYPE_EDGE_BOTH:
311 lvl_type = GPIO_INT_LVL_EDGE_BOTH;
312 break;
313
314 case IRQ_TYPE_LEVEL_HIGH:
315 lvl_type = GPIO_INT_LVL_LEVEL_HIGH;
316 break;
317
318 case IRQ_TYPE_LEVEL_LOW:
319 lvl_type = GPIO_INT_LVL_LEVEL_LOW;
320 break;
321
322 default:
323 return -EINVAL;
324 }
325
326 spin_lock_irqsave(&bank->lvl_lock[port], flags);
327
328 val = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
329 val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio));
330 val |= lvl_type << GPIO_BIT(gpio);
331 tegra_gpio_writel(tgi, val, GPIO_INT_LVL(tgi, gpio));
332
333 spin_unlock_irqrestore(&bank->lvl_lock[port], flags);
334
335 tegra_gpio_mask_write(tgi, GPIO_MSK_OE(tgi, gpio), gpio, 0);
336 tegra_gpio_enable(tgi, gpio);
337
338 ret = gpiochip_lock_as_irq(&tgi->gc, gpio);
339 if (ret) {
340 dev_err(tgi->dev,
341 "unable to lock Tegra GPIO %u as IRQ\n", gpio);
342 tegra_gpio_disable(tgi, gpio);
343 return ret;
344 }
345
346 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
347 irq_set_handler_locked(d, handle_level_irq);
348 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
349 irq_set_handler_locked(d, handle_edge_irq);
350
351 return 0;
352 }
353
tegra_gpio_irq_shutdown(struct irq_data * d)354 static void tegra_gpio_irq_shutdown(struct irq_data *d)
355 {
356 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
357 struct tegra_gpio_info *tgi = bank->tgi;
358 unsigned int gpio = d->hwirq;
359
360 tegra_gpio_irq_mask(d);
361 gpiochip_unlock_as_irq(&tgi->gc, gpio);
362 }
363
tegra_gpio_irq_handler(struct irq_desc * desc)364 static void tegra_gpio_irq_handler(struct irq_desc *desc)
365 {
366 unsigned int port, pin, gpio;
367 bool unmasked = false;
368 u32 lvl;
369 unsigned long sta;
370 struct irq_chip *chip = irq_desc_get_chip(desc);
371 struct tegra_gpio_bank *bank = irq_desc_get_handler_data(desc);
372 struct tegra_gpio_info *tgi = bank->tgi;
373
374 chained_irq_enter(chip, desc);
375
376 for (port = 0; port < 4; port++) {
377 gpio = tegra_gpio_compose(bank->bank, port, 0);
378 sta = tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)) &
379 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio));
380 lvl = tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio));
381
382 for_each_set_bit(pin, &sta, 8) {
383 tegra_gpio_writel(tgi, 1 << pin,
384 GPIO_INT_CLR(tgi, gpio));
385
386 /* if gpio is edge triggered, clear condition
387 * before executing the handler so that we don't
388 * miss edges
389 */
390 if (!unmasked && lvl & (0x100 << pin)) {
391 unmasked = true;
392 chained_irq_exit(chip, desc);
393 }
394
395 generic_handle_irq(irq_find_mapping(tgi->irq_domain,
396 gpio + pin));
397 }
398 }
399
400 if (!unmasked)
401 chained_irq_exit(chip, desc);
402
403 }
404
405 #ifdef CONFIG_PM_SLEEP
tegra_gpio_resume(struct device * dev)406 static int tegra_gpio_resume(struct device *dev)
407 {
408 struct platform_device *pdev = to_platform_device(dev);
409 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
410 unsigned long flags;
411 unsigned int b, p;
412
413 local_irq_save(flags);
414
415 for (b = 0; b < tgi->bank_count; b++) {
416 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
417
418 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
419 unsigned int gpio = (b << 5) | (p << 3);
420
421 tegra_gpio_writel(tgi, bank->cnf[p],
422 GPIO_CNF(tgi, gpio));
423
424 if (tgi->soc->debounce_supported) {
425 tegra_gpio_writel(tgi, bank->dbc_cnt[p],
426 GPIO_DBC_CNT(tgi, gpio));
427 tegra_gpio_writel(tgi, bank->dbc_enb[p],
428 GPIO_MSK_DBC_EN(tgi, gpio));
429 }
430
431 tegra_gpio_writel(tgi, bank->out[p],
432 GPIO_OUT(tgi, gpio));
433 tegra_gpio_writel(tgi, bank->oe[p],
434 GPIO_OE(tgi, gpio));
435 tegra_gpio_writel(tgi, bank->int_lvl[p],
436 GPIO_INT_LVL(tgi, gpio));
437 tegra_gpio_writel(tgi, bank->int_enb[p],
438 GPIO_INT_ENB(tgi, gpio));
439 }
440 }
441
442 local_irq_restore(flags);
443 return 0;
444 }
445
tegra_gpio_suspend(struct device * dev)446 static int tegra_gpio_suspend(struct device *dev)
447 {
448 struct platform_device *pdev = to_platform_device(dev);
449 struct tegra_gpio_info *tgi = platform_get_drvdata(pdev);
450 unsigned long flags;
451 unsigned int b, p;
452
453 local_irq_save(flags);
454 for (b = 0; b < tgi->bank_count; b++) {
455 struct tegra_gpio_bank *bank = &tgi->bank_info[b];
456
457 for (p = 0; p < ARRAY_SIZE(bank->oe); p++) {
458 unsigned int gpio = (b << 5) | (p << 3);
459
460 bank->cnf[p] = tegra_gpio_readl(tgi,
461 GPIO_CNF(tgi, gpio));
462 bank->out[p] = tegra_gpio_readl(tgi,
463 GPIO_OUT(tgi, gpio));
464 bank->oe[p] = tegra_gpio_readl(tgi,
465 GPIO_OE(tgi, gpio));
466 if (tgi->soc->debounce_supported) {
467 bank->dbc_enb[p] = tegra_gpio_readl(tgi,
468 GPIO_MSK_DBC_EN(tgi, gpio));
469 bank->dbc_enb[p] = (bank->dbc_enb[p] << 8) |
470 bank->dbc_enb[p];
471 }
472
473 bank->int_enb[p] = tegra_gpio_readl(tgi,
474 GPIO_INT_ENB(tgi, gpio));
475 bank->int_lvl[p] = tegra_gpio_readl(tgi,
476 GPIO_INT_LVL(tgi, gpio));
477
478 /* Enable gpio irq for wake up source */
479 tegra_gpio_writel(tgi, bank->wake_enb[p],
480 GPIO_INT_ENB(tgi, gpio));
481 }
482 }
483 local_irq_restore(flags);
484 return 0;
485 }
486
tegra_gpio_irq_set_wake(struct irq_data * d,unsigned int enable)487 static int tegra_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
488 {
489 struct tegra_gpio_bank *bank = irq_data_get_irq_chip_data(d);
490 unsigned int gpio = d->hwirq;
491 u32 port, bit, mask;
492
493 port = GPIO_PORT(gpio);
494 bit = GPIO_BIT(gpio);
495 mask = BIT(bit);
496
497 if (enable)
498 bank->wake_enb[port] |= mask;
499 else
500 bank->wake_enb[port] &= ~mask;
501
502 return irq_set_irq_wake(bank->irq, enable);
503 }
504 #endif
505
506 #ifdef CONFIG_DEBUG_FS
507
508 #include <linux/debugfs.h>
509 #include <linux/seq_file.h>
510
tegra_dbg_gpio_show(struct seq_file * s,void * unused)511 static int tegra_dbg_gpio_show(struct seq_file *s, void *unused)
512 {
513 struct tegra_gpio_info *tgi = s->private;
514 unsigned int i, j;
515
516 for (i = 0; i < tgi->bank_count; i++) {
517 for (j = 0; j < 4; j++) {
518 unsigned int gpio = tegra_gpio_compose(i, j, 0);
519
520 seq_printf(s,
521 "%u:%u %02x %02x %02x %02x %02x %02x %06x\n",
522 i, j,
523 tegra_gpio_readl(tgi, GPIO_CNF(tgi, gpio)),
524 tegra_gpio_readl(tgi, GPIO_OE(tgi, gpio)),
525 tegra_gpio_readl(tgi, GPIO_OUT(tgi, gpio)),
526 tegra_gpio_readl(tgi, GPIO_IN(tgi, gpio)),
527 tegra_gpio_readl(tgi, GPIO_INT_STA(tgi, gpio)),
528 tegra_gpio_readl(tgi, GPIO_INT_ENB(tgi, gpio)),
529 tegra_gpio_readl(tgi, GPIO_INT_LVL(tgi, gpio)));
530 }
531 }
532 return 0;
533 }
534
535 DEFINE_SHOW_ATTRIBUTE(tegra_dbg_gpio);
536
tegra_gpio_debuginit(struct tegra_gpio_info * tgi)537 static void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
538 {
539 (void) debugfs_create_file("tegra_gpio", 0444,
540 NULL, tgi, &tegra_dbg_gpio_fops);
541 }
542
543 #else
544
tegra_gpio_debuginit(struct tegra_gpio_info * tgi)545 static inline void tegra_gpio_debuginit(struct tegra_gpio_info *tgi)
546 {
547 }
548
549 #endif
550
551 static const struct dev_pm_ops tegra_gpio_pm_ops = {
552 SET_SYSTEM_SLEEP_PM_OPS(tegra_gpio_suspend, tegra_gpio_resume)
553 };
554
tegra_gpio_probe(struct platform_device * pdev)555 static int tegra_gpio_probe(struct platform_device *pdev)
556 {
557 struct tegra_gpio_info *tgi;
558 struct resource *res;
559 struct tegra_gpio_bank *bank;
560 unsigned int gpio, i, j;
561 int ret;
562
563 tgi = devm_kzalloc(&pdev->dev, sizeof(*tgi), GFP_KERNEL);
564 if (!tgi)
565 return -ENODEV;
566
567 tgi->soc = of_device_get_match_data(&pdev->dev);
568 tgi->dev = &pdev->dev;
569
570 ret = platform_irq_count(pdev);
571 if (ret < 0)
572 return ret;
573
574 tgi->bank_count = ret;
575
576 if (!tgi->bank_count) {
577 dev_err(&pdev->dev, "Missing IRQ resource\n");
578 return -ENODEV;
579 }
580
581 tgi->gc.label = "tegra-gpio";
582 tgi->gc.request = tegra_gpio_request;
583 tgi->gc.free = tegra_gpio_free;
584 tgi->gc.direction_input = tegra_gpio_direction_input;
585 tgi->gc.get = tegra_gpio_get;
586 tgi->gc.direction_output = tegra_gpio_direction_output;
587 tgi->gc.set = tegra_gpio_set;
588 tgi->gc.get_direction = tegra_gpio_get_direction;
589 tgi->gc.to_irq = tegra_gpio_to_irq;
590 tgi->gc.base = 0;
591 tgi->gc.ngpio = tgi->bank_count * 32;
592 tgi->gc.parent = &pdev->dev;
593 tgi->gc.of_node = pdev->dev.of_node;
594
595 tgi->ic.name = "GPIO";
596 tgi->ic.irq_ack = tegra_gpio_irq_ack;
597 tgi->ic.irq_mask = tegra_gpio_irq_mask;
598 tgi->ic.irq_unmask = tegra_gpio_irq_unmask;
599 tgi->ic.irq_set_type = tegra_gpio_irq_set_type;
600 tgi->ic.irq_shutdown = tegra_gpio_irq_shutdown;
601 #ifdef CONFIG_PM_SLEEP
602 tgi->ic.irq_set_wake = tegra_gpio_irq_set_wake;
603 #endif
604
605 platform_set_drvdata(pdev, tgi);
606
607 if (tgi->soc->debounce_supported)
608 tgi->gc.set_config = tegra_gpio_set_config;
609
610 tgi->bank_info = devm_kcalloc(&pdev->dev, tgi->bank_count,
611 sizeof(*tgi->bank_info), GFP_KERNEL);
612 if (!tgi->bank_info)
613 return -ENOMEM;
614
615 tgi->irq_domain = irq_domain_add_linear(pdev->dev.of_node,
616 tgi->gc.ngpio,
617 &irq_domain_simple_ops, NULL);
618 if (!tgi->irq_domain)
619 return -ENODEV;
620
621 for (i = 0; i < tgi->bank_count; i++) {
622 ret = platform_get_irq(pdev, i);
623 if (ret < 0) {
624 dev_err(&pdev->dev, "Missing IRQ resource: %d\n", ret);
625 return ret;
626 }
627
628 bank = &tgi->bank_info[i];
629 bank->bank = i;
630 bank->irq = ret;
631 bank->tgi = tgi;
632 }
633
634 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
635 tgi->regs = devm_ioremap_resource(&pdev->dev, res);
636 if (IS_ERR(tgi->regs))
637 return PTR_ERR(tgi->regs);
638
639 for (i = 0; i < tgi->bank_count; i++) {
640 for (j = 0; j < 4; j++) {
641 int gpio = tegra_gpio_compose(i, j, 0);
642
643 tegra_gpio_writel(tgi, 0x00, GPIO_INT_ENB(tgi, gpio));
644 }
645 }
646
647 ret = devm_gpiochip_add_data(&pdev->dev, &tgi->gc, tgi);
648 if (ret < 0) {
649 irq_domain_remove(tgi->irq_domain);
650 return ret;
651 }
652
653 for (gpio = 0; gpio < tgi->gc.ngpio; gpio++) {
654 int irq = irq_create_mapping(tgi->irq_domain, gpio);
655 /* No validity check; all Tegra GPIOs are valid IRQs */
656
657 bank = &tgi->bank_info[GPIO_BANK(gpio)];
658
659 irq_set_chip_data(irq, bank);
660 irq_set_chip_and_handler(irq, &tgi->ic, handle_simple_irq);
661 }
662
663 for (i = 0; i < tgi->bank_count; i++) {
664 bank = &tgi->bank_info[i];
665
666 irq_set_chained_handler_and_data(bank->irq,
667 tegra_gpio_irq_handler, bank);
668
669 for (j = 0; j < 4; j++) {
670 spin_lock_init(&bank->lvl_lock[j]);
671 spin_lock_init(&bank->dbc_lock[j]);
672 }
673 }
674
675 tegra_gpio_debuginit(tgi);
676
677 return 0;
678 }
679
680 static const struct tegra_gpio_soc_config tegra20_gpio_config = {
681 .bank_stride = 0x80,
682 .upper_offset = 0x800,
683 };
684
685 static const struct tegra_gpio_soc_config tegra30_gpio_config = {
686 .bank_stride = 0x100,
687 .upper_offset = 0x80,
688 };
689
690 static const struct tegra_gpio_soc_config tegra210_gpio_config = {
691 .debounce_supported = true,
692 .bank_stride = 0x100,
693 .upper_offset = 0x80,
694 };
695
696 static const struct of_device_id tegra_gpio_of_match[] = {
697 { .compatible = "nvidia,tegra210-gpio", .data = &tegra210_gpio_config },
698 { .compatible = "nvidia,tegra30-gpio", .data = &tegra30_gpio_config },
699 { .compatible = "nvidia,tegra20-gpio", .data = &tegra20_gpio_config },
700 { },
701 };
702
703 static struct platform_driver tegra_gpio_driver = {
704 .driver = {
705 .name = "tegra-gpio",
706 .pm = &tegra_gpio_pm_ops,
707 .of_match_table = tegra_gpio_of_match,
708 },
709 .probe = tegra_gpio_probe,
710 };
711
tegra_gpio_init(void)712 static int __init tegra_gpio_init(void)
713 {
714 return platform_driver_register(&tegra_gpio_driver);
715 }
716 subsys_initcall(tegra_gpio_init);
717