1 /*
2 * Copyright 2012-15 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: AMD
23 *
24 */
25
26 #include "dce/dce_8_0_d.h"
27 #include "dce/dce_8_0_sh_mask.h"
28
29 #include "dm_services.h"
30
31 #include "link_encoder.h"
32 #include "stream_encoder.h"
33
34 #include "resource.h"
35 #include "include/irq_service_interface.h"
36 #include "irq/dce80/irq_service_dce80.h"
37 #include "dce110/dce110_timing_generator.h"
38 #include "dce110/dce110_resource.h"
39 #include "dce80/dce80_timing_generator.h"
40 #include "dce/dce_mem_input.h"
41 #include "dce/dce_link_encoder.h"
42 #include "dce/dce_stream_encoder.h"
43 #include "dce/dce_mem_input.h"
44 #include "dce/dce_ipp.h"
45 #include "dce/dce_transform.h"
46 #include "dce/dce_opp.h"
47 #include "dce/dce_clocks.h"
48 #include "dce/dce_clock_source.h"
49 #include "dce/dce_audio.h"
50 #include "dce/dce_hwseq.h"
51 #include "dce80/dce80_hw_sequencer.h"
52 #include "dce100/dce100_resource.h"
53
54 #include "reg_helper.h"
55
56 #include "dce/dce_dmcu.h"
57 #include "dce/dce_aux.h"
58 #include "dce/dce_abm.h"
59 /* TODO remove this include */
60
61 #ifndef mmMC_HUB_RDREQ_DMIF_LIMIT
62 #include "gmc/gmc_7_1_d.h"
63 #include "gmc/gmc_7_1_sh_mask.h"
64 #endif
65
66 #ifndef mmDP_DPHY_INTERNAL_CTRL
67 #define mmDP_DPHY_INTERNAL_CTRL 0x1CDE
68 #define mmDP0_DP_DPHY_INTERNAL_CTRL 0x1CDE
69 #define mmDP1_DP_DPHY_INTERNAL_CTRL 0x1FDE
70 #define mmDP2_DP_DPHY_INTERNAL_CTRL 0x42DE
71 #define mmDP3_DP_DPHY_INTERNAL_CTRL 0x45DE
72 #define mmDP4_DP_DPHY_INTERNAL_CTRL 0x48DE
73 #define mmDP5_DP_DPHY_INTERNAL_CTRL 0x4BDE
74 #define mmDP6_DP_DPHY_INTERNAL_CTRL 0x4EDE
75 #endif
76
77
78 #ifndef mmBIOS_SCRATCH_2
79 #define mmBIOS_SCRATCH_2 0x05CB
80 #define mmBIOS_SCRATCH_6 0x05CF
81 #endif
82
83 #ifndef mmDP_DPHY_FAST_TRAINING
84 #define mmDP_DPHY_FAST_TRAINING 0x1CCE
85 #define mmDP0_DP_DPHY_FAST_TRAINING 0x1CCE
86 #define mmDP1_DP_DPHY_FAST_TRAINING 0x1FCE
87 #define mmDP2_DP_DPHY_FAST_TRAINING 0x42CE
88 #define mmDP3_DP_DPHY_FAST_TRAINING 0x45CE
89 #define mmDP4_DP_DPHY_FAST_TRAINING 0x48CE
90 #define mmDP5_DP_DPHY_FAST_TRAINING 0x4BCE
91 #define mmDP6_DP_DPHY_FAST_TRAINING 0x4ECE
92 #endif
93
94
95 #ifndef mmHPD_DC_HPD_CONTROL
96 #define mmHPD_DC_HPD_CONTROL 0x189A
97 #define mmHPD0_DC_HPD_CONTROL 0x189A
98 #define mmHPD1_DC_HPD_CONTROL 0x18A2
99 #define mmHPD2_DC_HPD_CONTROL 0x18AA
100 #define mmHPD3_DC_HPD_CONTROL 0x18B2
101 #define mmHPD4_DC_HPD_CONTROL 0x18BA
102 #define mmHPD5_DC_HPD_CONTROL 0x18C2
103 #endif
104
105 #define DCE11_DIG_FE_CNTL 0x4a00
106 #define DCE11_DIG_BE_CNTL 0x4a47
107 #define DCE11_DP_SEC 0x4ac3
108
109 static const struct dce110_timing_generator_offsets dce80_tg_offsets[] = {
110 {
111 .crtc = (mmCRTC0_CRTC_CONTROL - mmCRTC_CONTROL),
112 .dcp = (mmGRPH_CONTROL - mmGRPH_CONTROL),
113 .dmif = (mmDMIF_PG0_DPG_WATERMARK_MASK_CONTROL
114 - mmDPG_WATERMARK_MASK_CONTROL),
115 },
116 {
117 .crtc = (mmCRTC1_CRTC_CONTROL - mmCRTC_CONTROL),
118 .dcp = (mmDCP1_GRPH_CONTROL - mmGRPH_CONTROL),
119 .dmif = (mmDMIF_PG1_DPG_WATERMARK_MASK_CONTROL
120 - mmDPG_WATERMARK_MASK_CONTROL),
121 },
122 {
123 .crtc = (mmCRTC2_CRTC_CONTROL - mmCRTC_CONTROL),
124 .dcp = (mmDCP2_GRPH_CONTROL - mmGRPH_CONTROL),
125 .dmif = (mmDMIF_PG2_DPG_WATERMARK_MASK_CONTROL
126 - mmDPG_WATERMARK_MASK_CONTROL),
127 },
128 {
129 .crtc = (mmCRTC3_CRTC_CONTROL - mmCRTC_CONTROL),
130 .dcp = (mmDCP3_GRPH_CONTROL - mmGRPH_CONTROL),
131 .dmif = (mmDMIF_PG3_DPG_WATERMARK_MASK_CONTROL
132 - mmDPG_WATERMARK_MASK_CONTROL),
133 },
134 {
135 .crtc = (mmCRTC4_CRTC_CONTROL - mmCRTC_CONTROL),
136 .dcp = (mmDCP4_GRPH_CONTROL - mmGRPH_CONTROL),
137 .dmif = (mmDMIF_PG4_DPG_WATERMARK_MASK_CONTROL
138 - mmDPG_WATERMARK_MASK_CONTROL),
139 },
140 {
141 .crtc = (mmCRTC5_CRTC_CONTROL - mmCRTC_CONTROL),
142 .dcp = (mmDCP5_GRPH_CONTROL - mmGRPH_CONTROL),
143 .dmif = (mmDMIF_PG5_DPG_WATERMARK_MASK_CONTROL
144 - mmDPG_WATERMARK_MASK_CONTROL),
145 }
146 };
147
148 /* set register offset */
149 #define SR(reg_name)\
150 .reg_name = mm ## reg_name
151
152 /* set register offset with instance */
153 #define SRI(reg_name, block, id)\
154 .reg_name = mm ## block ## id ## _ ## reg_name
155
156
157 static const struct dccg_registers disp_clk_regs = {
158 CLK_COMMON_REG_LIST_DCE_BASE()
159 };
160
161 static const struct dccg_shift disp_clk_shift = {
162 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
163 };
164
165 static const struct dccg_mask disp_clk_mask = {
166 CLK_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
167 };
168
169 #define ipp_regs(id)\
170 [id] = {\
171 IPP_COMMON_REG_LIST_DCE_BASE(id)\
172 }
173
174 static const struct dce_ipp_registers ipp_regs[] = {
175 ipp_regs(0),
176 ipp_regs(1),
177 ipp_regs(2),
178 ipp_regs(3),
179 ipp_regs(4),
180 ipp_regs(5)
181 };
182
183 static const struct dce_ipp_shift ipp_shift = {
184 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
185 };
186
187 static const struct dce_ipp_mask ipp_mask = {
188 IPP_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
189 };
190
191 #define transform_regs(id)\
192 [id] = {\
193 XFM_COMMON_REG_LIST_DCE80(id)\
194 }
195
196 static const struct dce_transform_registers xfm_regs[] = {
197 transform_regs(0),
198 transform_regs(1),
199 transform_regs(2),
200 transform_regs(3),
201 transform_regs(4),
202 transform_regs(5)
203 };
204
205 static const struct dce_transform_shift xfm_shift = {
206 XFM_COMMON_MASK_SH_LIST_DCE80(__SHIFT)
207 };
208
209 static const struct dce_transform_mask xfm_mask = {
210 XFM_COMMON_MASK_SH_LIST_DCE80(_MASK)
211 };
212
213 #define aux_regs(id)\
214 [id] = {\
215 AUX_REG_LIST(id)\
216 }
217
218 static const struct dce110_link_enc_aux_registers link_enc_aux_regs[] = {
219 aux_regs(0),
220 aux_regs(1),
221 aux_regs(2),
222 aux_regs(3),
223 aux_regs(4),
224 aux_regs(5)
225 };
226
227 #define hpd_regs(id)\
228 [id] = {\
229 HPD_REG_LIST(id)\
230 }
231
232 static const struct dce110_link_enc_hpd_registers link_enc_hpd_regs[] = {
233 hpd_regs(0),
234 hpd_regs(1),
235 hpd_regs(2),
236 hpd_regs(3),
237 hpd_regs(4),
238 hpd_regs(5)
239 };
240
241 #define link_regs(id)\
242 [id] = {\
243 LE_DCE80_REG_LIST(id)\
244 }
245
246 static const struct dce110_link_enc_registers link_enc_regs[] = {
247 link_regs(0),
248 link_regs(1),
249 link_regs(2),
250 link_regs(3),
251 link_regs(4),
252 link_regs(5),
253 link_regs(6),
254 };
255
256 #define stream_enc_regs(id)\
257 [id] = {\
258 SE_COMMON_REG_LIST_DCE_BASE(id),\
259 .AFMT_CNTL = 0,\
260 }
261
262 static const struct dce110_stream_enc_registers stream_enc_regs[] = {
263 stream_enc_regs(0),
264 stream_enc_regs(1),
265 stream_enc_regs(2),
266 stream_enc_regs(3),
267 stream_enc_regs(4),
268 stream_enc_regs(5),
269 stream_enc_regs(6)
270 };
271
272 static const struct dce_stream_encoder_shift se_shift = {
273 SE_COMMON_MASK_SH_LIST_DCE80_100(__SHIFT)
274 };
275
276 static const struct dce_stream_encoder_mask se_mask = {
277 SE_COMMON_MASK_SH_LIST_DCE80_100(_MASK)
278 };
279
280 #define opp_regs(id)\
281 [id] = {\
282 OPP_DCE_80_REG_LIST(id),\
283 }
284
285 static const struct dce_opp_registers opp_regs[] = {
286 opp_regs(0),
287 opp_regs(1),
288 opp_regs(2),
289 opp_regs(3),
290 opp_regs(4),
291 opp_regs(5)
292 };
293
294 static const struct dce_opp_shift opp_shift = {
295 OPP_COMMON_MASK_SH_LIST_DCE_80(__SHIFT)
296 };
297
298 static const struct dce_opp_mask opp_mask = {
299 OPP_COMMON_MASK_SH_LIST_DCE_80(_MASK)
300 };
301
302 #define aux_engine_regs(id)\
303 [id] = {\
304 AUX_COMMON_REG_LIST(id), \
305 .AUX_RESET_MASK = 0 \
306 }
307
308 static const struct dce110_aux_registers aux_engine_regs[] = {
309 aux_engine_regs(0),
310 aux_engine_regs(1),
311 aux_engine_regs(2),
312 aux_engine_regs(3),
313 aux_engine_regs(4),
314 aux_engine_regs(5)
315 };
316
317 #define audio_regs(id)\
318 [id] = {\
319 AUD_COMMON_REG_LIST(id)\
320 }
321
322 static const struct dce_audio_registers audio_regs[] = {
323 audio_regs(0),
324 audio_regs(1),
325 audio_regs(2),
326 audio_regs(3),
327 audio_regs(4),
328 audio_regs(5),
329 audio_regs(6),
330 };
331
332 static const struct dce_audio_shift audio_shift = {
333 AUD_COMMON_MASK_SH_LIST(__SHIFT)
334 };
335
336 static const struct dce_aduio_mask audio_mask = {
337 AUD_COMMON_MASK_SH_LIST(_MASK)
338 };
339
340 #define clk_src_regs(id)\
341 [id] = {\
342 CS_COMMON_REG_LIST_DCE_80(id),\
343 }
344
345
346 static const struct dce110_clk_src_regs clk_src_regs[] = {
347 clk_src_regs(0),
348 clk_src_regs(1),
349 clk_src_regs(2)
350 };
351
352 static const struct dce110_clk_src_shift cs_shift = {
353 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(__SHIFT)
354 };
355
356 static const struct dce110_clk_src_mask cs_mask = {
357 CS_COMMON_MASK_SH_LIST_DCE_COMMON_BASE(_MASK)
358 };
359
360 static const struct bios_registers bios_regs = {
361 .BIOS_SCRATCH_6 = mmBIOS_SCRATCH_6
362 };
363
364 static const struct resource_caps res_cap = {
365 .num_timing_generator = 6,
366 .num_audio = 6,
367 .num_stream_encoder = 6,
368 .num_pll = 3,
369 };
370
371 static const struct resource_caps res_cap_81 = {
372 .num_timing_generator = 4,
373 .num_audio = 7,
374 .num_stream_encoder = 7,
375 .num_pll = 3,
376 };
377
378 static const struct resource_caps res_cap_83 = {
379 .num_timing_generator = 2,
380 .num_audio = 6,
381 .num_stream_encoder = 6,
382 .num_pll = 2,
383 };
384
385 static const struct dce_dmcu_registers dmcu_regs = {
386 DMCU_DCE80_REG_LIST()
387 };
388
389 static const struct dce_dmcu_shift dmcu_shift = {
390 DMCU_MASK_SH_LIST_DCE80(__SHIFT)
391 };
392
393 static const struct dce_dmcu_mask dmcu_mask = {
394 DMCU_MASK_SH_LIST_DCE80(_MASK)
395 };
396 static const struct dce_abm_registers abm_regs = {
397 ABM_DCE110_COMMON_REG_LIST()
398 };
399
400 static const struct dce_abm_shift abm_shift = {
401 ABM_MASK_SH_LIST_DCE110(__SHIFT)
402 };
403
404 static const struct dce_abm_mask abm_mask = {
405 ABM_MASK_SH_LIST_DCE110(_MASK)
406 };
407
408 #define CTX ctx
409 #define REG(reg) mm ## reg
410
411 #ifndef mmCC_DC_HDMI_STRAPS
412 #define mmCC_DC_HDMI_STRAPS 0x1918
413 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE_MASK 0x40
414 #define CC_DC_HDMI_STRAPS__HDMI_DISABLE__SHIFT 0x6
415 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER_MASK 0x700
416 #define CC_DC_HDMI_STRAPS__AUDIO_STREAM_NUMBER__SHIFT 0x8
417 #endif
418
read_dce_straps(struct dc_context * ctx,struct resource_straps * straps)419 static void read_dce_straps(
420 struct dc_context *ctx,
421 struct resource_straps *straps)
422 {
423 REG_GET_2(CC_DC_HDMI_STRAPS,
424 HDMI_DISABLE, &straps->hdmi_disable,
425 AUDIO_STREAM_NUMBER, &straps->audio_stream_number);
426
427 REG_GET(DC_PINSTRAPS, DC_PINSTRAPS_AUDIO, &straps->dc_pinstraps_audio);
428 }
429
create_audio(struct dc_context * ctx,unsigned int inst)430 static struct audio *create_audio(
431 struct dc_context *ctx, unsigned int inst)
432 {
433 return dce_audio_create(ctx, inst,
434 &audio_regs[inst], &audio_shift, &audio_mask);
435 }
436
dce80_timing_generator_create(struct dc_context * ctx,uint32_t instance,const struct dce110_timing_generator_offsets * offsets)437 static struct timing_generator *dce80_timing_generator_create(
438 struct dc_context *ctx,
439 uint32_t instance,
440 const struct dce110_timing_generator_offsets *offsets)
441 {
442 struct dce110_timing_generator *tg110 =
443 kzalloc(sizeof(struct dce110_timing_generator), GFP_KERNEL);
444
445 if (!tg110)
446 return NULL;
447
448 dce80_timing_generator_construct(tg110, ctx, instance, offsets);
449 return &tg110->base;
450 }
451
dce80_opp_create(struct dc_context * ctx,uint32_t inst)452 static struct output_pixel_processor *dce80_opp_create(
453 struct dc_context *ctx,
454 uint32_t inst)
455 {
456 struct dce110_opp *opp =
457 kzalloc(sizeof(struct dce110_opp), GFP_KERNEL);
458
459 if (!opp)
460 return NULL;
461
462 dce110_opp_construct(opp,
463 ctx, inst, &opp_regs[inst], &opp_shift, &opp_mask);
464 return &opp->base;
465 }
466
dce80_aux_engine_create(struct dc_context * ctx,uint32_t inst)467 struct aux_engine *dce80_aux_engine_create(
468 struct dc_context *ctx,
469 uint32_t inst)
470 {
471 struct aux_engine_dce110 *aux_engine =
472 kzalloc(sizeof(struct aux_engine_dce110), GFP_KERNEL);
473
474 if (!aux_engine)
475 return NULL;
476
477 dce110_aux_engine_construct(aux_engine, ctx, inst,
478 SW_AUX_TIMEOUT_PERIOD_MULTIPLIER * AUX_TIMEOUT_PERIOD,
479 &aux_engine_regs[inst]);
480
481 return &aux_engine->base;
482 }
483
dce80_stream_encoder_create(enum engine_id eng_id,struct dc_context * ctx)484 static struct stream_encoder *dce80_stream_encoder_create(
485 enum engine_id eng_id,
486 struct dc_context *ctx)
487 {
488 struct dce110_stream_encoder *enc110 =
489 kzalloc(sizeof(struct dce110_stream_encoder), GFP_KERNEL);
490
491 if (!enc110)
492 return NULL;
493
494 dce110_stream_encoder_construct(enc110, ctx, ctx->dc_bios, eng_id,
495 &stream_enc_regs[eng_id],
496 &se_shift, &se_mask);
497 return &enc110->base;
498 }
499
500 #define SRII(reg_name, block, id)\
501 .reg_name[id] = mm ## block ## id ## _ ## reg_name
502
503 static const struct dce_hwseq_registers hwseq_reg = {
504 HWSEQ_DCE8_REG_LIST()
505 };
506
507 static const struct dce_hwseq_shift hwseq_shift = {
508 HWSEQ_DCE8_MASK_SH_LIST(__SHIFT)
509 };
510
511 static const struct dce_hwseq_mask hwseq_mask = {
512 HWSEQ_DCE8_MASK_SH_LIST(_MASK)
513 };
514
dce80_hwseq_create(struct dc_context * ctx)515 static struct dce_hwseq *dce80_hwseq_create(
516 struct dc_context *ctx)
517 {
518 struct dce_hwseq *hws = kzalloc(sizeof(struct dce_hwseq), GFP_KERNEL);
519
520 if (hws) {
521 hws->ctx = ctx;
522 hws->regs = &hwseq_reg;
523 hws->shifts = &hwseq_shift;
524 hws->masks = &hwseq_mask;
525 }
526 return hws;
527 }
528
529 static const struct resource_create_funcs res_create_funcs = {
530 .read_dce_straps = read_dce_straps,
531 .create_audio = create_audio,
532 .create_stream_encoder = dce80_stream_encoder_create,
533 .create_hwseq = dce80_hwseq_create,
534 };
535
536 #define mi_inst_regs(id) { \
537 MI_DCE8_REG_LIST(id), \
538 .MC_HUB_RDREQ_DMIF_LIMIT = mmMC_HUB_RDREQ_DMIF_LIMIT \
539 }
540 static const struct dce_mem_input_registers mi_regs[] = {
541 mi_inst_regs(0),
542 mi_inst_regs(1),
543 mi_inst_regs(2),
544 mi_inst_regs(3),
545 mi_inst_regs(4),
546 mi_inst_regs(5),
547 };
548
549 static const struct dce_mem_input_shift mi_shifts = {
550 MI_DCE8_MASK_SH_LIST(__SHIFT),
551 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE__SHIFT
552 };
553
554 static const struct dce_mem_input_mask mi_masks = {
555 MI_DCE8_MASK_SH_LIST(_MASK),
556 .ENABLE = MC_HUB_RDREQ_DMIF_LIMIT__ENABLE_MASK
557 };
558
dce80_mem_input_create(struct dc_context * ctx,uint32_t inst)559 static struct mem_input *dce80_mem_input_create(
560 struct dc_context *ctx,
561 uint32_t inst)
562 {
563 struct dce_mem_input *dce_mi = kzalloc(sizeof(struct dce_mem_input),
564 GFP_KERNEL);
565
566 if (!dce_mi) {
567 BREAK_TO_DEBUGGER();
568 return NULL;
569 }
570
571 dce_mem_input_construct(dce_mi, ctx, inst, &mi_regs[inst], &mi_shifts, &mi_masks);
572 dce_mi->wa.single_head_rdreq_dmif_limit = 2;
573 return &dce_mi->base;
574 }
575
dce80_transform_destroy(struct transform ** xfm)576 static void dce80_transform_destroy(struct transform **xfm)
577 {
578 kfree(TO_DCE_TRANSFORM(*xfm));
579 *xfm = NULL;
580 }
581
dce80_transform_create(struct dc_context * ctx,uint32_t inst)582 static struct transform *dce80_transform_create(
583 struct dc_context *ctx,
584 uint32_t inst)
585 {
586 struct dce_transform *transform =
587 kzalloc(sizeof(struct dce_transform), GFP_KERNEL);
588
589 if (!transform)
590 return NULL;
591
592 dce_transform_construct(transform, ctx, inst,
593 &xfm_regs[inst], &xfm_shift, &xfm_mask);
594 transform->prescaler_on = false;
595 return &transform->base;
596 }
597
598 static const struct encoder_feature_support link_enc_feature = {
599 .max_hdmi_deep_color = COLOR_DEPTH_121212,
600 .max_hdmi_pixel_clock = 297000,
601 .flags.bits.IS_HBR2_CAPABLE = true,
602 .flags.bits.IS_TPS3_CAPABLE = true,
603 .flags.bits.IS_YCBCR_CAPABLE = true
604 };
605
dce80_link_encoder_create(const struct encoder_init_data * enc_init_data)606 struct link_encoder *dce80_link_encoder_create(
607 const struct encoder_init_data *enc_init_data)
608 {
609 struct dce110_link_encoder *enc110 =
610 kzalloc(sizeof(struct dce110_link_encoder), GFP_KERNEL);
611
612 if (!enc110)
613 return NULL;
614
615 dce110_link_encoder_construct(enc110,
616 enc_init_data,
617 &link_enc_feature,
618 &link_enc_regs[enc_init_data->transmitter],
619 &link_enc_aux_regs[enc_init_data->channel - 1],
620 &link_enc_hpd_regs[enc_init_data->hpd_source]);
621 return &enc110->base;
622 }
623
dce80_clock_source_create(struct dc_context * ctx,struct dc_bios * bios,enum clock_source_id id,const struct dce110_clk_src_regs * regs,bool dp_clk_src)624 struct clock_source *dce80_clock_source_create(
625 struct dc_context *ctx,
626 struct dc_bios *bios,
627 enum clock_source_id id,
628 const struct dce110_clk_src_regs *regs,
629 bool dp_clk_src)
630 {
631 struct dce110_clk_src *clk_src =
632 kzalloc(sizeof(struct dce110_clk_src), GFP_KERNEL);
633
634 if (!clk_src)
635 return NULL;
636
637 if (dce110_clk_src_construct(clk_src, ctx, bios, id,
638 regs, &cs_shift, &cs_mask)) {
639 clk_src->base.dp_clk_src = dp_clk_src;
640 return &clk_src->base;
641 }
642
643 kfree(clk_src);
644 BREAK_TO_DEBUGGER();
645 return NULL;
646 }
647
dce80_clock_source_destroy(struct clock_source ** clk_src)648 void dce80_clock_source_destroy(struct clock_source **clk_src)
649 {
650 kfree(TO_DCE110_CLK_SRC(*clk_src));
651 *clk_src = NULL;
652 }
653
dce80_ipp_create(struct dc_context * ctx,uint32_t inst)654 static struct input_pixel_processor *dce80_ipp_create(
655 struct dc_context *ctx, uint32_t inst)
656 {
657 struct dce_ipp *ipp = kzalloc(sizeof(struct dce_ipp), GFP_KERNEL);
658
659 if (!ipp) {
660 BREAK_TO_DEBUGGER();
661 return NULL;
662 }
663
664 dce_ipp_construct(ipp, ctx, inst,
665 &ipp_regs[inst], &ipp_shift, &ipp_mask);
666 return &ipp->base;
667 }
668
destruct(struct dce110_resource_pool * pool)669 static void destruct(struct dce110_resource_pool *pool)
670 {
671 unsigned int i;
672
673 for (i = 0; i < pool->base.pipe_count; i++) {
674 if (pool->base.opps[i] != NULL)
675 dce110_opp_destroy(&pool->base.opps[i]);
676
677 if (pool->base.transforms[i] != NULL)
678 dce80_transform_destroy(&pool->base.transforms[i]);
679
680 if (pool->base.ipps[i] != NULL)
681 dce_ipp_destroy(&pool->base.ipps[i]);
682
683 if (pool->base.mis[i] != NULL) {
684 kfree(TO_DCE_MEM_INPUT(pool->base.mis[i]));
685 pool->base.mis[i] = NULL;
686 }
687
688 if (pool->base.timing_generators[i] != NULL) {
689 kfree(DCE110TG_FROM_TG(pool->base.timing_generators[i]));
690 pool->base.timing_generators[i] = NULL;
691 }
692
693 if (pool->base.engines[i] != NULL)
694 dce110_engine_destroy(&pool->base.engines[i]);
695 }
696
697 for (i = 0; i < pool->base.stream_enc_count; i++) {
698 if (pool->base.stream_enc[i] != NULL)
699 kfree(DCE110STRENC_FROM_STRENC(pool->base.stream_enc[i]));
700 }
701
702 for (i = 0; i < pool->base.clk_src_count; i++) {
703 if (pool->base.clock_sources[i] != NULL) {
704 dce80_clock_source_destroy(&pool->base.clock_sources[i]);
705 }
706 }
707
708 if (pool->base.abm != NULL)
709 dce_abm_destroy(&pool->base.abm);
710
711 if (pool->base.dmcu != NULL)
712 dce_dmcu_destroy(&pool->base.dmcu);
713
714 if (pool->base.dp_clock_source != NULL)
715 dce80_clock_source_destroy(&pool->base.dp_clock_source);
716
717 for (i = 0; i < pool->base.audio_count; i++) {
718 if (pool->base.audios[i] != NULL) {
719 dce_aud_destroy(&pool->base.audios[i]);
720 }
721 }
722
723 if (pool->base.dccg != NULL)
724 dce_dccg_destroy(&pool->base.dccg);
725
726 if (pool->base.irqs != NULL) {
727 dal_irq_service_destroy(&pool->base.irqs);
728 }
729 }
730
dce80_validate_bandwidth(struct dc * dc,struct dc_state * context)731 bool dce80_validate_bandwidth(
732 struct dc *dc,
733 struct dc_state *context)
734 {
735 /* TODO implement when needed but for now hardcode max value*/
736 context->bw.dce.dispclk_khz = 681000;
737 context->bw.dce.yclk_khz = 250000 * MEMORY_TYPE_MULTIPLIER;
738
739 return true;
740 }
741
dce80_validate_surface_sets(struct dc_state * context)742 static bool dce80_validate_surface_sets(
743 struct dc_state *context)
744 {
745 int i;
746
747 for (i = 0; i < context->stream_count; i++) {
748 if (context->stream_status[i].plane_count == 0)
749 continue;
750
751 if (context->stream_status[i].plane_count > 1)
752 return false;
753
754 if (context->stream_status[i].plane_states[0]->format
755 >= SURFACE_PIXEL_FORMAT_VIDEO_BEGIN)
756 return false;
757 }
758
759 return true;
760 }
761
dce80_validate_global(struct dc * dc,struct dc_state * context)762 enum dc_status dce80_validate_global(
763 struct dc *dc,
764 struct dc_state *context)
765 {
766 if (!dce80_validate_surface_sets(context))
767 return DC_FAIL_SURFACE_VALIDATE;
768
769 return DC_OK;
770 }
771
dce80_destroy_resource_pool(struct resource_pool ** pool)772 static void dce80_destroy_resource_pool(struct resource_pool **pool)
773 {
774 struct dce110_resource_pool *dce110_pool = TO_DCE110_RES_POOL(*pool);
775
776 destruct(dce110_pool);
777 kfree(dce110_pool);
778 *pool = NULL;
779 }
780
781 static const struct resource_funcs dce80_res_pool_funcs = {
782 .destroy = dce80_destroy_resource_pool,
783 .link_enc_create = dce80_link_encoder_create,
784 .validate_bandwidth = dce80_validate_bandwidth,
785 .validate_plane = dce100_validate_plane,
786 .add_stream_to_ctx = dce100_add_stream_to_ctx,
787 .validate_global = dce80_validate_global
788 };
789
dce80_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)790 static bool dce80_construct(
791 uint8_t num_virtual_links,
792 struct dc *dc,
793 struct dce110_resource_pool *pool)
794 {
795 unsigned int i;
796 struct dc_context *ctx = dc->ctx;
797 struct dc_firmware_info info;
798 struct dc_bios *bp;
799 struct dm_pp_static_clock_info static_clk_info = {0};
800
801 ctx->dc_bios->regs = &bios_regs;
802
803 pool->base.res_cap = &res_cap;
804 pool->base.funcs = &dce80_res_pool_funcs;
805
806
807 /*************************************************
808 * Resource + asic cap harcoding *
809 *************************************************/
810 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
811 pool->base.pipe_count = res_cap.num_timing_generator;
812 pool->base.timing_generator_count = res_cap.num_timing_generator;
813 dc->caps.max_downscale_ratio = 200;
814 dc->caps.i2c_speed_in_khz = 40;
815 dc->caps.max_cursor_size = 128;
816 dc->caps.dual_link_dvi = true;
817
818 /*************************************************
819 * Create resources *
820 *************************************************/
821
822 bp = ctx->dc_bios;
823
824 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
825 info.external_clock_source_frequency_for_dp != 0) {
826 pool->base.dp_clock_source =
827 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
828
829 pool->base.clock_sources[0] =
830 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
831 pool->base.clock_sources[1] =
832 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
833 pool->base.clock_sources[2] =
834 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
835 pool->base.clk_src_count = 3;
836
837 } else {
838 pool->base.dp_clock_source =
839 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
840
841 pool->base.clock_sources[0] =
842 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
843 pool->base.clock_sources[1] =
844 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
845 pool->base.clk_src_count = 2;
846 }
847
848 if (pool->base.dp_clock_source == NULL) {
849 dm_error("DC: failed to create dp clock source!\n");
850 BREAK_TO_DEBUGGER();
851 goto res_create_fail;
852 }
853
854 for (i = 0; i < pool->base.clk_src_count; i++) {
855 if (pool->base.clock_sources[i] == NULL) {
856 dm_error("DC: failed to create clock sources!\n");
857 BREAK_TO_DEBUGGER();
858 goto res_create_fail;
859 }
860 }
861
862 pool->base.dccg = dce_dccg_create(ctx,
863 &disp_clk_regs,
864 &disp_clk_shift,
865 &disp_clk_mask);
866 if (pool->base.dccg == NULL) {
867 dm_error("DC: failed to create display clock!\n");
868 BREAK_TO_DEBUGGER();
869 goto res_create_fail;
870 }
871
872 pool->base.dmcu = dce_dmcu_create(ctx,
873 &dmcu_regs,
874 &dmcu_shift,
875 &dmcu_mask);
876 if (pool->base.dmcu == NULL) {
877 dm_error("DC: failed to create dmcu!\n");
878 BREAK_TO_DEBUGGER();
879 goto res_create_fail;
880 }
881
882 pool->base.abm = dce_abm_create(ctx,
883 &abm_regs,
884 &abm_shift,
885 &abm_mask);
886 if (pool->base.abm == NULL) {
887 dm_error("DC: failed to create abm!\n");
888 BREAK_TO_DEBUGGER();
889 goto res_create_fail;
890 }
891 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
892 pool->base.dccg->max_clks_state =
893 static_clk_info.max_clocks_state;
894
895 {
896 struct irq_service_init_data init_data;
897 init_data.ctx = dc->ctx;
898 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
899 if (!pool->base.irqs)
900 goto res_create_fail;
901 }
902
903 for (i = 0; i < pool->base.pipe_count; i++) {
904 pool->base.timing_generators[i] = dce80_timing_generator_create(
905 ctx, i, &dce80_tg_offsets[i]);
906 if (pool->base.timing_generators[i] == NULL) {
907 BREAK_TO_DEBUGGER();
908 dm_error("DC: failed to create tg!\n");
909 goto res_create_fail;
910 }
911
912 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
913 if (pool->base.mis[i] == NULL) {
914 BREAK_TO_DEBUGGER();
915 dm_error("DC: failed to create memory input!\n");
916 goto res_create_fail;
917 }
918
919 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
920 if (pool->base.ipps[i] == NULL) {
921 BREAK_TO_DEBUGGER();
922 dm_error("DC: failed to create input pixel processor!\n");
923 goto res_create_fail;
924 }
925
926 pool->base.transforms[i] = dce80_transform_create(ctx, i);
927 if (pool->base.transforms[i] == NULL) {
928 BREAK_TO_DEBUGGER();
929 dm_error("DC: failed to create transform!\n");
930 goto res_create_fail;
931 }
932
933 pool->base.opps[i] = dce80_opp_create(ctx, i);
934 if (pool->base.opps[i] == NULL) {
935 BREAK_TO_DEBUGGER();
936 dm_error("DC: failed to create output pixel processor!\n");
937 goto res_create_fail;
938 }
939
940 pool->base.engines[i] = dce80_aux_engine_create(ctx, i);
941 if (pool->base.engines[i] == NULL) {
942 BREAK_TO_DEBUGGER();
943 dm_error(
944 "DC:failed to create aux engine!!\n");
945 goto res_create_fail;
946 }
947 }
948
949 dc->caps.max_planes = pool->base.pipe_count;
950 dc->caps.disable_dp_clk_share = true;
951
952 if (!resource_construct(num_virtual_links, dc, &pool->base,
953 &res_create_funcs))
954 goto res_create_fail;
955
956 /* Create hardware sequencer */
957 dce80_hw_sequencer_construct(dc);
958
959 return true;
960
961 res_create_fail:
962 destruct(pool);
963 return false;
964 }
965
dce80_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)966 struct resource_pool *dce80_create_resource_pool(
967 uint8_t num_virtual_links,
968 struct dc *dc)
969 {
970 struct dce110_resource_pool *pool =
971 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
972
973 if (!pool)
974 return NULL;
975
976 if (dce80_construct(num_virtual_links, dc, pool))
977 return &pool->base;
978
979 BREAK_TO_DEBUGGER();
980 return NULL;
981 }
982
dce81_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)983 static bool dce81_construct(
984 uint8_t num_virtual_links,
985 struct dc *dc,
986 struct dce110_resource_pool *pool)
987 {
988 unsigned int i;
989 struct dc_context *ctx = dc->ctx;
990 struct dc_firmware_info info;
991 struct dc_bios *bp;
992 struct dm_pp_static_clock_info static_clk_info = {0};
993
994 ctx->dc_bios->regs = &bios_regs;
995
996 pool->base.res_cap = &res_cap_81;
997 pool->base.funcs = &dce80_res_pool_funcs;
998
999
1000 /*************************************************
1001 * Resource + asic cap harcoding *
1002 *************************************************/
1003 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1004 pool->base.pipe_count = res_cap_81.num_timing_generator;
1005 pool->base.timing_generator_count = res_cap_81.num_timing_generator;
1006 dc->caps.max_downscale_ratio = 200;
1007 dc->caps.i2c_speed_in_khz = 40;
1008 dc->caps.max_cursor_size = 128;
1009 dc->caps.is_apu = true;
1010
1011 /*************************************************
1012 * Create resources *
1013 *************************************************/
1014
1015 bp = ctx->dc_bios;
1016
1017 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1018 info.external_clock_source_frequency_for_dp != 0) {
1019 pool->base.dp_clock_source =
1020 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1021
1022 pool->base.clock_sources[0] =
1023 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], false);
1024 pool->base.clock_sources[1] =
1025 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1026 pool->base.clock_sources[2] =
1027 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1028 pool->base.clk_src_count = 3;
1029
1030 } else {
1031 pool->base.dp_clock_source =
1032 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL0, &clk_src_regs[0], true);
1033
1034 pool->base.clock_sources[0] =
1035 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[1], false);
1036 pool->base.clock_sources[1] =
1037 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[2], false);
1038 pool->base.clk_src_count = 2;
1039 }
1040
1041 if (pool->base.dp_clock_source == NULL) {
1042 dm_error("DC: failed to create dp clock source!\n");
1043 BREAK_TO_DEBUGGER();
1044 goto res_create_fail;
1045 }
1046
1047 for (i = 0; i < pool->base.clk_src_count; i++) {
1048 if (pool->base.clock_sources[i] == NULL) {
1049 dm_error("DC: failed to create clock sources!\n");
1050 BREAK_TO_DEBUGGER();
1051 goto res_create_fail;
1052 }
1053 }
1054
1055 pool->base.dccg = dce_dccg_create(ctx,
1056 &disp_clk_regs,
1057 &disp_clk_shift,
1058 &disp_clk_mask);
1059 if (pool->base.dccg == NULL) {
1060 dm_error("DC: failed to create display clock!\n");
1061 BREAK_TO_DEBUGGER();
1062 goto res_create_fail;
1063 }
1064
1065 pool->base.dmcu = dce_dmcu_create(ctx,
1066 &dmcu_regs,
1067 &dmcu_shift,
1068 &dmcu_mask);
1069 if (pool->base.dmcu == NULL) {
1070 dm_error("DC: failed to create dmcu!\n");
1071 BREAK_TO_DEBUGGER();
1072 goto res_create_fail;
1073 }
1074
1075 pool->base.abm = dce_abm_create(ctx,
1076 &abm_regs,
1077 &abm_shift,
1078 &abm_mask);
1079 if (pool->base.abm == NULL) {
1080 dm_error("DC: failed to create abm!\n");
1081 BREAK_TO_DEBUGGER();
1082 goto res_create_fail;
1083 }
1084
1085 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1086 pool->base.dccg->max_clks_state =
1087 static_clk_info.max_clocks_state;
1088
1089 {
1090 struct irq_service_init_data init_data;
1091 init_data.ctx = dc->ctx;
1092 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1093 if (!pool->base.irqs)
1094 goto res_create_fail;
1095 }
1096
1097 for (i = 0; i < pool->base.pipe_count; i++) {
1098 pool->base.timing_generators[i] = dce80_timing_generator_create(
1099 ctx, i, &dce80_tg_offsets[i]);
1100 if (pool->base.timing_generators[i] == NULL) {
1101 BREAK_TO_DEBUGGER();
1102 dm_error("DC: failed to create tg!\n");
1103 goto res_create_fail;
1104 }
1105
1106 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1107 if (pool->base.mis[i] == NULL) {
1108 BREAK_TO_DEBUGGER();
1109 dm_error("DC: failed to create memory input!\n");
1110 goto res_create_fail;
1111 }
1112
1113 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1114 if (pool->base.ipps[i] == NULL) {
1115 BREAK_TO_DEBUGGER();
1116 dm_error("DC: failed to create input pixel processor!\n");
1117 goto res_create_fail;
1118 }
1119
1120 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1121 if (pool->base.transforms[i] == NULL) {
1122 BREAK_TO_DEBUGGER();
1123 dm_error("DC: failed to create transform!\n");
1124 goto res_create_fail;
1125 }
1126
1127 pool->base.opps[i] = dce80_opp_create(ctx, i);
1128 if (pool->base.opps[i] == NULL) {
1129 BREAK_TO_DEBUGGER();
1130 dm_error("DC: failed to create output pixel processor!\n");
1131 goto res_create_fail;
1132 }
1133 }
1134
1135 dc->caps.max_planes = pool->base.pipe_count;
1136 dc->caps.disable_dp_clk_share = true;
1137
1138 if (!resource_construct(num_virtual_links, dc, &pool->base,
1139 &res_create_funcs))
1140 goto res_create_fail;
1141
1142 /* Create hardware sequencer */
1143 dce80_hw_sequencer_construct(dc);
1144
1145 return true;
1146
1147 res_create_fail:
1148 destruct(pool);
1149 return false;
1150 }
1151
dce81_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1152 struct resource_pool *dce81_create_resource_pool(
1153 uint8_t num_virtual_links,
1154 struct dc *dc)
1155 {
1156 struct dce110_resource_pool *pool =
1157 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1158
1159 if (!pool)
1160 return NULL;
1161
1162 if (dce81_construct(num_virtual_links, dc, pool))
1163 return &pool->base;
1164
1165 BREAK_TO_DEBUGGER();
1166 return NULL;
1167 }
1168
dce83_construct(uint8_t num_virtual_links,struct dc * dc,struct dce110_resource_pool * pool)1169 static bool dce83_construct(
1170 uint8_t num_virtual_links,
1171 struct dc *dc,
1172 struct dce110_resource_pool *pool)
1173 {
1174 unsigned int i;
1175 struct dc_context *ctx = dc->ctx;
1176 struct dc_firmware_info info;
1177 struct dc_bios *bp;
1178 struct dm_pp_static_clock_info static_clk_info = {0};
1179
1180 ctx->dc_bios->regs = &bios_regs;
1181
1182 pool->base.res_cap = &res_cap_83;
1183 pool->base.funcs = &dce80_res_pool_funcs;
1184
1185
1186 /*************************************************
1187 * Resource + asic cap harcoding *
1188 *************************************************/
1189 pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
1190 pool->base.pipe_count = res_cap_83.num_timing_generator;
1191 pool->base.timing_generator_count = res_cap_83.num_timing_generator;
1192 dc->caps.max_downscale_ratio = 200;
1193 dc->caps.i2c_speed_in_khz = 40;
1194 dc->caps.max_cursor_size = 128;
1195 dc->caps.is_apu = true;
1196
1197 /*************************************************
1198 * Create resources *
1199 *************************************************/
1200
1201 bp = ctx->dc_bios;
1202
1203 if ((bp->funcs->get_firmware_info(bp, &info) == BP_RESULT_OK) &&
1204 info.external_clock_source_frequency_for_dp != 0) {
1205 pool->base.dp_clock_source =
1206 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_EXTERNAL, NULL, true);
1207
1208 pool->base.clock_sources[0] =
1209 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], false);
1210 pool->base.clock_sources[1] =
1211 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1212 pool->base.clk_src_count = 2;
1213
1214 } else {
1215 pool->base.dp_clock_source =
1216 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL1, &clk_src_regs[0], true);
1217
1218 pool->base.clock_sources[0] =
1219 dce80_clock_source_create(ctx, bp, CLOCK_SOURCE_ID_PLL2, &clk_src_regs[1], false);
1220 pool->base.clk_src_count = 1;
1221 }
1222
1223 if (pool->base.dp_clock_source == NULL) {
1224 dm_error("DC: failed to create dp clock source!\n");
1225 BREAK_TO_DEBUGGER();
1226 goto res_create_fail;
1227 }
1228
1229 for (i = 0; i < pool->base.clk_src_count; i++) {
1230 if (pool->base.clock_sources[i] == NULL) {
1231 dm_error("DC: failed to create clock sources!\n");
1232 BREAK_TO_DEBUGGER();
1233 goto res_create_fail;
1234 }
1235 }
1236
1237 pool->base.dccg = dce_dccg_create(ctx,
1238 &disp_clk_regs,
1239 &disp_clk_shift,
1240 &disp_clk_mask);
1241 if (pool->base.dccg == NULL) {
1242 dm_error("DC: failed to create display clock!\n");
1243 BREAK_TO_DEBUGGER();
1244 goto res_create_fail;
1245 }
1246
1247 pool->base.dmcu = dce_dmcu_create(ctx,
1248 &dmcu_regs,
1249 &dmcu_shift,
1250 &dmcu_mask);
1251 if (pool->base.dmcu == NULL) {
1252 dm_error("DC: failed to create dmcu!\n");
1253 BREAK_TO_DEBUGGER();
1254 goto res_create_fail;
1255 }
1256
1257 pool->base.abm = dce_abm_create(ctx,
1258 &abm_regs,
1259 &abm_shift,
1260 &abm_mask);
1261 if (pool->base.abm == NULL) {
1262 dm_error("DC: failed to create abm!\n");
1263 BREAK_TO_DEBUGGER();
1264 goto res_create_fail;
1265 }
1266
1267 if (dm_pp_get_static_clocks(ctx, &static_clk_info))
1268 pool->base.dccg->max_clks_state =
1269 static_clk_info.max_clocks_state;
1270
1271 {
1272 struct irq_service_init_data init_data;
1273 init_data.ctx = dc->ctx;
1274 pool->base.irqs = dal_irq_service_dce80_create(&init_data);
1275 if (!pool->base.irqs)
1276 goto res_create_fail;
1277 }
1278
1279 for (i = 0; i < pool->base.pipe_count; i++) {
1280 pool->base.timing_generators[i] = dce80_timing_generator_create(
1281 ctx, i, &dce80_tg_offsets[i]);
1282 if (pool->base.timing_generators[i] == NULL) {
1283 BREAK_TO_DEBUGGER();
1284 dm_error("DC: failed to create tg!\n");
1285 goto res_create_fail;
1286 }
1287
1288 pool->base.mis[i] = dce80_mem_input_create(ctx, i);
1289 if (pool->base.mis[i] == NULL) {
1290 BREAK_TO_DEBUGGER();
1291 dm_error("DC: failed to create memory input!\n");
1292 goto res_create_fail;
1293 }
1294
1295 pool->base.ipps[i] = dce80_ipp_create(ctx, i);
1296 if (pool->base.ipps[i] == NULL) {
1297 BREAK_TO_DEBUGGER();
1298 dm_error("DC: failed to create input pixel processor!\n");
1299 goto res_create_fail;
1300 }
1301
1302 pool->base.transforms[i] = dce80_transform_create(ctx, i);
1303 if (pool->base.transforms[i] == NULL) {
1304 BREAK_TO_DEBUGGER();
1305 dm_error("DC: failed to create transform!\n");
1306 goto res_create_fail;
1307 }
1308
1309 pool->base.opps[i] = dce80_opp_create(ctx, i);
1310 if (pool->base.opps[i] == NULL) {
1311 BREAK_TO_DEBUGGER();
1312 dm_error("DC: failed to create output pixel processor!\n");
1313 goto res_create_fail;
1314 }
1315 }
1316
1317 dc->caps.max_planes = pool->base.pipe_count;
1318 dc->caps.disable_dp_clk_share = true;
1319
1320 if (!resource_construct(num_virtual_links, dc, &pool->base,
1321 &res_create_funcs))
1322 goto res_create_fail;
1323
1324 /* Create hardware sequencer */
1325 dce80_hw_sequencer_construct(dc);
1326
1327 return true;
1328
1329 res_create_fail:
1330 destruct(pool);
1331 return false;
1332 }
1333
dce83_create_resource_pool(uint8_t num_virtual_links,struct dc * dc)1334 struct resource_pool *dce83_create_resource_pool(
1335 uint8_t num_virtual_links,
1336 struct dc *dc)
1337 {
1338 struct dce110_resource_pool *pool =
1339 kzalloc(sizeof(struct dce110_resource_pool), GFP_KERNEL);
1340
1341 if (!pool)
1342 return NULL;
1343
1344 if (dce83_construct(num_virtual_links, dc, pool))
1345 return &pool->base;
1346
1347 BREAK_TO_DEBUGGER();
1348 return NULL;
1349 }
1350