1 /*
2 * Copyright(c) 2016, Analogix Semiconductor.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * Based on anx7808 driver obtained from chromeos with copyright:
14 * Copyright(c) 2013, Google Inc.
15 *
16 */
17 #include <linux/delay.h>
18 #include <linux/err.h>
19 #include <linux/interrupt.h>
20 #include <linux/i2c.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/of_gpio.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_platform.h>
26 #include <linux/regmap.h>
27 #include <linux/types.h>
28 #include <linux/gpio/consumer.h>
29 #include <linux/regulator/consumer.h>
30
31 #include <drm/drmP.h>
32 #include <drm/drm_atomic_helper.h>
33 #include <drm/drm_crtc.h>
34 #include <drm/drm_crtc_helper.h>
35 #include <drm/drm_dp_helper.h>
36 #include <drm/drm_edid.h>
37
38 #include "analogix-anx78xx.h"
39
40 #define I2C_NUM_ADDRESSES 5
41 #define I2C_IDX_TX_P0 0
42 #define I2C_IDX_TX_P1 1
43 #define I2C_IDX_TX_P2 2
44 #define I2C_IDX_RX_P0 3
45 #define I2C_IDX_RX_P1 4
46
47 #define XTAL_CLK 270 /* 27M */
48 #define AUX_CH_BUFFER_SIZE 16
49 #define AUX_WAIT_TIMEOUT_MS 15
50
51 static const u8 anx78xx_i2c_addresses[] = {
52 [I2C_IDX_TX_P0] = TX_P0,
53 [I2C_IDX_TX_P1] = TX_P1,
54 [I2C_IDX_TX_P2] = TX_P2,
55 [I2C_IDX_RX_P0] = RX_P0,
56 [I2C_IDX_RX_P1] = RX_P1,
57 };
58
59 struct anx78xx_platform_data {
60 struct regulator *dvdd10;
61 struct gpio_desc *gpiod_hpd;
62 struct gpio_desc *gpiod_pd;
63 struct gpio_desc *gpiod_reset;
64
65 int hpd_irq;
66 int intp_irq;
67 };
68
69 struct anx78xx {
70 struct drm_dp_aux aux;
71 struct drm_bridge bridge;
72 struct i2c_client *client;
73 struct edid *edid;
74 struct drm_connector connector;
75 struct drm_dp_link link;
76 struct anx78xx_platform_data pdata;
77 struct mutex lock;
78
79 /*
80 * I2C Slave addresses of ANX7814 are mapped as TX_P0, TX_P1, TX_P2,
81 * RX_P0 and RX_P1.
82 */
83 struct i2c_client *i2c_dummy[I2C_NUM_ADDRESSES];
84 struct regmap *map[I2C_NUM_ADDRESSES];
85
86 u16 chipid;
87 u8 dpcd[DP_RECEIVER_CAP_SIZE];
88
89 bool powered;
90 };
91
connector_to_anx78xx(struct drm_connector * c)92 static inline struct anx78xx *connector_to_anx78xx(struct drm_connector *c)
93 {
94 return container_of(c, struct anx78xx, connector);
95 }
96
bridge_to_anx78xx(struct drm_bridge * bridge)97 static inline struct anx78xx *bridge_to_anx78xx(struct drm_bridge *bridge)
98 {
99 return container_of(bridge, struct anx78xx, bridge);
100 }
101
anx78xx_set_bits(struct regmap * map,u8 reg,u8 mask)102 static int anx78xx_set_bits(struct regmap *map, u8 reg, u8 mask)
103 {
104 return regmap_update_bits(map, reg, mask, mask);
105 }
106
anx78xx_clear_bits(struct regmap * map,u8 reg,u8 mask)107 static int anx78xx_clear_bits(struct regmap *map, u8 reg, u8 mask)
108 {
109 return regmap_update_bits(map, reg, mask, 0);
110 }
111
anx78xx_aux_op_finished(struct anx78xx * anx78xx)112 static bool anx78xx_aux_op_finished(struct anx78xx *anx78xx)
113 {
114 unsigned int value;
115 int err;
116
117 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
118 &value);
119 if (err < 0)
120 return false;
121
122 return (value & SP_AUX_EN) == 0;
123 }
124
anx78xx_aux_wait(struct anx78xx * anx78xx)125 static int anx78xx_aux_wait(struct anx78xx *anx78xx)
126 {
127 unsigned long timeout;
128 unsigned int status;
129 int err;
130
131 timeout = jiffies + msecs_to_jiffies(AUX_WAIT_TIMEOUT_MS) + 1;
132
133 while (!anx78xx_aux_op_finished(anx78xx)) {
134 if (time_after(jiffies, timeout)) {
135 if (!anx78xx_aux_op_finished(anx78xx)) {
136 DRM_ERROR("Timed out waiting AUX to finish\n");
137 return -ETIMEDOUT;
138 }
139
140 break;
141 }
142
143 usleep_range(1000, 2000);
144 }
145
146 /* Read the AUX channel access status */
147 err = regmap_read(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_CH_STATUS_REG,
148 &status);
149 if (err < 0) {
150 DRM_ERROR("Failed to read from AUX channel: %d\n", err);
151 return err;
152 }
153
154 if (status & SP_AUX_STATUS) {
155 DRM_ERROR("Failed to wait for AUX channel (status: %02x)\n",
156 status);
157 return -ETIMEDOUT;
158 }
159
160 return 0;
161 }
162
anx78xx_aux_address(struct anx78xx * anx78xx,unsigned int addr)163 static int anx78xx_aux_address(struct anx78xx *anx78xx, unsigned int addr)
164 {
165 int err;
166
167 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_7_0_REG,
168 addr & 0xff);
169 if (err)
170 return err;
171
172 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_ADDR_15_8_REG,
173 (addr & 0xff00) >> 8);
174 if (err)
175 return err;
176
177 /*
178 * DP AUX CH Address Register #2, only update bits[3:0]
179 * [7:4] RESERVED
180 * [3:0] AUX_ADDR[19:16], Register control AUX CH address.
181 */
182 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
183 SP_AUX_ADDR_19_16_REG,
184 SP_AUX_ADDR_19_16_MASK,
185 (addr & 0xf0000) >> 16);
186
187 if (err)
188 return err;
189
190 return 0;
191 }
192
anx78xx_aux_transfer(struct drm_dp_aux * aux,struct drm_dp_aux_msg * msg)193 static ssize_t anx78xx_aux_transfer(struct drm_dp_aux *aux,
194 struct drm_dp_aux_msg *msg)
195 {
196 struct anx78xx *anx78xx = container_of(aux, struct anx78xx, aux);
197 u8 ctrl1 = msg->request;
198 u8 ctrl2 = SP_AUX_EN;
199 u8 *buffer = msg->buffer;
200 int err;
201
202 /* The DP AUX transmit and receive buffer has 16 bytes. */
203 if (WARN_ON(msg->size > AUX_CH_BUFFER_SIZE))
204 return -E2BIG;
205
206 /* Zero-sized messages specify address-only transactions. */
207 if (msg->size < 1)
208 ctrl2 |= SP_ADDR_ONLY;
209 else /* For non-zero-sized set the length field. */
210 ctrl1 |= (msg->size - 1) << SP_AUX_LENGTH_SHIFT;
211
212 if ((msg->request & DP_AUX_I2C_READ) == 0) {
213 /* When WRITE | MOT write values to data buffer */
214 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P0],
215 SP_DP_BUF_DATA0_REG, buffer,
216 msg->size);
217 if (err)
218 return err;
219 }
220
221 /* Write address and request */
222 err = anx78xx_aux_address(anx78xx, msg->address);
223 if (err)
224 return err;
225
226 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL1_REG,
227 ctrl1);
228 if (err)
229 return err;
230
231 /* Start transaction */
232 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P0],
233 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY |
234 SP_AUX_EN, ctrl2);
235 if (err)
236 return err;
237
238 err = anx78xx_aux_wait(anx78xx);
239 if (err)
240 return err;
241
242 msg->reply = DP_AUX_I2C_REPLY_ACK;
243
244 if ((msg->size > 0) && (msg->request & DP_AUX_I2C_READ)) {
245 /* Read values from data buffer */
246 err = regmap_bulk_read(anx78xx->map[I2C_IDX_TX_P0],
247 SP_DP_BUF_DATA0_REG, buffer,
248 msg->size);
249 if (err)
250 return err;
251 }
252
253 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
254 SP_DP_AUX_CH_CTRL2_REG, SP_ADDR_ONLY);
255 if (err)
256 return err;
257
258 return msg->size;
259 }
260
anx78xx_set_hpd(struct anx78xx * anx78xx)261 static int anx78xx_set_hpd(struct anx78xx *anx78xx)
262 {
263 int err;
264
265 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
266 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
267 if (err)
268 return err;
269
270 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
271 SP_HPD_OUT);
272 if (err)
273 return err;
274
275 return 0;
276 }
277
anx78xx_clear_hpd(struct anx78xx * anx78xx)278 static int anx78xx_clear_hpd(struct anx78xx *anx78xx)
279 {
280 int err;
281
282 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL3_REG,
283 SP_HPD_OUT);
284 if (err)
285 return err;
286
287 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
288 SP_TMDS_CTRL_BASE + 7, SP_PD_RT);
289 if (err)
290 return err;
291
292 return 0;
293 }
294
295 static const struct reg_sequence tmds_phy_initialization[] = {
296 { SP_TMDS_CTRL_BASE + 1, 0x90 },
297 { SP_TMDS_CTRL_BASE + 2, 0xa9 },
298 { SP_TMDS_CTRL_BASE + 6, 0x92 },
299 { SP_TMDS_CTRL_BASE + 7, 0x80 },
300 { SP_TMDS_CTRL_BASE + 20, 0xf2 },
301 { SP_TMDS_CTRL_BASE + 22, 0xc4 },
302 { SP_TMDS_CTRL_BASE + 23, 0x18 },
303 };
304
anx78xx_rx_initialization(struct anx78xx * anx78xx)305 static int anx78xx_rx_initialization(struct anx78xx *anx78xx)
306 {
307 int err;
308
309 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
310 SP_AUD_MUTE | SP_VID_MUTE);
311 if (err)
312 return err;
313
314 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_CHIP_CTRL_REG,
315 SP_MAN_HDMI5V_DET | SP_PLLLOCK_CKDT_EN |
316 SP_DIGITAL_CKDT_EN);
317 if (err)
318 return err;
319
320 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
321 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
322 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
323 if (err)
324 return err;
325
326 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
327 SP_SOFTWARE_RESET1_REG, SP_HDCP_MAN_RST |
328 SP_SW_MAN_RST | SP_TMDS_RST | SP_VIDEO_RST);
329 if (err)
330 return err;
331
332 /* Sync detect change, GP set mute */
333 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
334 SP_AUD_EXCEPTION_ENABLE_BASE + 1, BIT(5) |
335 BIT(6));
336 if (err)
337 return err;
338
339 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
340 SP_AUD_EXCEPTION_ENABLE_BASE + 3,
341 SP_AEC_EN21);
342 if (err)
343 return err;
344
345 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0], SP_AUDVID_CTRL_REG,
346 SP_AVC_EN | SP_AAC_OE | SP_AAC_EN);
347 if (err)
348 return err;
349
350 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_RX_P0],
351 SP_SYSTEM_POWER_DOWN1_REG, SP_PWDN_CTRL);
352 if (err)
353 return err;
354
355 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_RX_P0],
356 SP_VID_DATA_RANGE_CTRL_REG, SP_R2Y_INPUT_LIMIT);
357 if (err)
358 return err;
359
360 /* Enable DDC stretch */
361 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
362 SP_DP_EXTRA_I2C_DEV_ADDR_REG, SP_I2C_EXTRA_ADDR);
363 if (err)
364 return err;
365
366 /* TMDS phy initialization */
367 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_RX_P0],
368 tmds_phy_initialization,
369 ARRAY_SIZE(tmds_phy_initialization));
370 if (err)
371 return err;
372
373 err = anx78xx_clear_hpd(anx78xx);
374 if (err)
375 return err;
376
377 return 0;
378 }
379
380 static const u8 dp_tx_output_precise_tune_bits[20] = {
381 0x01, 0x03, 0x07, 0x7f, 0x71, 0x6b, 0x7f,
382 0x73, 0x7f, 0x7f, 0x00, 0x00, 0x00, 0x00,
383 0x0c, 0x42, 0x1e, 0x3e, 0x72, 0x7e,
384 };
385
anx78xx_link_phy_initialization(struct anx78xx * anx78xx)386 static int anx78xx_link_phy_initialization(struct anx78xx *anx78xx)
387 {
388 int err;
389
390 /*
391 * REVISIT : It is writing to a RESERVED bits in Analog Control 0
392 * register.
393 */
394 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_ANALOG_CTRL0_REG,
395 0x02);
396 if (err)
397 return err;
398
399 /*
400 * Write DP TX output emphasis precise tune bits.
401 */
402 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P1],
403 SP_DP_TX_LT_CTRL0_REG,
404 dp_tx_output_precise_tune_bits,
405 ARRAY_SIZE(dp_tx_output_precise_tune_bits));
406
407 if (err)
408 return err;
409
410 return 0;
411 }
412
anx78xx_xtal_clk_sel(struct anx78xx * anx78xx)413 static int anx78xx_xtal_clk_sel(struct anx78xx *anx78xx)
414 {
415 unsigned int value;
416 int err;
417
418 err = regmap_update_bits(anx78xx->map[I2C_IDX_TX_P2],
419 SP_ANALOG_DEBUG2_REG,
420 SP_XTAL_FRQ | SP_FORCE_SW_OFF_BYPASS,
421 SP_XTAL_FRQ_27M);
422 if (err)
423 return err;
424
425 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL3_REG,
426 XTAL_CLK & SP_WAIT_COUNTER_7_0_MASK);
427 if (err)
428 return err;
429
430 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL4_REG,
431 ((XTAL_CLK & 0xff00) >> 2) | (XTAL_CLK / 10));
432 if (err)
433 return err;
434
435 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
436 SP_I2C_GEN_10US_TIMER0_REG, XTAL_CLK & 0xff);
437 if (err)
438 return err;
439
440 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
441 SP_I2C_GEN_10US_TIMER1_REG,
442 (XTAL_CLK & 0xff00) >> 8);
443 if (err)
444 return err;
445
446 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_MISC_CTRL_REG,
447 XTAL_CLK / 10 - 1);
448 if (err)
449 return err;
450
451 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
452 SP_HDMI_US_TIMER_CTRL_REG,
453 &value);
454 if (err)
455 return err;
456
457 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0],
458 SP_HDMI_US_TIMER_CTRL_REG,
459 (value & SP_MS_TIMER_MARGIN_10_8_MASK) |
460 ((((XTAL_CLK / 10) >> 1) - 2) << 3));
461 if (err)
462 return err;
463
464 return 0;
465 }
466
467 static const struct reg_sequence otp_key_protect[] = {
468 { SP_OTP_KEY_PROTECT1_REG, SP_OTP_PSW1 },
469 { SP_OTP_KEY_PROTECT2_REG, SP_OTP_PSW2 },
470 { SP_OTP_KEY_PROTECT3_REG, SP_OTP_PSW3 },
471 };
472
anx78xx_tx_initialization(struct anx78xx * anx78xx)473 static int anx78xx_tx_initialization(struct anx78xx *anx78xx)
474 {
475 int err;
476
477 /* Set terminal resistor to 50 ohm */
478 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_AUX_CH_CTRL2_REG,
479 0x30);
480 if (err)
481 return err;
482
483 /* Enable aux double diff output */
484 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
485 SP_DP_AUX_CH_CTRL2_REG, 0x08);
486 if (err)
487 return err;
488
489 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
490 SP_DP_HDCP_CTRL_REG, SP_AUTO_EN |
491 SP_AUTO_START);
492 if (err)
493 return err;
494
495 err = regmap_multi_reg_write(anx78xx->map[I2C_IDX_TX_P0],
496 otp_key_protect,
497 ARRAY_SIZE(otp_key_protect));
498 if (err)
499 return err;
500
501 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
502 SP_HDCP_KEY_COMMAND_REG, SP_DISABLE_SYNC_HDCP);
503 if (err)
504 return err;
505
506 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL8_REG,
507 SP_VID_VRES_TH);
508 if (err)
509 return err;
510
511 /*
512 * DP HDCP auto authentication wait timer (when downstream starts to
513 * auth, DP side will wait for this period then do auth automatically)
514 */
515 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_HDCP_AUTO_TIMER_REG,
516 0x00);
517 if (err)
518 return err;
519
520 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
521 SP_DP_HDCP_CTRL_REG, SP_LINK_POLLING);
522 if (err)
523 return err;
524
525 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
526 SP_DP_LINK_DEBUG_CTRL_REG, SP_M_VID_DEBUG);
527 if (err)
528 return err;
529
530 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2],
531 SP_ANALOG_DEBUG2_REG, SP_POWERON_TIME_1P5MS);
532 if (err)
533 return err;
534
535 err = anx78xx_xtal_clk_sel(anx78xx);
536 if (err)
537 return err;
538
539 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_AUX_DEFER_CTRL_REG,
540 SP_DEFER_CTRL_EN | 0x0c);
541 if (err)
542 return err;
543
544 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
545 SP_DP_POLLING_CTRL_REG,
546 SP_AUTO_POLLING_DISABLE);
547 if (err)
548 return err;
549
550 /*
551 * Short the link integrity check timer to speed up bstatus
552 * polling for HDCP CTS item 1A-07
553 */
554 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
555 SP_HDCP_LINK_CHECK_TIMER_REG, 0x1d);
556 if (err)
557 return err;
558
559 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
560 SP_DP_MISC_CTRL_REG, SP_EQ_TRAINING_LOOP);
561 if (err)
562 return err;
563
564 /* Power down the main link by default */
565 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
566 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
567 if (err)
568 return err;
569
570 err = anx78xx_link_phy_initialization(anx78xx);
571 if (err)
572 return err;
573
574 /* Gen m_clk with downspreading */
575 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
576 SP_DP_M_CALCULATION_CTRL_REG, SP_M_GEN_CLK_SEL);
577 if (err)
578 return err;
579
580 return 0;
581 }
582
anx78xx_enable_interrupts(struct anx78xx * anx78xx)583 static int anx78xx_enable_interrupts(struct anx78xx *anx78xx)
584 {
585 int err;
586
587 /*
588 * BIT0: INT pin assertion polarity: 1 = assert high
589 * BIT1: INT pin output type: 0 = push/pull
590 */
591 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_INT_CTRL_REG, 0x01);
592 if (err)
593 return err;
594
595 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
596 SP_COMMON_INT_MASK4_REG, SP_HPD_LOST | SP_HPD_PLUG);
597 if (err)
598 return err;
599
600 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_MASK1_REG,
601 SP_TRAINING_FINISH);
602 if (err)
603 return err;
604
605 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_MASK1_REG,
606 SP_CKDT_CHG | SP_SCDT_CHG);
607 if (err)
608 return err;
609
610 return 0;
611 }
612
anx78xx_poweron(struct anx78xx * anx78xx)613 static void anx78xx_poweron(struct anx78xx *anx78xx)
614 {
615 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
616 int err;
617
618 if (WARN_ON(anx78xx->powered))
619 return;
620
621 if (pdata->dvdd10) {
622 err = regulator_enable(pdata->dvdd10);
623 if (err) {
624 DRM_ERROR("Failed to enable DVDD10 regulator: %d\n",
625 err);
626 return;
627 }
628
629 usleep_range(1000, 2000);
630 }
631
632 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
633 usleep_range(1000, 2000);
634
635 gpiod_set_value_cansleep(pdata->gpiod_pd, 0);
636 usleep_range(1000, 2000);
637
638 gpiod_set_value_cansleep(pdata->gpiod_reset, 0);
639
640 /* Power on registers module */
641 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
642 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
643 anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
644 SP_REGISTER_PD | SP_TOTAL_PD);
645
646 anx78xx->powered = true;
647 }
648
anx78xx_poweroff(struct anx78xx * anx78xx)649 static void anx78xx_poweroff(struct anx78xx *anx78xx)
650 {
651 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
652 int err;
653
654 if (WARN_ON(!anx78xx->powered))
655 return;
656
657 gpiod_set_value_cansleep(pdata->gpiod_reset, 1);
658 usleep_range(1000, 2000);
659
660 gpiod_set_value_cansleep(pdata->gpiod_pd, 1);
661 usleep_range(1000, 2000);
662
663 if (pdata->dvdd10) {
664 err = regulator_disable(pdata->dvdd10);
665 if (err) {
666 DRM_ERROR("Failed to disable DVDD10 regulator: %d\n",
667 err);
668 return;
669 }
670
671 usleep_range(1000, 2000);
672 }
673
674 anx78xx->powered = false;
675 }
676
anx78xx_start(struct anx78xx * anx78xx)677 static int anx78xx_start(struct anx78xx *anx78xx)
678 {
679 int err;
680
681 /* Power on all modules */
682 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
683 SP_POWERDOWN_CTRL_REG,
684 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD |
685 SP_LINK_PD);
686
687 err = anx78xx_enable_interrupts(anx78xx);
688 if (err) {
689 DRM_ERROR("Failed to enable interrupts: %d\n", err);
690 goto err_poweroff;
691 }
692
693 err = anx78xx_rx_initialization(anx78xx);
694 if (err) {
695 DRM_ERROR("Failed receiver initialization: %d\n", err);
696 goto err_poweroff;
697 }
698
699 err = anx78xx_tx_initialization(anx78xx);
700 if (err) {
701 DRM_ERROR("Failed transmitter initialization: %d\n", err);
702 goto err_poweroff;
703 }
704
705 /*
706 * This delay seems to help keep the hardware in a good state. Without
707 * it, there are times where it fails silently.
708 */
709 usleep_range(10000, 15000);
710
711 return 0;
712
713 err_poweroff:
714 DRM_ERROR("Failed SlimPort transmitter initialization: %d\n", err);
715 anx78xx_poweroff(anx78xx);
716
717 return err;
718 }
719
anx78xx_init_pdata(struct anx78xx * anx78xx)720 static int anx78xx_init_pdata(struct anx78xx *anx78xx)
721 {
722 struct anx78xx_platform_data *pdata = &anx78xx->pdata;
723 struct device *dev = &anx78xx->client->dev;
724
725 /* 1.0V digital core power regulator */
726 pdata->dvdd10 = devm_regulator_get(dev, "dvdd10");
727 if (IS_ERR(pdata->dvdd10)) {
728 if (PTR_ERR(pdata->dvdd10) != -EPROBE_DEFER)
729 DRM_ERROR("DVDD10 regulator not found\n");
730
731 return PTR_ERR(pdata->dvdd10);
732 }
733
734 /* GPIO for HPD */
735 pdata->gpiod_hpd = devm_gpiod_get(dev, "hpd", GPIOD_IN);
736 if (IS_ERR(pdata->gpiod_hpd))
737 return PTR_ERR(pdata->gpiod_hpd);
738
739 /* GPIO for chip power down */
740 pdata->gpiod_pd = devm_gpiod_get(dev, "pd", GPIOD_OUT_HIGH);
741 if (IS_ERR(pdata->gpiod_pd))
742 return PTR_ERR(pdata->gpiod_pd);
743
744 /* GPIO for chip reset */
745 pdata->gpiod_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW);
746
747 return PTR_ERR_OR_ZERO(pdata->gpiod_reset);
748 }
749
anx78xx_dp_link_training(struct anx78xx * anx78xx)750 static int anx78xx_dp_link_training(struct anx78xx *anx78xx)
751 {
752 u8 dp_bw, value;
753 int err;
754
755 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_HDMI_MUTE_CTRL_REG,
756 0x0);
757 if (err)
758 return err;
759
760 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
761 SP_POWERDOWN_CTRL_REG,
762 SP_TOTAL_PD);
763 if (err)
764 return err;
765
766 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_MAX_LINK_RATE, &dp_bw);
767 if (err < 0)
768 return err;
769
770 switch (dp_bw) {
771 case DP_LINK_BW_1_62:
772 case DP_LINK_BW_2_7:
773 case DP_LINK_BW_5_4:
774 break;
775
776 default:
777 DRM_DEBUG_KMS("DP bandwidth (%#02x) not supported\n", dp_bw);
778 return -EINVAL;
779 }
780
781 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
782 SP_VIDEO_MUTE);
783 if (err)
784 return err;
785
786 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2],
787 SP_VID_CTRL1_REG, SP_VIDEO_EN);
788 if (err)
789 return err;
790
791 /* Get DPCD info */
792 err = drm_dp_dpcd_read(&anx78xx->aux, DP_DPCD_REV,
793 &anx78xx->dpcd, DP_RECEIVER_CAP_SIZE);
794 if (err < 0) {
795 DRM_ERROR("Failed to read DPCD: %d\n", err);
796 return err;
797 }
798
799 /* Clear channel x SERDES power down */
800 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
801 SP_DP_ANALOG_POWER_DOWN_REG, SP_CH0_PD);
802 if (err)
803 return err;
804
805 /* Check link capabilities */
806 err = drm_dp_link_probe(&anx78xx->aux, &anx78xx->link);
807 if (err < 0) {
808 DRM_ERROR("Failed to probe link capabilities: %d\n", err);
809 return err;
810 }
811
812 /* Power up the sink */
813 err = drm_dp_link_power_up(&anx78xx->aux, &anx78xx->link);
814 if (err < 0) {
815 DRM_ERROR("Failed to power up DisplayPort link: %d\n", err);
816 return err;
817 }
818
819 /* Possibly enable downspread on the sink */
820 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
821 SP_DP_DOWNSPREAD_CTRL1_REG, 0);
822 if (err)
823 return err;
824
825 if (anx78xx->dpcd[DP_MAX_DOWNSPREAD] & DP_MAX_DOWNSPREAD_0_5) {
826 DRM_DEBUG("Enable downspread on the sink\n");
827 /* 4000PPM */
828 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
829 SP_DP_DOWNSPREAD_CTRL1_REG, 8);
830 if (err)
831 return err;
832
833 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL,
834 DP_SPREAD_AMP_0_5);
835 if (err < 0)
836 return err;
837 } else {
838 err = drm_dp_dpcd_writeb(&anx78xx->aux, DP_DOWNSPREAD_CTRL, 0);
839 if (err < 0)
840 return err;
841 }
842
843 /* Set the lane count and the link rate on the sink */
844 if (drm_dp_enhanced_frame_cap(anx78xx->dpcd))
845 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
846 SP_DP_SYSTEM_CTRL_BASE + 4,
847 SP_ENHANCED_MODE);
848 else
849 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
850 SP_DP_SYSTEM_CTRL_BASE + 4,
851 SP_ENHANCED_MODE);
852 if (err)
853 return err;
854
855 value = drm_dp_link_rate_to_bw_code(anx78xx->link.rate);
856 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0],
857 SP_DP_MAIN_LINK_BW_SET_REG, value);
858 if (err)
859 return err;
860
861 err = drm_dp_link_configure(&anx78xx->aux, &anx78xx->link);
862 if (err < 0) {
863 DRM_ERROR("Failed to configure DisplayPort link: %d\n", err);
864 return err;
865 }
866
867 /* Start training on the source */
868 err = regmap_write(anx78xx->map[I2C_IDX_TX_P0], SP_DP_LT_CTRL_REG,
869 SP_LT_EN);
870 if (err)
871 return err;
872
873 return 0;
874 }
875
anx78xx_config_dp_output(struct anx78xx * anx78xx)876 static int anx78xx_config_dp_output(struct anx78xx *anx78xx)
877 {
878 int err;
879
880 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
881 SP_VIDEO_MUTE);
882 if (err)
883 return err;
884
885 /* Enable DP output */
886 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_VID_CTRL1_REG,
887 SP_VIDEO_EN);
888 if (err)
889 return err;
890
891 return 0;
892 }
893
anx78xx_send_video_infoframe(struct anx78xx * anx78xx,struct hdmi_avi_infoframe * frame)894 static int anx78xx_send_video_infoframe(struct anx78xx *anx78xx,
895 struct hdmi_avi_infoframe *frame)
896 {
897 u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_AVI_INFOFRAME_SIZE];
898 int err;
899
900 err = hdmi_avi_infoframe_pack(frame, buffer, sizeof(buffer));
901 if (err < 0) {
902 DRM_ERROR("Failed to pack AVI infoframe: %d\n", err);
903 return err;
904 }
905
906 err = anx78xx_clear_bits(anx78xx->map[I2C_IDX_TX_P0],
907 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
908 if (err)
909 return err;
910
911 err = regmap_bulk_write(anx78xx->map[I2C_IDX_TX_P2],
912 SP_INFOFRAME_AVI_DB1_REG, buffer,
913 frame->length);
914 if (err)
915 return err;
916
917 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
918 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_UD);
919 if (err)
920 return err;
921
922 err = anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P0],
923 SP_PACKET_SEND_CTRL_REG, SP_AVI_IF_EN);
924 if (err)
925 return err;
926
927 return 0;
928 }
929
anx78xx_get_downstream_info(struct anx78xx * anx78xx)930 static int anx78xx_get_downstream_info(struct anx78xx *anx78xx)
931 {
932 u8 value;
933 int err;
934
935 err = drm_dp_dpcd_readb(&anx78xx->aux, DP_SINK_COUNT, &value);
936 if (err < 0) {
937 DRM_ERROR("Get sink count failed %d\n", err);
938 return err;
939 }
940
941 if (!DP_GET_SINK_COUNT(value)) {
942 DRM_ERROR("Downstream disconnected\n");
943 return -EIO;
944 }
945
946 return 0;
947 }
948
anx78xx_get_modes(struct drm_connector * connector)949 static int anx78xx_get_modes(struct drm_connector *connector)
950 {
951 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
952 int err, num_modes = 0;
953
954 if (WARN_ON(!anx78xx->powered))
955 return 0;
956
957 if (anx78xx->edid)
958 return drm_add_edid_modes(connector, anx78xx->edid);
959
960 mutex_lock(&anx78xx->lock);
961
962 err = anx78xx_get_downstream_info(anx78xx);
963 if (err) {
964 DRM_ERROR("Failed to get downstream info: %d\n", err);
965 goto unlock;
966 }
967
968 anx78xx->edid = drm_get_edid(connector, &anx78xx->aux.ddc);
969 if (!anx78xx->edid) {
970 DRM_ERROR("Failed to read EDID\n");
971 goto unlock;
972 }
973
974 err = drm_connector_update_edid_property(connector,
975 anx78xx->edid);
976 if (err) {
977 DRM_ERROR("Failed to update EDID property: %d\n", err);
978 goto unlock;
979 }
980
981 num_modes = drm_add_edid_modes(connector, anx78xx->edid);
982
983 unlock:
984 mutex_unlock(&anx78xx->lock);
985
986 return num_modes;
987 }
988
989 static const struct drm_connector_helper_funcs anx78xx_connector_helper_funcs = {
990 .get_modes = anx78xx_get_modes,
991 };
992
anx78xx_detect(struct drm_connector * connector,bool force)993 static enum drm_connector_status anx78xx_detect(struct drm_connector *connector,
994 bool force)
995 {
996 struct anx78xx *anx78xx = connector_to_anx78xx(connector);
997
998 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
999 return connector_status_disconnected;
1000
1001 return connector_status_connected;
1002 }
1003
1004 static const struct drm_connector_funcs anx78xx_connector_funcs = {
1005 .fill_modes = drm_helper_probe_single_connector_modes,
1006 .detect = anx78xx_detect,
1007 .destroy = drm_connector_cleanup,
1008 .reset = drm_atomic_helper_connector_reset,
1009 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1010 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1011 };
1012
anx78xx_bridge_attach(struct drm_bridge * bridge)1013 static int anx78xx_bridge_attach(struct drm_bridge *bridge)
1014 {
1015 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1016 int err;
1017
1018 if (!bridge->encoder) {
1019 DRM_ERROR("Parent encoder object not found");
1020 return -ENODEV;
1021 }
1022
1023 /* Register aux channel */
1024 anx78xx->aux.name = "DP-AUX";
1025 anx78xx->aux.dev = &anx78xx->client->dev;
1026 anx78xx->aux.transfer = anx78xx_aux_transfer;
1027
1028 err = drm_dp_aux_register(&anx78xx->aux);
1029 if (err < 0) {
1030 DRM_ERROR("Failed to register aux channel: %d\n", err);
1031 return err;
1032 }
1033
1034 err = drm_connector_init(bridge->dev, &anx78xx->connector,
1035 &anx78xx_connector_funcs,
1036 DRM_MODE_CONNECTOR_DisplayPort);
1037 if (err) {
1038 DRM_ERROR("Failed to initialize connector: %d\n", err);
1039 return err;
1040 }
1041
1042 drm_connector_helper_add(&anx78xx->connector,
1043 &anx78xx_connector_helper_funcs);
1044
1045 err = drm_connector_register(&anx78xx->connector);
1046 if (err) {
1047 DRM_ERROR("Failed to register connector: %d\n", err);
1048 return err;
1049 }
1050
1051 anx78xx->connector.polled = DRM_CONNECTOR_POLL_HPD;
1052
1053 err = drm_connector_attach_encoder(&anx78xx->connector,
1054 bridge->encoder);
1055 if (err) {
1056 DRM_ERROR("Failed to link up connector to encoder: %d\n", err);
1057 return err;
1058 }
1059
1060 return 0;
1061 }
1062
1063 static enum drm_mode_status
anx78xx_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_mode * mode)1064 anx78xx_bridge_mode_valid(struct drm_bridge *bridge,
1065 const struct drm_display_mode *mode)
1066 {
1067 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1068 return MODE_NO_INTERLACE;
1069
1070 /* Max 1200p at 5.4 Ghz, one lane */
1071 if (mode->clock > 154000)
1072 return MODE_CLOCK_HIGH;
1073
1074 return MODE_OK;
1075 }
1076
anx78xx_bridge_disable(struct drm_bridge * bridge)1077 static void anx78xx_bridge_disable(struct drm_bridge *bridge)
1078 {
1079 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1080
1081 /* Power off all modules except configuration registers access */
1082 anx78xx_set_bits(anx78xx->map[I2C_IDX_TX_P2], SP_POWERDOWN_CTRL_REG,
1083 SP_HDCP_PD | SP_AUDIO_PD | SP_VIDEO_PD | SP_LINK_PD);
1084 }
1085
anx78xx_bridge_mode_set(struct drm_bridge * bridge,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)1086 static void anx78xx_bridge_mode_set(struct drm_bridge *bridge,
1087 struct drm_display_mode *mode,
1088 struct drm_display_mode *adjusted_mode)
1089 {
1090 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1091 struct hdmi_avi_infoframe frame;
1092 int err;
1093
1094 if (WARN_ON(!anx78xx->powered))
1095 return;
1096
1097 mutex_lock(&anx78xx->lock);
1098
1099 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, adjusted_mode,
1100 false);
1101 if (err) {
1102 DRM_ERROR("Failed to setup AVI infoframe: %d\n", err);
1103 goto unlock;
1104 }
1105
1106 err = anx78xx_send_video_infoframe(anx78xx, &frame);
1107 if (err)
1108 DRM_ERROR("Failed to send AVI infoframe: %d\n", err);
1109
1110 unlock:
1111 mutex_unlock(&anx78xx->lock);
1112 }
1113
anx78xx_bridge_enable(struct drm_bridge * bridge)1114 static void anx78xx_bridge_enable(struct drm_bridge *bridge)
1115 {
1116 struct anx78xx *anx78xx = bridge_to_anx78xx(bridge);
1117 int err;
1118
1119 err = anx78xx_start(anx78xx);
1120 if (err) {
1121 DRM_ERROR("Failed to initialize: %d\n", err);
1122 return;
1123 }
1124
1125 err = anx78xx_set_hpd(anx78xx);
1126 if (err)
1127 DRM_ERROR("Failed to set HPD: %d\n", err);
1128 }
1129
1130 static const struct drm_bridge_funcs anx78xx_bridge_funcs = {
1131 .attach = anx78xx_bridge_attach,
1132 .mode_valid = anx78xx_bridge_mode_valid,
1133 .disable = anx78xx_bridge_disable,
1134 .mode_set = anx78xx_bridge_mode_set,
1135 .enable = anx78xx_bridge_enable,
1136 };
1137
anx78xx_hpd_threaded_handler(int irq,void * data)1138 static irqreturn_t anx78xx_hpd_threaded_handler(int irq, void *data)
1139 {
1140 struct anx78xx *anx78xx = data;
1141 int err;
1142
1143 if (anx78xx->powered)
1144 return IRQ_HANDLED;
1145
1146 mutex_lock(&anx78xx->lock);
1147
1148 /* Cable is pulled, power on the chip */
1149 anx78xx_poweron(anx78xx);
1150
1151 err = anx78xx_enable_interrupts(anx78xx);
1152 if (err)
1153 DRM_ERROR("Failed to enable interrupts: %d\n", err);
1154
1155 mutex_unlock(&anx78xx->lock);
1156
1157 return IRQ_HANDLED;
1158 }
1159
anx78xx_handle_dp_int_1(struct anx78xx * anx78xx,u8 irq)1160 static int anx78xx_handle_dp_int_1(struct anx78xx *anx78xx, u8 irq)
1161 {
1162 int err;
1163
1164 DRM_DEBUG_KMS("Handle DP interrupt 1: %02x\n", irq);
1165
1166 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1167 irq);
1168 if (err)
1169 return err;
1170
1171 if (irq & SP_TRAINING_FINISH) {
1172 DRM_DEBUG_KMS("IRQ: hardware link training finished\n");
1173 err = anx78xx_config_dp_output(anx78xx);
1174 }
1175
1176 return err;
1177 }
1178
anx78xx_handle_common_int_4(struct anx78xx * anx78xx,u8 irq)1179 static bool anx78xx_handle_common_int_4(struct anx78xx *anx78xx, u8 irq)
1180 {
1181 bool event = false;
1182 int err;
1183
1184 DRM_DEBUG_KMS("Handle common interrupt 4: %02x\n", irq);
1185
1186 err = regmap_write(anx78xx->map[I2C_IDX_TX_P2],
1187 SP_COMMON_INT_STATUS4_REG, irq);
1188 if (err) {
1189 DRM_ERROR("Failed to write SP_COMMON_INT_STATUS4 %d\n", err);
1190 return event;
1191 }
1192
1193 if (irq & SP_HPD_LOST) {
1194 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable is pulled out\n");
1195 event = true;
1196 anx78xx_poweroff(anx78xx);
1197 /* Free cached EDID */
1198 kfree(anx78xx->edid);
1199 anx78xx->edid = NULL;
1200 } else if (irq & SP_HPD_PLUG) {
1201 DRM_DEBUG_KMS("IRQ: Hot plug detect - cable plug\n");
1202 event = true;
1203 }
1204
1205 return event;
1206 }
1207
anx78xx_handle_hdmi_int_1(struct anx78xx * anx78xx,u8 irq)1208 static void anx78xx_handle_hdmi_int_1(struct anx78xx *anx78xx, u8 irq)
1209 {
1210 unsigned int value;
1211 int err;
1212
1213 DRM_DEBUG_KMS("Handle HDMI interrupt 1: %02x\n", irq);
1214
1215 err = regmap_write(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1216 irq);
1217 if (err) {
1218 DRM_ERROR("Write HDMI int 1 failed: %d\n", err);
1219 return;
1220 }
1221
1222 if ((irq & SP_CKDT_CHG) || (irq & SP_SCDT_CHG)) {
1223 DRM_DEBUG_KMS("IRQ: HDMI input detected\n");
1224
1225 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0],
1226 SP_SYSTEM_STATUS_REG, &value);
1227 if (err) {
1228 DRM_ERROR("Read system status reg failed: %d\n", err);
1229 return;
1230 }
1231
1232 if (!(value & SP_TMDS_CLOCK_DET)) {
1233 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI clock ***\n");
1234 return;
1235 }
1236
1237 if (!(value & SP_TMDS_DE_DET)) {
1238 DRM_DEBUG_KMS("IRQ: *** Waiting for HDMI signal ***\n");
1239 return;
1240 }
1241
1242 err = anx78xx_dp_link_training(anx78xx);
1243 if (err)
1244 DRM_ERROR("Failed to start link training: %d\n", err);
1245 }
1246 }
1247
anx78xx_intp_threaded_handler(int unused,void * data)1248 static irqreturn_t anx78xx_intp_threaded_handler(int unused, void *data)
1249 {
1250 struct anx78xx *anx78xx = data;
1251 bool event = false;
1252 unsigned int irq;
1253 int err;
1254
1255 mutex_lock(&anx78xx->lock);
1256
1257 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DP_INT_STATUS1_REG,
1258 &irq);
1259 if (err) {
1260 DRM_ERROR("Failed to read DP interrupt 1 status: %d\n", err);
1261 goto unlock;
1262 }
1263
1264 if (irq)
1265 anx78xx_handle_dp_int_1(anx78xx, irq);
1266
1267 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2],
1268 SP_COMMON_INT_STATUS4_REG, &irq);
1269 if (err) {
1270 DRM_ERROR("Failed to read common interrupt 4 status: %d\n",
1271 err);
1272 goto unlock;
1273 }
1274
1275 if (irq)
1276 event = anx78xx_handle_common_int_4(anx78xx, irq);
1277
1278 /* Make sure we are still powered after handle HPD events */
1279 if (!anx78xx->powered)
1280 goto unlock;
1281
1282 err = regmap_read(anx78xx->map[I2C_IDX_RX_P0], SP_INT_STATUS1_REG,
1283 &irq);
1284 if (err) {
1285 DRM_ERROR("Failed to read HDMI int 1 status: %d\n", err);
1286 goto unlock;
1287 }
1288
1289 if (irq)
1290 anx78xx_handle_hdmi_int_1(anx78xx, irq);
1291
1292 unlock:
1293 mutex_unlock(&anx78xx->lock);
1294
1295 if (event)
1296 drm_helper_hpd_irq_event(anx78xx->connector.dev);
1297
1298 return IRQ_HANDLED;
1299 }
1300
unregister_i2c_dummy_clients(struct anx78xx * anx78xx)1301 static void unregister_i2c_dummy_clients(struct anx78xx *anx78xx)
1302 {
1303 unsigned int i;
1304
1305 for (i = 0; i < ARRAY_SIZE(anx78xx->i2c_dummy); i++)
1306 i2c_unregister_device(anx78xx->i2c_dummy[i]);
1307 }
1308
1309 static const struct regmap_config anx78xx_regmap_config = {
1310 .reg_bits = 8,
1311 .val_bits = 8,
1312 };
1313
1314 static const u16 anx78xx_chipid_list[] = {
1315 0x7812,
1316 0x7814,
1317 0x7818,
1318 };
1319
anx78xx_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)1320 static int anx78xx_i2c_probe(struct i2c_client *client,
1321 const struct i2c_device_id *id)
1322 {
1323 struct anx78xx *anx78xx;
1324 struct anx78xx_platform_data *pdata;
1325 unsigned int i, idl, idh, version;
1326 bool found = false;
1327 int err;
1328
1329 anx78xx = devm_kzalloc(&client->dev, sizeof(*anx78xx), GFP_KERNEL);
1330 if (!anx78xx)
1331 return -ENOMEM;
1332
1333 pdata = &anx78xx->pdata;
1334
1335 mutex_init(&anx78xx->lock);
1336
1337 #if IS_ENABLED(CONFIG_OF)
1338 anx78xx->bridge.of_node = client->dev.of_node;
1339 #endif
1340
1341 anx78xx->client = client;
1342 i2c_set_clientdata(client, anx78xx);
1343
1344 err = anx78xx_init_pdata(anx78xx);
1345 if (err) {
1346 if (err != -EPROBE_DEFER)
1347 DRM_ERROR("Failed to initialize pdata: %d\n", err);
1348
1349 return err;
1350 }
1351
1352 pdata->hpd_irq = gpiod_to_irq(pdata->gpiod_hpd);
1353 if (pdata->hpd_irq < 0) {
1354 DRM_ERROR("Failed to get HPD IRQ: %d\n", pdata->hpd_irq);
1355 return -ENODEV;
1356 }
1357
1358 pdata->intp_irq = client->irq;
1359 if (!pdata->intp_irq) {
1360 DRM_ERROR("Failed to get CABLE_DET and INTP IRQ\n");
1361 return -ENODEV;
1362 }
1363
1364 /* Map slave addresses of ANX7814 */
1365 for (i = 0; i < I2C_NUM_ADDRESSES; i++) {
1366 anx78xx->i2c_dummy[i] = i2c_new_dummy(client->adapter,
1367 anx78xx_i2c_addresses[i] >> 1);
1368 if (!anx78xx->i2c_dummy[i]) {
1369 err = -ENOMEM;
1370 DRM_ERROR("Failed to reserve I2C bus %02x\n",
1371 anx78xx_i2c_addresses[i]);
1372 goto err_unregister_i2c;
1373 }
1374
1375 anx78xx->map[i] = devm_regmap_init_i2c(anx78xx->i2c_dummy[i],
1376 &anx78xx_regmap_config);
1377 if (IS_ERR(anx78xx->map[i])) {
1378 err = PTR_ERR(anx78xx->map[i]);
1379 DRM_ERROR("Failed regmap initialization %02x\n",
1380 anx78xx_i2c_addresses[i]);
1381 goto err_unregister_i2c;
1382 }
1383 }
1384
1385 /* Look for supported chip ID */
1386 anx78xx_poweron(anx78xx);
1387
1388 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDL_REG,
1389 &idl);
1390 if (err)
1391 goto err_poweroff;
1392
1393 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_IDH_REG,
1394 &idh);
1395 if (err)
1396 goto err_poweroff;
1397
1398 anx78xx->chipid = (u8)idl | ((u8)idh << 8);
1399
1400 err = regmap_read(anx78xx->map[I2C_IDX_TX_P2], SP_DEVICE_VERSION_REG,
1401 &version);
1402 if (err)
1403 goto err_poweroff;
1404
1405 for (i = 0; i < ARRAY_SIZE(anx78xx_chipid_list); i++) {
1406 if (anx78xx->chipid == anx78xx_chipid_list[i]) {
1407 DRM_INFO("Found ANX%x (ver. %d) SlimPort Transmitter\n",
1408 anx78xx->chipid, version);
1409 found = true;
1410 break;
1411 }
1412 }
1413
1414 if (!found) {
1415 DRM_ERROR("ANX%x (ver. %d) not supported by this driver\n",
1416 anx78xx->chipid, version);
1417 err = -ENODEV;
1418 goto err_poweroff;
1419 }
1420
1421 err = devm_request_threaded_irq(&client->dev, pdata->hpd_irq, NULL,
1422 anx78xx_hpd_threaded_handler,
1423 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1424 "anx78xx-hpd", anx78xx);
1425 if (err) {
1426 DRM_ERROR("Failed to request CABLE_DET threaded IRQ: %d\n",
1427 err);
1428 goto err_poweroff;
1429 }
1430
1431 err = devm_request_threaded_irq(&client->dev, pdata->intp_irq, NULL,
1432 anx78xx_intp_threaded_handler,
1433 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
1434 "anx78xx-intp", anx78xx);
1435 if (err) {
1436 DRM_ERROR("Failed to request INTP threaded IRQ: %d\n", err);
1437 goto err_poweroff;
1438 }
1439
1440 anx78xx->bridge.funcs = &anx78xx_bridge_funcs;
1441
1442 drm_bridge_add(&anx78xx->bridge);
1443
1444 /* If cable is pulled out, just poweroff and wait for HPD event */
1445 if (!gpiod_get_value(anx78xx->pdata.gpiod_hpd))
1446 anx78xx_poweroff(anx78xx);
1447
1448 return 0;
1449
1450 err_poweroff:
1451 anx78xx_poweroff(anx78xx);
1452
1453 err_unregister_i2c:
1454 unregister_i2c_dummy_clients(anx78xx);
1455 return err;
1456 }
1457
anx78xx_i2c_remove(struct i2c_client * client)1458 static int anx78xx_i2c_remove(struct i2c_client *client)
1459 {
1460 struct anx78xx *anx78xx = i2c_get_clientdata(client);
1461
1462 drm_bridge_remove(&anx78xx->bridge);
1463
1464 unregister_i2c_dummy_clients(anx78xx);
1465
1466 kfree(anx78xx->edid);
1467
1468 return 0;
1469 }
1470
1471 static const struct i2c_device_id anx78xx_id[] = {
1472 { "anx7814", 0 },
1473 { /* sentinel */ }
1474 };
1475 MODULE_DEVICE_TABLE(i2c, anx78xx_id);
1476
1477 #if IS_ENABLED(CONFIG_OF)
1478 static const struct of_device_id anx78xx_match_table[] = {
1479 { .compatible = "analogix,anx7814", },
1480 { /* sentinel */ },
1481 };
1482 MODULE_DEVICE_TABLE(of, anx78xx_match_table);
1483 #endif
1484
1485 static struct i2c_driver anx78xx_driver = {
1486 .driver = {
1487 .name = "anx7814",
1488 .of_match_table = of_match_ptr(anx78xx_match_table),
1489 },
1490 .probe = anx78xx_i2c_probe,
1491 .remove = anx78xx_i2c_remove,
1492 .id_table = anx78xx_id,
1493 };
1494 module_i2c_driver(anx78xx_driver);
1495
1496 MODULE_DESCRIPTION("ANX78xx SlimPort Transmitter driver");
1497 MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
1498 MODULE_LICENSE("GPL v2");
1499