1 /*
2 * Copyright (C) 2015 Samsung Electronics Co.Ltd
3 * Authors:
4 * Hyungwon Hwang <human.hwang@samsung.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundationr
9 */
10
11 #include <linux/platform_device.h>
12 #include <video/of_videomode.h>
13 #include <linux/of_address.h>
14 #include <video/videomode.h>
15 #include <linux/module.h>
16 #include <linux/delay.h>
17 #include <linux/mutex.h>
18 #include <linux/of.h>
19 #include <linux/of_graph.h>
20 #include <linux/clk.h>
21 #include <linux/component.h>
22 #include <linux/pm_runtime.h>
23 #include <drm/drmP.h>
24 #include <drm/drm_encoder.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/regmap.h>
27
28 #include "exynos_drm_drv.h"
29
30 /* Sysreg registers for MIC */
31 #define DSD_CFG_MUX 0x1004
32 #define MIC0_RGB_MUX (1 << 0)
33 #define MIC0_I80_MUX (1 << 1)
34 #define MIC0_ON_MUX (1 << 5)
35
36 /* MIC registers */
37 #define MIC_OP 0x0
38 #define MIC_IP_VER 0x0004
39 #define MIC_V_TIMING_0 0x0008
40 #define MIC_V_TIMING_1 0x000C
41 #define MIC_IMG_SIZE 0x0010
42 #define MIC_INPUT_TIMING_0 0x0014
43 #define MIC_INPUT_TIMING_1 0x0018
44 #define MIC_2D_OUTPUT_TIMING_0 0x001C
45 #define MIC_2D_OUTPUT_TIMING_1 0x0020
46 #define MIC_2D_OUTPUT_TIMING_2 0x0024
47 #define MIC_3D_OUTPUT_TIMING_0 0x0028
48 #define MIC_3D_OUTPUT_TIMING_1 0x002C
49 #define MIC_3D_OUTPUT_TIMING_2 0x0030
50 #define MIC_CORE_PARA_0 0x0034
51 #define MIC_CORE_PARA_1 0x0038
52 #define MIC_CTC_CTRL 0x0040
53 #define MIC_RD_DATA 0x0044
54
55 #define MIC_UPD_REG (1 << 31)
56 #define MIC_ON_REG (1 << 30)
57 #define MIC_TD_ON_REG (1 << 29)
58 #define MIC_BS_CHG_OUT (1 << 16)
59 #define MIC_VIDEO_TYPE(x) (((x) & 0xf) << 12)
60 #define MIC_PSR_EN (1 << 5)
61 #define MIC_SW_RST (1 << 4)
62 #define MIC_ALL_RST (1 << 3)
63 #define MIC_CORE_VER_CONTROL (1 << 2)
64 #define MIC_MODE_SEL_COMMAND_MODE (1 << 1)
65 #define MIC_MODE_SEL_MASK (1 << 1)
66 #define MIC_CORE_EN (1 << 0)
67
68 #define MIC_V_PULSE_WIDTH(x) (((x) & 0x3fff) << 16)
69 #define MIC_V_PERIOD_LINE(x) ((x) & 0x3fff)
70
71 #define MIC_VBP_SIZE(x) (((x) & 0x3fff) << 16)
72 #define MIC_VFP_SIZE(x) ((x) & 0x3fff)
73
74 #define MIC_IMG_V_SIZE(x) (((x) & 0x3fff) << 16)
75 #define MIC_IMG_H_SIZE(x) ((x) & 0x3fff)
76
77 #define MIC_H_PULSE_WIDTH_IN(x) (((x) & 0x3fff) << 16)
78 #define MIC_H_PERIOD_PIXEL_IN(x) ((x) & 0x3fff)
79
80 #define MIC_HBP_SIZE_IN(x) (((x) & 0x3fff) << 16)
81 #define MIC_HFP_SIZE_IN(x) ((x) & 0x3fff)
82
83 #define MIC_H_PULSE_WIDTH_2D(x) (((x) & 0x3fff) << 16)
84 #define MIC_H_PERIOD_PIXEL_2D(x) ((x) & 0x3fff)
85
86 #define MIC_HBP_SIZE_2D(x) (((x) & 0x3fff) << 16)
87 #define MIC_HFP_SIZE_2D(x) ((x) & 0x3fff)
88
89 #define MIC_BS_SIZE_2D(x) ((x) & 0x3fff)
90
91 static char *clk_names[] = { "pclk_mic0", "sclk_rgb_vclk_to_mic0" };
92 #define NUM_CLKS ARRAY_SIZE(clk_names)
93 static DEFINE_MUTEX(mic_mutex);
94
95 struct exynos_mic {
96 struct device *dev;
97 void __iomem *reg;
98 struct regmap *sysreg;
99 struct clk *clks[NUM_CLKS];
100
101 bool i80_mode;
102 struct videomode vm;
103 struct drm_encoder *encoder;
104 struct drm_bridge bridge;
105
106 bool enabled;
107 };
108
mic_set_path(struct exynos_mic * mic,bool enable)109 static void mic_set_path(struct exynos_mic *mic, bool enable)
110 {
111 int ret;
112 unsigned int val;
113
114 ret = regmap_read(mic->sysreg, DSD_CFG_MUX, &val);
115 if (ret) {
116 DRM_ERROR("mic: Failed to read system register\n");
117 return;
118 }
119
120 if (enable) {
121 if (mic->i80_mode)
122 val |= MIC0_I80_MUX;
123 else
124 val |= MIC0_RGB_MUX;
125
126 val |= MIC0_ON_MUX;
127 } else
128 val &= ~(MIC0_RGB_MUX | MIC0_I80_MUX | MIC0_ON_MUX);
129
130 ret = regmap_write(mic->sysreg, DSD_CFG_MUX, val);
131 if (ret)
132 DRM_ERROR("mic: Failed to read system register\n");
133 }
134
mic_sw_reset(struct exynos_mic * mic)135 static int mic_sw_reset(struct exynos_mic *mic)
136 {
137 unsigned int retry = 100;
138 int ret;
139
140 writel(MIC_SW_RST, mic->reg + MIC_OP);
141
142 while (retry-- > 0) {
143 ret = readl(mic->reg + MIC_OP);
144 if (!(ret & MIC_SW_RST))
145 return 0;
146
147 udelay(10);
148 }
149
150 return -ETIMEDOUT;
151 }
152
mic_set_porch_timing(struct exynos_mic * mic)153 static void mic_set_porch_timing(struct exynos_mic *mic)
154 {
155 struct videomode vm = mic->vm;
156 u32 reg;
157
158 reg = MIC_V_PULSE_WIDTH(vm.vsync_len) +
159 MIC_V_PERIOD_LINE(vm.vsync_len + vm.vactive +
160 vm.vback_porch + vm.vfront_porch);
161 writel(reg, mic->reg + MIC_V_TIMING_0);
162
163 reg = MIC_VBP_SIZE(vm.vback_porch) +
164 MIC_VFP_SIZE(vm.vfront_porch);
165 writel(reg, mic->reg + MIC_V_TIMING_1);
166
167 reg = MIC_V_PULSE_WIDTH(vm.hsync_len) +
168 MIC_V_PERIOD_LINE(vm.hsync_len + vm.hactive +
169 vm.hback_porch + vm.hfront_porch);
170 writel(reg, mic->reg + MIC_INPUT_TIMING_0);
171
172 reg = MIC_VBP_SIZE(vm.hback_porch) +
173 MIC_VFP_SIZE(vm.hfront_porch);
174 writel(reg, mic->reg + MIC_INPUT_TIMING_1);
175 }
176
mic_set_img_size(struct exynos_mic * mic)177 static void mic_set_img_size(struct exynos_mic *mic)
178 {
179 struct videomode *vm = &mic->vm;
180 u32 reg;
181
182 reg = MIC_IMG_H_SIZE(vm->hactive) +
183 MIC_IMG_V_SIZE(vm->vactive);
184
185 writel(reg, mic->reg + MIC_IMG_SIZE);
186 }
187
mic_set_output_timing(struct exynos_mic * mic)188 static void mic_set_output_timing(struct exynos_mic *mic)
189 {
190 struct videomode vm = mic->vm;
191 u32 reg, bs_size_2d;
192
193 DRM_DEBUG("w: %u, h: %u\n", vm.hactive, vm.vactive);
194 bs_size_2d = ((vm.hactive >> 2) << 1) + (vm.vactive % 4);
195 reg = MIC_BS_SIZE_2D(bs_size_2d);
196 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_2);
197
198 if (!mic->i80_mode) {
199 reg = MIC_H_PULSE_WIDTH_2D(vm.hsync_len) +
200 MIC_H_PERIOD_PIXEL_2D(vm.hsync_len + bs_size_2d +
201 vm.hback_porch + vm.hfront_porch);
202 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_0);
203
204 reg = MIC_HBP_SIZE_2D(vm.hback_porch) +
205 MIC_H_PERIOD_PIXEL_2D(vm.hfront_porch);
206 writel(reg, mic->reg + MIC_2D_OUTPUT_TIMING_1);
207 }
208 }
209
mic_set_reg_on(struct exynos_mic * mic,bool enable)210 static void mic_set_reg_on(struct exynos_mic *mic, bool enable)
211 {
212 u32 reg = readl(mic->reg + MIC_OP);
213
214 if (enable) {
215 reg &= ~(MIC_MODE_SEL_MASK | MIC_CORE_VER_CONTROL | MIC_PSR_EN);
216 reg |= (MIC_CORE_EN | MIC_BS_CHG_OUT | MIC_ON_REG);
217
218 reg &= ~MIC_MODE_SEL_COMMAND_MODE;
219 if (mic->i80_mode)
220 reg |= MIC_MODE_SEL_COMMAND_MODE;
221 } else {
222 reg &= ~MIC_CORE_EN;
223 }
224
225 reg |= MIC_UPD_REG;
226 writel(reg, mic->reg + MIC_OP);
227 }
228
mic_disable(struct drm_bridge * bridge)229 static void mic_disable(struct drm_bridge *bridge) { }
230
mic_post_disable(struct drm_bridge * bridge)231 static void mic_post_disable(struct drm_bridge *bridge)
232 {
233 struct exynos_mic *mic = bridge->driver_private;
234
235 mutex_lock(&mic_mutex);
236 if (!mic->enabled)
237 goto already_disabled;
238
239 mic_set_path(mic, 0);
240
241 pm_runtime_put(mic->dev);
242 mic->enabled = 0;
243
244 already_disabled:
245 mutex_unlock(&mic_mutex);
246 }
247
mic_mode_set(struct drm_bridge * bridge,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)248 static void mic_mode_set(struct drm_bridge *bridge,
249 struct drm_display_mode *mode,
250 struct drm_display_mode *adjusted_mode)
251 {
252 struct exynos_mic *mic = bridge->driver_private;
253
254 mutex_lock(&mic_mutex);
255 drm_display_mode_to_videomode(mode, &mic->vm);
256 mic->i80_mode = to_exynos_crtc(bridge->encoder->crtc)->i80_mode;
257 mutex_unlock(&mic_mutex);
258 }
259
mic_pre_enable(struct drm_bridge * bridge)260 static void mic_pre_enable(struct drm_bridge *bridge)
261 {
262 struct exynos_mic *mic = bridge->driver_private;
263 int ret;
264
265 mutex_lock(&mic_mutex);
266 if (mic->enabled)
267 goto unlock;
268
269 ret = pm_runtime_get_sync(mic->dev);
270 if (ret < 0) {
271 pm_runtime_put_noidle(mic->dev);
272 goto unlock;
273 }
274
275 mic_set_path(mic, 1);
276
277 ret = mic_sw_reset(mic);
278 if (ret) {
279 DRM_ERROR("Failed to reset\n");
280 goto turn_off;
281 }
282
283 if (!mic->i80_mode)
284 mic_set_porch_timing(mic);
285 mic_set_img_size(mic);
286 mic_set_output_timing(mic);
287 mic_set_reg_on(mic, 1);
288 mic->enabled = 1;
289 mutex_unlock(&mic_mutex);
290
291 return;
292
293 turn_off:
294 pm_runtime_put(mic->dev);
295 unlock:
296 mutex_unlock(&mic_mutex);
297 }
298
mic_enable(struct drm_bridge * bridge)299 static void mic_enable(struct drm_bridge *bridge) { }
300
301 static const struct drm_bridge_funcs mic_bridge_funcs = {
302 .disable = mic_disable,
303 .post_disable = mic_post_disable,
304 .mode_set = mic_mode_set,
305 .pre_enable = mic_pre_enable,
306 .enable = mic_enable,
307 };
308
exynos_mic_bind(struct device * dev,struct device * master,void * data)309 static int exynos_mic_bind(struct device *dev, struct device *master,
310 void *data)
311 {
312 struct exynos_mic *mic = dev_get_drvdata(dev);
313
314 mic->bridge.driver_private = mic;
315
316 return 0;
317 }
318
exynos_mic_unbind(struct device * dev,struct device * master,void * data)319 static void exynos_mic_unbind(struct device *dev, struct device *master,
320 void *data)
321 {
322 struct exynos_mic *mic = dev_get_drvdata(dev);
323
324 mutex_lock(&mic_mutex);
325 if (!mic->enabled)
326 goto already_disabled;
327
328 pm_runtime_put(mic->dev);
329
330 already_disabled:
331 mutex_unlock(&mic_mutex);
332 }
333
334 static const struct component_ops exynos_mic_component_ops = {
335 .bind = exynos_mic_bind,
336 .unbind = exynos_mic_unbind,
337 };
338
339 #ifdef CONFIG_PM
exynos_mic_suspend(struct device * dev)340 static int exynos_mic_suspend(struct device *dev)
341 {
342 struct exynos_mic *mic = dev_get_drvdata(dev);
343 int i;
344
345 for (i = NUM_CLKS - 1; i > -1; i--)
346 clk_disable_unprepare(mic->clks[i]);
347
348 return 0;
349 }
350
exynos_mic_resume(struct device * dev)351 static int exynos_mic_resume(struct device *dev)
352 {
353 struct exynos_mic *mic = dev_get_drvdata(dev);
354 int ret, i;
355
356 for (i = 0; i < NUM_CLKS; i++) {
357 ret = clk_prepare_enable(mic->clks[i]);
358 if (ret < 0) {
359 DRM_ERROR("Failed to enable clock (%s)\n",
360 clk_names[i]);
361 while (--i > -1)
362 clk_disable_unprepare(mic->clks[i]);
363 return ret;
364 }
365 }
366 return 0;
367 }
368 #endif
369
370 static const struct dev_pm_ops exynos_mic_pm_ops = {
371 SET_RUNTIME_PM_OPS(exynos_mic_suspend, exynos_mic_resume, NULL)
372 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
373 pm_runtime_force_resume)
374 };
375
exynos_mic_probe(struct platform_device * pdev)376 static int exynos_mic_probe(struct platform_device *pdev)
377 {
378 struct device *dev = &pdev->dev;
379 struct exynos_mic *mic;
380 struct resource res;
381 int ret, i;
382
383 mic = devm_kzalloc(dev, sizeof(*mic), GFP_KERNEL);
384 if (!mic) {
385 DRM_ERROR("mic: Failed to allocate memory for MIC object\n");
386 ret = -ENOMEM;
387 goto err;
388 }
389
390 mic->dev = dev;
391
392 ret = of_address_to_resource(dev->of_node, 0, &res);
393 if (ret) {
394 DRM_ERROR("mic: Failed to get mem region for MIC\n");
395 goto err;
396 }
397 mic->reg = devm_ioremap(dev, res.start, resource_size(&res));
398 if (!mic->reg) {
399 DRM_ERROR("mic: Failed to remap for MIC\n");
400 ret = -ENOMEM;
401 goto err;
402 }
403
404 mic->sysreg = syscon_regmap_lookup_by_phandle(dev->of_node,
405 "samsung,disp-syscon");
406 if (IS_ERR(mic->sysreg)) {
407 DRM_ERROR("mic: Failed to get system register.\n");
408 ret = PTR_ERR(mic->sysreg);
409 goto err;
410 }
411
412 for (i = 0; i < NUM_CLKS; i++) {
413 mic->clks[i] = devm_clk_get(dev, clk_names[i]);
414 if (IS_ERR(mic->clks[i])) {
415 DRM_ERROR("mic: Failed to get clock (%s)\n",
416 clk_names[i]);
417 ret = PTR_ERR(mic->clks[i]);
418 goto err;
419 }
420 }
421
422 platform_set_drvdata(pdev, mic);
423
424 mic->bridge.funcs = &mic_bridge_funcs;
425 mic->bridge.of_node = dev->of_node;
426
427 drm_bridge_add(&mic->bridge);
428
429 pm_runtime_enable(dev);
430
431 ret = component_add(dev, &exynos_mic_component_ops);
432 if (ret)
433 goto err_pm;
434
435 DRM_DEBUG_KMS("MIC has been probed\n");
436
437 return 0;
438
439 err_pm:
440 pm_runtime_disable(dev);
441 err:
442 return ret;
443 }
444
exynos_mic_remove(struct platform_device * pdev)445 static int exynos_mic_remove(struct platform_device *pdev)
446 {
447 struct exynos_mic *mic = platform_get_drvdata(pdev);
448
449 component_del(&pdev->dev, &exynos_mic_component_ops);
450 pm_runtime_disable(&pdev->dev);
451
452 drm_bridge_remove(&mic->bridge);
453
454 return 0;
455 }
456
457 static const struct of_device_id exynos_mic_of_match[] = {
458 { .compatible = "samsung,exynos5433-mic" },
459 { }
460 };
461 MODULE_DEVICE_TABLE(of, exynos_mic_of_match);
462
463 struct platform_driver mic_driver = {
464 .probe = exynos_mic_probe,
465 .remove = exynos_mic_remove,
466 .driver = {
467 .name = "exynos-mic",
468 .pm = &exynos_mic_pm_ops,
469 .owner = THIS_MODULE,
470 .of_match_table = exynos_mic_of_match,
471 },
472 };
473