1 /*
2 * SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2018, The Linux Foundation
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/iopoll.h>
9
10 #include "dsi_pll.h"
11 #include "dsi.xml.h"
12
13 /*
14 * DSI PLL 10nm - clock diagram (eg: DSI0):
15 *
16 * dsi0_pll_out_div_clk dsi0_pll_bit_clk
17 * | |
18 * | |
19 * +---------+ | +----------+ | +----+
20 * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk
21 * +---------+ | +----------+ | +----+
22 * | |
23 * | | dsi0_pll_by_2_bit_clk
24 * | | |
25 * | | +----+ | |\ dsi0_pclk_mux
26 * | |--| /2 |--o--| \ |
27 * | | +----+ | \ | +---------+
28 * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk
29 * |------------------------------| / +---------+
30 * | +-----+ | /
31 * -----------| /4? |--o----------|/
32 * +-----+ | |
33 * | |dsiclk_sel
34 * |
35 * dsi0_pll_post_out_div_clk
36 */
37
38 #define DSI_BYTE_PLL_CLK 0
39 #define DSI_PIXEL_PLL_CLK 1
40 #define NUM_PROVIDED_CLKS 2
41
42 #define VCO_REF_CLK_RATE 19200000
43
44 struct dsi_pll_regs {
45 u32 pll_prop_gain_rate;
46 u32 pll_lockdet_rate;
47 u32 decimal_div_start;
48 u32 frac_div_start_low;
49 u32 frac_div_start_mid;
50 u32 frac_div_start_high;
51 u32 pll_clock_inverters;
52 u32 ssc_stepsize_low;
53 u32 ssc_stepsize_high;
54 u32 ssc_div_per_low;
55 u32 ssc_div_per_high;
56 u32 ssc_adjper_low;
57 u32 ssc_adjper_high;
58 u32 ssc_control;
59 };
60
61 struct dsi_pll_config {
62 u32 ref_freq;
63 bool div_override;
64 u32 output_div;
65 bool ignore_frac;
66 bool disable_prescaler;
67 bool enable_ssc;
68 bool ssc_center;
69 u32 dec_bits;
70 u32 frac_bits;
71 u32 lock_timer;
72 u32 ssc_freq;
73 u32 ssc_offset;
74 u32 ssc_adj_per;
75 u32 thresh_cycles;
76 u32 refclk_cycles;
77 };
78
79 struct pll_10nm_cached_state {
80 unsigned long vco_rate;
81 u8 bit_clk_div;
82 u8 pix_clk_div;
83 u8 pll_out_div;
84 u8 pll_mux;
85 };
86
87 struct dsi_pll_10nm {
88 struct msm_dsi_pll base;
89
90 int id;
91 struct platform_device *pdev;
92
93 void __iomem *phy_cmn_mmio;
94 void __iomem *mmio;
95
96 u64 vco_ref_clk_rate;
97 u64 vco_current_rate;
98
99 /* protects REG_DSI_10nm_PHY_CMN_CLK_CFG0 register */
100 spinlock_t postdiv_lock;
101
102 int vco_delay;
103 struct dsi_pll_config pll_configuration;
104 struct dsi_pll_regs reg_setup;
105
106 /* private clocks: */
107 struct clk_hw *hws[NUM_DSI_CLOCKS_MAX];
108 u32 num_hws;
109
110 /* clock-provider: */
111 struct clk_hw_onecell_data *hw_data;
112
113 struct pll_10nm_cached_state cached_state;
114
115 enum msm_dsi_phy_usecase uc;
116 struct dsi_pll_10nm *slave;
117 };
118
119 #define to_pll_10nm(x) container_of(x, struct dsi_pll_10nm, base)
120
121 /*
122 * Global list of private DSI PLL struct pointers. We need this for Dual DSI
123 * mode, where the master PLL's clk_ops needs access the slave's private data
124 */
125 static struct dsi_pll_10nm *pll_10nm_list[DSI_MAX];
126
dsi_pll_setup_config(struct dsi_pll_10nm * pll)127 static void dsi_pll_setup_config(struct dsi_pll_10nm *pll)
128 {
129 struct dsi_pll_config *config = &pll->pll_configuration;
130
131 config->ref_freq = pll->vco_ref_clk_rate;
132 config->output_div = 1;
133 config->dec_bits = 8;
134 config->frac_bits = 18;
135 config->lock_timer = 64;
136 config->ssc_freq = 31500;
137 config->ssc_offset = 5000;
138 config->ssc_adj_per = 2;
139 config->thresh_cycles = 32;
140 config->refclk_cycles = 256;
141
142 config->div_override = false;
143 config->ignore_frac = false;
144 config->disable_prescaler = false;
145
146 config->enable_ssc = false;
147 config->ssc_center = 0;
148 }
149
dsi_pll_calc_dec_frac(struct dsi_pll_10nm * pll)150 static void dsi_pll_calc_dec_frac(struct dsi_pll_10nm *pll)
151 {
152 struct dsi_pll_config *config = &pll->pll_configuration;
153 struct dsi_pll_regs *regs = &pll->reg_setup;
154 u64 fref = pll->vco_ref_clk_rate;
155 u64 pll_freq;
156 u64 divider;
157 u64 dec, dec_multiple;
158 u32 frac;
159 u64 multiplier;
160
161 pll_freq = pll->vco_current_rate;
162
163 if (config->disable_prescaler)
164 divider = fref;
165 else
166 divider = fref * 2;
167
168 multiplier = 1 << config->frac_bits;
169 dec_multiple = div_u64(pll_freq * multiplier, divider);
170 div_u64_rem(dec_multiple, multiplier, &frac);
171
172 dec = div_u64(dec_multiple, multiplier);
173
174 if (pll_freq <= 1900000000UL)
175 regs->pll_prop_gain_rate = 8;
176 else if (pll_freq <= 3000000000UL)
177 regs->pll_prop_gain_rate = 10;
178 else
179 regs->pll_prop_gain_rate = 12;
180 if (pll_freq < 1100000000UL)
181 regs->pll_clock_inverters = 8;
182 else
183 regs->pll_clock_inverters = 0;
184
185 regs->pll_lockdet_rate = config->lock_timer;
186 regs->decimal_div_start = dec;
187 regs->frac_div_start_low = (frac & 0xff);
188 regs->frac_div_start_mid = (frac & 0xff00) >> 8;
189 regs->frac_div_start_high = (frac & 0x30000) >> 16;
190 }
191
192 #define SSC_CENTER BIT(0)
193 #define SSC_EN BIT(1)
194
dsi_pll_calc_ssc(struct dsi_pll_10nm * pll)195 static void dsi_pll_calc_ssc(struct dsi_pll_10nm *pll)
196 {
197 struct dsi_pll_config *config = &pll->pll_configuration;
198 struct dsi_pll_regs *regs = &pll->reg_setup;
199 u32 ssc_per;
200 u32 ssc_mod;
201 u64 ssc_step_size;
202 u64 frac;
203
204 if (!config->enable_ssc) {
205 DBG("SSC not enabled\n");
206 return;
207 }
208
209 ssc_per = DIV_ROUND_CLOSEST(config->ref_freq, config->ssc_freq) / 2 - 1;
210 ssc_mod = (ssc_per + 1) % (config->ssc_adj_per + 1);
211 ssc_per -= ssc_mod;
212
213 frac = regs->frac_div_start_low |
214 (regs->frac_div_start_mid << 8) |
215 (regs->frac_div_start_high << 16);
216 ssc_step_size = regs->decimal_div_start;
217 ssc_step_size *= (1 << config->frac_bits);
218 ssc_step_size += frac;
219 ssc_step_size *= config->ssc_offset;
220 ssc_step_size *= (config->ssc_adj_per + 1);
221 ssc_step_size = div_u64(ssc_step_size, (ssc_per + 1));
222 ssc_step_size = DIV_ROUND_CLOSEST_ULL(ssc_step_size, 1000000);
223
224 regs->ssc_div_per_low = ssc_per & 0xFF;
225 regs->ssc_div_per_high = (ssc_per & 0xFF00) >> 8;
226 regs->ssc_stepsize_low = (u32)(ssc_step_size & 0xFF);
227 regs->ssc_stepsize_high = (u32)((ssc_step_size & 0xFF00) >> 8);
228 regs->ssc_adjper_low = config->ssc_adj_per & 0xFF;
229 regs->ssc_adjper_high = (config->ssc_adj_per & 0xFF00) >> 8;
230
231 regs->ssc_control = config->ssc_center ? SSC_CENTER : 0;
232
233 pr_debug("SCC: Dec:%d, frac:%llu, frac_bits:%d\n",
234 regs->decimal_div_start, frac, config->frac_bits);
235 pr_debug("SSC: div_per:0x%X, stepsize:0x%X, adjper:0x%X\n",
236 ssc_per, (u32)ssc_step_size, config->ssc_adj_per);
237 }
238
dsi_pll_ssc_commit(struct dsi_pll_10nm * pll)239 static void dsi_pll_ssc_commit(struct dsi_pll_10nm *pll)
240 {
241 void __iomem *base = pll->mmio;
242 struct dsi_pll_regs *regs = &pll->reg_setup;
243
244 if (pll->pll_configuration.enable_ssc) {
245 pr_debug("SSC is enabled\n");
246
247 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1,
248 regs->ssc_stepsize_low);
249 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1,
250 regs->ssc_stepsize_high);
251 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1,
252 regs->ssc_div_per_low);
253 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1,
254 regs->ssc_div_per_high);
255 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1,
256 regs->ssc_adjper_low);
257 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1,
258 regs->ssc_adjper_high);
259 pll_write(base + REG_DSI_10nm_PHY_PLL_SSC_CONTROL,
260 SSC_EN | regs->ssc_control);
261 }
262 }
263
dsi_pll_config_hzindep_reg(struct dsi_pll_10nm * pll)264 static void dsi_pll_config_hzindep_reg(struct dsi_pll_10nm *pll)
265 {
266 void __iomem *base = pll->mmio;
267
268 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE, 0x80);
269 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO, 0x03);
270 pll_write(base + REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE, 0x00);
271 pll_write(base + REG_DSI_10nm_PHY_PLL_DSM_DIVIDER, 0x00);
272 pll_write(base + REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER, 0x4e);
273 pll_write(base + REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS, 0x40);
274 pll_write(base + REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE,
275 0xba);
276 pll_write(base + REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE, 0x0c);
277 pll_write(base + REG_DSI_10nm_PHY_PLL_OUTDIV, 0x00);
278 pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE, 0x00);
279 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO, 0x08);
280 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1, 0x08);
281 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1, 0xc0);
282 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1, 0xfa);
283 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1,
284 0x4c);
285 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE, 0x80);
286 pll_write(base + REG_DSI_10nm_PHY_PLL_PFILT, 0x29);
287 pll_write(base + REG_DSI_10nm_PHY_PLL_IFILT, 0x3f);
288 }
289
dsi_pll_commit(struct dsi_pll_10nm * pll)290 static void dsi_pll_commit(struct dsi_pll_10nm *pll)
291 {
292 void __iomem *base = pll->mmio;
293 struct dsi_pll_regs *reg = &pll->reg_setup;
294
295 pll_write(base + REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE, 0x12);
296 pll_write(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1,
297 reg->decimal_div_start);
298 pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1,
299 reg->frac_div_start_low);
300 pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1,
301 reg->frac_div_start_mid);
302 pll_write(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1,
303 reg->frac_div_start_high);
304 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1, 0x40);
305 pll_write(base + REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY, 0x06);
306 pll_write(base + REG_DSI_10nm_PHY_PLL_CMODE, 0x10);
307 pll_write(base + REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS,
308 reg->pll_clock_inverters);
309 }
310
dsi_pll_10nm_vco_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)311 static int dsi_pll_10nm_vco_set_rate(struct clk_hw *hw, unsigned long rate,
312 unsigned long parent_rate)
313 {
314 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
315 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
316
317 DBG("DSI PLL%d rate=%lu, parent's=%lu", pll_10nm->id, rate,
318 parent_rate);
319
320 pll_10nm->vco_current_rate = rate;
321 pll_10nm->vco_ref_clk_rate = VCO_REF_CLK_RATE;
322
323 dsi_pll_setup_config(pll_10nm);
324
325 dsi_pll_calc_dec_frac(pll_10nm);
326
327 dsi_pll_calc_ssc(pll_10nm);
328
329 dsi_pll_commit(pll_10nm);
330
331 dsi_pll_config_hzindep_reg(pll_10nm);
332
333 dsi_pll_ssc_commit(pll_10nm);
334
335 /* flush, ensure all register writes are done*/
336 wmb();
337
338 return 0;
339 }
340
dsi_pll_10nm_lock_status(struct dsi_pll_10nm * pll)341 static int dsi_pll_10nm_lock_status(struct dsi_pll_10nm *pll)
342 {
343 int rc;
344 u32 status = 0;
345 u32 const delay_us = 100;
346 u32 const timeout_us = 5000;
347
348 rc = readl_poll_timeout_atomic(pll->mmio +
349 REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE,
350 status,
351 ((status & BIT(0)) > 0),
352 delay_us,
353 timeout_us);
354 if (rc)
355 pr_err("DSI PLL(%d) lock failed, status=0x%08x\n",
356 pll->id, status);
357
358 return rc;
359 }
360
dsi_pll_disable_pll_bias(struct dsi_pll_10nm * pll)361 static void dsi_pll_disable_pll_bias(struct dsi_pll_10nm *pll)
362 {
363 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
364
365 pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0);
366 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
367 data & ~BIT(5));
368 ndelay(250);
369 }
370
dsi_pll_enable_pll_bias(struct dsi_pll_10nm * pll)371 static void dsi_pll_enable_pll_bias(struct dsi_pll_10nm *pll)
372 {
373 u32 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0);
374
375 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CTRL_0,
376 data | BIT(5));
377 pll_write(pll->mmio + REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES, 0xc0);
378 ndelay(250);
379 }
380
dsi_pll_disable_global_clk(struct dsi_pll_10nm * pll)381 static void dsi_pll_disable_global_clk(struct dsi_pll_10nm *pll)
382 {
383 u32 data;
384
385 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
386 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
387 data & ~BIT(5));
388 }
389
dsi_pll_enable_global_clk(struct dsi_pll_10nm * pll)390 static void dsi_pll_enable_global_clk(struct dsi_pll_10nm *pll)
391 {
392 u32 data;
393
394 data = pll_read(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
395 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_CLK_CFG1,
396 data | BIT(5));
397 }
398
dsi_pll_10nm_vco_prepare(struct clk_hw * hw)399 static int dsi_pll_10nm_vco_prepare(struct clk_hw *hw)
400 {
401 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
402 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
403 int rc;
404
405 dsi_pll_enable_pll_bias(pll_10nm);
406 if (pll_10nm->slave)
407 dsi_pll_enable_pll_bias(pll_10nm->slave);
408
409 rc = dsi_pll_10nm_vco_set_rate(hw,pll_10nm->vco_current_rate, 0);
410 if (rc) {
411 pr_err("vco_set_rate failed, rc=%d\n", rc);
412 return rc;
413 }
414
415 /* Start PLL */
416 pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL,
417 0x01);
418
419 /*
420 * ensure all PLL configurations are written prior to checking
421 * for PLL lock.
422 */
423 wmb();
424
425 /* Check for PLL lock */
426 rc = dsi_pll_10nm_lock_status(pll_10nm);
427 if (rc) {
428 pr_err("PLL(%d) lock failed\n", pll_10nm->id);
429 goto error;
430 }
431
432 pll->pll_on = true;
433
434 dsi_pll_enable_global_clk(pll_10nm);
435 if (pll_10nm->slave)
436 dsi_pll_enable_global_clk(pll_10nm->slave);
437
438 pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL,
439 0x01);
440 if (pll_10nm->slave)
441 pll_write(pll_10nm->slave->phy_cmn_mmio +
442 REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0x01);
443
444 error:
445 return rc;
446 }
447
dsi_pll_disable_sub(struct dsi_pll_10nm * pll)448 static void dsi_pll_disable_sub(struct dsi_pll_10nm *pll)
449 {
450 pll_write(pll->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_RBUF_CTRL, 0);
451 dsi_pll_disable_pll_bias(pll);
452 }
453
dsi_pll_10nm_vco_unprepare(struct clk_hw * hw)454 static void dsi_pll_10nm_vco_unprepare(struct clk_hw *hw)
455 {
456 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
457 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
458
459 /*
460 * To avoid any stray glitches while abruptly powering down the PLL
461 * make sure to gate the clock using the clock enable bit before
462 * powering down the PLL
463 */
464 dsi_pll_disable_global_clk(pll_10nm);
465 pll_write(pll_10nm->phy_cmn_mmio + REG_DSI_10nm_PHY_CMN_PLL_CNTRL, 0);
466 dsi_pll_disable_sub(pll_10nm);
467 if (pll_10nm->slave) {
468 dsi_pll_disable_global_clk(pll_10nm->slave);
469 dsi_pll_disable_sub(pll_10nm->slave);
470 }
471 /* flush, ensure all register writes are done */
472 wmb();
473 pll->pll_on = false;
474 }
475
dsi_pll_10nm_vco_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)476 static unsigned long dsi_pll_10nm_vco_recalc_rate(struct clk_hw *hw,
477 unsigned long parent_rate)
478 {
479 struct msm_dsi_pll *pll = hw_clk_to_pll(hw);
480 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
481 void __iomem *base = pll_10nm->mmio;
482 u64 ref_clk = pll_10nm->vco_ref_clk_rate;
483 u64 vco_rate = 0x0;
484 u64 multiplier;
485 u32 frac;
486 u32 dec;
487 u64 pll_freq, tmp64;
488
489 dec = pll_read(base + REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1);
490 dec &= 0xff;
491
492 frac = pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1);
493 frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1) &
494 0xff) << 8);
495 frac |= ((pll_read(base + REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1) &
496 0x3) << 16);
497
498 /*
499 * TODO:
500 * 1. Assumes prescaler is disabled
501 * 2. Multiplier is 2^18. it should be 2^(num_of_frac_bits)
502 */
503 multiplier = 1 << 18;
504 pll_freq = dec * (ref_clk * 2);
505 tmp64 = (ref_clk * 2 * frac);
506 pll_freq += div_u64(tmp64, multiplier);
507
508 vco_rate = pll_freq;
509
510 DBG("DSI PLL%d returning vco rate = %lu, dec = %x, frac = %x",
511 pll_10nm->id, (unsigned long)vco_rate, dec, frac);
512
513 return (unsigned long)vco_rate;
514 }
515
516 static const struct clk_ops clk_ops_dsi_pll_10nm_vco = {
517 .round_rate = msm_dsi_pll_helper_clk_round_rate,
518 .set_rate = dsi_pll_10nm_vco_set_rate,
519 .recalc_rate = dsi_pll_10nm_vco_recalc_rate,
520 .prepare = dsi_pll_10nm_vco_prepare,
521 .unprepare = dsi_pll_10nm_vco_unprepare,
522 };
523
524 /*
525 * PLL Callbacks
526 */
527
dsi_pll_10nm_save_state(struct msm_dsi_pll * pll)528 static void dsi_pll_10nm_save_state(struct msm_dsi_pll *pll)
529 {
530 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
531 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
532 void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
533 u32 cmn_clk_cfg0, cmn_clk_cfg1;
534
535 cached->pll_out_div = pll_read(pll_10nm->mmio +
536 REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
537 cached->pll_out_div &= 0x3;
538
539 cmn_clk_cfg0 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0);
540 cached->bit_clk_div = cmn_clk_cfg0 & 0xf;
541 cached->pix_clk_div = (cmn_clk_cfg0 & 0xf0) >> 4;
542
543 cmn_clk_cfg1 = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
544 cached->pll_mux = cmn_clk_cfg1 & 0x3;
545
546 DBG("DSI PLL%d outdiv %x bit_clk_div %x pix_clk_div %x pll_mux %x",
547 pll_10nm->id, cached->pll_out_div, cached->bit_clk_div,
548 cached->pix_clk_div, cached->pll_mux);
549 }
550
dsi_pll_10nm_restore_state(struct msm_dsi_pll * pll)551 static int dsi_pll_10nm_restore_state(struct msm_dsi_pll *pll)
552 {
553 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
554 struct pll_10nm_cached_state *cached = &pll_10nm->cached_state;
555 void __iomem *phy_base = pll_10nm->phy_cmn_mmio;
556 u32 val;
557
558 val = pll_read(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE);
559 val &= ~0x3;
560 val |= cached->pll_out_div;
561 pll_write(pll_10nm->mmio + REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE, val);
562
563 pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG0,
564 cached->bit_clk_div | (cached->pix_clk_div << 4));
565
566 val = pll_read(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1);
567 val &= ~0x3;
568 val |= cached->pll_mux;
569 pll_write(phy_base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, val);
570
571 DBG("DSI PLL%d", pll_10nm->id);
572
573 return 0;
574 }
575
dsi_pll_10nm_set_usecase(struct msm_dsi_pll * pll,enum msm_dsi_phy_usecase uc)576 static int dsi_pll_10nm_set_usecase(struct msm_dsi_pll *pll,
577 enum msm_dsi_phy_usecase uc)
578 {
579 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
580 void __iomem *base = pll_10nm->phy_cmn_mmio;
581 u32 data = 0x0; /* internal PLL */
582
583 DBG("DSI PLL%d", pll_10nm->id);
584
585 switch (uc) {
586 case MSM_DSI_PHY_STANDALONE:
587 break;
588 case MSM_DSI_PHY_MASTER:
589 pll_10nm->slave = pll_10nm_list[(pll_10nm->id + 1) % DSI_MAX];
590 break;
591 case MSM_DSI_PHY_SLAVE:
592 data = 0x1; /* external PLL */
593 break;
594 default:
595 return -EINVAL;
596 }
597
598 /* set PLL src */
599 pll_write(base + REG_DSI_10nm_PHY_CMN_CLK_CFG1, (data << 2));
600
601 pll_10nm->uc = uc;
602
603 return 0;
604 }
605
dsi_pll_10nm_get_provider(struct msm_dsi_pll * pll,struct clk ** byte_clk_provider,struct clk ** pixel_clk_provider)606 static int dsi_pll_10nm_get_provider(struct msm_dsi_pll *pll,
607 struct clk **byte_clk_provider,
608 struct clk **pixel_clk_provider)
609 {
610 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
611 struct clk_hw_onecell_data *hw_data = pll_10nm->hw_data;
612
613 DBG("DSI PLL%d", pll_10nm->id);
614
615 if (byte_clk_provider)
616 *byte_clk_provider = hw_data->hws[DSI_BYTE_PLL_CLK]->clk;
617 if (pixel_clk_provider)
618 *pixel_clk_provider = hw_data->hws[DSI_PIXEL_PLL_CLK]->clk;
619
620 return 0;
621 }
622
dsi_pll_10nm_destroy(struct msm_dsi_pll * pll)623 static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
624 {
625 struct dsi_pll_10nm *pll_10nm = to_pll_10nm(pll);
626
627 DBG("DSI PLL%d", pll_10nm->id);
628 }
629
630 /*
631 * The post dividers and mux clocks are created using the standard divider and
632 * mux API. Unlike the 14nm PHY, the slave PLL doesn't need its dividers/mux
633 * state to follow the master PLL's divider/mux state. Therefore, we don't
634 * require special clock ops that also configure the slave PLL registers
635 */
pll_10nm_register(struct dsi_pll_10nm * pll_10nm)636 static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
637 {
638 char clk_name[32], parent[32], vco_name[32];
639 char parent2[32], parent3[32], parent4[32];
640 struct clk_init_data vco_init = {
641 .parent_names = (const char *[]){ "xo" },
642 .num_parents = 1,
643 .name = vco_name,
644 .flags = CLK_IGNORE_UNUSED,
645 .ops = &clk_ops_dsi_pll_10nm_vco,
646 };
647 struct device *dev = &pll_10nm->pdev->dev;
648 struct clk_hw **hws = pll_10nm->hws;
649 struct clk_hw_onecell_data *hw_data;
650 struct clk_hw *hw;
651 int num = 0;
652 int ret;
653
654 DBG("DSI%d", pll_10nm->id);
655
656 hw_data = devm_kzalloc(dev, sizeof(*hw_data) +
657 NUM_PROVIDED_CLKS * sizeof(struct clk_hw *),
658 GFP_KERNEL);
659 if (!hw_data)
660 return -ENOMEM;
661
662 snprintf(vco_name, 32, "dsi%dvco_clk", pll_10nm->id);
663 pll_10nm->base.clk_hw.init = &vco_init;
664
665 ret = clk_hw_register(dev, &pll_10nm->base.clk_hw);
666 if (ret)
667 return ret;
668
669 hws[num++] = &pll_10nm->base.clk_hw;
670
671 snprintf(clk_name, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
672 snprintf(parent, 32, "dsi%dvco_clk", pll_10nm->id);
673
674 hw = clk_hw_register_divider(dev, clk_name,
675 parent, CLK_SET_RATE_PARENT,
676 pll_10nm->mmio +
677 REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE,
678 0, 2, CLK_DIVIDER_POWER_OF_TWO, NULL);
679 if (IS_ERR(hw))
680 return PTR_ERR(hw);
681
682 hws[num++] = hw;
683
684 snprintf(clk_name, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
685 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
686
687 /* BIT CLK: DIV_CTRL_3_0 */
688 hw = clk_hw_register_divider(dev, clk_name, parent,
689 CLK_SET_RATE_PARENT,
690 pll_10nm->phy_cmn_mmio +
691 REG_DSI_10nm_PHY_CMN_CLK_CFG0,
692 0, 4, CLK_DIVIDER_ONE_BASED,
693 &pll_10nm->postdiv_lock);
694 if (IS_ERR(hw))
695 return PTR_ERR(hw);
696
697 hws[num++] = hw;
698
699 snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);
700 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
701
702 /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */
703 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
704 CLK_SET_RATE_PARENT, 1, 8);
705 if (IS_ERR(hw))
706 return PTR_ERR(hw);
707
708 hws[num++] = hw;
709 hw_data->hws[DSI_BYTE_PLL_CLK] = hw;
710
711 snprintf(clk_name, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
712 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
713
714 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
715 0, 1, 2);
716 if (IS_ERR(hw))
717 return PTR_ERR(hw);
718
719 hws[num++] = hw;
720
721 snprintf(clk_name, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
722 snprintf(parent, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
723
724 hw = clk_hw_register_fixed_factor(dev, clk_name, parent,
725 0, 1, 4);
726 if (IS_ERR(hw))
727 return PTR_ERR(hw);
728
729 hws[num++] = hw;
730
731 snprintf(clk_name, 32, "dsi%d_pclk_mux", pll_10nm->id);
732 snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);
733 snprintf(parent2, 32, "dsi%d_pll_by_2_bit_clk", pll_10nm->id);
734 snprintf(parent3, 32, "dsi%d_pll_out_div_clk", pll_10nm->id);
735 snprintf(parent4, 32, "dsi%d_pll_post_out_div_clk", pll_10nm->id);
736
737 hw = clk_hw_register_mux(dev, clk_name,
738 (const char *[]){
739 parent, parent2, parent3, parent4
740 }, 4, 0, pll_10nm->phy_cmn_mmio +
741 REG_DSI_10nm_PHY_CMN_CLK_CFG1,
742 0, 2, 0, NULL);
743 if (IS_ERR(hw))
744 return PTR_ERR(hw);
745
746 hws[num++] = hw;
747
748 snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);
749 snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);
750
751 /* PIX CLK DIV : DIV_CTRL_7_4*/
752 hw = clk_hw_register_divider(dev, clk_name, parent,
753 0, pll_10nm->phy_cmn_mmio +
754 REG_DSI_10nm_PHY_CMN_CLK_CFG0,
755 4, 4, CLK_DIVIDER_ONE_BASED,
756 &pll_10nm->postdiv_lock);
757 if (IS_ERR(hw))
758 return PTR_ERR(hw);
759
760 hws[num++] = hw;
761 hw_data->hws[DSI_PIXEL_PLL_CLK] = hw;
762
763 pll_10nm->num_hws = num;
764
765 hw_data->num = NUM_PROVIDED_CLKS;
766 pll_10nm->hw_data = hw_data;
767
768 ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
769 pll_10nm->hw_data);
770 if (ret) {
771 dev_err(dev, "failed to register clk provider: %d\n", ret);
772 return ret;
773 }
774
775 return 0;
776 }
777
msm_dsi_pll_10nm_init(struct platform_device * pdev,int id)778 struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
779 {
780 struct dsi_pll_10nm *pll_10nm;
781 struct msm_dsi_pll *pll;
782 int ret;
783
784 if (!pdev)
785 return ERR_PTR(-ENODEV);
786
787 pll_10nm = devm_kzalloc(&pdev->dev, sizeof(*pll_10nm), GFP_KERNEL);
788 if (!pll_10nm)
789 return ERR_PTR(-ENOMEM);
790
791 DBG("DSI PLL%d", id);
792
793 pll_10nm->pdev = pdev;
794 pll_10nm->id = id;
795 pll_10nm_list[id] = pll_10nm;
796
797 pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
798 if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
799 dev_err(&pdev->dev, "failed to map CMN PHY base\n");
800 return ERR_PTR(-ENOMEM);
801 }
802
803 pll_10nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
804 if (IS_ERR_OR_NULL(pll_10nm->mmio)) {
805 dev_err(&pdev->dev, "failed to map PLL base\n");
806 return ERR_PTR(-ENOMEM);
807 }
808
809 spin_lock_init(&pll_10nm->postdiv_lock);
810
811 pll = &pll_10nm->base;
812 pll->min_rate = 1000000000UL;
813 pll->max_rate = 3500000000UL;
814 pll->get_provider = dsi_pll_10nm_get_provider;
815 pll->destroy = dsi_pll_10nm_destroy;
816 pll->save_state = dsi_pll_10nm_save_state;
817 pll->restore_state = dsi_pll_10nm_restore_state;
818 pll->set_usecase = dsi_pll_10nm_set_usecase;
819
820 pll_10nm->vco_delay = 1;
821
822 ret = pll_10nm_register(pll_10nm);
823 if (ret) {
824 dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
825 return ERR_PTR(ret);
826 }
827
828 /* TODO: Remove this when we have proper display handover support */
829 msm_dsi_pll_save_state(pll);
830
831 return pll;
832 }
833