1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 *
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 *
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 *
17 *
18 * TODO: orientation events
19 */
20
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34
35 #define MMA8452_STATUS 0x00
36 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
37 #define MMA8452_OUT_X 0x01 /* MSB first */
38 #define MMA8452_OUT_Y 0x03
39 #define MMA8452_OUT_Z 0x05
40 #define MMA8452_INT_SRC 0x0c
41 #define MMA8452_WHO_AM_I 0x0d
42 #define MMA8452_DATA_CFG 0x0e
43 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
44 #define MMA8452_DATA_CFG_FS_2G 0
45 #define MMA8452_DATA_CFG_FS_4G 1
46 #define MMA8452_DATA_CFG_FS_8G 2
47 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
48 #define MMA8452_HP_FILTER_CUTOFF 0x0f
49 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
50 #define MMA8452_FF_MT_CFG 0x15
51 #define MMA8452_FF_MT_CFG_OAE BIT(6)
52 #define MMA8452_FF_MT_CFG_ELE BIT(7)
53 #define MMA8452_FF_MT_SRC 0x16
54 #define MMA8452_FF_MT_SRC_XHE BIT(1)
55 #define MMA8452_FF_MT_SRC_YHE BIT(3)
56 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
57 #define MMA8452_FF_MT_THS 0x17
58 #define MMA8452_FF_MT_THS_MASK 0x7f
59 #define MMA8452_FF_MT_COUNT 0x18
60 #define MMA8452_FF_MT_CHAN_SHIFT 3
61 #define MMA8452_TRANSIENT_CFG 0x1d
62 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
73 #define MMA8452_CTRL_REG1 0x2a
74 #define MMA8452_CTRL_ACTIVE BIT(0)
75 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
76 #define MMA8452_CTRL_DR_SHIFT 3
77 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
78 #define MMA8452_CTRL_REG2 0x2b
79 #define MMA8452_CTRL_REG2_RST BIT(6)
80 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
81 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
82 #define MMA8452_CTRL_REG4 0x2d
83 #define MMA8452_CTRL_REG5 0x2e
84 #define MMA8452_OFF_X 0x2f
85 #define MMA8452_OFF_Y 0x30
86 #define MMA8452_OFF_Z 0x31
87
88 #define MMA8452_MAX_REG 0x31
89
90 #define MMA8452_INT_DRDY BIT(0)
91 #define MMA8452_INT_FF_MT BIT(2)
92 #define MMA8452_INT_TRANS BIT(5)
93
94 #define MMA8451_DEVICE_ID 0x1a
95 #define MMA8452_DEVICE_ID 0x2a
96 #define MMA8453_DEVICE_ID 0x3a
97 #define MMA8652_DEVICE_ID 0x4a
98 #define MMA8653_DEVICE_ID 0x5a
99 #define FXLS8471_DEVICE_ID 0x6a
100
101 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
102
103 struct mma8452_data {
104 struct i2c_client *client;
105 struct mutex lock;
106 u8 ctrl_reg1;
107 u8 data_cfg;
108 const struct mma_chip_info *chip_info;
109 int sleep_val;
110
111 /* Ensure correct alignment of time stamp when present */
112 struct {
113 __be16 channels[3];
114 s64 ts __aligned(8);
115 } buffer;
116 };
117
118 /**
119 * struct mma8452_event_regs - chip specific data related to events
120 * @ev_cfg: event config register address
121 * @ev_cfg_ele: latch bit in event config register
122 * @ev_cfg_chan_shift: number of the bit to enable events in X
123 * direction; in event config register
124 * @ev_src: event source register address
125 * @ev_ths: event threshold register address
126 * @ev_ths_mask: mask for the threshold value
127 * @ev_count: event count (period) register address
128 *
129 * Since not all chips supported by the driver support comparing high pass
130 * filtered data for events (interrupts), different interrupt sources are
131 * used for different chips and the relevant registers are included here.
132 */
133 struct mma8452_event_regs {
134 u8 ev_cfg;
135 u8 ev_cfg_ele;
136 u8 ev_cfg_chan_shift;
137 u8 ev_src;
138 u8 ev_ths;
139 u8 ev_ths_mask;
140 u8 ev_count;
141 };
142
143 static const struct mma8452_event_regs ff_mt_ev_regs = {
144 .ev_cfg = MMA8452_FF_MT_CFG,
145 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
146 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
147 .ev_src = MMA8452_FF_MT_SRC,
148 .ev_ths = MMA8452_FF_MT_THS,
149 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
150 .ev_count = MMA8452_FF_MT_COUNT
151 };
152
153 static const struct mma8452_event_regs trans_ev_regs = {
154 .ev_cfg = MMA8452_TRANSIENT_CFG,
155 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
156 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
157 .ev_src = MMA8452_TRANSIENT_SRC,
158 .ev_ths = MMA8452_TRANSIENT_THS,
159 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
160 .ev_count = MMA8452_TRANSIENT_COUNT,
161 };
162
163 /**
164 * struct mma_chip_info - chip specific data
165 * @chip_id: WHO_AM_I register's value
166 * @channels: struct iio_chan_spec matching the device's
167 * capabilities
168 * @num_channels: number of channels
169 * @mma_scales: scale factors for converting register values
170 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
171 * per mode: m/s^2 and micro m/s^2
172 * @all_events: all events supported by this chip
173 * @enabled_events: event flags enabled and handled by this driver
174 */
175 struct mma_chip_info {
176 u8 chip_id;
177 const struct iio_chan_spec *channels;
178 int num_channels;
179 const int mma_scales[3][2];
180 int all_events;
181 int enabled_events;
182 };
183
184 enum {
185 idx_x,
186 idx_y,
187 idx_z,
188 idx_ts,
189 };
190
mma8452_drdy(struct mma8452_data * data)191 static int mma8452_drdy(struct mma8452_data *data)
192 {
193 int tries = 150;
194
195 while (tries-- > 0) {
196 int ret = i2c_smbus_read_byte_data(data->client,
197 MMA8452_STATUS);
198 if (ret < 0)
199 return ret;
200 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
201 return 0;
202
203 if (data->sleep_val <= 20)
204 usleep_range(data->sleep_val * 250,
205 data->sleep_val * 500);
206 else
207 msleep(20);
208 }
209
210 dev_err(&data->client->dev, "data not ready\n");
211
212 return -EIO;
213 }
214
mma8452_set_runtime_pm_state(struct i2c_client * client,bool on)215 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
216 {
217 #ifdef CONFIG_PM
218 int ret;
219
220 if (on) {
221 ret = pm_runtime_get_sync(&client->dev);
222 } else {
223 pm_runtime_mark_last_busy(&client->dev);
224 ret = pm_runtime_put_autosuspend(&client->dev);
225 }
226
227 if (ret < 0) {
228 dev_err(&client->dev,
229 "failed to change power state to %d\n", on);
230 if (on)
231 pm_runtime_put_noidle(&client->dev);
232
233 return ret;
234 }
235 #endif
236
237 return 0;
238 }
239
mma8452_read(struct mma8452_data * data,__be16 buf[3])240 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
241 {
242 int ret = mma8452_drdy(data);
243
244 if (ret < 0)
245 return ret;
246
247 ret = mma8452_set_runtime_pm_state(data->client, true);
248 if (ret)
249 return ret;
250
251 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
252 3 * sizeof(__be16), (u8 *)buf);
253
254 ret = mma8452_set_runtime_pm_state(data->client, false);
255
256 return ret;
257 }
258
mma8452_show_int_plus_micros(char * buf,const int (* vals)[2],int n)259 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
260 int n)
261 {
262 size_t len = 0;
263
264 while (n-- > 0)
265 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
266 vals[n][0], vals[n][1]);
267
268 /* replace trailing space by newline */
269 buf[len - 1] = '\n';
270
271 return len;
272 }
273
mma8452_get_int_plus_micros_index(const int (* vals)[2],int n,int val,int val2)274 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
275 int val, int val2)
276 {
277 while (n-- > 0)
278 if (val == vals[n][0] && val2 == vals[n][1])
279 return n;
280
281 return -EINVAL;
282 }
283
mma8452_get_odr_index(struct mma8452_data * data)284 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
285 {
286 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
287 MMA8452_CTRL_DR_SHIFT;
288 }
289
290 static const int mma8452_samp_freq[8][2] = {
291 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
292 {6, 250000}, {1, 560000}
293 };
294
295 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
296 static const unsigned int mma8452_time_step_us[4][8] = {
297 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
298 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
299 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
300 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
301 };
302
303 /* Datasheet table "High-Pass Filter Cutoff Options" */
304 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
305 { /* normal */
306 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
307 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
308 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
309 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
310 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
311 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
314 },
315 { /* low noise low power */
316 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
317 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
318 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
319 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
320 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
321 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
322 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
324 },
325 { /* high resolution */
326 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
327 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
334 },
335 { /* low power */
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
337 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
338 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
339 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
340 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
341 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
342 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
344 }
345 };
346
347 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
348 static const u16 mma8452_os_ratio[4][8] = {
349 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
350 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
351 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
352 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
353 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
354 };
355
mma8452_get_power_mode(struct mma8452_data * data)356 static int mma8452_get_power_mode(struct mma8452_data *data)
357 {
358 int reg;
359
360 reg = i2c_smbus_read_byte_data(data->client,
361 MMA8452_CTRL_REG2);
362 if (reg < 0)
363 return reg;
364
365 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
366 MMA8452_CTRL_REG2_MODS_SHIFT);
367 }
368
mma8452_show_samp_freq_avail(struct device * dev,struct device_attribute * attr,char * buf)369 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
370 struct device_attribute *attr,
371 char *buf)
372 {
373 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
374 ARRAY_SIZE(mma8452_samp_freq));
375 }
376
mma8452_show_scale_avail(struct device * dev,struct device_attribute * attr,char * buf)377 static ssize_t mma8452_show_scale_avail(struct device *dev,
378 struct device_attribute *attr,
379 char *buf)
380 {
381 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
382 to_i2c_client(dev)));
383
384 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
385 ARRAY_SIZE(data->chip_info->mma_scales));
386 }
387
mma8452_show_hp_cutoff_avail(struct device * dev,struct device_attribute * attr,char * buf)388 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
389 struct device_attribute *attr,
390 char *buf)
391 {
392 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
393 struct mma8452_data *data = iio_priv(indio_dev);
394 int i, j;
395
396 i = mma8452_get_odr_index(data);
397 j = mma8452_get_power_mode(data);
398 if (j < 0)
399 return j;
400
401 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
402 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
403 }
404
mma8452_show_os_ratio_avail(struct device * dev,struct device_attribute * attr,char * buf)405 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
406 struct device_attribute *attr,
407 char *buf)
408 {
409 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
410 struct mma8452_data *data = iio_priv(indio_dev);
411 int i = mma8452_get_odr_index(data);
412 int j;
413 u16 val = 0;
414 size_t len = 0;
415
416 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
417 if (val == mma8452_os_ratio[j][i])
418 continue;
419
420 val = mma8452_os_ratio[j][i];
421
422 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
423 }
424 buf[len - 1] = '\n';
425
426 return len;
427 }
428
429 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
430 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
431 mma8452_show_scale_avail, NULL, 0);
432 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
433 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
434 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
435 mma8452_show_os_ratio_avail, NULL, 0);
436
mma8452_get_samp_freq_index(struct mma8452_data * data,int val,int val2)437 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
438 int val, int val2)
439 {
440 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
441 ARRAY_SIZE(mma8452_samp_freq),
442 val, val2);
443 }
444
mma8452_get_scale_index(struct mma8452_data * data,int val,int val2)445 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
446 {
447 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
448 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
449 }
450
mma8452_get_hp_filter_index(struct mma8452_data * data,int val,int val2)451 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
452 int val, int val2)
453 {
454 int i, j;
455
456 i = mma8452_get_odr_index(data);
457 j = mma8452_get_power_mode(data);
458 if (j < 0)
459 return j;
460
461 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
462 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
463 }
464
mma8452_read_hp_filter(struct mma8452_data * data,int * hz,int * uHz)465 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
466 {
467 int j, i, ret;
468
469 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
470 if (ret < 0)
471 return ret;
472
473 i = mma8452_get_odr_index(data);
474 j = mma8452_get_power_mode(data);
475 if (j < 0)
476 return j;
477
478 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
479 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
480 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
481
482 return 0;
483 }
484
mma8452_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long mask)485 static int mma8452_read_raw(struct iio_dev *indio_dev,
486 struct iio_chan_spec const *chan,
487 int *val, int *val2, long mask)
488 {
489 struct mma8452_data *data = iio_priv(indio_dev);
490 __be16 buffer[3];
491 int i, ret;
492
493 switch (mask) {
494 case IIO_CHAN_INFO_RAW:
495 ret = iio_device_claim_direct_mode(indio_dev);
496 if (ret)
497 return ret;
498
499 mutex_lock(&data->lock);
500 ret = mma8452_read(data, buffer);
501 mutex_unlock(&data->lock);
502 iio_device_release_direct_mode(indio_dev);
503 if (ret < 0)
504 return ret;
505
506 *val = sign_extend32(be16_to_cpu(
507 buffer[chan->scan_index]) >> chan->scan_type.shift,
508 chan->scan_type.realbits - 1);
509
510 return IIO_VAL_INT;
511 case IIO_CHAN_INFO_SCALE:
512 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
513 *val = data->chip_info->mma_scales[i][0];
514 *val2 = data->chip_info->mma_scales[i][1];
515
516 return IIO_VAL_INT_PLUS_MICRO;
517 case IIO_CHAN_INFO_SAMP_FREQ:
518 i = mma8452_get_odr_index(data);
519 *val = mma8452_samp_freq[i][0];
520 *val2 = mma8452_samp_freq[i][1];
521
522 return IIO_VAL_INT_PLUS_MICRO;
523 case IIO_CHAN_INFO_CALIBBIAS:
524 ret = i2c_smbus_read_byte_data(data->client,
525 MMA8452_OFF_X +
526 chan->scan_index);
527 if (ret < 0)
528 return ret;
529
530 *val = sign_extend32(ret, 7);
531
532 return IIO_VAL_INT;
533 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
534 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
535 ret = mma8452_read_hp_filter(data, val, val2);
536 if (ret < 0)
537 return ret;
538 } else {
539 *val = 0;
540 *val2 = 0;
541 }
542
543 return IIO_VAL_INT_PLUS_MICRO;
544 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
545 ret = mma8452_get_power_mode(data);
546 if (ret < 0)
547 return ret;
548
549 i = mma8452_get_odr_index(data);
550
551 *val = mma8452_os_ratio[ret][i];
552 return IIO_VAL_INT;
553 }
554
555 return -EINVAL;
556 }
557
mma8452_calculate_sleep(struct mma8452_data * data)558 static int mma8452_calculate_sleep(struct mma8452_data *data)
559 {
560 int ret, i = mma8452_get_odr_index(data);
561
562 if (mma8452_samp_freq[i][0] > 0)
563 ret = 1000 / mma8452_samp_freq[i][0];
564 else
565 ret = 1000;
566
567 return ret == 0 ? 1 : ret;
568 }
569
mma8452_standby(struct mma8452_data * data)570 static int mma8452_standby(struct mma8452_data *data)
571 {
572 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
573 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
574 }
575
mma8452_active(struct mma8452_data * data)576 static int mma8452_active(struct mma8452_data *data)
577 {
578 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
579 data->ctrl_reg1);
580 }
581
582 /* returns >0 if active, 0 if in standby and <0 on error */
mma8452_is_active(struct mma8452_data * data)583 static int mma8452_is_active(struct mma8452_data *data)
584 {
585 int reg;
586
587 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
588 if (reg < 0)
589 return reg;
590
591 return reg & MMA8452_CTRL_ACTIVE;
592 }
593
mma8452_change_config(struct mma8452_data * data,u8 reg,u8 val)594 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
595 {
596 int ret;
597 int is_active;
598
599 mutex_lock(&data->lock);
600
601 is_active = mma8452_is_active(data);
602 if (is_active < 0) {
603 ret = is_active;
604 goto fail;
605 }
606
607 /* config can only be changed when in standby */
608 if (is_active > 0) {
609 ret = mma8452_standby(data);
610 if (ret < 0)
611 goto fail;
612 }
613
614 ret = i2c_smbus_write_byte_data(data->client, reg, val);
615 if (ret < 0)
616 goto fail;
617
618 if (is_active > 0) {
619 ret = mma8452_active(data);
620 if (ret < 0)
621 goto fail;
622 }
623
624 ret = 0;
625 fail:
626 mutex_unlock(&data->lock);
627
628 return ret;
629 }
630
mma8452_set_power_mode(struct mma8452_data * data,u8 mode)631 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
632 {
633 int reg;
634
635 reg = i2c_smbus_read_byte_data(data->client,
636 MMA8452_CTRL_REG2);
637 if (reg < 0)
638 return reg;
639
640 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
641 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
642
643 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
644 }
645
646 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
mma8452_freefall_mode_enabled(struct mma8452_data * data)647 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
648 {
649 int val;
650
651 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
652 if (val < 0)
653 return val;
654
655 return !(val & MMA8452_FF_MT_CFG_OAE);
656 }
657
mma8452_set_freefall_mode(struct mma8452_data * data,bool state)658 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
659 {
660 int val;
661
662 if ((state && mma8452_freefall_mode_enabled(data)) ||
663 (!state && !(mma8452_freefall_mode_enabled(data))))
664 return 0;
665
666 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
667 if (val < 0)
668 return val;
669
670 if (state) {
671 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
672 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
673 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
674 val &= ~MMA8452_FF_MT_CFG_OAE;
675 } else {
676 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
677 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
678 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
679 val |= MMA8452_FF_MT_CFG_OAE;
680 }
681
682 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
683 }
684
mma8452_set_hp_filter_frequency(struct mma8452_data * data,int val,int val2)685 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
686 int val, int val2)
687 {
688 int i, reg;
689
690 i = mma8452_get_hp_filter_index(data, val, val2);
691 if (i < 0)
692 return i;
693
694 reg = i2c_smbus_read_byte_data(data->client,
695 MMA8452_HP_FILTER_CUTOFF);
696 if (reg < 0)
697 return reg;
698
699 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
700 reg |= i;
701
702 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
703 }
704
mma8452_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)705 static int mma8452_write_raw(struct iio_dev *indio_dev,
706 struct iio_chan_spec const *chan,
707 int val, int val2, long mask)
708 {
709 struct mma8452_data *data = iio_priv(indio_dev);
710 int i, ret;
711
712 ret = iio_device_claim_direct_mode(indio_dev);
713 if (ret)
714 return ret;
715
716 switch (mask) {
717 case IIO_CHAN_INFO_SAMP_FREQ:
718 i = mma8452_get_samp_freq_index(data, val, val2);
719 if (i < 0) {
720 ret = i;
721 break;
722 }
723 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
724 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
725
726 data->sleep_val = mma8452_calculate_sleep(data);
727
728 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
729 data->ctrl_reg1);
730 break;
731 case IIO_CHAN_INFO_SCALE:
732 i = mma8452_get_scale_index(data, val, val2);
733 if (i < 0) {
734 ret = i;
735 break;
736 }
737
738 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
739 data->data_cfg |= i;
740
741 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
742 data->data_cfg);
743 break;
744 case IIO_CHAN_INFO_CALIBBIAS:
745 if (val < -128 || val > 127) {
746 ret = -EINVAL;
747 break;
748 }
749
750 ret = mma8452_change_config(data,
751 MMA8452_OFF_X + chan->scan_index,
752 val);
753 break;
754
755 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
756 if (val == 0 && val2 == 0) {
757 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
758 } else {
759 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
760 ret = mma8452_set_hp_filter_frequency(data, val, val2);
761 if (ret < 0)
762 break;
763 }
764
765 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
766 data->data_cfg);
767 break;
768
769 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
770 ret = mma8452_get_odr_index(data);
771
772 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
773 if (mma8452_os_ratio[i][ret] == val) {
774 ret = mma8452_set_power_mode(data, i);
775 break;
776 }
777 }
778 break;
779 default:
780 ret = -EINVAL;
781 break;
782 }
783
784 iio_device_release_direct_mode(indio_dev);
785 return ret;
786 }
787
mma8452_get_event_regs(struct mma8452_data * data,const struct iio_chan_spec * chan,enum iio_event_direction dir,const struct mma8452_event_regs ** ev_reg)788 static int mma8452_get_event_regs(struct mma8452_data *data,
789 const struct iio_chan_spec *chan, enum iio_event_direction dir,
790 const struct mma8452_event_regs **ev_reg)
791 {
792 if (!chan)
793 return -EINVAL;
794
795 switch (chan->type) {
796 case IIO_ACCEL:
797 switch (dir) {
798 case IIO_EV_DIR_RISING:
799 if ((data->chip_info->all_events
800 & MMA8452_INT_TRANS) &&
801 (data->chip_info->enabled_events
802 & MMA8452_INT_TRANS))
803 *ev_reg = &trans_ev_regs;
804 else
805 *ev_reg = &ff_mt_ev_regs;
806 return 0;
807 case IIO_EV_DIR_FALLING:
808 *ev_reg = &ff_mt_ev_regs;
809 return 0;
810 default:
811 return -EINVAL;
812 }
813 default:
814 return -EINVAL;
815 }
816 }
817
mma8452_read_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int * val,int * val2)818 static int mma8452_read_event_value(struct iio_dev *indio_dev,
819 const struct iio_chan_spec *chan,
820 enum iio_event_type type,
821 enum iio_event_direction dir,
822 enum iio_event_info info,
823 int *val, int *val2)
824 {
825 struct mma8452_data *data = iio_priv(indio_dev);
826 int ret, us, power_mode;
827 const struct mma8452_event_regs *ev_regs;
828
829 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
830 if (ret)
831 return ret;
832
833 switch (info) {
834 case IIO_EV_INFO_VALUE:
835 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
836 if (ret < 0)
837 return ret;
838
839 *val = ret & ev_regs->ev_ths_mask;
840
841 return IIO_VAL_INT;
842
843 case IIO_EV_INFO_PERIOD:
844 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
845 if (ret < 0)
846 return ret;
847
848 power_mode = mma8452_get_power_mode(data);
849 if (power_mode < 0)
850 return power_mode;
851
852 us = ret * mma8452_time_step_us[power_mode][
853 mma8452_get_odr_index(data)];
854 *val = us / USEC_PER_SEC;
855 *val2 = us % USEC_PER_SEC;
856
857 return IIO_VAL_INT_PLUS_MICRO;
858
859 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
860 ret = i2c_smbus_read_byte_data(data->client,
861 MMA8452_TRANSIENT_CFG);
862 if (ret < 0)
863 return ret;
864
865 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
866 *val = 0;
867 *val2 = 0;
868 } else {
869 ret = mma8452_read_hp_filter(data, val, val2);
870 if (ret < 0)
871 return ret;
872 }
873
874 return IIO_VAL_INT_PLUS_MICRO;
875
876 default:
877 return -EINVAL;
878 }
879 }
880
mma8452_write_event_value(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,enum iio_event_info info,int val,int val2)881 static int mma8452_write_event_value(struct iio_dev *indio_dev,
882 const struct iio_chan_spec *chan,
883 enum iio_event_type type,
884 enum iio_event_direction dir,
885 enum iio_event_info info,
886 int val, int val2)
887 {
888 struct mma8452_data *data = iio_priv(indio_dev);
889 int ret, reg, steps;
890 const struct mma8452_event_regs *ev_regs;
891
892 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
893 if (ret)
894 return ret;
895
896 switch (info) {
897 case IIO_EV_INFO_VALUE:
898 if (val < 0 || val > ev_regs->ev_ths_mask)
899 return -EINVAL;
900
901 return mma8452_change_config(data, ev_regs->ev_ths, val);
902
903 case IIO_EV_INFO_PERIOD:
904 ret = mma8452_get_power_mode(data);
905 if (ret < 0)
906 return ret;
907
908 steps = (val * USEC_PER_SEC + val2) /
909 mma8452_time_step_us[ret][
910 mma8452_get_odr_index(data)];
911
912 if (steps < 0 || steps > 0xff)
913 return -EINVAL;
914
915 return mma8452_change_config(data, ev_regs->ev_count, steps);
916
917 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
918 reg = i2c_smbus_read_byte_data(data->client,
919 MMA8452_TRANSIENT_CFG);
920 if (reg < 0)
921 return reg;
922
923 if (val == 0 && val2 == 0) {
924 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
925 } else {
926 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
927 ret = mma8452_set_hp_filter_frequency(data, val, val2);
928 if (ret < 0)
929 return ret;
930 }
931
932 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
933
934 default:
935 return -EINVAL;
936 }
937 }
938
mma8452_read_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir)939 static int mma8452_read_event_config(struct iio_dev *indio_dev,
940 const struct iio_chan_spec *chan,
941 enum iio_event_type type,
942 enum iio_event_direction dir)
943 {
944 struct mma8452_data *data = iio_priv(indio_dev);
945 int ret;
946 const struct mma8452_event_regs *ev_regs;
947
948 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
949 if (ret)
950 return ret;
951
952 switch (dir) {
953 case IIO_EV_DIR_FALLING:
954 return mma8452_freefall_mode_enabled(data);
955 case IIO_EV_DIR_RISING:
956 ret = i2c_smbus_read_byte_data(data->client,
957 ev_regs->ev_cfg);
958 if (ret < 0)
959 return ret;
960
961 return !!(ret & BIT(chan->scan_index +
962 ev_regs->ev_cfg_chan_shift));
963 default:
964 return -EINVAL;
965 }
966 }
967
mma8452_write_event_config(struct iio_dev * indio_dev,const struct iio_chan_spec * chan,enum iio_event_type type,enum iio_event_direction dir,int state)968 static int mma8452_write_event_config(struct iio_dev *indio_dev,
969 const struct iio_chan_spec *chan,
970 enum iio_event_type type,
971 enum iio_event_direction dir,
972 int state)
973 {
974 struct mma8452_data *data = iio_priv(indio_dev);
975 int val, ret;
976 const struct mma8452_event_regs *ev_regs;
977
978 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
979 if (ret)
980 return ret;
981
982 ret = mma8452_set_runtime_pm_state(data->client, state);
983 if (ret)
984 return ret;
985
986 switch (dir) {
987 case IIO_EV_DIR_FALLING:
988 return mma8452_set_freefall_mode(data, state);
989 case IIO_EV_DIR_RISING:
990 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
991 if (val < 0)
992 return val;
993
994 if (state) {
995 if (mma8452_freefall_mode_enabled(data)) {
996 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
997 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
998 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
999 val |= MMA8452_FF_MT_CFG_OAE;
1000 }
1001 val |= BIT(chan->scan_index +
1002 ev_regs->ev_cfg_chan_shift);
1003 } else {
1004 if (mma8452_freefall_mode_enabled(data))
1005 return 0;
1006
1007 val &= ~BIT(chan->scan_index +
1008 ev_regs->ev_cfg_chan_shift);
1009 }
1010
1011 val |= ev_regs->ev_cfg_ele;
1012
1013 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1014 default:
1015 return -EINVAL;
1016 }
1017 }
1018
mma8452_transient_interrupt(struct iio_dev * indio_dev)1019 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1020 {
1021 struct mma8452_data *data = iio_priv(indio_dev);
1022 s64 ts = iio_get_time_ns(indio_dev);
1023 int src;
1024
1025 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1026 if (src < 0)
1027 return;
1028
1029 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1030 iio_push_event(indio_dev,
1031 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1032 IIO_EV_TYPE_MAG,
1033 IIO_EV_DIR_RISING),
1034 ts);
1035
1036 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1037 iio_push_event(indio_dev,
1038 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1039 IIO_EV_TYPE_MAG,
1040 IIO_EV_DIR_RISING),
1041 ts);
1042
1043 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1044 iio_push_event(indio_dev,
1045 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1046 IIO_EV_TYPE_MAG,
1047 IIO_EV_DIR_RISING),
1048 ts);
1049 }
1050
mma8452_interrupt(int irq,void * p)1051 static irqreturn_t mma8452_interrupt(int irq, void *p)
1052 {
1053 struct iio_dev *indio_dev = p;
1054 struct mma8452_data *data = iio_priv(indio_dev);
1055 int ret = IRQ_NONE;
1056 int src;
1057
1058 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1059 if (src < 0)
1060 return IRQ_NONE;
1061
1062 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1063 return IRQ_NONE;
1064
1065 if (src & MMA8452_INT_DRDY) {
1066 iio_trigger_poll_chained(indio_dev->trig);
1067 ret = IRQ_HANDLED;
1068 }
1069
1070 if (src & MMA8452_INT_FF_MT) {
1071 if (mma8452_freefall_mode_enabled(data)) {
1072 s64 ts = iio_get_time_ns(indio_dev);
1073
1074 iio_push_event(indio_dev,
1075 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1076 IIO_MOD_X_AND_Y_AND_Z,
1077 IIO_EV_TYPE_MAG,
1078 IIO_EV_DIR_FALLING),
1079 ts);
1080 }
1081 ret = IRQ_HANDLED;
1082 }
1083
1084 if (src & MMA8452_INT_TRANS) {
1085 mma8452_transient_interrupt(indio_dev);
1086 ret = IRQ_HANDLED;
1087 }
1088
1089 return ret;
1090 }
1091
mma8452_trigger_handler(int irq,void * p)1092 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1093 {
1094 struct iio_poll_func *pf = p;
1095 struct iio_dev *indio_dev = pf->indio_dev;
1096 struct mma8452_data *data = iio_priv(indio_dev);
1097 int ret;
1098
1099 ret = mma8452_read(data, data->buffer.channels);
1100 if (ret < 0)
1101 goto done;
1102
1103 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1104 iio_get_time_ns(indio_dev));
1105
1106 done:
1107 iio_trigger_notify_done(indio_dev->trig);
1108
1109 return IRQ_HANDLED;
1110 }
1111
mma8452_reg_access_dbg(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)1112 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1113 unsigned int reg, unsigned int writeval,
1114 unsigned int *readval)
1115 {
1116 int ret;
1117 struct mma8452_data *data = iio_priv(indio_dev);
1118
1119 if (reg > MMA8452_MAX_REG)
1120 return -EINVAL;
1121
1122 if (!readval)
1123 return mma8452_change_config(data, reg, writeval);
1124
1125 ret = i2c_smbus_read_byte_data(data->client, reg);
1126 if (ret < 0)
1127 return ret;
1128
1129 *readval = ret;
1130
1131 return 0;
1132 }
1133
1134 static const struct iio_event_spec mma8452_freefall_event[] = {
1135 {
1136 .type = IIO_EV_TYPE_MAG,
1137 .dir = IIO_EV_DIR_FALLING,
1138 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1139 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1140 BIT(IIO_EV_INFO_PERIOD) |
1141 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1142 },
1143 };
1144
1145 static const struct iio_event_spec mma8652_freefall_event[] = {
1146 {
1147 .type = IIO_EV_TYPE_MAG,
1148 .dir = IIO_EV_DIR_FALLING,
1149 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1150 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1151 BIT(IIO_EV_INFO_PERIOD)
1152 },
1153 };
1154
1155 static const struct iio_event_spec mma8452_transient_event[] = {
1156 {
1157 .type = IIO_EV_TYPE_MAG,
1158 .dir = IIO_EV_DIR_RISING,
1159 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1160 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1161 BIT(IIO_EV_INFO_PERIOD) |
1162 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1163 },
1164 };
1165
1166 static const struct iio_event_spec mma8452_motion_event[] = {
1167 {
1168 .type = IIO_EV_TYPE_MAG,
1169 .dir = IIO_EV_DIR_RISING,
1170 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1171 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1172 BIT(IIO_EV_INFO_PERIOD)
1173 },
1174 };
1175
1176 /*
1177 * Threshold is configured in fixed 8G/127 steps regardless of
1178 * currently selected scale for measurement.
1179 */
1180 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1181
1182 static struct attribute *mma8452_event_attributes[] = {
1183 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1184 NULL,
1185 };
1186
1187 static struct attribute_group mma8452_event_attribute_group = {
1188 .attrs = mma8452_event_attributes,
1189 };
1190
1191 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1192 .type = IIO_ACCEL, \
1193 .modified = 1, \
1194 .channel2 = modifier, \
1195 .scan_index = -1, \
1196 .event_spec = mma8452_freefall_event, \
1197 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1198 }
1199
1200 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1201 .type = IIO_ACCEL, \
1202 .modified = 1, \
1203 .channel2 = modifier, \
1204 .scan_index = -1, \
1205 .event_spec = mma8652_freefall_event, \
1206 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1207 }
1208
1209 #define MMA8452_CHANNEL(axis, idx, bits) { \
1210 .type = IIO_ACCEL, \
1211 .modified = 1, \
1212 .channel2 = IIO_MOD_##axis, \
1213 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1214 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1215 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1216 BIT(IIO_CHAN_INFO_SCALE) | \
1217 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1218 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1219 .scan_index = idx, \
1220 .scan_type = { \
1221 .sign = 's', \
1222 .realbits = (bits), \
1223 .storagebits = 16, \
1224 .shift = 16 - (bits), \
1225 .endianness = IIO_BE, \
1226 }, \
1227 .event_spec = mma8452_transient_event, \
1228 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1229 }
1230
1231 #define MMA8652_CHANNEL(axis, idx, bits) { \
1232 .type = IIO_ACCEL, \
1233 .modified = 1, \
1234 .channel2 = IIO_MOD_##axis, \
1235 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1236 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1237 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1238 BIT(IIO_CHAN_INFO_SCALE) | \
1239 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1240 .scan_index = idx, \
1241 .scan_type = { \
1242 .sign = 's', \
1243 .realbits = (bits), \
1244 .storagebits = 16, \
1245 .shift = 16 - (bits), \
1246 .endianness = IIO_BE, \
1247 }, \
1248 .event_spec = mma8452_motion_event, \
1249 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1250 }
1251
1252 static const struct iio_chan_spec mma8451_channels[] = {
1253 MMA8452_CHANNEL(X, idx_x, 14),
1254 MMA8452_CHANNEL(Y, idx_y, 14),
1255 MMA8452_CHANNEL(Z, idx_z, 14),
1256 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1257 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1258 };
1259
1260 static const struct iio_chan_spec mma8452_channels[] = {
1261 MMA8452_CHANNEL(X, idx_x, 12),
1262 MMA8452_CHANNEL(Y, idx_y, 12),
1263 MMA8452_CHANNEL(Z, idx_z, 12),
1264 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1265 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1266 };
1267
1268 static const struct iio_chan_spec mma8453_channels[] = {
1269 MMA8452_CHANNEL(X, idx_x, 10),
1270 MMA8452_CHANNEL(Y, idx_y, 10),
1271 MMA8452_CHANNEL(Z, idx_z, 10),
1272 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1273 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1274 };
1275
1276 static const struct iio_chan_spec mma8652_channels[] = {
1277 MMA8652_CHANNEL(X, idx_x, 12),
1278 MMA8652_CHANNEL(Y, idx_y, 12),
1279 MMA8652_CHANNEL(Z, idx_z, 12),
1280 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1281 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1282 };
1283
1284 static const struct iio_chan_spec mma8653_channels[] = {
1285 MMA8652_CHANNEL(X, idx_x, 10),
1286 MMA8652_CHANNEL(Y, idx_y, 10),
1287 MMA8652_CHANNEL(Z, idx_z, 10),
1288 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1289 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1290 };
1291
1292 enum {
1293 mma8451,
1294 mma8452,
1295 mma8453,
1296 mma8652,
1297 mma8653,
1298 fxls8471,
1299 };
1300
1301 static const struct mma_chip_info mma_chip_info_table[] = {
1302 [mma8451] = {
1303 .chip_id = MMA8451_DEVICE_ID,
1304 .channels = mma8451_channels,
1305 .num_channels = ARRAY_SIZE(mma8451_channels),
1306 /*
1307 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1308 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1309 * bit.
1310 * The userspace interface uses m/s^2 and we declare micro units
1311 * So scale factor for 12 bit here is given by:
1312 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1313 */
1314 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1315 /*
1316 * Although we enable the interrupt sources once and for
1317 * all here the event detection itself is not enabled until
1318 * userspace asks for it by mma8452_write_event_config()
1319 */
1320 .all_events = MMA8452_INT_DRDY |
1321 MMA8452_INT_TRANS |
1322 MMA8452_INT_FF_MT,
1323 .enabled_events = MMA8452_INT_TRANS |
1324 MMA8452_INT_FF_MT,
1325 },
1326 [mma8452] = {
1327 .chip_id = MMA8452_DEVICE_ID,
1328 .channels = mma8452_channels,
1329 .num_channels = ARRAY_SIZE(mma8452_channels),
1330 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1331 /*
1332 * Although we enable the interrupt sources once and for
1333 * all here the event detection itself is not enabled until
1334 * userspace asks for it by mma8452_write_event_config()
1335 */
1336 .all_events = MMA8452_INT_DRDY |
1337 MMA8452_INT_TRANS |
1338 MMA8452_INT_FF_MT,
1339 .enabled_events = MMA8452_INT_TRANS |
1340 MMA8452_INT_FF_MT,
1341 },
1342 [mma8453] = {
1343 .chip_id = MMA8453_DEVICE_ID,
1344 .channels = mma8453_channels,
1345 .num_channels = ARRAY_SIZE(mma8453_channels),
1346 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1347 /*
1348 * Although we enable the interrupt sources once and for
1349 * all here the event detection itself is not enabled until
1350 * userspace asks for it by mma8452_write_event_config()
1351 */
1352 .all_events = MMA8452_INT_DRDY |
1353 MMA8452_INT_TRANS |
1354 MMA8452_INT_FF_MT,
1355 .enabled_events = MMA8452_INT_TRANS |
1356 MMA8452_INT_FF_MT,
1357 },
1358 [mma8652] = {
1359 .chip_id = MMA8652_DEVICE_ID,
1360 .channels = mma8652_channels,
1361 .num_channels = ARRAY_SIZE(mma8652_channels),
1362 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1363 .all_events = MMA8452_INT_DRDY |
1364 MMA8452_INT_FF_MT,
1365 .enabled_events = MMA8452_INT_FF_MT,
1366 },
1367 [mma8653] = {
1368 .chip_id = MMA8653_DEVICE_ID,
1369 .channels = mma8653_channels,
1370 .num_channels = ARRAY_SIZE(mma8653_channels),
1371 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1372 /*
1373 * Although we enable the interrupt sources once and for
1374 * all here the event detection itself is not enabled until
1375 * userspace asks for it by mma8452_write_event_config()
1376 */
1377 .all_events = MMA8452_INT_DRDY |
1378 MMA8452_INT_FF_MT,
1379 .enabled_events = MMA8452_INT_FF_MT,
1380 },
1381 [fxls8471] = {
1382 .chip_id = FXLS8471_DEVICE_ID,
1383 .channels = mma8451_channels,
1384 .num_channels = ARRAY_SIZE(mma8451_channels),
1385 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1386 /*
1387 * Although we enable the interrupt sources once and for
1388 * all here the event detection itself is not enabled until
1389 * userspace asks for it by mma8452_write_event_config()
1390 */
1391 .all_events = MMA8452_INT_DRDY |
1392 MMA8452_INT_TRANS |
1393 MMA8452_INT_FF_MT,
1394 .enabled_events = MMA8452_INT_TRANS |
1395 MMA8452_INT_FF_MT,
1396 },
1397 };
1398
1399 static struct attribute *mma8452_attributes[] = {
1400 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1401 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1402 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1403 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1404 NULL
1405 };
1406
1407 static const struct attribute_group mma8452_group = {
1408 .attrs = mma8452_attributes,
1409 };
1410
1411 static const struct iio_info mma8452_info = {
1412 .attrs = &mma8452_group,
1413 .read_raw = &mma8452_read_raw,
1414 .write_raw = &mma8452_write_raw,
1415 .event_attrs = &mma8452_event_attribute_group,
1416 .read_event_value = &mma8452_read_event_value,
1417 .write_event_value = &mma8452_write_event_value,
1418 .read_event_config = &mma8452_read_event_config,
1419 .write_event_config = &mma8452_write_event_config,
1420 .debugfs_reg_access = &mma8452_reg_access_dbg,
1421 };
1422
1423 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1424
mma8452_data_rdy_trigger_set_state(struct iio_trigger * trig,bool state)1425 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1426 bool state)
1427 {
1428 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1429 struct mma8452_data *data = iio_priv(indio_dev);
1430 int reg, ret;
1431
1432 ret = mma8452_set_runtime_pm_state(data->client, state);
1433 if (ret)
1434 return ret;
1435
1436 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1437 if (reg < 0)
1438 return reg;
1439
1440 if (state)
1441 reg |= MMA8452_INT_DRDY;
1442 else
1443 reg &= ~MMA8452_INT_DRDY;
1444
1445 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1446 }
1447
1448 static const struct iio_trigger_ops mma8452_trigger_ops = {
1449 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1450 .validate_device = iio_trigger_validate_own_device,
1451 };
1452
mma8452_trigger_setup(struct iio_dev * indio_dev)1453 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1454 {
1455 struct mma8452_data *data = iio_priv(indio_dev);
1456 struct iio_trigger *trig;
1457 int ret;
1458
1459 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1460 indio_dev->name,
1461 indio_dev->id);
1462 if (!trig)
1463 return -ENOMEM;
1464
1465 trig->dev.parent = &data->client->dev;
1466 trig->ops = &mma8452_trigger_ops;
1467 iio_trigger_set_drvdata(trig, indio_dev);
1468
1469 ret = iio_trigger_register(trig);
1470 if (ret)
1471 return ret;
1472
1473 indio_dev->trig = trig;
1474
1475 return 0;
1476 }
1477
mma8452_trigger_cleanup(struct iio_dev * indio_dev)1478 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1479 {
1480 if (indio_dev->trig)
1481 iio_trigger_unregister(indio_dev->trig);
1482 }
1483
mma8452_reset(struct i2c_client * client)1484 static int mma8452_reset(struct i2c_client *client)
1485 {
1486 int i;
1487 int ret;
1488
1489 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1490 MMA8452_CTRL_REG2_RST);
1491 if (ret < 0)
1492 return ret;
1493
1494 for (i = 0; i < 10; i++) {
1495 usleep_range(100, 200);
1496 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1497 if (ret == -EIO)
1498 continue; /* I2C comm reset */
1499 if (ret < 0)
1500 return ret;
1501 if (!(ret & MMA8452_CTRL_REG2_RST))
1502 return 0;
1503 }
1504
1505 return -ETIMEDOUT;
1506 }
1507
1508 static const struct of_device_id mma8452_dt_ids[] = {
1509 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1510 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1511 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1512 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1513 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1514 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1515 { }
1516 };
1517 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1518
mma8452_probe(struct i2c_client * client,const struct i2c_device_id * id)1519 static int mma8452_probe(struct i2c_client *client,
1520 const struct i2c_device_id *id)
1521 {
1522 struct mma8452_data *data;
1523 struct iio_dev *indio_dev;
1524 int ret;
1525 const struct of_device_id *match;
1526
1527 match = of_match_device(mma8452_dt_ids, &client->dev);
1528 if (!match) {
1529 dev_err(&client->dev, "unknown device model\n");
1530 return -ENODEV;
1531 }
1532
1533 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1534 if (!indio_dev)
1535 return -ENOMEM;
1536
1537 data = iio_priv(indio_dev);
1538 data->client = client;
1539 mutex_init(&data->lock);
1540 data->chip_info = match->data;
1541
1542 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1543 if (ret < 0)
1544 return ret;
1545
1546 switch (ret) {
1547 case MMA8451_DEVICE_ID:
1548 case MMA8452_DEVICE_ID:
1549 case MMA8453_DEVICE_ID:
1550 case MMA8652_DEVICE_ID:
1551 case MMA8653_DEVICE_ID:
1552 case FXLS8471_DEVICE_ID:
1553 if (ret == data->chip_info->chip_id)
1554 break;
1555 /* else: fall through */
1556 default:
1557 return -ENODEV;
1558 }
1559
1560 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1561 match->compatible, data->chip_info->chip_id);
1562
1563 i2c_set_clientdata(client, indio_dev);
1564 indio_dev->info = &mma8452_info;
1565 indio_dev->name = id->name;
1566 indio_dev->dev.parent = &client->dev;
1567 indio_dev->modes = INDIO_DIRECT_MODE;
1568 indio_dev->channels = data->chip_info->channels;
1569 indio_dev->num_channels = data->chip_info->num_channels;
1570 indio_dev->available_scan_masks = mma8452_scan_masks;
1571
1572 ret = mma8452_reset(client);
1573 if (ret < 0)
1574 return ret;
1575
1576 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1577 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1578 data->data_cfg);
1579 if (ret < 0)
1580 return ret;
1581
1582 /*
1583 * By default set transient threshold to max to avoid events if
1584 * enabling without configuring threshold.
1585 */
1586 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1587 MMA8452_TRANSIENT_THS_MASK);
1588 if (ret < 0)
1589 return ret;
1590
1591 if (client->irq) {
1592 int irq2;
1593
1594 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1595
1596 if (irq2 == client->irq) {
1597 dev_dbg(&client->dev, "using interrupt line INT2\n");
1598 } else {
1599 ret = i2c_smbus_write_byte_data(client,
1600 MMA8452_CTRL_REG5,
1601 data->chip_info->all_events);
1602 if (ret < 0)
1603 return ret;
1604
1605 dev_dbg(&client->dev, "using interrupt line INT1\n");
1606 }
1607
1608 ret = i2c_smbus_write_byte_data(client,
1609 MMA8452_CTRL_REG4,
1610 data->chip_info->enabled_events);
1611 if (ret < 0)
1612 return ret;
1613
1614 ret = mma8452_trigger_setup(indio_dev);
1615 if (ret < 0)
1616 return ret;
1617 }
1618
1619 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1620 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1621
1622 data->sleep_val = mma8452_calculate_sleep(data);
1623
1624 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1625 data->ctrl_reg1);
1626 if (ret < 0)
1627 goto trigger_cleanup;
1628
1629 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1630 mma8452_trigger_handler, NULL);
1631 if (ret < 0)
1632 goto trigger_cleanup;
1633
1634 if (client->irq) {
1635 ret = devm_request_threaded_irq(&client->dev,
1636 client->irq,
1637 NULL, mma8452_interrupt,
1638 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1639 client->name, indio_dev);
1640 if (ret)
1641 goto buffer_cleanup;
1642 }
1643
1644 ret = pm_runtime_set_active(&client->dev);
1645 if (ret < 0)
1646 goto buffer_cleanup;
1647
1648 pm_runtime_enable(&client->dev);
1649 pm_runtime_set_autosuspend_delay(&client->dev,
1650 MMA8452_AUTO_SUSPEND_DELAY_MS);
1651 pm_runtime_use_autosuspend(&client->dev);
1652
1653 ret = iio_device_register(indio_dev);
1654 if (ret < 0)
1655 goto buffer_cleanup;
1656
1657 ret = mma8452_set_freefall_mode(data, false);
1658 if (ret < 0)
1659 goto unregister_device;
1660
1661 return 0;
1662
1663 unregister_device:
1664 iio_device_unregister(indio_dev);
1665
1666 buffer_cleanup:
1667 iio_triggered_buffer_cleanup(indio_dev);
1668
1669 trigger_cleanup:
1670 mma8452_trigger_cleanup(indio_dev);
1671
1672 return ret;
1673 }
1674
mma8452_remove(struct i2c_client * client)1675 static int mma8452_remove(struct i2c_client *client)
1676 {
1677 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1678
1679 iio_device_unregister(indio_dev);
1680
1681 pm_runtime_disable(&client->dev);
1682 pm_runtime_set_suspended(&client->dev);
1683 pm_runtime_put_noidle(&client->dev);
1684
1685 iio_triggered_buffer_cleanup(indio_dev);
1686 mma8452_trigger_cleanup(indio_dev);
1687 mma8452_standby(iio_priv(indio_dev));
1688
1689 return 0;
1690 }
1691
1692 #ifdef CONFIG_PM
mma8452_runtime_suspend(struct device * dev)1693 static int mma8452_runtime_suspend(struct device *dev)
1694 {
1695 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1696 struct mma8452_data *data = iio_priv(indio_dev);
1697 int ret;
1698
1699 mutex_lock(&data->lock);
1700 ret = mma8452_standby(data);
1701 mutex_unlock(&data->lock);
1702 if (ret < 0) {
1703 dev_err(&data->client->dev, "powering off device failed\n");
1704 return -EAGAIN;
1705 }
1706
1707 return 0;
1708 }
1709
mma8452_runtime_resume(struct device * dev)1710 static int mma8452_runtime_resume(struct device *dev)
1711 {
1712 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1713 struct mma8452_data *data = iio_priv(indio_dev);
1714 int ret, sleep_val;
1715
1716 ret = mma8452_active(data);
1717 if (ret < 0)
1718 return ret;
1719
1720 ret = mma8452_get_odr_index(data);
1721 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1722 if (sleep_val < 20)
1723 usleep_range(sleep_val * 1000, 20000);
1724 else
1725 msleep_interruptible(sleep_val);
1726
1727 return 0;
1728 }
1729 #endif
1730
1731 #ifdef CONFIG_PM_SLEEP
mma8452_suspend(struct device * dev)1732 static int mma8452_suspend(struct device *dev)
1733 {
1734 return mma8452_standby(iio_priv(i2c_get_clientdata(
1735 to_i2c_client(dev))));
1736 }
1737
mma8452_resume(struct device * dev)1738 static int mma8452_resume(struct device *dev)
1739 {
1740 return mma8452_active(iio_priv(i2c_get_clientdata(
1741 to_i2c_client(dev))));
1742 }
1743 #endif
1744
1745 static const struct dev_pm_ops mma8452_pm_ops = {
1746 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1747 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1748 mma8452_runtime_resume, NULL)
1749 };
1750
1751 static const struct i2c_device_id mma8452_id[] = {
1752 { "mma8451", mma8451 },
1753 { "mma8452", mma8452 },
1754 { "mma8453", mma8453 },
1755 { "mma8652", mma8652 },
1756 { "mma8653", mma8653 },
1757 { "fxls8471", fxls8471 },
1758 { }
1759 };
1760 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1761
1762 static struct i2c_driver mma8452_driver = {
1763 .driver = {
1764 .name = "mma8452",
1765 .of_match_table = of_match_ptr(mma8452_dt_ids),
1766 .pm = &mma8452_pm_ops,
1767 },
1768 .probe = mma8452_probe,
1769 .remove = mma8452_remove,
1770 .id_table = mma8452_id,
1771 };
1772 module_i2c_driver(mma8452_driver);
1773
1774 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1775 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1776 MODULE_LICENSE("GPL");
1777