1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments ADS7950 SPI ADC driver
4 *
5 * Copyright 2016 David Lechner <david@lechnology.com>
6 *
7 * Based on iio/ad7923.c:
8 * Copyright 2011 Analog Devices Inc
9 * Copyright 2012 CS Systemes d'Information
10 *
11 * And also on hwmon/ads79xx.c
12 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
13 * Nishanth Menon
14 */
15
16 #include <linux/acpi.h>
17 #include <linux/bitops.h>
18 #include <linux/device.h>
19 #include <linux/err.h>
20 #include <linux/interrupt.h>
21 #include <linux/kernel.h>
22 #include <linux/module.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/slab.h>
25 #include <linux/spi/spi.h>
26
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/sysfs.h>
30 #include <linux/iio/trigger_consumer.h>
31 #include <linux/iio/triggered_buffer.h>
32
33 /*
34 * In case of ACPI, we use the 5000 mV as default for the reference pin.
35 * Device tree users encode that via the vref-supply regulator.
36 */
37 #define TI_ADS7950_VA_MV_ACPI_DEFAULT 5000
38
39 #define TI_ADS7950_CR_MANUAL BIT(12)
40 #define TI_ADS7950_CR_WRITE BIT(11)
41 #define TI_ADS7950_CR_CHAN(ch) ((ch) << 7)
42 #define TI_ADS7950_CR_RANGE_5V BIT(6)
43
44 #define TI_ADS7950_MAX_CHAN 16
45
46 #define TI_ADS7950_TIMESTAMP_SIZE (sizeof(int64_t) / sizeof(__be16))
47
48 /* val = value, dec = left shift, bits = number of bits of the mask */
49 #define TI_ADS7950_EXTRACT(val, dec, bits) \
50 (((val) >> (dec)) & ((1 << (bits)) - 1))
51
52 struct ti_ads7950_state {
53 struct spi_device *spi;
54 struct spi_transfer ring_xfer[TI_ADS7950_MAX_CHAN + 2];
55 struct spi_transfer scan_single_xfer[3];
56 struct spi_message ring_msg;
57 struct spi_message scan_single_msg;
58
59 /* Lock to protect the spi xfer buffers */
60 struct mutex slock;
61
62 struct regulator *reg;
63 unsigned int vref_mv;
64
65 unsigned int settings;
66
67 /*
68 * DMA (thus cache coherency maintenance) requires the
69 * transfer buffers to live in their own cache lines.
70 */
71 __be16 rx_buf[TI_ADS7950_MAX_CHAN + TI_ADS7950_TIMESTAMP_SIZE]
72 ____cacheline_aligned;
73 __be16 tx_buf[TI_ADS7950_MAX_CHAN];
74 __be16 single_tx;
75 __be16 single_rx;
76
77 };
78
79 struct ti_ads7950_chip_info {
80 const struct iio_chan_spec *channels;
81 unsigned int num_channels;
82 };
83
84 enum ti_ads7950_id {
85 TI_ADS7950,
86 TI_ADS7951,
87 TI_ADS7952,
88 TI_ADS7953,
89 TI_ADS7954,
90 TI_ADS7955,
91 TI_ADS7956,
92 TI_ADS7957,
93 TI_ADS7958,
94 TI_ADS7959,
95 TI_ADS7960,
96 TI_ADS7961,
97 };
98
99 #define TI_ADS7950_V_CHAN(index, bits) \
100 { \
101 .type = IIO_VOLTAGE, \
102 .indexed = 1, \
103 .channel = index, \
104 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
105 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
106 .address = index, \
107 .datasheet_name = "CH##index", \
108 .scan_index = index, \
109 .scan_type = { \
110 .sign = 'u', \
111 .realbits = bits, \
112 .storagebits = 16, \
113 .shift = 12 - (bits), \
114 .endianness = IIO_BE, \
115 }, \
116 }
117
118 #define DECLARE_TI_ADS7950_4_CHANNELS(name, bits) \
119 const struct iio_chan_spec name ## _channels[] = { \
120 TI_ADS7950_V_CHAN(0, bits), \
121 TI_ADS7950_V_CHAN(1, bits), \
122 TI_ADS7950_V_CHAN(2, bits), \
123 TI_ADS7950_V_CHAN(3, bits), \
124 IIO_CHAN_SOFT_TIMESTAMP(4), \
125 }
126
127 #define DECLARE_TI_ADS7950_8_CHANNELS(name, bits) \
128 const struct iio_chan_spec name ## _channels[] = { \
129 TI_ADS7950_V_CHAN(0, bits), \
130 TI_ADS7950_V_CHAN(1, bits), \
131 TI_ADS7950_V_CHAN(2, bits), \
132 TI_ADS7950_V_CHAN(3, bits), \
133 TI_ADS7950_V_CHAN(4, bits), \
134 TI_ADS7950_V_CHAN(5, bits), \
135 TI_ADS7950_V_CHAN(6, bits), \
136 TI_ADS7950_V_CHAN(7, bits), \
137 IIO_CHAN_SOFT_TIMESTAMP(8), \
138 }
139
140 #define DECLARE_TI_ADS7950_12_CHANNELS(name, bits) \
141 const struct iio_chan_spec name ## _channels[] = { \
142 TI_ADS7950_V_CHAN(0, bits), \
143 TI_ADS7950_V_CHAN(1, bits), \
144 TI_ADS7950_V_CHAN(2, bits), \
145 TI_ADS7950_V_CHAN(3, bits), \
146 TI_ADS7950_V_CHAN(4, bits), \
147 TI_ADS7950_V_CHAN(5, bits), \
148 TI_ADS7950_V_CHAN(6, bits), \
149 TI_ADS7950_V_CHAN(7, bits), \
150 TI_ADS7950_V_CHAN(8, bits), \
151 TI_ADS7950_V_CHAN(9, bits), \
152 TI_ADS7950_V_CHAN(10, bits), \
153 TI_ADS7950_V_CHAN(11, bits), \
154 IIO_CHAN_SOFT_TIMESTAMP(12), \
155 }
156
157 #define DECLARE_TI_ADS7950_16_CHANNELS(name, bits) \
158 const struct iio_chan_spec name ## _channels[] = { \
159 TI_ADS7950_V_CHAN(0, bits), \
160 TI_ADS7950_V_CHAN(1, bits), \
161 TI_ADS7950_V_CHAN(2, bits), \
162 TI_ADS7950_V_CHAN(3, bits), \
163 TI_ADS7950_V_CHAN(4, bits), \
164 TI_ADS7950_V_CHAN(5, bits), \
165 TI_ADS7950_V_CHAN(6, bits), \
166 TI_ADS7950_V_CHAN(7, bits), \
167 TI_ADS7950_V_CHAN(8, bits), \
168 TI_ADS7950_V_CHAN(9, bits), \
169 TI_ADS7950_V_CHAN(10, bits), \
170 TI_ADS7950_V_CHAN(11, bits), \
171 TI_ADS7950_V_CHAN(12, bits), \
172 TI_ADS7950_V_CHAN(13, bits), \
173 TI_ADS7950_V_CHAN(14, bits), \
174 TI_ADS7950_V_CHAN(15, bits), \
175 IIO_CHAN_SOFT_TIMESTAMP(16), \
176 }
177
178 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7950, 12);
179 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7951, 12);
180 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7952, 12);
181 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7953, 12);
182 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7954, 10);
183 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7955, 10);
184 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7956, 10);
185 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7957, 10);
186 static DECLARE_TI_ADS7950_4_CHANNELS(ti_ads7958, 8);
187 static DECLARE_TI_ADS7950_8_CHANNELS(ti_ads7959, 8);
188 static DECLARE_TI_ADS7950_12_CHANNELS(ti_ads7960, 8);
189 static DECLARE_TI_ADS7950_16_CHANNELS(ti_ads7961, 8);
190
191 static const struct ti_ads7950_chip_info ti_ads7950_chip_info[] = {
192 [TI_ADS7950] = {
193 .channels = ti_ads7950_channels,
194 .num_channels = ARRAY_SIZE(ti_ads7950_channels),
195 },
196 [TI_ADS7951] = {
197 .channels = ti_ads7951_channels,
198 .num_channels = ARRAY_SIZE(ti_ads7951_channels),
199 },
200 [TI_ADS7952] = {
201 .channels = ti_ads7952_channels,
202 .num_channels = ARRAY_SIZE(ti_ads7952_channels),
203 },
204 [TI_ADS7953] = {
205 .channels = ti_ads7953_channels,
206 .num_channels = ARRAY_SIZE(ti_ads7953_channels),
207 },
208 [TI_ADS7954] = {
209 .channels = ti_ads7954_channels,
210 .num_channels = ARRAY_SIZE(ti_ads7954_channels),
211 },
212 [TI_ADS7955] = {
213 .channels = ti_ads7955_channels,
214 .num_channels = ARRAY_SIZE(ti_ads7955_channels),
215 },
216 [TI_ADS7956] = {
217 .channels = ti_ads7956_channels,
218 .num_channels = ARRAY_SIZE(ti_ads7956_channels),
219 },
220 [TI_ADS7957] = {
221 .channels = ti_ads7957_channels,
222 .num_channels = ARRAY_SIZE(ti_ads7957_channels),
223 },
224 [TI_ADS7958] = {
225 .channels = ti_ads7958_channels,
226 .num_channels = ARRAY_SIZE(ti_ads7958_channels),
227 },
228 [TI_ADS7959] = {
229 .channels = ti_ads7959_channels,
230 .num_channels = ARRAY_SIZE(ti_ads7959_channels),
231 },
232 [TI_ADS7960] = {
233 .channels = ti_ads7960_channels,
234 .num_channels = ARRAY_SIZE(ti_ads7960_channels),
235 },
236 [TI_ADS7961] = {
237 .channels = ti_ads7961_channels,
238 .num_channels = ARRAY_SIZE(ti_ads7961_channels),
239 },
240 };
241
242 /*
243 * ti_ads7950_update_scan_mode() setup the spi transfer buffer for the new
244 * scan mask
245 */
ti_ads7950_update_scan_mode(struct iio_dev * indio_dev,const unsigned long * active_scan_mask)246 static int ti_ads7950_update_scan_mode(struct iio_dev *indio_dev,
247 const unsigned long *active_scan_mask)
248 {
249 struct ti_ads7950_state *st = iio_priv(indio_dev);
250 int i, cmd, len;
251
252 len = 0;
253 for_each_set_bit(i, active_scan_mask, indio_dev->num_channels) {
254 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(i) | st->settings;
255 st->tx_buf[len++] = cpu_to_be16(cmd);
256 }
257
258 /* Data for the 1st channel is not returned until the 3rd transfer */
259 len += 2;
260 for (i = 0; i < len; i++) {
261 if ((i + 2) < len)
262 st->ring_xfer[i].tx_buf = &st->tx_buf[i];
263 if (i >= 2)
264 st->ring_xfer[i].rx_buf = &st->rx_buf[i - 2];
265 st->ring_xfer[i].len = 2;
266 st->ring_xfer[i].cs_change = 1;
267 }
268 /* make sure last transfer's cs_change is not set */
269 st->ring_xfer[len - 1].cs_change = 0;
270
271 spi_message_init_with_transfers(&st->ring_msg, st->ring_xfer, len);
272
273 return 0;
274 }
275
ti_ads7950_trigger_handler(int irq,void * p)276 static irqreturn_t ti_ads7950_trigger_handler(int irq, void *p)
277 {
278 struct iio_poll_func *pf = p;
279 struct iio_dev *indio_dev = pf->indio_dev;
280 struct ti_ads7950_state *st = iio_priv(indio_dev);
281 int ret;
282
283 mutex_lock(&st->slock);
284 ret = spi_sync(st->spi, &st->ring_msg);
285 if (ret < 0)
286 goto out;
287
288 iio_push_to_buffers_with_timestamp(indio_dev, st->rx_buf,
289 iio_get_time_ns(indio_dev));
290
291 out:
292 mutex_unlock(&st->slock);
293 iio_trigger_notify_done(indio_dev->trig);
294
295 return IRQ_HANDLED;
296 }
297
ti_ads7950_scan_direct(struct iio_dev * indio_dev,unsigned int ch)298 static int ti_ads7950_scan_direct(struct iio_dev *indio_dev, unsigned int ch)
299 {
300 struct ti_ads7950_state *st = iio_priv(indio_dev);
301 int ret, cmd;
302
303 mutex_lock(&st->slock);
304
305 cmd = TI_ADS7950_CR_WRITE | TI_ADS7950_CR_CHAN(ch) | st->settings;
306 st->single_tx = cpu_to_be16(cmd);
307
308 ret = spi_sync(st->spi, &st->scan_single_msg);
309 if (ret)
310 goto out;
311
312 ret = be16_to_cpu(st->single_rx);
313
314 out:
315 mutex_unlock(&st->slock);
316
317 return ret;
318 }
319
ti_ads7950_get_range(struct ti_ads7950_state * st)320 static int ti_ads7950_get_range(struct ti_ads7950_state *st)
321 {
322 int vref;
323
324 if (st->vref_mv) {
325 vref = st->vref_mv;
326 } else {
327 vref = regulator_get_voltage(st->reg);
328 if (vref < 0)
329 return vref;
330
331 vref /= 1000;
332 }
333
334 if (st->settings & TI_ADS7950_CR_RANGE_5V)
335 vref *= 2;
336
337 return vref;
338 }
339
ti_ads7950_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long m)340 static int ti_ads7950_read_raw(struct iio_dev *indio_dev,
341 struct iio_chan_spec const *chan,
342 int *val, int *val2, long m)
343 {
344 struct ti_ads7950_state *st = iio_priv(indio_dev);
345 int ret;
346
347 switch (m) {
348 case IIO_CHAN_INFO_RAW:
349 ret = ti_ads7950_scan_direct(indio_dev, chan->address);
350 if (ret < 0)
351 return ret;
352
353 if (chan->address != TI_ADS7950_EXTRACT(ret, 12, 4))
354 return -EIO;
355
356 *val = TI_ADS7950_EXTRACT(ret, chan->scan_type.shift,
357 chan->scan_type.realbits);
358
359 return IIO_VAL_INT;
360 case IIO_CHAN_INFO_SCALE:
361 ret = ti_ads7950_get_range(st);
362 if (ret < 0)
363 return ret;
364
365 *val = ret;
366 *val2 = (1 << chan->scan_type.realbits) - 1;
367
368 return IIO_VAL_FRACTIONAL;
369 }
370
371 return -EINVAL;
372 }
373
374 static const struct iio_info ti_ads7950_info = {
375 .read_raw = &ti_ads7950_read_raw,
376 .update_scan_mode = ti_ads7950_update_scan_mode,
377 };
378
ti_ads7950_probe(struct spi_device * spi)379 static int ti_ads7950_probe(struct spi_device *spi)
380 {
381 struct ti_ads7950_state *st;
382 struct iio_dev *indio_dev;
383 const struct ti_ads7950_chip_info *info;
384 int ret;
385
386 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
387 if (!indio_dev)
388 return -ENOMEM;
389
390 st = iio_priv(indio_dev);
391
392 spi_set_drvdata(spi, indio_dev);
393
394 st->spi = spi;
395 st->settings = TI_ADS7950_CR_MANUAL | TI_ADS7950_CR_RANGE_5V;
396
397 info = &ti_ads7950_chip_info[spi_get_device_id(spi)->driver_data];
398
399 indio_dev->name = spi_get_device_id(spi)->name;
400 indio_dev->dev.parent = &spi->dev;
401 indio_dev->modes = INDIO_DIRECT_MODE;
402 indio_dev->channels = info->channels;
403 indio_dev->num_channels = info->num_channels;
404 indio_dev->info = &ti_ads7950_info;
405
406 /*
407 * Setup default message. The sample is read at the end of the first
408 * transfer, then it takes one full cycle to convert the sample and one
409 * more cycle to send the value. The conversion process is driven by
410 * the SPI clock, which is why we have 3 transfers. The middle one is
411 * just dummy data sent while the chip is converting the sample that
412 * was read at the end of the first transfer.
413 */
414
415 st->scan_single_xfer[0].tx_buf = &st->single_tx;
416 st->scan_single_xfer[0].len = 2;
417 st->scan_single_xfer[0].cs_change = 1;
418 st->scan_single_xfer[1].tx_buf = &st->single_tx;
419 st->scan_single_xfer[1].len = 2;
420 st->scan_single_xfer[1].cs_change = 1;
421 st->scan_single_xfer[2].rx_buf = &st->single_rx;
422 st->scan_single_xfer[2].len = 2;
423
424 spi_message_init_with_transfers(&st->scan_single_msg,
425 st->scan_single_xfer, 3);
426
427 /* Use hard coded value for reference voltage in ACPI case */
428 if (ACPI_COMPANION(&spi->dev))
429 st->vref_mv = TI_ADS7950_VA_MV_ACPI_DEFAULT;
430
431 mutex_init(&st->slock);
432
433 st->reg = devm_regulator_get(&spi->dev, "vref");
434 if (IS_ERR(st->reg)) {
435 dev_err(&spi->dev, "Failed get get regulator \"vref\"\n");
436 ret = PTR_ERR(st->reg);
437 goto error_destroy_mutex;
438 }
439
440 ret = regulator_enable(st->reg);
441 if (ret) {
442 dev_err(&spi->dev, "Failed to enable regulator \"vref\"\n");
443 goto error_destroy_mutex;
444 }
445
446 ret = iio_triggered_buffer_setup(indio_dev, NULL,
447 &ti_ads7950_trigger_handler, NULL);
448 if (ret) {
449 dev_err(&spi->dev, "Failed to setup triggered buffer\n");
450 goto error_disable_reg;
451 }
452
453 ret = iio_device_register(indio_dev);
454 if (ret) {
455 dev_err(&spi->dev, "Failed to register iio device\n");
456 goto error_cleanup_ring;
457 }
458
459 return 0;
460
461 error_cleanup_ring:
462 iio_triggered_buffer_cleanup(indio_dev);
463 error_disable_reg:
464 regulator_disable(st->reg);
465 error_destroy_mutex:
466 mutex_destroy(&st->slock);
467
468 return ret;
469 }
470
ti_ads7950_remove(struct spi_device * spi)471 static int ti_ads7950_remove(struct spi_device *spi)
472 {
473 struct iio_dev *indio_dev = spi_get_drvdata(spi);
474 struct ti_ads7950_state *st = iio_priv(indio_dev);
475
476 iio_device_unregister(indio_dev);
477 iio_triggered_buffer_cleanup(indio_dev);
478 regulator_disable(st->reg);
479 mutex_destroy(&st->slock);
480
481 return 0;
482 }
483
484 static const struct spi_device_id ti_ads7950_id[] = {
485 { "ads7950", TI_ADS7950 },
486 { "ads7951", TI_ADS7951 },
487 { "ads7952", TI_ADS7952 },
488 { "ads7953", TI_ADS7953 },
489 { "ads7954", TI_ADS7954 },
490 { "ads7955", TI_ADS7955 },
491 { "ads7956", TI_ADS7956 },
492 { "ads7957", TI_ADS7957 },
493 { "ads7958", TI_ADS7958 },
494 { "ads7959", TI_ADS7959 },
495 { "ads7960", TI_ADS7960 },
496 { "ads7961", TI_ADS7961 },
497 { }
498 };
499 MODULE_DEVICE_TABLE(spi, ti_ads7950_id);
500
501 static const struct of_device_id ads7950_of_table[] = {
502 { .compatible = "ti,ads7950", .data = &ti_ads7950_chip_info[TI_ADS7950] },
503 { .compatible = "ti,ads7951", .data = &ti_ads7950_chip_info[TI_ADS7951] },
504 { .compatible = "ti,ads7952", .data = &ti_ads7950_chip_info[TI_ADS7952] },
505 { .compatible = "ti,ads7953", .data = &ti_ads7950_chip_info[TI_ADS7953] },
506 { .compatible = "ti,ads7954", .data = &ti_ads7950_chip_info[TI_ADS7954] },
507 { .compatible = "ti,ads7955", .data = &ti_ads7950_chip_info[TI_ADS7955] },
508 { .compatible = "ti,ads7956", .data = &ti_ads7950_chip_info[TI_ADS7956] },
509 { .compatible = "ti,ads7957", .data = &ti_ads7950_chip_info[TI_ADS7957] },
510 { .compatible = "ti,ads7958", .data = &ti_ads7950_chip_info[TI_ADS7958] },
511 { .compatible = "ti,ads7959", .data = &ti_ads7950_chip_info[TI_ADS7959] },
512 { .compatible = "ti,ads7960", .data = &ti_ads7950_chip_info[TI_ADS7960] },
513 { .compatible = "ti,ads7961", .data = &ti_ads7950_chip_info[TI_ADS7961] },
514 { },
515 };
516 MODULE_DEVICE_TABLE(of, ads7950_of_table);
517
518 static struct spi_driver ti_ads7950_driver = {
519 .driver = {
520 .name = "ads7950",
521 .of_match_table = ads7950_of_table,
522 },
523 .probe = ti_ads7950_probe,
524 .remove = ti_ads7950_remove,
525 .id_table = ti_ads7950_id,
526 };
527 module_spi_driver(ti_ads7950_driver);
528
529 MODULE_AUTHOR("David Lechner <david@lechnology.com>");
530 MODULE_DESCRIPTION("TI TI_ADS7950 ADC");
531 MODULE_LICENSE("GPL v2");
532