1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/pci.h>
35 #include <linux/platform_device.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_umem.h>
38 #include "hns_roce_common.h"
39 #include "hns_roce_device.h"
40 #include "hns_roce_hem.h"
41 #include <rdma/hns-abi.h>
42
43 #define SQP_NUM (2 * HNS_ROCE_MAX_PORTS)
44
hns_roce_qp_event(struct hns_roce_dev * hr_dev,u32 qpn,int event_type)45 void hns_roce_qp_event(struct hns_roce_dev *hr_dev, u32 qpn, int event_type)
46 {
47 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
48 struct device *dev = hr_dev->dev;
49 struct hns_roce_qp *qp;
50
51 spin_lock(&qp_table->lock);
52
53 qp = __hns_roce_qp_lookup(hr_dev, qpn);
54 if (qp)
55 atomic_inc(&qp->refcount);
56
57 spin_unlock(&qp_table->lock);
58
59 if (!qp) {
60 dev_warn(dev, "Async event for bogus QP %08x\n", qpn);
61 return;
62 }
63
64 qp->event(qp, (enum hns_roce_event)event_type);
65
66 if (atomic_dec_and_test(&qp->refcount))
67 complete(&qp->free);
68 }
69 EXPORT_SYMBOL_GPL(hns_roce_qp_event);
70
hns_roce_ib_qp_event(struct hns_roce_qp * hr_qp,enum hns_roce_event type)71 static void hns_roce_ib_qp_event(struct hns_roce_qp *hr_qp,
72 enum hns_roce_event type)
73 {
74 struct ib_event event;
75 struct ib_qp *ibqp = &hr_qp->ibqp;
76
77 if (ibqp->event_handler) {
78 event.device = ibqp->device;
79 event.element.qp = ibqp;
80 switch (type) {
81 case HNS_ROCE_EVENT_TYPE_PATH_MIG:
82 event.event = IB_EVENT_PATH_MIG;
83 break;
84 case HNS_ROCE_EVENT_TYPE_COMM_EST:
85 event.event = IB_EVENT_COMM_EST;
86 break;
87 case HNS_ROCE_EVENT_TYPE_SQ_DRAINED:
88 event.event = IB_EVENT_SQ_DRAINED;
89 break;
90 case HNS_ROCE_EVENT_TYPE_SRQ_LAST_WQE_REACH:
91 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
92 break;
93 case HNS_ROCE_EVENT_TYPE_WQ_CATAS_ERROR:
94 event.event = IB_EVENT_QP_FATAL;
95 break;
96 case HNS_ROCE_EVENT_TYPE_PATH_MIG_FAILED:
97 event.event = IB_EVENT_PATH_MIG_ERR;
98 break;
99 case HNS_ROCE_EVENT_TYPE_INV_REQ_LOCAL_WQ_ERROR:
100 event.event = IB_EVENT_QP_REQ_ERR;
101 break;
102 case HNS_ROCE_EVENT_TYPE_LOCAL_WQ_ACCESS_ERROR:
103 event.event = IB_EVENT_QP_ACCESS_ERR;
104 break;
105 default:
106 dev_dbg(ibqp->device->dev.parent, "roce_ib: Unexpected event type %d on QP %06lx\n",
107 type, hr_qp->qpn);
108 return;
109 }
110 ibqp->event_handler(&event, ibqp->qp_context);
111 }
112 }
113
hns_roce_reserve_range_qp(struct hns_roce_dev * hr_dev,int cnt,int align,unsigned long * base)114 static int hns_roce_reserve_range_qp(struct hns_roce_dev *hr_dev, int cnt,
115 int align, unsigned long *base)
116 {
117 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
118
119 return hns_roce_bitmap_alloc_range(&qp_table->bitmap, cnt, align,
120 base) ?
121 -ENOMEM :
122 0;
123 }
124
to_hns_roce_state(enum ib_qp_state state)125 enum hns_roce_qp_state to_hns_roce_state(enum ib_qp_state state)
126 {
127 switch (state) {
128 case IB_QPS_RESET:
129 return HNS_ROCE_QP_STATE_RST;
130 case IB_QPS_INIT:
131 return HNS_ROCE_QP_STATE_INIT;
132 case IB_QPS_RTR:
133 return HNS_ROCE_QP_STATE_RTR;
134 case IB_QPS_RTS:
135 return HNS_ROCE_QP_STATE_RTS;
136 case IB_QPS_SQD:
137 return HNS_ROCE_QP_STATE_SQD;
138 case IB_QPS_ERR:
139 return HNS_ROCE_QP_STATE_ERR;
140 default:
141 return HNS_ROCE_QP_NUM_STATE;
142 }
143 }
144 EXPORT_SYMBOL_GPL(to_hns_roce_state);
145
hns_roce_gsi_qp_alloc(struct hns_roce_dev * hr_dev,unsigned long qpn,struct hns_roce_qp * hr_qp)146 static int hns_roce_gsi_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
147 struct hns_roce_qp *hr_qp)
148 {
149 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
150 int ret;
151
152 if (!qpn)
153 return -EINVAL;
154
155 hr_qp->qpn = qpn;
156
157 spin_lock_irq(&qp_table->lock);
158 ret = radix_tree_insert(&hr_dev->qp_table_tree,
159 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
160 spin_unlock_irq(&qp_table->lock);
161 if (ret) {
162 dev_err(hr_dev->dev, "QPC radix_tree_insert failed\n");
163 goto err_put_irrl;
164 }
165
166 atomic_set(&hr_qp->refcount, 1);
167 init_completion(&hr_qp->free);
168
169 return 0;
170
171 err_put_irrl:
172
173 return ret;
174 }
175
hns_roce_qp_alloc(struct hns_roce_dev * hr_dev,unsigned long qpn,struct hns_roce_qp * hr_qp)176 static int hns_roce_qp_alloc(struct hns_roce_dev *hr_dev, unsigned long qpn,
177 struct hns_roce_qp *hr_qp)
178 {
179 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
180 struct device *dev = hr_dev->dev;
181 int ret;
182
183 if (!qpn)
184 return -EINVAL;
185
186 hr_qp->qpn = qpn;
187
188 /* Alloc memory for QPC */
189 ret = hns_roce_table_get(hr_dev, &qp_table->qp_table, hr_qp->qpn);
190 if (ret) {
191 dev_err(dev, "QPC table get failed\n");
192 goto err_out;
193 }
194
195 /* Alloc memory for IRRL */
196 ret = hns_roce_table_get(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
197 if (ret) {
198 dev_err(dev, "IRRL table get failed\n");
199 goto err_put_qp;
200 }
201
202 if (hr_dev->caps.trrl_entry_sz) {
203 /* Alloc memory for TRRL */
204 ret = hns_roce_table_get(hr_dev, &qp_table->trrl_table,
205 hr_qp->qpn);
206 if (ret) {
207 dev_err(dev, "TRRL table get failed\n");
208 goto err_put_irrl;
209 }
210 }
211
212 spin_lock_irq(&qp_table->lock);
213 ret = radix_tree_insert(&hr_dev->qp_table_tree,
214 hr_qp->qpn & (hr_dev->caps.num_qps - 1), hr_qp);
215 spin_unlock_irq(&qp_table->lock);
216 if (ret) {
217 dev_err(dev, "QPC radix_tree_insert failed\n");
218 goto err_put_trrl;
219 }
220
221 atomic_set(&hr_qp->refcount, 1);
222 init_completion(&hr_qp->free);
223
224 return 0;
225
226 err_put_trrl:
227 if (hr_dev->caps.trrl_entry_sz)
228 hns_roce_table_put(hr_dev, &qp_table->trrl_table, hr_qp->qpn);
229
230 err_put_irrl:
231 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
232
233 err_put_qp:
234 hns_roce_table_put(hr_dev, &qp_table->qp_table, hr_qp->qpn);
235
236 err_out:
237 return ret;
238 }
239
hns_roce_qp_remove(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)240 void hns_roce_qp_remove(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
241 {
242 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
243 unsigned long flags;
244
245 spin_lock_irqsave(&qp_table->lock, flags);
246 radix_tree_delete(&hr_dev->qp_table_tree,
247 hr_qp->qpn & (hr_dev->caps.num_qps - 1));
248 spin_unlock_irqrestore(&qp_table->lock, flags);
249 }
250 EXPORT_SYMBOL_GPL(hns_roce_qp_remove);
251
hns_roce_qp_free(struct hns_roce_dev * hr_dev,struct hns_roce_qp * hr_qp)252 void hns_roce_qp_free(struct hns_roce_dev *hr_dev, struct hns_roce_qp *hr_qp)
253 {
254 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
255
256 if (atomic_dec_and_test(&hr_qp->refcount))
257 complete(&hr_qp->free);
258 wait_for_completion(&hr_qp->free);
259
260 if ((hr_qp->ibqp.qp_type) != IB_QPT_GSI) {
261 if (hr_dev->caps.trrl_entry_sz)
262 hns_roce_table_put(hr_dev, &qp_table->trrl_table,
263 hr_qp->qpn);
264 hns_roce_table_put(hr_dev, &qp_table->irrl_table, hr_qp->qpn);
265 }
266 }
267 EXPORT_SYMBOL_GPL(hns_roce_qp_free);
268
hns_roce_release_range_qp(struct hns_roce_dev * hr_dev,int base_qpn,int cnt)269 void hns_roce_release_range_qp(struct hns_roce_dev *hr_dev, int base_qpn,
270 int cnt)
271 {
272 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
273
274 if (base_qpn < SQP_NUM)
275 return;
276
277 hns_roce_bitmap_free_range(&qp_table->bitmap, base_qpn, cnt, BITMAP_RR);
278 }
279 EXPORT_SYMBOL_GPL(hns_roce_release_range_qp);
280
hns_roce_set_rq_size(struct hns_roce_dev * hr_dev,struct ib_qp_cap * cap,int is_user,int has_srq,struct hns_roce_qp * hr_qp)281 static int hns_roce_set_rq_size(struct hns_roce_dev *hr_dev,
282 struct ib_qp_cap *cap, int is_user, int has_srq,
283 struct hns_roce_qp *hr_qp)
284 {
285 struct device *dev = hr_dev->dev;
286 u32 max_cnt;
287
288 /* Check the validity of QP support capacity */
289 if (cap->max_recv_wr > hr_dev->caps.max_wqes ||
290 cap->max_recv_sge > hr_dev->caps.max_rq_sg) {
291 dev_err(dev, "RQ WR or sge error!max_recv_wr=%d max_recv_sge=%d\n",
292 cap->max_recv_wr, cap->max_recv_sge);
293 return -EINVAL;
294 }
295
296 /* If srq exit, set zero for relative number of rq */
297 if (has_srq) {
298 if (cap->max_recv_wr) {
299 dev_dbg(dev, "srq no need config max_recv_wr\n");
300 return -EINVAL;
301 }
302
303 hr_qp->rq.wqe_cnt = hr_qp->rq.max_gs = 0;
304 } else {
305 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge)) {
306 dev_err(dev, "user space no need config max_recv_wr max_recv_sge\n");
307 return -EINVAL;
308 }
309
310 if (hr_dev->caps.min_wqes)
311 max_cnt = max(cap->max_recv_wr, hr_dev->caps.min_wqes);
312 else
313 max_cnt = cap->max_recv_wr;
314
315 hr_qp->rq.wqe_cnt = roundup_pow_of_two(max_cnt);
316
317 if ((u32)hr_qp->rq.wqe_cnt > hr_dev->caps.max_wqes) {
318 dev_err(dev, "while setting rq size, rq.wqe_cnt too large\n");
319 return -EINVAL;
320 }
321
322 max_cnt = max(1U, cap->max_recv_sge);
323 hr_qp->rq.max_gs = roundup_pow_of_two(max_cnt);
324 if (hr_dev->caps.max_rq_sg <= 2)
325 hr_qp->rq.wqe_shift =
326 ilog2(hr_dev->caps.max_rq_desc_sz);
327 else
328 hr_qp->rq.wqe_shift =
329 ilog2(hr_dev->caps.max_rq_desc_sz
330 * hr_qp->rq.max_gs);
331 }
332
333 cap->max_recv_wr = hr_qp->rq.max_post = hr_qp->rq.wqe_cnt;
334 cap->max_recv_sge = hr_qp->rq.max_gs;
335
336 return 0;
337 }
338
hns_roce_set_user_sq_size(struct hns_roce_dev * hr_dev,struct ib_qp_cap * cap,struct hns_roce_qp * hr_qp,struct hns_roce_ib_create_qp * ucmd)339 static int hns_roce_set_user_sq_size(struct hns_roce_dev *hr_dev,
340 struct ib_qp_cap *cap,
341 struct hns_roce_qp *hr_qp,
342 struct hns_roce_ib_create_qp *ucmd)
343 {
344 u32 roundup_sq_stride = roundup_pow_of_two(hr_dev->caps.max_sq_desc_sz);
345 u8 max_sq_stride = ilog2(roundup_sq_stride);
346 u32 page_size;
347 u32 max_cnt;
348
349 /* Sanity check SQ size before proceeding */
350 if ((u32)(1 << ucmd->log_sq_bb_count) > hr_dev->caps.max_wqes ||
351 ucmd->log_sq_stride > max_sq_stride ||
352 ucmd->log_sq_stride < HNS_ROCE_IB_MIN_SQ_STRIDE) {
353 dev_err(hr_dev->dev, "check SQ size error!\n");
354 return -EINVAL;
355 }
356
357 if (cap->max_send_sge > hr_dev->caps.max_sq_sg) {
358 dev_err(hr_dev->dev, "SQ sge error! max_send_sge=%d\n",
359 cap->max_send_sge);
360 return -EINVAL;
361 }
362
363 hr_qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
364 hr_qp->sq.wqe_shift = ucmd->log_sq_stride;
365
366 max_cnt = max(1U, cap->max_send_sge);
367 if (hr_dev->caps.max_sq_sg <= 2)
368 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
369 else
370 hr_qp->sq.max_gs = max_cnt;
371
372 if (hr_qp->sq.max_gs > 2)
373 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
374 (hr_qp->sq.max_gs - 2));
375
376 if ((hr_qp->sq.max_gs > 2) && (hr_dev->pci_dev->revision == 0x20)) {
377 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
378 dev_err(hr_dev->dev,
379 "The extended sge cnt error! sge_cnt=%d\n",
380 hr_qp->sge.sge_cnt);
381 return -EINVAL;
382 }
383 }
384
385 hr_qp->sge.sge_shift = 4;
386
387 /* Get buf size, SQ and RQ are aligned to page_szie */
388 if (hr_dev->caps.max_sq_sg <= 2) {
389 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
390 hr_qp->rq.wqe_shift), PAGE_SIZE) +
391 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
392 hr_qp->sq.wqe_shift), PAGE_SIZE);
393
394 hr_qp->sq.offset = 0;
395 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
396 hr_qp->sq.wqe_shift), PAGE_SIZE);
397 } else {
398 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
399 hr_qp->buff_size = HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt <<
400 hr_qp->rq.wqe_shift), page_size) +
401 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
402 hr_qp->sge.sge_shift), page_size) +
403 HNS_ROCE_ALOGN_UP((hr_qp->sq.wqe_cnt <<
404 hr_qp->sq.wqe_shift), page_size);
405
406 hr_qp->sq.offset = 0;
407 if (hr_qp->sge.sge_cnt) {
408 hr_qp->sge.offset = HNS_ROCE_ALOGN_UP(
409 (hr_qp->sq.wqe_cnt <<
410 hr_qp->sq.wqe_shift),
411 page_size);
412 hr_qp->rq.offset = hr_qp->sge.offset +
413 HNS_ROCE_ALOGN_UP((hr_qp->sge.sge_cnt <<
414 hr_qp->sge.sge_shift),
415 page_size);
416 } else {
417 hr_qp->rq.offset = HNS_ROCE_ALOGN_UP(
418 (hr_qp->sq.wqe_cnt <<
419 hr_qp->sq.wqe_shift),
420 page_size);
421 }
422 }
423
424 return 0;
425 }
426
hns_roce_set_kernel_sq_size(struct hns_roce_dev * hr_dev,struct ib_qp_cap * cap,struct hns_roce_qp * hr_qp)427 static int hns_roce_set_kernel_sq_size(struct hns_roce_dev *hr_dev,
428 struct ib_qp_cap *cap,
429 struct hns_roce_qp *hr_qp)
430 {
431 struct device *dev = hr_dev->dev;
432 u32 page_size;
433 u32 max_cnt;
434 int size;
435
436 if (cap->max_send_wr > hr_dev->caps.max_wqes ||
437 cap->max_send_sge > hr_dev->caps.max_sq_sg ||
438 cap->max_inline_data > hr_dev->caps.max_sq_inline) {
439 dev_err(dev, "SQ WR or sge or inline data error!\n");
440 return -EINVAL;
441 }
442
443 hr_qp->sq.wqe_shift = ilog2(hr_dev->caps.max_sq_desc_sz);
444 hr_qp->sq_max_wqes_per_wr = 1;
445 hr_qp->sq_spare_wqes = 0;
446
447 if (hr_dev->caps.min_wqes)
448 max_cnt = max(cap->max_send_wr, hr_dev->caps.min_wqes);
449 else
450 max_cnt = cap->max_send_wr;
451
452 hr_qp->sq.wqe_cnt = roundup_pow_of_two(max_cnt);
453 if ((u32)hr_qp->sq.wqe_cnt > hr_dev->caps.max_wqes) {
454 dev_err(dev, "while setting kernel sq size, sq.wqe_cnt too large\n");
455 return -EINVAL;
456 }
457
458 /* Get data_seg numbers */
459 max_cnt = max(1U, cap->max_send_sge);
460 if (hr_dev->caps.max_sq_sg <= 2)
461 hr_qp->sq.max_gs = roundup_pow_of_two(max_cnt);
462 else
463 hr_qp->sq.max_gs = max_cnt;
464
465 if (hr_qp->sq.max_gs > 2) {
466 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
467 (hr_qp->sq.max_gs - 2));
468 hr_qp->sge.sge_shift = 4;
469 }
470
471 /* ud sqwqe's sge use extend sge */
472 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->ibqp.qp_type == IB_QPT_GSI) {
473 hr_qp->sge.sge_cnt = roundup_pow_of_two(hr_qp->sq.wqe_cnt *
474 hr_qp->sq.max_gs);
475 hr_qp->sge.sge_shift = 4;
476 }
477
478 if ((hr_qp->sq.max_gs > 2) && hr_dev->pci_dev->revision == 0x20) {
479 if (hr_qp->sge.sge_cnt > hr_dev->caps.max_extend_sg) {
480 dev_err(dev, "The extended sge cnt error! sge_cnt=%d\n",
481 hr_qp->sge.sge_cnt);
482 return -EINVAL;
483 }
484 }
485
486 /* Get buf size, SQ and RQ are aligned to PAGE_SIZE */
487 page_size = 1 << (hr_dev->caps.mtt_buf_pg_sz + PAGE_SHIFT);
488 hr_qp->sq.offset = 0;
489 size = HNS_ROCE_ALOGN_UP(hr_qp->sq.wqe_cnt << hr_qp->sq.wqe_shift,
490 page_size);
491
492 if (hr_dev->caps.max_sq_sg > 2 && hr_qp->sge.sge_cnt) {
493 hr_qp->sge.offset = size;
494 size += HNS_ROCE_ALOGN_UP(hr_qp->sge.sge_cnt <<
495 hr_qp->sge.sge_shift, page_size);
496 }
497
498 hr_qp->rq.offset = size;
499 size += HNS_ROCE_ALOGN_UP((hr_qp->rq.wqe_cnt << hr_qp->rq.wqe_shift),
500 page_size);
501 hr_qp->buff_size = size;
502
503 /* Get wr and sge number which send */
504 cap->max_send_wr = hr_qp->sq.max_post = hr_qp->sq.wqe_cnt;
505 cap->max_send_sge = hr_qp->sq.max_gs;
506
507 /* We don't support inline sends for kernel QPs (yet) */
508 cap->max_inline_data = 0;
509
510 return 0;
511 }
512
hns_roce_qp_has_sq(struct ib_qp_init_attr * attr)513 static int hns_roce_qp_has_sq(struct ib_qp_init_attr *attr)
514 {
515 if (attr->qp_type == IB_QPT_XRC_TGT || !attr->cap.max_send_wr)
516 return 0;
517
518 return 1;
519 }
520
hns_roce_qp_has_rq(struct ib_qp_init_attr * attr)521 static int hns_roce_qp_has_rq(struct ib_qp_init_attr *attr)
522 {
523 if (attr->qp_type == IB_QPT_XRC_INI ||
524 attr->qp_type == IB_QPT_XRC_TGT || attr->srq ||
525 !attr->cap.max_recv_wr)
526 return 0;
527
528 return 1;
529 }
530
hns_roce_create_qp_common(struct hns_roce_dev * hr_dev,struct ib_pd * ib_pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,unsigned long sqpn,struct hns_roce_qp * hr_qp)531 static int hns_roce_create_qp_common(struct hns_roce_dev *hr_dev,
532 struct ib_pd *ib_pd,
533 struct ib_qp_init_attr *init_attr,
534 struct ib_udata *udata, unsigned long sqpn,
535 struct hns_roce_qp *hr_qp)
536 {
537 struct device *dev = hr_dev->dev;
538 struct hns_roce_ib_create_qp ucmd;
539 struct hns_roce_ib_create_qp_resp resp = {};
540 unsigned long qpn = 0;
541 int ret = 0;
542 u32 page_shift;
543 u32 npages;
544 int i;
545
546 mutex_init(&hr_qp->mutex);
547 spin_lock_init(&hr_qp->sq.lock);
548 spin_lock_init(&hr_qp->rq.lock);
549
550 hr_qp->state = IB_QPS_RESET;
551
552 hr_qp->ibqp.qp_type = init_attr->qp_type;
553
554 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
555 hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_ALL_WR);
556 else
557 hr_qp->sq_signal_bits = cpu_to_le32(IB_SIGNAL_REQ_WR);
558
559 ret = hns_roce_set_rq_size(hr_dev, &init_attr->cap, !!ib_pd->uobject,
560 !!init_attr->srq, hr_qp);
561 if (ret) {
562 dev_err(dev, "hns_roce_set_rq_size failed\n");
563 goto err_out;
564 }
565
566 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE) {
567 /* allocate recv inline buf */
568 hr_qp->rq_inl_buf.wqe_list = kcalloc(hr_qp->rq.wqe_cnt,
569 sizeof(struct hns_roce_rinl_wqe),
570 GFP_KERNEL);
571 if (!hr_qp->rq_inl_buf.wqe_list) {
572 ret = -ENOMEM;
573 goto err_out;
574 }
575
576 hr_qp->rq_inl_buf.wqe_cnt = hr_qp->rq.wqe_cnt;
577
578 /* Firstly, allocate a list of sge space buffer */
579 hr_qp->rq_inl_buf.wqe_list[0].sg_list =
580 kcalloc(hr_qp->rq_inl_buf.wqe_cnt,
581 init_attr->cap.max_recv_sge *
582 sizeof(struct hns_roce_rinl_sge),
583 GFP_KERNEL);
584 if (!hr_qp->rq_inl_buf.wqe_list[0].sg_list) {
585 ret = -ENOMEM;
586 goto err_wqe_list;
587 }
588
589 for (i = 1; i < hr_qp->rq_inl_buf.wqe_cnt; i++)
590 /* Secondly, reallocate the buffer */
591 hr_qp->rq_inl_buf.wqe_list[i].sg_list =
592 &hr_qp->rq_inl_buf.wqe_list[0].sg_list[i *
593 init_attr->cap.max_recv_sge];
594 }
595
596 if (ib_pd->uobject) {
597 if (ib_copy_from_udata(&ucmd, udata, sizeof(ucmd))) {
598 dev_err(dev, "ib_copy_from_udata error for create qp\n");
599 ret = -EFAULT;
600 goto err_rq_sge_list;
601 }
602
603 ret = hns_roce_set_user_sq_size(hr_dev, &init_attr->cap, hr_qp,
604 &ucmd);
605 if (ret) {
606 dev_err(dev, "hns_roce_set_user_sq_size error for create qp\n");
607 goto err_rq_sge_list;
608 }
609
610 hr_qp->umem = ib_umem_get(ib_pd->uobject->context,
611 ucmd.buf_addr, hr_qp->buff_size, 0,
612 0);
613 if (IS_ERR(hr_qp->umem)) {
614 dev_err(dev, "ib_umem_get error for create qp\n");
615 ret = PTR_ERR(hr_qp->umem);
616 goto err_rq_sge_list;
617 }
618
619 hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
620 if (hr_dev->caps.mtt_buf_pg_sz) {
621 npages = (ib_umem_page_count(hr_qp->umem) +
622 (1 << hr_dev->caps.mtt_buf_pg_sz) - 1) /
623 (1 << hr_dev->caps.mtt_buf_pg_sz);
624 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
625 ret = hns_roce_mtt_init(hr_dev, npages,
626 page_shift,
627 &hr_qp->mtt);
628 } else {
629 ret = hns_roce_mtt_init(hr_dev,
630 ib_umem_page_count(hr_qp->umem),
631 hr_qp->umem->page_shift,
632 &hr_qp->mtt);
633 }
634 if (ret) {
635 dev_err(dev, "hns_roce_mtt_init error for create qp\n");
636 goto err_buf;
637 }
638
639 ret = hns_roce_ib_umem_write_mtt(hr_dev, &hr_qp->mtt,
640 hr_qp->umem);
641 if (ret) {
642 dev_err(dev, "hns_roce_ib_umem_write_mtt error for create qp\n");
643 goto err_mtt;
644 }
645
646 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
647 (udata->inlen >= sizeof(ucmd)) &&
648 (udata->outlen >= sizeof(resp)) &&
649 hns_roce_qp_has_sq(init_attr)) {
650 ret = hns_roce_db_map_user(
651 to_hr_ucontext(ib_pd->uobject->context),
652 ucmd.sdb_addr, &hr_qp->sdb);
653 if (ret) {
654 dev_err(dev, "sq record doorbell map failed!\n");
655 goto err_mtt;
656 }
657
658 /* indicate kernel supports sq record db */
659 resp.cap_flags |= HNS_ROCE_SUPPORT_SQ_RECORD_DB;
660 hr_qp->sdb_en = 1;
661 }
662
663 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
664 (udata->outlen >= sizeof(resp)) &&
665 hns_roce_qp_has_rq(init_attr)) {
666 ret = hns_roce_db_map_user(
667 to_hr_ucontext(ib_pd->uobject->context),
668 ucmd.db_addr, &hr_qp->rdb);
669 if (ret) {
670 dev_err(dev, "rq record doorbell map failed!\n");
671 goto err_sq_dbmap;
672 }
673 }
674 } else {
675 if (init_attr->create_flags &
676 IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK) {
677 dev_err(dev, "init_attr->create_flags error!\n");
678 ret = -EINVAL;
679 goto err_rq_sge_list;
680 }
681
682 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO) {
683 dev_err(dev, "init_attr->create_flags error!\n");
684 ret = -EINVAL;
685 goto err_rq_sge_list;
686 }
687
688 /* Set SQ size */
689 ret = hns_roce_set_kernel_sq_size(hr_dev, &init_attr->cap,
690 hr_qp);
691 if (ret) {
692 dev_err(dev, "hns_roce_set_kernel_sq_size error!\n");
693 goto err_rq_sge_list;
694 }
695
696 /* QP doorbell register address */
697 hr_qp->sq.db_reg_l = hr_dev->reg_base + hr_dev->sdb_offset +
698 DB_REG_OFFSET * hr_dev->priv_uar.index;
699 hr_qp->rq.db_reg_l = hr_dev->reg_base + hr_dev->odb_offset +
700 DB_REG_OFFSET * hr_dev->priv_uar.index;
701
702 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
703 hns_roce_qp_has_rq(init_attr)) {
704 ret = hns_roce_alloc_db(hr_dev, &hr_qp->rdb, 0);
705 if (ret) {
706 dev_err(dev, "rq record doorbell alloc failed!\n");
707 goto err_rq_sge_list;
708 }
709 *hr_qp->rdb.db_record = 0;
710 hr_qp->rdb_en = 1;
711 }
712
713 /* Allocate QP buf */
714 page_shift = PAGE_SHIFT + hr_dev->caps.mtt_buf_pg_sz;
715 if (hns_roce_buf_alloc(hr_dev, hr_qp->buff_size,
716 (1 << page_shift) * 2,
717 &hr_qp->hr_buf, page_shift)) {
718 dev_err(dev, "hns_roce_buf_alloc error!\n");
719 ret = -ENOMEM;
720 goto err_db;
721 }
722
723 hr_qp->mtt.mtt_type = MTT_TYPE_WQE;
724 /* Write MTT */
725 ret = hns_roce_mtt_init(hr_dev, hr_qp->hr_buf.npages,
726 hr_qp->hr_buf.page_shift, &hr_qp->mtt);
727 if (ret) {
728 dev_err(dev, "hns_roce_mtt_init error for kernel create qp\n");
729 goto err_buf;
730 }
731
732 ret = hns_roce_buf_write_mtt(hr_dev, &hr_qp->mtt,
733 &hr_qp->hr_buf);
734 if (ret) {
735 dev_err(dev, "hns_roce_buf_write_mtt error for kernel create qp\n");
736 goto err_mtt;
737 }
738
739 hr_qp->sq.wrid = kmalloc_array(hr_qp->sq.wqe_cnt, sizeof(u64),
740 GFP_KERNEL);
741 hr_qp->rq.wrid = kmalloc_array(hr_qp->rq.wqe_cnt, sizeof(u64),
742 GFP_KERNEL);
743 if (!hr_qp->sq.wrid || !hr_qp->rq.wrid) {
744 ret = -ENOMEM;
745 goto err_wrid;
746 }
747 }
748
749 if (sqpn) {
750 qpn = sqpn;
751 } else {
752 /* Get QPN */
753 ret = hns_roce_reserve_range_qp(hr_dev, 1, 1, &qpn);
754 if (ret) {
755 dev_err(dev, "hns_roce_reserve_range_qp alloc qpn error\n");
756 goto err_wrid;
757 }
758 }
759
760 if (init_attr->qp_type == IB_QPT_GSI &&
761 hr_dev->hw_rev == HNS_ROCE_HW_VER1) {
762 /* In v1 engine, GSI QP context in RoCE engine's register */
763 ret = hns_roce_gsi_qp_alloc(hr_dev, qpn, hr_qp);
764 if (ret) {
765 dev_err(dev, "hns_roce_qp_alloc failed!\n");
766 goto err_qpn;
767 }
768 } else {
769 ret = hns_roce_qp_alloc(hr_dev, qpn, hr_qp);
770 if (ret) {
771 dev_err(dev, "hns_roce_qp_alloc failed!\n");
772 goto err_qpn;
773 }
774 }
775
776 if (sqpn)
777 hr_qp->doorbell_qpn = 1;
778 else
779 hr_qp->doorbell_qpn = cpu_to_le64(hr_qp->qpn);
780
781 if (ib_pd->uobject && (udata->outlen >= sizeof(resp)) &&
782 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB)) {
783
784 /* indicate kernel supports rq record db */
785 resp.cap_flags |= HNS_ROCE_SUPPORT_RQ_RECORD_DB;
786 ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
787 if (ret)
788 goto err_qp;
789
790 hr_qp->rdb_en = 1;
791 }
792 hr_qp->event = hns_roce_ib_qp_event;
793
794 return 0;
795
796 err_qp:
797 if (init_attr->qp_type == IB_QPT_GSI &&
798 hr_dev->hw_rev == HNS_ROCE_HW_VER1)
799 hns_roce_qp_remove(hr_dev, hr_qp);
800 else
801 hns_roce_qp_free(hr_dev, hr_qp);
802
803 err_qpn:
804 if (!sqpn)
805 hns_roce_release_range_qp(hr_dev, qpn, 1);
806
807 err_wrid:
808 if (ib_pd->uobject) {
809 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) &&
810 (udata->outlen >= sizeof(resp)) &&
811 hns_roce_qp_has_rq(init_attr))
812 hns_roce_db_unmap_user(
813 to_hr_ucontext(ib_pd->uobject->context),
814 &hr_qp->rdb);
815 } else {
816 kfree(hr_qp->sq.wrid);
817 kfree(hr_qp->rq.wrid);
818 }
819
820 err_sq_dbmap:
821 if (ib_pd->uobject)
822 if ((hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SQ_RECORD_DB) &&
823 (udata->inlen >= sizeof(ucmd)) &&
824 (udata->outlen >= sizeof(resp)) &&
825 hns_roce_qp_has_sq(init_attr))
826 hns_roce_db_unmap_user(
827 to_hr_ucontext(ib_pd->uobject->context),
828 &hr_qp->sdb);
829
830 err_mtt:
831 hns_roce_mtt_cleanup(hr_dev, &hr_qp->mtt);
832
833 err_buf:
834 if (ib_pd->uobject)
835 ib_umem_release(hr_qp->umem);
836 else
837 hns_roce_buf_free(hr_dev, hr_qp->buff_size, &hr_qp->hr_buf);
838
839 err_db:
840 if (!ib_pd->uobject && hns_roce_qp_has_rq(init_attr) &&
841 (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB))
842 hns_roce_free_db(hr_dev, &hr_qp->rdb);
843
844 err_rq_sge_list:
845 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
846 kfree(hr_qp->rq_inl_buf.wqe_list[0].sg_list);
847
848 err_wqe_list:
849 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RQ_INLINE)
850 kfree(hr_qp->rq_inl_buf.wqe_list);
851
852 err_out:
853 return ret;
854 }
855
hns_roce_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)856 struct ib_qp *hns_roce_create_qp(struct ib_pd *pd,
857 struct ib_qp_init_attr *init_attr,
858 struct ib_udata *udata)
859 {
860 struct hns_roce_dev *hr_dev = to_hr_dev(pd->device);
861 struct device *dev = hr_dev->dev;
862 struct hns_roce_sqp *hr_sqp;
863 struct hns_roce_qp *hr_qp;
864 int ret;
865
866 switch (init_attr->qp_type) {
867 case IB_QPT_RC: {
868 hr_qp = kzalloc(sizeof(*hr_qp), GFP_KERNEL);
869 if (!hr_qp)
870 return ERR_PTR(-ENOMEM);
871
872 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata, 0,
873 hr_qp);
874 if (ret) {
875 dev_err(dev, "Create RC QP failed\n");
876 kfree(hr_qp);
877 return ERR_PTR(ret);
878 }
879
880 hr_qp->ibqp.qp_num = hr_qp->qpn;
881
882 break;
883 }
884 case IB_QPT_GSI: {
885 /* Userspace is not allowed to create special QPs: */
886 if (pd->uobject) {
887 dev_err(dev, "not support usr space GSI\n");
888 return ERR_PTR(-EINVAL);
889 }
890
891 hr_sqp = kzalloc(sizeof(*hr_sqp), GFP_KERNEL);
892 if (!hr_sqp)
893 return ERR_PTR(-ENOMEM);
894
895 hr_qp = &hr_sqp->hr_qp;
896 hr_qp->port = init_attr->port_num - 1;
897 hr_qp->phy_port = hr_dev->iboe.phy_port[hr_qp->port];
898
899 /* when hw version is v1, the sqpn is allocated */
900 if (hr_dev->caps.max_sq_sg <= 2)
901 hr_qp->ibqp.qp_num = HNS_ROCE_MAX_PORTS +
902 hr_dev->iboe.phy_port[hr_qp->port];
903 else
904 hr_qp->ibqp.qp_num = 1;
905
906 ret = hns_roce_create_qp_common(hr_dev, pd, init_attr, udata,
907 hr_qp->ibqp.qp_num, hr_qp);
908 if (ret) {
909 dev_err(dev, "Create GSI QP failed!\n");
910 kfree(hr_sqp);
911 return ERR_PTR(ret);
912 }
913
914 break;
915 }
916 default:{
917 dev_err(dev, "not support QP type %d\n", init_attr->qp_type);
918 return ERR_PTR(-EINVAL);
919 }
920 }
921
922 return &hr_qp->ibqp;
923 }
924 EXPORT_SYMBOL_GPL(hns_roce_create_qp);
925
to_hr_qp_type(int qp_type)926 int to_hr_qp_type(int qp_type)
927 {
928 int transport_type;
929
930 if (qp_type == IB_QPT_RC)
931 transport_type = SERV_TYPE_RC;
932 else if (qp_type == IB_QPT_UC)
933 transport_type = SERV_TYPE_UC;
934 else if (qp_type == IB_QPT_UD)
935 transport_type = SERV_TYPE_UD;
936 else if (qp_type == IB_QPT_GSI)
937 transport_type = SERV_TYPE_UD;
938 else
939 transport_type = -1;
940
941 return transport_type;
942 }
943 EXPORT_SYMBOL_GPL(to_hr_qp_type);
944
hns_roce_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)945 int hns_roce_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
946 int attr_mask, struct ib_udata *udata)
947 {
948 struct hns_roce_dev *hr_dev = to_hr_dev(ibqp->device);
949 struct hns_roce_qp *hr_qp = to_hr_qp(ibqp);
950 enum ib_qp_state cur_state, new_state;
951 struct device *dev = hr_dev->dev;
952 int ret = -EINVAL;
953 int p;
954 enum ib_mtu active_mtu;
955
956 mutex_lock(&hr_qp->mutex);
957
958 cur_state = attr_mask & IB_QP_CUR_STATE ?
959 attr->cur_qp_state : (enum ib_qp_state)hr_qp->state;
960 new_state = attr_mask & IB_QP_STATE ?
961 attr->qp_state : cur_state;
962
963 if (ibqp->uobject &&
964 (attr_mask & IB_QP_STATE) && new_state == IB_QPS_ERR) {
965 if (hr_qp->sdb_en == 1) {
966 hr_qp->sq.head = *(int *)(hr_qp->sdb.virt_addr);
967 hr_qp->rq.head = *(int *)(hr_qp->rdb.virt_addr);
968 } else {
969 dev_warn(dev, "flush cqe is not supported in userspace!\n");
970 goto out;
971 }
972 }
973
974 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type, attr_mask,
975 IB_LINK_LAYER_ETHERNET)) {
976 dev_err(dev, "ib_modify_qp_is_ok failed\n");
977 goto out;
978 }
979
980 if ((attr_mask & IB_QP_PORT) &&
981 (attr->port_num == 0 || attr->port_num > hr_dev->caps.num_ports)) {
982 dev_err(dev, "attr port_num invalid.attr->port_num=%d\n",
983 attr->port_num);
984 goto out;
985 }
986
987 if (attr_mask & IB_QP_PKEY_INDEX) {
988 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
989 if (attr->pkey_index >= hr_dev->caps.pkey_table_len[p]) {
990 dev_err(dev, "attr pkey_index invalid.attr->pkey_index=%d\n",
991 attr->pkey_index);
992 goto out;
993 }
994 }
995
996 if (attr_mask & IB_QP_PATH_MTU) {
997 p = attr_mask & IB_QP_PORT ? (attr->port_num - 1) : hr_qp->port;
998 active_mtu = iboe_get_mtu(hr_dev->iboe.netdevs[p]->mtu);
999
1000 if ((hr_dev->caps.max_mtu == IB_MTU_4096 &&
1001 attr->path_mtu > IB_MTU_4096) ||
1002 (hr_dev->caps.max_mtu == IB_MTU_2048 &&
1003 attr->path_mtu > IB_MTU_2048) ||
1004 attr->path_mtu < IB_MTU_256 ||
1005 attr->path_mtu > active_mtu) {
1006 dev_err(dev, "attr path_mtu(%d)invalid while modify qp",
1007 attr->path_mtu);
1008 goto out;
1009 }
1010 }
1011
1012 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
1013 attr->max_rd_atomic > hr_dev->caps.max_qp_init_rdma) {
1014 dev_err(dev, "attr max_rd_atomic invalid.attr->max_rd_atomic=%d\n",
1015 attr->max_rd_atomic);
1016 goto out;
1017 }
1018
1019 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
1020 attr->max_dest_rd_atomic > hr_dev->caps.max_qp_dest_rdma) {
1021 dev_err(dev, "attr max_dest_rd_atomic invalid.attr->max_dest_rd_atomic=%d\n",
1022 attr->max_dest_rd_atomic);
1023 goto out;
1024 }
1025
1026 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
1027 if (hr_dev->caps.min_wqes) {
1028 ret = -EPERM;
1029 dev_err(dev, "cur_state=%d new_state=%d\n", cur_state,
1030 new_state);
1031 } else {
1032 ret = 0;
1033 }
1034
1035 goto out;
1036 }
1037
1038 ret = hr_dev->hw->modify_qp(ibqp, attr, attr_mask, cur_state,
1039 new_state);
1040
1041 out:
1042 mutex_unlock(&hr_qp->mutex);
1043
1044 return ret;
1045 }
1046
hns_roce_lock_cqs(struct hns_roce_cq * send_cq,struct hns_roce_cq * recv_cq)1047 void hns_roce_lock_cqs(struct hns_roce_cq *send_cq, struct hns_roce_cq *recv_cq)
1048 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1049 {
1050 if (send_cq == recv_cq) {
1051 spin_lock_irq(&send_cq->lock);
1052 __acquire(&recv_cq->lock);
1053 } else if (send_cq->cqn < recv_cq->cqn) {
1054 spin_lock_irq(&send_cq->lock);
1055 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1056 } else {
1057 spin_lock_irq(&recv_cq->lock);
1058 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1059 }
1060 }
1061 EXPORT_SYMBOL_GPL(hns_roce_lock_cqs);
1062
hns_roce_unlock_cqs(struct hns_roce_cq * send_cq,struct hns_roce_cq * recv_cq)1063 void hns_roce_unlock_cqs(struct hns_roce_cq *send_cq,
1064 struct hns_roce_cq *recv_cq) __releases(&send_cq->lock)
1065 __releases(&recv_cq->lock)
1066 {
1067 if (send_cq == recv_cq) {
1068 __release(&recv_cq->lock);
1069 spin_unlock_irq(&send_cq->lock);
1070 } else if (send_cq->cqn < recv_cq->cqn) {
1071 spin_unlock(&recv_cq->lock);
1072 spin_unlock_irq(&send_cq->lock);
1073 } else {
1074 spin_unlock(&send_cq->lock);
1075 spin_unlock_irq(&recv_cq->lock);
1076 }
1077 }
1078 EXPORT_SYMBOL_GPL(hns_roce_unlock_cqs);
1079
get_wqe(struct hns_roce_qp * hr_qp,int offset)1080 static void *get_wqe(struct hns_roce_qp *hr_qp, int offset)
1081 {
1082
1083 return hns_roce_buf_offset(&hr_qp->hr_buf, offset);
1084 }
1085
get_recv_wqe(struct hns_roce_qp * hr_qp,int n)1086 void *get_recv_wqe(struct hns_roce_qp *hr_qp, int n)
1087 {
1088 return get_wqe(hr_qp, hr_qp->rq.offset + (n << hr_qp->rq.wqe_shift));
1089 }
1090 EXPORT_SYMBOL_GPL(get_recv_wqe);
1091
get_send_wqe(struct hns_roce_qp * hr_qp,int n)1092 void *get_send_wqe(struct hns_roce_qp *hr_qp, int n)
1093 {
1094 return get_wqe(hr_qp, hr_qp->sq.offset + (n << hr_qp->sq.wqe_shift));
1095 }
1096 EXPORT_SYMBOL_GPL(get_send_wqe);
1097
get_send_extend_sge(struct hns_roce_qp * hr_qp,int n)1098 void *get_send_extend_sge(struct hns_roce_qp *hr_qp, int n)
1099 {
1100 return hns_roce_buf_offset(&hr_qp->hr_buf, hr_qp->sge.offset +
1101 (n << hr_qp->sge.sge_shift));
1102 }
1103 EXPORT_SYMBOL_GPL(get_send_extend_sge);
1104
hns_roce_wq_overflow(struct hns_roce_wq * hr_wq,int nreq,struct ib_cq * ib_cq)1105 bool hns_roce_wq_overflow(struct hns_roce_wq *hr_wq, int nreq,
1106 struct ib_cq *ib_cq)
1107 {
1108 struct hns_roce_cq *hr_cq;
1109 u32 cur;
1110
1111 cur = hr_wq->head - hr_wq->tail;
1112 if (likely(cur + nreq < hr_wq->max_post))
1113 return false;
1114
1115 hr_cq = to_hr_cq(ib_cq);
1116 spin_lock(&hr_cq->lock);
1117 cur = hr_wq->head - hr_wq->tail;
1118 spin_unlock(&hr_cq->lock);
1119
1120 return cur + nreq >= hr_wq->max_post;
1121 }
1122 EXPORT_SYMBOL_GPL(hns_roce_wq_overflow);
1123
hns_roce_init_qp_table(struct hns_roce_dev * hr_dev)1124 int hns_roce_init_qp_table(struct hns_roce_dev *hr_dev)
1125 {
1126 struct hns_roce_qp_table *qp_table = &hr_dev->qp_table;
1127 int reserved_from_top = 0;
1128 int reserved_from_bot;
1129 int ret;
1130
1131 spin_lock_init(&qp_table->lock);
1132 INIT_RADIX_TREE(&hr_dev->qp_table_tree, GFP_ATOMIC);
1133
1134 /* In hw v1, a port include two SQP, six ports total 12 */
1135 if (hr_dev->caps.max_sq_sg <= 2)
1136 reserved_from_bot = SQP_NUM;
1137 else
1138 reserved_from_bot = hr_dev->caps.reserved_qps;
1139
1140 ret = hns_roce_bitmap_init(&qp_table->bitmap, hr_dev->caps.num_qps,
1141 hr_dev->caps.num_qps - 1, reserved_from_bot,
1142 reserved_from_top);
1143 if (ret) {
1144 dev_err(hr_dev->dev, "qp bitmap init failed!error=%d\n",
1145 ret);
1146 return ret;
1147 }
1148
1149 return 0;
1150 }
1151
hns_roce_cleanup_qp_table(struct hns_roce_dev * hr_dev)1152 void hns_roce_cleanup_qp_table(struct hns_roce_dev *hr_dev)
1153 {
1154 hns_roce_bitmap_cleanup(&hr_dev->qp_table.bitmap);
1155 }
1156