1 /*
2 * Copyright (c) 2007 Cisco Systems, Inc. All rights reserved.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33
34 #include <linux/log2.h>
35 #include <linux/etherdevice.h>
36 #include <net/ip.h>
37 #include <linux/slab.h>
38 #include <linux/netdevice.h>
39
40 #include <rdma/ib_cache.h>
41 #include <rdma/ib_pack.h>
42 #include <rdma/ib_addr.h>
43 #include <rdma/ib_mad.h>
44
45 #include <linux/mlx4/driver.h>
46 #include <linux/mlx4/qp.h>
47
48 #include "mlx4_ib.h"
49 #include <rdma/mlx4-abi.h>
50
51 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq,
52 struct mlx4_ib_cq *recv_cq);
53 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq,
54 struct mlx4_ib_cq *recv_cq);
55 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state);
56
57 enum {
58 MLX4_IB_ACK_REQ_FREQ = 8,
59 };
60
61 enum {
62 MLX4_IB_DEFAULT_SCHED_QUEUE = 0x83,
63 MLX4_IB_DEFAULT_QP0_SCHED_QUEUE = 0x3f,
64 MLX4_IB_LINK_TYPE_IB = 0,
65 MLX4_IB_LINK_TYPE_ETH = 1
66 };
67
68 enum {
69 /*
70 * Largest possible UD header: send with GRH and immediate
71 * data plus 18 bytes for an Ethernet header with VLAN/802.1Q
72 * tag. (LRH would only use 8 bytes, so Ethernet is the
73 * biggest case)
74 */
75 MLX4_IB_UD_HEADER_SIZE = 82,
76 MLX4_IB_LSO_HEADER_SPARE = 128,
77 };
78
79 struct mlx4_ib_sqp {
80 struct mlx4_ib_qp qp;
81 int pkey_index;
82 u32 qkey;
83 u32 send_psn;
84 struct ib_ud_header ud_header;
85 u8 header_buf[MLX4_IB_UD_HEADER_SIZE];
86 struct ib_qp *roce_v2_gsi;
87 };
88
89 enum {
90 MLX4_IB_MIN_SQ_STRIDE = 6,
91 MLX4_IB_CACHE_LINE_SIZE = 64,
92 };
93
94 enum {
95 MLX4_RAW_QP_MTU = 7,
96 MLX4_RAW_QP_MSGMAX = 31,
97 };
98
99 #ifndef ETH_ALEN
100 #define ETH_ALEN 6
101 #endif
102
103 static const __be32 mlx4_ib_opcode[] = {
104 [IB_WR_SEND] = cpu_to_be32(MLX4_OPCODE_SEND),
105 [IB_WR_LSO] = cpu_to_be32(MLX4_OPCODE_LSO),
106 [IB_WR_SEND_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_SEND_IMM),
107 [IB_WR_RDMA_WRITE] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE),
108 [IB_WR_RDMA_WRITE_WITH_IMM] = cpu_to_be32(MLX4_OPCODE_RDMA_WRITE_IMM),
109 [IB_WR_RDMA_READ] = cpu_to_be32(MLX4_OPCODE_RDMA_READ),
110 [IB_WR_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_ATOMIC_CS),
111 [IB_WR_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_ATOMIC_FA),
112 [IB_WR_SEND_WITH_INV] = cpu_to_be32(MLX4_OPCODE_SEND_INVAL),
113 [IB_WR_LOCAL_INV] = cpu_to_be32(MLX4_OPCODE_LOCAL_INVAL),
114 [IB_WR_REG_MR] = cpu_to_be32(MLX4_OPCODE_FMR),
115 [IB_WR_MASKED_ATOMIC_CMP_AND_SWP] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_CS),
116 [IB_WR_MASKED_ATOMIC_FETCH_AND_ADD] = cpu_to_be32(MLX4_OPCODE_MASKED_ATOMIC_FA),
117 };
118
119 enum mlx4_ib_source_type {
120 MLX4_IB_QP_SRC = 0,
121 MLX4_IB_RWQ_SRC = 1,
122 };
123
to_msqp(struct mlx4_ib_qp * mqp)124 static struct mlx4_ib_sqp *to_msqp(struct mlx4_ib_qp *mqp)
125 {
126 return container_of(mqp, struct mlx4_ib_sqp, qp);
127 }
128
is_tunnel_qp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)129 static int is_tunnel_qp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
130 {
131 if (!mlx4_is_master(dev->dev))
132 return 0;
133
134 return qp->mqp.qpn >= dev->dev->phys_caps.base_tunnel_sqpn &&
135 qp->mqp.qpn < dev->dev->phys_caps.base_tunnel_sqpn +
136 8 * MLX4_MFUNC_MAX;
137 }
138
is_sqp(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)139 static int is_sqp(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
140 {
141 int proxy_sqp = 0;
142 int real_sqp = 0;
143 int i;
144 /* PPF or Native -- real SQP */
145 real_sqp = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
146 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
147 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 3);
148 if (real_sqp)
149 return 1;
150 /* VF or PF -- proxy SQP */
151 if (mlx4_is_mfunc(dev->dev)) {
152 for (i = 0; i < dev->dev->caps.num_ports; i++) {
153 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy ||
154 qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp1_proxy) {
155 proxy_sqp = 1;
156 break;
157 }
158 }
159 }
160 if (proxy_sqp)
161 return 1;
162
163 return !!(qp->flags & MLX4_IB_ROCE_V2_GSI_QP);
164 }
165
166 /* used for INIT/CLOSE port logic */
is_qp0(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)167 static int is_qp0(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
168 {
169 int proxy_qp0 = 0;
170 int real_qp0 = 0;
171 int i;
172 /* PPF or Native -- real QP0 */
173 real_qp0 = ((mlx4_is_master(dev->dev) || !mlx4_is_mfunc(dev->dev)) &&
174 qp->mqp.qpn >= dev->dev->phys_caps.base_sqpn &&
175 qp->mqp.qpn <= dev->dev->phys_caps.base_sqpn + 1);
176 if (real_qp0)
177 return 1;
178 /* VF or PF -- proxy QP0 */
179 if (mlx4_is_mfunc(dev->dev)) {
180 for (i = 0; i < dev->dev->caps.num_ports; i++) {
181 if (qp->mqp.qpn == dev->dev->caps.spec_qps[i].qp0_proxy) {
182 proxy_qp0 = 1;
183 break;
184 }
185 }
186 }
187 return proxy_qp0;
188 }
189
get_wqe(struct mlx4_ib_qp * qp,int offset)190 static void *get_wqe(struct mlx4_ib_qp *qp, int offset)
191 {
192 return mlx4_buf_offset(&qp->buf, offset);
193 }
194
get_recv_wqe(struct mlx4_ib_qp * qp,int n)195 static void *get_recv_wqe(struct mlx4_ib_qp *qp, int n)
196 {
197 return get_wqe(qp, qp->rq.offset + (n << qp->rq.wqe_shift));
198 }
199
get_send_wqe(struct mlx4_ib_qp * qp,int n)200 static void *get_send_wqe(struct mlx4_ib_qp *qp, int n)
201 {
202 return get_wqe(qp, qp->sq.offset + (n << qp->sq.wqe_shift));
203 }
204
205 /*
206 * Stamp a SQ WQE so that it is invalid if prefetched by marking the
207 * first four bytes of every 64 byte chunk with 0xffffffff, except for
208 * the very first chunk of the WQE.
209 */
stamp_send_wqe(struct mlx4_ib_qp * qp,int n)210 static void stamp_send_wqe(struct mlx4_ib_qp *qp, int n)
211 {
212 __be32 *wqe;
213 int i;
214 int s;
215 void *buf;
216 struct mlx4_wqe_ctrl_seg *ctrl;
217
218 buf = get_send_wqe(qp, n & (qp->sq.wqe_cnt - 1));
219 ctrl = (struct mlx4_wqe_ctrl_seg *)buf;
220 s = (ctrl->qpn_vlan.fence_size & 0x3f) << 4;
221 for (i = 64; i < s; i += 64) {
222 wqe = buf + i;
223 *wqe = cpu_to_be32(0xffffffff);
224 }
225 }
226
mlx4_ib_qp_event(struct mlx4_qp * qp,enum mlx4_event type)227 static void mlx4_ib_qp_event(struct mlx4_qp *qp, enum mlx4_event type)
228 {
229 struct ib_event event;
230 struct ib_qp *ibqp = &to_mibqp(qp)->ibqp;
231
232 if (type == MLX4_EVENT_TYPE_PATH_MIG)
233 to_mibqp(qp)->port = to_mibqp(qp)->alt_port;
234
235 if (ibqp->event_handler) {
236 event.device = ibqp->device;
237 event.element.qp = ibqp;
238 switch (type) {
239 case MLX4_EVENT_TYPE_PATH_MIG:
240 event.event = IB_EVENT_PATH_MIG;
241 break;
242 case MLX4_EVENT_TYPE_COMM_EST:
243 event.event = IB_EVENT_COMM_EST;
244 break;
245 case MLX4_EVENT_TYPE_SQ_DRAINED:
246 event.event = IB_EVENT_SQ_DRAINED;
247 break;
248 case MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE:
249 event.event = IB_EVENT_QP_LAST_WQE_REACHED;
250 break;
251 case MLX4_EVENT_TYPE_WQ_CATAS_ERROR:
252 event.event = IB_EVENT_QP_FATAL;
253 break;
254 case MLX4_EVENT_TYPE_PATH_MIG_FAILED:
255 event.event = IB_EVENT_PATH_MIG_ERR;
256 break;
257 case MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR:
258 event.event = IB_EVENT_QP_REQ_ERR;
259 break;
260 case MLX4_EVENT_TYPE_WQ_ACCESS_ERROR:
261 event.event = IB_EVENT_QP_ACCESS_ERR;
262 break;
263 default:
264 pr_warn("Unexpected event type %d "
265 "on QP %06x\n", type, qp->qpn);
266 return;
267 }
268
269 ibqp->event_handler(&event, ibqp->qp_context);
270 }
271 }
272
mlx4_ib_wq_event(struct mlx4_qp * qp,enum mlx4_event type)273 static void mlx4_ib_wq_event(struct mlx4_qp *qp, enum mlx4_event type)
274 {
275 pr_warn_ratelimited("Unexpected event type %d on WQ 0x%06x. Events are not supported for WQs\n",
276 type, qp->qpn);
277 }
278
send_wqe_overhead(enum mlx4_ib_qp_type type,u32 flags)279 static int send_wqe_overhead(enum mlx4_ib_qp_type type, u32 flags)
280 {
281 /*
282 * UD WQEs must have a datagram segment.
283 * RC and UC WQEs might have a remote address segment.
284 * MLX WQEs need two extra inline data segments (for the UD
285 * header and space for the ICRC).
286 */
287 switch (type) {
288 case MLX4_IB_QPT_UD:
289 return sizeof (struct mlx4_wqe_ctrl_seg) +
290 sizeof (struct mlx4_wqe_datagram_seg) +
291 ((flags & MLX4_IB_QP_LSO) ? MLX4_IB_LSO_HEADER_SPARE : 0);
292 case MLX4_IB_QPT_PROXY_SMI_OWNER:
293 case MLX4_IB_QPT_PROXY_SMI:
294 case MLX4_IB_QPT_PROXY_GSI:
295 return sizeof (struct mlx4_wqe_ctrl_seg) +
296 sizeof (struct mlx4_wqe_datagram_seg) + 64;
297 case MLX4_IB_QPT_TUN_SMI_OWNER:
298 case MLX4_IB_QPT_TUN_GSI:
299 return sizeof (struct mlx4_wqe_ctrl_seg) +
300 sizeof (struct mlx4_wqe_datagram_seg);
301
302 case MLX4_IB_QPT_UC:
303 return sizeof (struct mlx4_wqe_ctrl_seg) +
304 sizeof (struct mlx4_wqe_raddr_seg);
305 case MLX4_IB_QPT_RC:
306 return sizeof (struct mlx4_wqe_ctrl_seg) +
307 sizeof (struct mlx4_wqe_masked_atomic_seg) +
308 sizeof (struct mlx4_wqe_raddr_seg);
309 case MLX4_IB_QPT_SMI:
310 case MLX4_IB_QPT_GSI:
311 return sizeof (struct mlx4_wqe_ctrl_seg) +
312 ALIGN(MLX4_IB_UD_HEADER_SIZE +
313 DIV_ROUND_UP(MLX4_IB_UD_HEADER_SIZE,
314 MLX4_INLINE_ALIGN) *
315 sizeof (struct mlx4_wqe_inline_seg),
316 sizeof (struct mlx4_wqe_data_seg)) +
317 ALIGN(4 +
318 sizeof (struct mlx4_wqe_inline_seg),
319 sizeof (struct mlx4_wqe_data_seg));
320 default:
321 return sizeof (struct mlx4_wqe_ctrl_seg);
322 }
323 }
324
set_rq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,int is_user,int has_rq,struct mlx4_ib_qp * qp,u32 inl_recv_sz)325 static int set_rq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
326 int is_user, int has_rq, struct mlx4_ib_qp *qp,
327 u32 inl_recv_sz)
328 {
329 /* Sanity check RQ size before proceeding */
330 if (cap->max_recv_wr > dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE ||
331 cap->max_recv_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg))
332 return -EINVAL;
333
334 if (!has_rq) {
335 if (cap->max_recv_wr || inl_recv_sz)
336 return -EINVAL;
337
338 qp->rq.wqe_cnt = qp->rq.max_gs = 0;
339 } else {
340 u32 max_inl_recv_sz = dev->dev->caps.max_rq_sg *
341 sizeof(struct mlx4_wqe_data_seg);
342 u32 wqe_size;
343
344 /* HW requires >= 1 RQ entry with >= 1 gather entry */
345 if (is_user && (!cap->max_recv_wr || !cap->max_recv_sge ||
346 inl_recv_sz > max_inl_recv_sz))
347 return -EINVAL;
348
349 qp->rq.wqe_cnt = roundup_pow_of_two(max(1U, cap->max_recv_wr));
350 qp->rq.max_gs = roundup_pow_of_two(max(1U, cap->max_recv_sge));
351 wqe_size = qp->rq.max_gs * sizeof(struct mlx4_wqe_data_seg);
352 qp->rq.wqe_shift = ilog2(max_t(u32, wqe_size, inl_recv_sz));
353 }
354
355 /* leave userspace return values as they were, so as not to break ABI */
356 if (is_user) {
357 cap->max_recv_wr = qp->rq.max_post = qp->rq.wqe_cnt;
358 cap->max_recv_sge = qp->rq.max_gs;
359 } else {
360 cap->max_recv_wr = qp->rq.max_post =
361 min(dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE, qp->rq.wqe_cnt);
362 cap->max_recv_sge = min(qp->rq.max_gs,
363 min(dev->dev->caps.max_sq_sg,
364 dev->dev->caps.max_rq_sg));
365 }
366
367 return 0;
368 }
369
set_kernel_sq_size(struct mlx4_ib_dev * dev,struct ib_qp_cap * cap,enum mlx4_ib_qp_type type,struct mlx4_ib_qp * qp)370 static int set_kernel_sq_size(struct mlx4_ib_dev *dev, struct ib_qp_cap *cap,
371 enum mlx4_ib_qp_type type, struct mlx4_ib_qp *qp)
372 {
373 int s;
374
375 /* Sanity check SQ size before proceeding */
376 if (cap->max_send_wr > (dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE) ||
377 cap->max_send_sge > min(dev->dev->caps.max_sq_sg, dev->dev->caps.max_rq_sg) ||
378 cap->max_inline_data + send_wqe_overhead(type, qp->flags) +
379 sizeof (struct mlx4_wqe_inline_seg) > dev->dev->caps.max_sq_desc_sz)
380 return -EINVAL;
381
382 /*
383 * For MLX transport we need 2 extra S/G entries:
384 * one for the header and one for the checksum at the end
385 */
386 if ((type == MLX4_IB_QPT_SMI || type == MLX4_IB_QPT_GSI ||
387 type & (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) &&
388 cap->max_send_sge + 2 > dev->dev->caps.max_sq_sg)
389 return -EINVAL;
390
391 s = max(cap->max_send_sge * sizeof (struct mlx4_wqe_data_seg),
392 cap->max_inline_data + sizeof (struct mlx4_wqe_inline_seg)) +
393 send_wqe_overhead(type, qp->flags);
394
395 if (s > dev->dev->caps.max_sq_desc_sz)
396 return -EINVAL;
397
398 qp->sq.wqe_shift = ilog2(roundup_pow_of_two(s));
399
400 /*
401 * We need to leave 2 KB + 1 WR of headroom in the SQ to
402 * allow HW to prefetch.
403 */
404 qp->sq_spare_wqes = (2048 >> qp->sq.wqe_shift) + 1;
405 qp->sq.wqe_cnt = roundup_pow_of_two(cap->max_send_wr +
406 qp->sq_spare_wqes);
407
408 qp->sq.max_gs =
409 (min(dev->dev->caps.max_sq_desc_sz,
410 (1 << qp->sq.wqe_shift)) -
411 send_wqe_overhead(type, qp->flags)) /
412 sizeof (struct mlx4_wqe_data_seg);
413
414 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
415 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
416 if (qp->rq.wqe_shift > qp->sq.wqe_shift) {
417 qp->rq.offset = 0;
418 qp->sq.offset = qp->rq.wqe_cnt << qp->rq.wqe_shift;
419 } else {
420 qp->rq.offset = qp->sq.wqe_cnt << qp->sq.wqe_shift;
421 qp->sq.offset = 0;
422 }
423
424 cap->max_send_wr = qp->sq.max_post =
425 qp->sq.wqe_cnt - qp->sq_spare_wqes;
426 cap->max_send_sge = min(qp->sq.max_gs,
427 min(dev->dev->caps.max_sq_sg,
428 dev->dev->caps.max_rq_sg));
429 /* We don't support inline sends for kernel QPs (yet) */
430 cap->max_inline_data = 0;
431
432 return 0;
433 }
434
set_user_sq_size(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_ib_create_qp * ucmd)435 static int set_user_sq_size(struct mlx4_ib_dev *dev,
436 struct mlx4_ib_qp *qp,
437 struct mlx4_ib_create_qp *ucmd)
438 {
439 /* Sanity check SQ size before proceeding */
440 if ((1 << ucmd->log_sq_bb_count) > dev->dev->caps.max_wqes ||
441 ucmd->log_sq_stride >
442 ilog2(roundup_pow_of_two(dev->dev->caps.max_sq_desc_sz)) ||
443 ucmd->log_sq_stride < MLX4_IB_MIN_SQ_STRIDE)
444 return -EINVAL;
445
446 qp->sq.wqe_cnt = 1 << ucmd->log_sq_bb_count;
447 qp->sq.wqe_shift = ucmd->log_sq_stride;
448
449 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
450 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
451
452 return 0;
453 }
454
alloc_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)455 static int alloc_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
456 {
457 int i;
458
459 qp->sqp_proxy_rcv =
460 kmalloc_array(qp->rq.wqe_cnt, sizeof(struct mlx4_ib_buf),
461 GFP_KERNEL);
462 if (!qp->sqp_proxy_rcv)
463 return -ENOMEM;
464 for (i = 0; i < qp->rq.wqe_cnt; i++) {
465 qp->sqp_proxy_rcv[i].addr =
466 kmalloc(sizeof (struct mlx4_ib_proxy_sqp_hdr),
467 GFP_KERNEL);
468 if (!qp->sqp_proxy_rcv[i].addr)
469 goto err;
470 qp->sqp_proxy_rcv[i].map =
471 ib_dma_map_single(dev, qp->sqp_proxy_rcv[i].addr,
472 sizeof (struct mlx4_ib_proxy_sqp_hdr),
473 DMA_FROM_DEVICE);
474 if (ib_dma_mapping_error(dev, qp->sqp_proxy_rcv[i].map)) {
475 kfree(qp->sqp_proxy_rcv[i].addr);
476 goto err;
477 }
478 }
479 return 0;
480
481 err:
482 while (i > 0) {
483 --i;
484 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
485 sizeof (struct mlx4_ib_proxy_sqp_hdr),
486 DMA_FROM_DEVICE);
487 kfree(qp->sqp_proxy_rcv[i].addr);
488 }
489 kfree(qp->sqp_proxy_rcv);
490 qp->sqp_proxy_rcv = NULL;
491 return -ENOMEM;
492 }
493
free_proxy_bufs(struct ib_device * dev,struct mlx4_ib_qp * qp)494 static void free_proxy_bufs(struct ib_device *dev, struct mlx4_ib_qp *qp)
495 {
496 int i;
497
498 for (i = 0; i < qp->rq.wqe_cnt; i++) {
499 ib_dma_unmap_single(dev, qp->sqp_proxy_rcv[i].map,
500 sizeof (struct mlx4_ib_proxy_sqp_hdr),
501 DMA_FROM_DEVICE);
502 kfree(qp->sqp_proxy_rcv[i].addr);
503 }
504 kfree(qp->sqp_proxy_rcv);
505 }
506
qp_has_rq(struct ib_qp_init_attr * attr)507 static int qp_has_rq(struct ib_qp_init_attr *attr)
508 {
509 if (attr->qp_type == IB_QPT_XRC_INI || attr->qp_type == IB_QPT_XRC_TGT)
510 return 0;
511
512 return !attr->srq;
513 }
514
qp0_enabled_vf(struct mlx4_dev * dev,int qpn)515 static int qp0_enabled_vf(struct mlx4_dev *dev, int qpn)
516 {
517 int i;
518 for (i = 0; i < dev->caps.num_ports; i++) {
519 if (qpn == dev->caps.spec_qps[i].qp0_proxy)
520 return !!dev->caps.spec_qps[i].qp0_qkey;
521 }
522 return 0;
523 }
524
mlx4_ib_free_qp_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)525 static void mlx4_ib_free_qp_counter(struct mlx4_ib_dev *dev,
526 struct mlx4_ib_qp *qp)
527 {
528 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
529 mlx4_counter_free(dev->dev, qp->counter_index->index);
530 list_del(&qp->counter_index->list);
531 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
532
533 kfree(qp->counter_index);
534 qp->counter_index = NULL;
535 }
536
set_qp_rss(struct mlx4_ib_dev * dev,struct mlx4_ib_rss * rss_ctx,struct ib_qp_init_attr * init_attr,struct mlx4_ib_create_qp_rss * ucmd)537 static int set_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_rss *rss_ctx,
538 struct ib_qp_init_attr *init_attr,
539 struct mlx4_ib_create_qp_rss *ucmd)
540 {
541 rss_ctx->base_qpn_tbl_sz = init_attr->rwq_ind_tbl->ind_tbl[0]->wq_num |
542 (init_attr->rwq_ind_tbl->log_ind_tbl_size << 24);
543
544 if ((ucmd->rx_hash_function == MLX4_IB_RX_HASH_FUNC_TOEPLITZ) &&
545 (dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RSS_TOP)) {
546 memcpy(rss_ctx->rss_key, ucmd->rx_hash_key,
547 MLX4_EN_RSS_KEY_SIZE);
548 } else {
549 pr_debug("RX Hash function is not supported\n");
550 return (-EOPNOTSUPP);
551 }
552
553 if (ucmd->rx_hash_fields_mask & ~(MLX4_IB_RX_HASH_SRC_IPV4 |
554 MLX4_IB_RX_HASH_DST_IPV4 |
555 MLX4_IB_RX_HASH_SRC_IPV6 |
556 MLX4_IB_RX_HASH_DST_IPV6 |
557 MLX4_IB_RX_HASH_SRC_PORT_TCP |
558 MLX4_IB_RX_HASH_DST_PORT_TCP |
559 MLX4_IB_RX_HASH_SRC_PORT_UDP |
560 MLX4_IB_RX_HASH_DST_PORT_UDP |
561 MLX4_IB_RX_HASH_INNER)) {
562 pr_debug("RX Hash fields_mask has unsupported mask (0x%llx)\n",
563 ucmd->rx_hash_fields_mask);
564 return (-EOPNOTSUPP);
565 }
566
567 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) &&
568 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
569 rss_ctx->flags = MLX4_RSS_IPV4;
570 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV4) ||
571 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV4)) {
572 pr_debug("RX Hash fields_mask is not supported - both IPv4 SRC and DST must be set\n");
573 return (-EOPNOTSUPP);
574 }
575
576 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) &&
577 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
578 rss_ctx->flags |= MLX4_RSS_IPV6;
579 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_IPV6) ||
580 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_IPV6)) {
581 pr_debug("RX Hash fields_mask is not supported - both IPv6 SRC and DST must be set\n");
582 return (-EOPNOTSUPP);
583 }
584
585 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) &&
586 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
587 if (!(dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UDP_RSS)) {
588 pr_debug("RX Hash fields_mask for UDP is not supported\n");
589 return (-EOPNOTSUPP);
590 }
591
592 if (rss_ctx->flags & MLX4_RSS_IPV4)
593 rss_ctx->flags |= MLX4_RSS_UDP_IPV4;
594 if (rss_ctx->flags & MLX4_RSS_IPV6)
595 rss_ctx->flags |= MLX4_RSS_UDP_IPV6;
596 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
597 pr_debug("RX Hash fields_mask is not supported - UDP must be set with IPv4 or IPv6\n");
598 return (-EOPNOTSUPP);
599 }
600 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_UDP) ||
601 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_UDP)) {
602 pr_debug("RX Hash fields_mask is not supported - both UDP SRC and DST must be set\n");
603 return (-EOPNOTSUPP);
604 }
605
606 if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) &&
607 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
608 if (rss_ctx->flags & MLX4_RSS_IPV4)
609 rss_ctx->flags |= MLX4_RSS_TCP_IPV4;
610 if (rss_ctx->flags & MLX4_RSS_IPV6)
611 rss_ctx->flags |= MLX4_RSS_TCP_IPV6;
612 if (!(rss_ctx->flags & (MLX4_RSS_IPV6 | MLX4_RSS_IPV4))) {
613 pr_debug("RX Hash fields_mask is not supported - TCP must be set with IPv4 or IPv6\n");
614 return (-EOPNOTSUPP);
615 }
616 } else if ((ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_SRC_PORT_TCP) ||
617 (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_DST_PORT_TCP)) {
618 pr_debug("RX Hash fields_mask is not supported - both TCP SRC and DST must be set\n");
619 return (-EOPNOTSUPP);
620 }
621
622 if (ucmd->rx_hash_fields_mask & MLX4_IB_RX_HASH_INNER) {
623 if (dev->dev->caps.tunnel_offload_mode ==
624 MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
625 /*
626 * Hash according to inner headers if exist, otherwise
627 * according to outer headers.
628 */
629 rss_ctx->flags |= MLX4_RSS_BY_INNER_HEADERS_IPONLY;
630 } else {
631 pr_debug("RSS Hash for inner headers isn't supported\n");
632 return (-EOPNOTSUPP);
633 }
634 }
635
636 return 0;
637 }
638
create_qp_rss(struct mlx4_ib_dev * dev,struct ib_qp_init_attr * init_attr,struct mlx4_ib_create_qp_rss * ucmd,struct mlx4_ib_qp * qp)639 static int create_qp_rss(struct mlx4_ib_dev *dev,
640 struct ib_qp_init_attr *init_attr,
641 struct mlx4_ib_create_qp_rss *ucmd,
642 struct mlx4_ib_qp *qp)
643 {
644 int qpn;
645 int err;
646
647 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
648
649 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn, 0, qp->mqp.usage);
650 if (err)
651 return err;
652
653 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
654 if (err)
655 goto err_qpn;
656
657 mutex_init(&qp->mutex);
658
659 INIT_LIST_HEAD(&qp->gid_list);
660 INIT_LIST_HEAD(&qp->steering_rules);
661
662 qp->mlx4_ib_qp_type = MLX4_IB_QPT_RAW_PACKET;
663 qp->state = IB_QPS_RESET;
664
665 /* Set dummy send resources to be compatible with HV and PRM */
666 qp->sq_no_prefetch = 1;
667 qp->sq.wqe_cnt = 1;
668 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
669 qp->buf_size = qp->sq.wqe_cnt << MLX4_IB_MIN_SQ_STRIDE;
670 qp->mtt = (to_mqp(
671 (struct ib_qp *)init_attr->rwq_ind_tbl->ind_tbl[0]))->mtt;
672
673 qp->rss_ctx = kzalloc(sizeof(*qp->rss_ctx), GFP_KERNEL);
674 if (!qp->rss_ctx) {
675 err = -ENOMEM;
676 goto err_qp_alloc;
677 }
678
679 err = set_qp_rss(dev, qp->rss_ctx, init_attr, ucmd);
680 if (err)
681 goto err;
682
683 return 0;
684
685 err:
686 kfree(qp->rss_ctx);
687
688 err_qp_alloc:
689 mlx4_qp_remove(dev->dev, &qp->mqp);
690 mlx4_qp_free(dev->dev, &qp->mqp);
691
692 err_qpn:
693 mlx4_qp_release_range(dev->dev, qpn, 1);
694 return err;
695 }
696
_mlx4_ib_create_qp_rss(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)697 static struct ib_qp *_mlx4_ib_create_qp_rss(struct ib_pd *pd,
698 struct ib_qp_init_attr *init_attr,
699 struct ib_udata *udata)
700 {
701 struct mlx4_ib_qp *qp;
702 struct mlx4_ib_create_qp_rss ucmd = {};
703 size_t required_cmd_sz;
704 int err;
705
706 if (!udata) {
707 pr_debug("RSS QP with NULL udata\n");
708 return ERR_PTR(-EINVAL);
709 }
710
711 if (udata->outlen)
712 return ERR_PTR(-EOPNOTSUPP);
713
714 required_cmd_sz = offsetof(typeof(ucmd), reserved1) +
715 sizeof(ucmd.reserved1);
716 if (udata->inlen < required_cmd_sz) {
717 pr_debug("invalid inlen\n");
718 return ERR_PTR(-EINVAL);
719 }
720
721 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen))) {
722 pr_debug("copy failed\n");
723 return ERR_PTR(-EFAULT);
724 }
725
726 if (memchr_inv(ucmd.reserved, 0, sizeof(ucmd.reserved)))
727 return ERR_PTR(-EOPNOTSUPP);
728
729 if (ucmd.comp_mask || ucmd.reserved1)
730 return ERR_PTR(-EOPNOTSUPP);
731
732 if (udata->inlen > sizeof(ucmd) &&
733 !ib_is_udata_cleared(udata, sizeof(ucmd),
734 udata->inlen - sizeof(ucmd))) {
735 pr_debug("inlen is not supported\n");
736 return ERR_PTR(-EOPNOTSUPP);
737 }
738
739 if (init_attr->qp_type != IB_QPT_RAW_PACKET) {
740 pr_debug("RSS QP with unsupported QP type %d\n",
741 init_attr->qp_type);
742 return ERR_PTR(-EOPNOTSUPP);
743 }
744
745 if (init_attr->create_flags) {
746 pr_debug("RSS QP doesn't support create flags\n");
747 return ERR_PTR(-EOPNOTSUPP);
748 }
749
750 if (init_attr->send_cq || init_attr->cap.max_send_wr) {
751 pr_debug("RSS QP with unsupported send attributes\n");
752 return ERR_PTR(-EOPNOTSUPP);
753 }
754
755 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
756 if (!qp)
757 return ERR_PTR(-ENOMEM);
758
759 qp->pri.vid = 0xFFFF;
760 qp->alt.vid = 0xFFFF;
761
762 err = create_qp_rss(to_mdev(pd->device), init_attr, &ucmd, qp);
763 if (err) {
764 kfree(qp);
765 return ERR_PTR(err);
766 }
767
768 qp->ibqp.qp_num = qp->mqp.qpn;
769
770 return &qp->ibqp;
771 }
772
773 /*
774 * This function allocates a WQN from a range which is consecutive and aligned
775 * to its size. In case the range is full, then it creates a new range and
776 * allocates WQN from it. The new range will be used for following allocations.
777 */
mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext * context,struct mlx4_ib_qp * qp,int range_size,int * wqn)778 static int mlx4_ib_alloc_wqn(struct mlx4_ib_ucontext *context,
779 struct mlx4_ib_qp *qp, int range_size, int *wqn)
780 {
781 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
782 struct mlx4_wqn_range *range;
783 int err = 0;
784
785 mutex_lock(&context->wqn_ranges_mutex);
786
787 range = list_first_entry_or_null(&context->wqn_ranges_list,
788 struct mlx4_wqn_range, list);
789
790 if (!range || (range->refcount == range->size) || range->dirty) {
791 range = kzalloc(sizeof(*range), GFP_KERNEL);
792 if (!range) {
793 err = -ENOMEM;
794 goto out;
795 }
796
797 err = mlx4_qp_reserve_range(dev->dev, range_size,
798 range_size, &range->base_wqn, 0,
799 qp->mqp.usage);
800 if (err) {
801 kfree(range);
802 goto out;
803 }
804
805 range->size = range_size;
806 list_add(&range->list, &context->wqn_ranges_list);
807 } else if (range_size != 1) {
808 /*
809 * Requesting a new range (>1) when last range is still open, is
810 * not valid.
811 */
812 err = -EINVAL;
813 goto out;
814 }
815
816 qp->wqn_range = range;
817
818 *wqn = range->base_wqn + range->refcount;
819
820 range->refcount++;
821
822 out:
823 mutex_unlock(&context->wqn_ranges_mutex);
824
825 return err;
826 }
827
mlx4_ib_release_wqn(struct mlx4_ib_ucontext * context,struct mlx4_ib_qp * qp,bool dirty_release)828 static void mlx4_ib_release_wqn(struct mlx4_ib_ucontext *context,
829 struct mlx4_ib_qp *qp, bool dirty_release)
830 {
831 struct mlx4_ib_dev *dev = to_mdev(context->ibucontext.device);
832 struct mlx4_wqn_range *range;
833
834 mutex_lock(&context->wqn_ranges_mutex);
835
836 range = qp->wqn_range;
837
838 range->refcount--;
839 if (!range->refcount) {
840 mlx4_qp_release_range(dev->dev, range->base_wqn,
841 range->size);
842 list_del(&range->list);
843 kfree(range);
844 } else if (dirty_release) {
845 /*
846 * A range which one of its WQNs is destroyed, won't be able to be
847 * reused for further WQN allocations.
848 * The next created WQ will allocate a new range.
849 */
850 range->dirty = 1;
851 }
852
853 mutex_unlock(&context->wqn_ranges_mutex);
854 }
855
create_qp_common(struct mlx4_ib_dev * dev,struct ib_pd * pd,enum mlx4_ib_source_type src,struct ib_qp_init_attr * init_attr,struct ib_udata * udata,int sqpn,struct mlx4_ib_qp ** caller_qp)856 static int create_qp_common(struct mlx4_ib_dev *dev, struct ib_pd *pd,
857 enum mlx4_ib_source_type src,
858 struct ib_qp_init_attr *init_attr,
859 struct ib_udata *udata, int sqpn,
860 struct mlx4_ib_qp **caller_qp)
861 {
862 int qpn;
863 int err;
864 struct mlx4_ib_sqp *sqp = NULL;
865 struct mlx4_ib_qp *qp;
866 enum mlx4_ib_qp_type qp_type = (enum mlx4_ib_qp_type) init_attr->qp_type;
867 struct mlx4_ib_cq *mcq;
868 unsigned long flags;
869 int range_size = 0;
870
871 /* When tunneling special qps, we use a plain UD qp */
872 if (sqpn) {
873 if (mlx4_is_mfunc(dev->dev) &&
874 (!mlx4_is_master(dev->dev) ||
875 !(init_attr->create_flags & MLX4_IB_SRIOV_SQP))) {
876 if (init_attr->qp_type == IB_QPT_GSI)
877 qp_type = MLX4_IB_QPT_PROXY_GSI;
878 else {
879 if (mlx4_is_master(dev->dev) ||
880 qp0_enabled_vf(dev->dev, sqpn))
881 qp_type = MLX4_IB_QPT_PROXY_SMI_OWNER;
882 else
883 qp_type = MLX4_IB_QPT_PROXY_SMI;
884 }
885 }
886 qpn = sqpn;
887 /* add extra sg entry for tunneling */
888 init_attr->cap.max_recv_sge++;
889 } else if (init_attr->create_flags & MLX4_IB_SRIOV_TUNNEL_QP) {
890 struct mlx4_ib_qp_tunnel_init_attr *tnl_init =
891 container_of(init_attr,
892 struct mlx4_ib_qp_tunnel_init_attr, init_attr);
893 if ((tnl_init->proxy_qp_type != IB_QPT_SMI &&
894 tnl_init->proxy_qp_type != IB_QPT_GSI) ||
895 !mlx4_is_master(dev->dev))
896 return -EINVAL;
897 if (tnl_init->proxy_qp_type == IB_QPT_GSI)
898 qp_type = MLX4_IB_QPT_TUN_GSI;
899 else if (tnl_init->slave == mlx4_master_func_num(dev->dev) ||
900 mlx4_vf_smi_enabled(dev->dev, tnl_init->slave,
901 tnl_init->port))
902 qp_type = MLX4_IB_QPT_TUN_SMI_OWNER;
903 else
904 qp_type = MLX4_IB_QPT_TUN_SMI;
905 /* we are definitely in the PPF here, since we are creating
906 * tunnel QPs. base_tunnel_sqpn is therefore valid. */
907 qpn = dev->dev->phys_caps.base_tunnel_sqpn + 8 * tnl_init->slave
908 + tnl_init->proxy_qp_type * 2 + tnl_init->port - 1;
909 sqpn = qpn;
910 }
911
912 if (!*caller_qp) {
913 if (qp_type == MLX4_IB_QPT_SMI || qp_type == MLX4_IB_QPT_GSI ||
914 (qp_type & (MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_SMI_OWNER |
915 MLX4_IB_QPT_PROXY_GSI | MLX4_IB_QPT_TUN_SMI_OWNER))) {
916 sqp = kzalloc(sizeof(struct mlx4_ib_sqp), GFP_KERNEL);
917 if (!sqp)
918 return -ENOMEM;
919 qp = &sqp->qp;
920 qp->pri.vid = 0xFFFF;
921 qp->alt.vid = 0xFFFF;
922 } else {
923 qp = kzalloc(sizeof(struct mlx4_ib_qp), GFP_KERNEL);
924 if (!qp)
925 return -ENOMEM;
926 qp->pri.vid = 0xFFFF;
927 qp->alt.vid = 0xFFFF;
928 }
929 } else
930 qp = *caller_qp;
931
932 qp->mlx4_ib_qp_type = qp_type;
933
934 mutex_init(&qp->mutex);
935 spin_lock_init(&qp->sq.lock);
936 spin_lock_init(&qp->rq.lock);
937 INIT_LIST_HEAD(&qp->gid_list);
938 INIT_LIST_HEAD(&qp->steering_rules);
939
940 qp->state = IB_QPS_RESET;
941 if (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR)
942 qp->sq_signal_bits = cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
943
944
945 if (pd->uobject) {
946 union {
947 struct mlx4_ib_create_qp qp;
948 struct mlx4_ib_create_wq wq;
949 } ucmd;
950 size_t copy_len;
951 int shift;
952 int n;
953
954 copy_len = (src == MLX4_IB_QP_SRC) ?
955 sizeof(struct mlx4_ib_create_qp) :
956 min(sizeof(struct mlx4_ib_create_wq), udata->inlen);
957
958 if (ib_copy_from_udata(&ucmd, udata, copy_len)) {
959 err = -EFAULT;
960 goto err;
961 }
962
963 if (src == MLX4_IB_RWQ_SRC) {
964 if (ucmd.wq.comp_mask || ucmd.wq.reserved[0] ||
965 ucmd.wq.reserved[1] || ucmd.wq.reserved[2]) {
966 pr_debug("user command isn't supported\n");
967 err = -EOPNOTSUPP;
968 goto err;
969 }
970
971 if (ucmd.wq.log_range_size >
972 ilog2(dev->dev->caps.max_rss_tbl_sz)) {
973 pr_debug("WQN range size must be equal or smaller than %d\n",
974 dev->dev->caps.max_rss_tbl_sz);
975 err = -EOPNOTSUPP;
976 goto err;
977 }
978 range_size = 1 << ucmd.wq.log_range_size;
979 } else {
980 qp->inl_recv_sz = ucmd.qp.inl_recv_sz;
981 }
982
983 if (init_attr->create_flags & IB_QP_CREATE_SCATTER_FCS) {
984 if (!(dev->dev->caps.flags &
985 MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
986 pr_debug("scatter FCS is unsupported\n");
987 err = -EOPNOTSUPP;
988 goto err;
989 }
990
991 qp->flags |= MLX4_IB_QP_SCATTER_FCS;
992 }
993
994 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
995 qp_has_rq(init_attr), qp, qp->inl_recv_sz);
996 if (err)
997 goto err;
998
999 if (src == MLX4_IB_QP_SRC) {
1000 qp->sq_no_prefetch = ucmd.qp.sq_no_prefetch;
1001
1002 err = set_user_sq_size(dev, qp,
1003 (struct mlx4_ib_create_qp *)
1004 &ucmd);
1005 if (err)
1006 goto err;
1007 } else {
1008 qp->sq_no_prefetch = 1;
1009 qp->sq.wqe_cnt = 1;
1010 qp->sq.wqe_shift = MLX4_IB_MIN_SQ_STRIDE;
1011 /* Allocated buffer expects to have at least that SQ
1012 * size.
1013 */
1014 qp->buf_size = (qp->rq.wqe_cnt << qp->rq.wqe_shift) +
1015 (qp->sq.wqe_cnt << qp->sq.wqe_shift);
1016 }
1017
1018 qp->umem = ib_umem_get(pd->uobject->context,
1019 (src == MLX4_IB_QP_SRC) ? ucmd.qp.buf_addr :
1020 ucmd.wq.buf_addr, qp->buf_size, 0, 0);
1021 if (IS_ERR(qp->umem)) {
1022 err = PTR_ERR(qp->umem);
1023 goto err;
1024 }
1025
1026 n = ib_umem_page_count(qp->umem);
1027 shift = mlx4_ib_umem_calc_optimal_mtt_size(qp->umem, 0, &n);
1028 err = mlx4_mtt_init(dev->dev, n, shift, &qp->mtt);
1029
1030 if (err)
1031 goto err_buf;
1032
1033 err = mlx4_ib_umem_write_mtt(dev, &qp->mtt, qp->umem);
1034 if (err)
1035 goto err_mtt;
1036
1037 if (qp_has_rq(init_attr)) {
1038 err = mlx4_ib_db_map_user(to_mucontext(pd->uobject->context),
1039 (src == MLX4_IB_QP_SRC) ? ucmd.qp.db_addr :
1040 ucmd.wq.db_addr, &qp->db);
1041 if (err)
1042 goto err_mtt;
1043 }
1044 qp->mqp.usage = MLX4_RES_USAGE_USER_VERBS;
1045 } else {
1046 err = set_rq_size(dev, &init_attr->cap, !!pd->uobject,
1047 qp_has_rq(init_attr), qp, 0);
1048 if (err)
1049 goto err;
1050
1051 qp->sq_no_prefetch = 0;
1052
1053 if (init_attr->create_flags & IB_QP_CREATE_IPOIB_UD_LSO)
1054 qp->flags |= MLX4_IB_QP_LSO;
1055
1056 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1057 if (dev->steering_support ==
1058 MLX4_STEERING_MODE_DEVICE_MANAGED)
1059 qp->flags |= MLX4_IB_QP_NETIF;
1060 else
1061 goto err;
1062 }
1063
1064 err = set_kernel_sq_size(dev, &init_attr->cap, qp_type, qp);
1065 if (err)
1066 goto err;
1067
1068 if (qp_has_rq(init_attr)) {
1069 err = mlx4_db_alloc(dev->dev, &qp->db, 0);
1070 if (err)
1071 goto err;
1072
1073 *qp->db.db = 0;
1074 }
1075
1076 if (mlx4_buf_alloc(dev->dev, qp->buf_size, PAGE_SIZE * 2,
1077 &qp->buf)) {
1078 err = -ENOMEM;
1079 goto err_db;
1080 }
1081
1082 err = mlx4_mtt_init(dev->dev, qp->buf.npages, qp->buf.page_shift,
1083 &qp->mtt);
1084 if (err)
1085 goto err_buf;
1086
1087 err = mlx4_buf_write_mtt(dev->dev, &qp->mtt, &qp->buf);
1088 if (err)
1089 goto err_mtt;
1090
1091 qp->sq.wrid = kvmalloc_array(qp->sq.wqe_cnt,
1092 sizeof(u64), GFP_KERNEL);
1093 qp->rq.wrid = kvmalloc_array(qp->rq.wqe_cnt,
1094 sizeof(u64), GFP_KERNEL);
1095 if (!qp->sq.wrid || !qp->rq.wrid) {
1096 err = -ENOMEM;
1097 goto err_wrid;
1098 }
1099 qp->mqp.usage = MLX4_RES_USAGE_DRIVER;
1100 }
1101
1102 if (sqpn) {
1103 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1104 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
1105 if (alloc_proxy_bufs(pd->device, qp)) {
1106 err = -ENOMEM;
1107 goto err_wrid;
1108 }
1109 }
1110 } else if (src == MLX4_IB_RWQ_SRC) {
1111 err = mlx4_ib_alloc_wqn(to_mucontext(pd->uobject->context), qp,
1112 range_size, &qpn);
1113 if (err)
1114 goto err_wrid;
1115 } else {
1116 /* Raw packet QPNs may not have bits 6,7 set in their qp_num;
1117 * otherwise, the WQE BlueFlame setup flow wrongly causes
1118 * VLAN insertion. */
1119 if (init_attr->qp_type == IB_QPT_RAW_PACKET)
1120 err = mlx4_qp_reserve_range(dev->dev, 1, 1, &qpn,
1121 (init_attr->cap.max_send_wr ?
1122 MLX4_RESERVE_ETH_BF_QP : 0) |
1123 (init_attr->cap.max_recv_wr ?
1124 MLX4_RESERVE_A0_QP : 0),
1125 qp->mqp.usage);
1126 else
1127 if (qp->flags & MLX4_IB_QP_NETIF)
1128 err = mlx4_ib_steer_qp_alloc(dev, 1, &qpn);
1129 else
1130 err = mlx4_qp_reserve_range(dev->dev, 1, 1,
1131 &qpn, 0, qp->mqp.usage);
1132 if (err)
1133 goto err_proxy;
1134 }
1135
1136 if (init_attr->create_flags & IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK)
1137 qp->flags |= MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1138
1139 err = mlx4_qp_alloc(dev->dev, qpn, &qp->mqp);
1140 if (err)
1141 goto err_qpn;
1142
1143 if (init_attr->qp_type == IB_QPT_XRC_TGT)
1144 qp->mqp.qpn |= (1 << 23);
1145
1146 /*
1147 * Hardware wants QPN written in big-endian order (after
1148 * shifting) for send doorbell. Precompute this value to save
1149 * a little bit when posting sends.
1150 */
1151 qp->doorbell_qpn = swab32(qp->mqp.qpn << 8);
1152
1153 qp->mqp.event = (src == MLX4_IB_QP_SRC) ? mlx4_ib_qp_event :
1154 mlx4_ib_wq_event;
1155
1156 if (!*caller_qp)
1157 *caller_qp = qp;
1158
1159 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1160 mlx4_ib_lock_cqs(to_mcq(init_attr->send_cq),
1161 to_mcq(init_attr->recv_cq));
1162 /* Maintain device to QPs access, needed for further handling
1163 * via reset flow
1164 */
1165 list_add_tail(&qp->qps_list, &dev->qp_list);
1166 /* Maintain CQ to QPs access, needed for further handling
1167 * via reset flow
1168 */
1169 mcq = to_mcq(init_attr->send_cq);
1170 list_add_tail(&qp->cq_send_list, &mcq->send_qp_list);
1171 mcq = to_mcq(init_attr->recv_cq);
1172 list_add_tail(&qp->cq_recv_list, &mcq->recv_qp_list);
1173 mlx4_ib_unlock_cqs(to_mcq(init_attr->send_cq),
1174 to_mcq(init_attr->recv_cq));
1175 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1176 return 0;
1177
1178 err_qpn:
1179 if (!sqpn) {
1180 if (qp->flags & MLX4_IB_QP_NETIF)
1181 mlx4_ib_steer_qp_free(dev, qpn, 1);
1182 else if (src == MLX4_IB_RWQ_SRC)
1183 mlx4_ib_release_wqn(to_mucontext(pd->uobject->context),
1184 qp, 0);
1185 else
1186 mlx4_qp_release_range(dev->dev, qpn, 1);
1187 }
1188 err_proxy:
1189 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
1190 free_proxy_bufs(pd->device, qp);
1191 err_wrid:
1192 if (pd->uobject) {
1193 if (qp_has_rq(init_attr))
1194 mlx4_ib_db_unmap_user(to_mucontext(pd->uobject->context), &qp->db);
1195 } else {
1196 kvfree(qp->sq.wrid);
1197 kvfree(qp->rq.wrid);
1198 }
1199
1200 err_mtt:
1201 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1202
1203 err_buf:
1204 if (pd->uobject)
1205 ib_umem_release(qp->umem);
1206 else
1207 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1208
1209 err_db:
1210 if (!pd->uobject && qp_has_rq(init_attr))
1211 mlx4_db_free(dev->dev, &qp->db);
1212
1213 err:
1214 if (sqp)
1215 kfree(sqp);
1216 else if (!*caller_qp)
1217 kfree(qp);
1218 return err;
1219 }
1220
to_mlx4_state(enum ib_qp_state state)1221 static enum mlx4_qp_state to_mlx4_state(enum ib_qp_state state)
1222 {
1223 switch (state) {
1224 case IB_QPS_RESET: return MLX4_QP_STATE_RST;
1225 case IB_QPS_INIT: return MLX4_QP_STATE_INIT;
1226 case IB_QPS_RTR: return MLX4_QP_STATE_RTR;
1227 case IB_QPS_RTS: return MLX4_QP_STATE_RTS;
1228 case IB_QPS_SQD: return MLX4_QP_STATE_SQD;
1229 case IB_QPS_SQE: return MLX4_QP_STATE_SQER;
1230 case IB_QPS_ERR: return MLX4_QP_STATE_ERR;
1231 default: return -1;
1232 }
1233 }
1234
mlx4_ib_lock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)1235 static void mlx4_ib_lock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1236 __acquires(&send_cq->lock) __acquires(&recv_cq->lock)
1237 {
1238 if (send_cq == recv_cq) {
1239 spin_lock(&send_cq->lock);
1240 __acquire(&recv_cq->lock);
1241 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1242 spin_lock(&send_cq->lock);
1243 spin_lock_nested(&recv_cq->lock, SINGLE_DEPTH_NESTING);
1244 } else {
1245 spin_lock(&recv_cq->lock);
1246 spin_lock_nested(&send_cq->lock, SINGLE_DEPTH_NESTING);
1247 }
1248 }
1249
mlx4_ib_unlock_cqs(struct mlx4_ib_cq * send_cq,struct mlx4_ib_cq * recv_cq)1250 static void mlx4_ib_unlock_cqs(struct mlx4_ib_cq *send_cq, struct mlx4_ib_cq *recv_cq)
1251 __releases(&send_cq->lock) __releases(&recv_cq->lock)
1252 {
1253 if (send_cq == recv_cq) {
1254 __release(&recv_cq->lock);
1255 spin_unlock(&send_cq->lock);
1256 } else if (send_cq->mcq.cqn < recv_cq->mcq.cqn) {
1257 spin_unlock(&recv_cq->lock);
1258 spin_unlock(&send_cq->lock);
1259 } else {
1260 spin_unlock(&send_cq->lock);
1261 spin_unlock(&recv_cq->lock);
1262 }
1263 }
1264
del_gid_entries(struct mlx4_ib_qp * qp)1265 static void del_gid_entries(struct mlx4_ib_qp *qp)
1266 {
1267 struct mlx4_ib_gid_entry *ge, *tmp;
1268
1269 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1270 list_del(&ge->list);
1271 kfree(ge);
1272 }
1273 }
1274
get_pd(struct mlx4_ib_qp * qp)1275 static struct mlx4_ib_pd *get_pd(struct mlx4_ib_qp *qp)
1276 {
1277 if (qp->ibqp.qp_type == IB_QPT_XRC_TGT)
1278 return to_mpd(to_mxrcd(qp->ibqp.xrcd)->pd);
1279 else
1280 return to_mpd(qp->ibqp.pd);
1281 }
1282
get_cqs(struct mlx4_ib_qp * qp,enum mlx4_ib_source_type src,struct mlx4_ib_cq ** send_cq,struct mlx4_ib_cq ** recv_cq)1283 static void get_cqs(struct mlx4_ib_qp *qp, enum mlx4_ib_source_type src,
1284 struct mlx4_ib_cq **send_cq, struct mlx4_ib_cq **recv_cq)
1285 {
1286 switch (qp->ibqp.qp_type) {
1287 case IB_QPT_XRC_TGT:
1288 *send_cq = to_mcq(to_mxrcd(qp->ibqp.xrcd)->cq);
1289 *recv_cq = *send_cq;
1290 break;
1291 case IB_QPT_XRC_INI:
1292 *send_cq = to_mcq(qp->ibqp.send_cq);
1293 *recv_cq = *send_cq;
1294 break;
1295 default:
1296 *recv_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.recv_cq) :
1297 to_mcq(qp->ibwq.cq);
1298 *send_cq = (src == MLX4_IB_QP_SRC) ? to_mcq(qp->ibqp.send_cq) :
1299 *recv_cq;
1300 break;
1301 }
1302 }
1303
destroy_qp_rss(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1304 static void destroy_qp_rss(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1305 {
1306 if (qp->state != IB_QPS_RESET) {
1307 int i;
1308
1309 for (i = 0; i < (1 << qp->ibqp.rwq_ind_tbl->log_ind_tbl_size);
1310 i++) {
1311 struct ib_wq *ibwq = qp->ibqp.rwq_ind_tbl->ind_tbl[i];
1312 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1313
1314 mutex_lock(&wq->mutex);
1315
1316 wq->rss_usecnt--;
1317
1318 mutex_unlock(&wq->mutex);
1319 }
1320
1321 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1322 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1323 pr_warn("modify QP %06x to RESET failed.\n",
1324 qp->mqp.qpn);
1325 }
1326
1327 mlx4_qp_remove(dev->dev, &qp->mqp);
1328 mlx4_qp_free(dev->dev, &qp->mqp);
1329 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1330 del_gid_entries(qp);
1331 kfree(qp->rss_ctx);
1332 }
1333
destroy_qp_common(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,enum mlx4_ib_source_type src,int is_user)1334 static void destroy_qp_common(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp,
1335 enum mlx4_ib_source_type src, int is_user)
1336 {
1337 struct mlx4_ib_cq *send_cq, *recv_cq;
1338 unsigned long flags;
1339
1340 if (qp->state != IB_QPS_RESET) {
1341 if (mlx4_qp_modify(dev->dev, NULL, to_mlx4_state(qp->state),
1342 MLX4_QP_STATE_RST, NULL, 0, 0, &qp->mqp))
1343 pr_warn("modify QP %06x to RESET failed.\n",
1344 qp->mqp.qpn);
1345 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
1346 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
1347 qp->pri.smac = 0;
1348 qp->pri.smac_port = 0;
1349 }
1350 if (qp->alt.smac) {
1351 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
1352 qp->alt.smac = 0;
1353 }
1354 if (qp->pri.vid < 0x1000) {
1355 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
1356 qp->pri.vid = 0xFFFF;
1357 qp->pri.candidate_vid = 0xFFFF;
1358 qp->pri.update_vid = 0;
1359 }
1360 if (qp->alt.vid < 0x1000) {
1361 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
1362 qp->alt.vid = 0xFFFF;
1363 qp->alt.candidate_vid = 0xFFFF;
1364 qp->alt.update_vid = 0;
1365 }
1366 }
1367
1368 get_cqs(qp, src, &send_cq, &recv_cq);
1369
1370 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
1371 mlx4_ib_lock_cqs(send_cq, recv_cq);
1372
1373 /* del from lists under both locks above to protect reset flow paths */
1374 list_del(&qp->qps_list);
1375 list_del(&qp->cq_send_list);
1376 list_del(&qp->cq_recv_list);
1377 if (!is_user) {
1378 __mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
1379 qp->ibqp.srq ? to_msrq(qp->ibqp.srq): NULL);
1380 if (send_cq != recv_cq)
1381 __mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
1382 }
1383
1384 mlx4_qp_remove(dev->dev, &qp->mqp);
1385
1386 mlx4_ib_unlock_cqs(send_cq, recv_cq);
1387 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
1388
1389 mlx4_qp_free(dev->dev, &qp->mqp);
1390
1391 if (!is_sqp(dev, qp) && !is_tunnel_qp(dev, qp)) {
1392 if (qp->flags & MLX4_IB_QP_NETIF)
1393 mlx4_ib_steer_qp_free(dev, qp->mqp.qpn, 1);
1394 else if (src == MLX4_IB_RWQ_SRC)
1395 mlx4_ib_release_wqn(to_mucontext(
1396 qp->ibwq.uobject->context), qp, 1);
1397 else
1398 mlx4_qp_release_range(dev->dev, qp->mqp.qpn, 1);
1399 }
1400
1401 mlx4_mtt_cleanup(dev->dev, &qp->mtt);
1402
1403 if (is_user) {
1404 if (qp->rq.wqe_cnt) {
1405 struct mlx4_ib_ucontext *mcontext = !src ?
1406 to_mucontext(qp->ibqp.uobject->context) :
1407 to_mucontext(qp->ibwq.uobject->context);
1408 mlx4_ib_db_unmap_user(mcontext, &qp->db);
1409 }
1410 ib_umem_release(qp->umem);
1411 } else {
1412 kvfree(qp->sq.wrid);
1413 kvfree(qp->rq.wrid);
1414 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
1415 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI))
1416 free_proxy_bufs(&dev->ib_dev, qp);
1417 mlx4_buf_free(dev->dev, qp->buf_size, &qp->buf);
1418 if (qp->rq.wqe_cnt)
1419 mlx4_db_free(dev->dev, &qp->db);
1420 }
1421
1422 del_gid_entries(qp);
1423 }
1424
get_sqp_num(struct mlx4_ib_dev * dev,struct ib_qp_init_attr * attr)1425 static u32 get_sqp_num(struct mlx4_ib_dev *dev, struct ib_qp_init_attr *attr)
1426 {
1427 /* Native or PPF */
1428 if (!mlx4_is_mfunc(dev->dev) ||
1429 (mlx4_is_master(dev->dev) &&
1430 attr->create_flags & MLX4_IB_SRIOV_SQP)) {
1431 return dev->dev->phys_caps.base_sqpn +
1432 (attr->qp_type == IB_QPT_SMI ? 0 : 2) +
1433 attr->port_num - 1;
1434 }
1435 /* PF or VF -- creating proxies */
1436 if (attr->qp_type == IB_QPT_SMI)
1437 return dev->dev->caps.spec_qps[attr->port_num - 1].qp0_proxy;
1438 else
1439 return dev->dev->caps.spec_qps[attr->port_num - 1].qp1_proxy;
1440 }
1441
_mlx4_ib_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1442 static struct ib_qp *_mlx4_ib_create_qp(struct ib_pd *pd,
1443 struct ib_qp_init_attr *init_attr,
1444 struct ib_udata *udata)
1445 {
1446 struct mlx4_ib_qp *qp = NULL;
1447 int err;
1448 int sup_u_create_flags = MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK;
1449 u16 xrcdn = 0;
1450
1451 if (init_attr->rwq_ind_tbl)
1452 return _mlx4_ib_create_qp_rss(pd, init_attr, udata);
1453
1454 /*
1455 * We only support LSO, vendor flag1, and multicast loopback blocking,
1456 * and only for kernel UD QPs.
1457 */
1458 if (init_attr->create_flags & ~(MLX4_IB_QP_LSO |
1459 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK |
1460 MLX4_IB_SRIOV_TUNNEL_QP |
1461 MLX4_IB_SRIOV_SQP |
1462 MLX4_IB_QP_NETIF |
1463 MLX4_IB_QP_CREATE_ROCE_V2_GSI))
1464 return ERR_PTR(-EINVAL);
1465
1466 if (init_attr->create_flags & IB_QP_CREATE_NETIF_QP) {
1467 if (init_attr->qp_type != IB_QPT_UD)
1468 return ERR_PTR(-EINVAL);
1469 }
1470
1471 if (init_attr->create_flags) {
1472 if (udata && init_attr->create_flags & ~(sup_u_create_flags))
1473 return ERR_PTR(-EINVAL);
1474
1475 if ((init_attr->create_flags & ~(MLX4_IB_SRIOV_SQP |
1476 MLX4_IB_QP_CREATE_ROCE_V2_GSI |
1477 MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) &&
1478 init_attr->qp_type != IB_QPT_UD) ||
1479 (init_attr->create_flags & MLX4_IB_SRIOV_SQP &&
1480 init_attr->qp_type > IB_QPT_GSI) ||
1481 (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI &&
1482 init_attr->qp_type != IB_QPT_GSI))
1483 return ERR_PTR(-EINVAL);
1484 }
1485
1486 switch (init_attr->qp_type) {
1487 case IB_QPT_XRC_TGT:
1488 pd = to_mxrcd(init_attr->xrcd)->pd;
1489 xrcdn = to_mxrcd(init_attr->xrcd)->xrcdn;
1490 init_attr->send_cq = to_mxrcd(init_attr->xrcd)->cq;
1491 /* fall through */
1492 case IB_QPT_XRC_INI:
1493 if (!(to_mdev(pd->device)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
1494 return ERR_PTR(-ENOSYS);
1495 init_attr->recv_cq = init_attr->send_cq;
1496 /* fall through */
1497 case IB_QPT_RC:
1498 case IB_QPT_UC:
1499 case IB_QPT_RAW_PACKET:
1500 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
1501 if (!qp)
1502 return ERR_PTR(-ENOMEM);
1503 qp->pri.vid = 0xFFFF;
1504 qp->alt.vid = 0xFFFF;
1505 /* fall through */
1506 case IB_QPT_UD:
1507 {
1508 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1509 init_attr, udata, 0, &qp);
1510 if (err) {
1511 kfree(qp);
1512 return ERR_PTR(err);
1513 }
1514
1515 qp->ibqp.qp_num = qp->mqp.qpn;
1516 qp->xrcdn = xrcdn;
1517
1518 break;
1519 }
1520 case IB_QPT_SMI:
1521 case IB_QPT_GSI:
1522 {
1523 int sqpn;
1524
1525 /* Userspace is not allowed to create special QPs: */
1526 if (udata)
1527 return ERR_PTR(-EINVAL);
1528 if (init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI) {
1529 int res = mlx4_qp_reserve_range(to_mdev(pd->device)->dev,
1530 1, 1, &sqpn, 0,
1531 MLX4_RES_USAGE_DRIVER);
1532
1533 if (res)
1534 return ERR_PTR(res);
1535 } else {
1536 sqpn = get_sqp_num(to_mdev(pd->device), init_attr);
1537 }
1538
1539 err = create_qp_common(to_mdev(pd->device), pd, MLX4_IB_QP_SRC,
1540 init_attr, udata, sqpn, &qp);
1541 if (err)
1542 return ERR_PTR(err);
1543
1544 qp->port = init_attr->port_num;
1545 qp->ibqp.qp_num = init_attr->qp_type == IB_QPT_SMI ? 0 :
1546 init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI ? sqpn : 1;
1547 break;
1548 }
1549 default:
1550 /* Don't support raw QPs */
1551 return ERR_PTR(-EINVAL);
1552 }
1553
1554 return &qp->ibqp;
1555 }
1556
mlx4_ib_create_qp(struct ib_pd * pd,struct ib_qp_init_attr * init_attr,struct ib_udata * udata)1557 struct ib_qp *mlx4_ib_create_qp(struct ib_pd *pd,
1558 struct ib_qp_init_attr *init_attr,
1559 struct ib_udata *udata) {
1560 struct ib_device *device = pd ? pd->device : init_attr->xrcd->device;
1561 struct ib_qp *ibqp;
1562 struct mlx4_ib_dev *dev = to_mdev(device);
1563
1564 ibqp = _mlx4_ib_create_qp(pd, init_attr, udata);
1565
1566 if (!IS_ERR(ibqp) &&
1567 (init_attr->qp_type == IB_QPT_GSI) &&
1568 !(init_attr->create_flags & MLX4_IB_QP_CREATE_ROCE_V2_GSI)) {
1569 struct mlx4_ib_sqp *sqp = to_msqp((to_mqp(ibqp)));
1570 int is_eth = rdma_cap_eth_ah(&dev->ib_dev, init_attr->port_num);
1571
1572 if (is_eth &&
1573 dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ROCE_V1_V2) {
1574 init_attr->create_flags |= MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1575 sqp->roce_v2_gsi = ib_create_qp(pd, init_attr);
1576
1577 if (IS_ERR(sqp->roce_v2_gsi)) {
1578 pr_err("Failed to create GSI QP for RoCEv2 (%ld)\n", PTR_ERR(sqp->roce_v2_gsi));
1579 sqp->roce_v2_gsi = NULL;
1580 } else {
1581 sqp = to_msqp(to_mqp(sqp->roce_v2_gsi));
1582 sqp->qp.flags |= MLX4_IB_ROCE_V2_GSI_QP;
1583 }
1584
1585 init_attr->create_flags &= ~MLX4_IB_QP_CREATE_ROCE_V2_GSI;
1586 }
1587 }
1588 return ibqp;
1589 }
1590
_mlx4_ib_destroy_qp(struct ib_qp * qp)1591 static int _mlx4_ib_destroy_qp(struct ib_qp *qp)
1592 {
1593 struct mlx4_ib_dev *dev = to_mdev(qp->device);
1594 struct mlx4_ib_qp *mqp = to_mqp(qp);
1595
1596 if (is_qp0(dev, mqp))
1597 mlx4_CLOSE_PORT(dev->dev, mqp->port);
1598
1599 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI &&
1600 dev->qp1_proxy[mqp->port - 1] == mqp) {
1601 mutex_lock(&dev->qp1_proxy_lock[mqp->port - 1]);
1602 dev->qp1_proxy[mqp->port - 1] = NULL;
1603 mutex_unlock(&dev->qp1_proxy_lock[mqp->port - 1]);
1604 }
1605
1606 if (mqp->counter_index)
1607 mlx4_ib_free_qp_counter(dev, mqp);
1608
1609 if (qp->rwq_ind_tbl) {
1610 destroy_qp_rss(dev, mqp);
1611 } else {
1612 struct mlx4_ib_pd *pd;
1613
1614 pd = get_pd(mqp);
1615 destroy_qp_common(dev, mqp, MLX4_IB_QP_SRC, !!pd->ibpd.uobject);
1616 }
1617
1618 if (is_sqp(dev, mqp))
1619 kfree(to_msqp(mqp));
1620 else
1621 kfree(mqp);
1622
1623 return 0;
1624 }
1625
mlx4_ib_destroy_qp(struct ib_qp * qp)1626 int mlx4_ib_destroy_qp(struct ib_qp *qp)
1627 {
1628 struct mlx4_ib_qp *mqp = to_mqp(qp);
1629
1630 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
1631 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
1632
1633 if (sqp->roce_v2_gsi)
1634 ib_destroy_qp(sqp->roce_v2_gsi);
1635 }
1636
1637 return _mlx4_ib_destroy_qp(qp);
1638 }
1639
to_mlx4_st(struct mlx4_ib_dev * dev,enum mlx4_ib_qp_type type)1640 static int to_mlx4_st(struct mlx4_ib_dev *dev, enum mlx4_ib_qp_type type)
1641 {
1642 switch (type) {
1643 case MLX4_IB_QPT_RC: return MLX4_QP_ST_RC;
1644 case MLX4_IB_QPT_UC: return MLX4_QP_ST_UC;
1645 case MLX4_IB_QPT_UD: return MLX4_QP_ST_UD;
1646 case MLX4_IB_QPT_XRC_INI:
1647 case MLX4_IB_QPT_XRC_TGT: return MLX4_QP_ST_XRC;
1648 case MLX4_IB_QPT_SMI:
1649 case MLX4_IB_QPT_GSI:
1650 case MLX4_IB_QPT_RAW_PACKET: return MLX4_QP_ST_MLX;
1651
1652 case MLX4_IB_QPT_PROXY_SMI_OWNER:
1653 case MLX4_IB_QPT_TUN_SMI_OWNER: return (mlx4_is_mfunc(dev->dev) ?
1654 MLX4_QP_ST_MLX : -1);
1655 case MLX4_IB_QPT_PROXY_SMI:
1656 case MLX4_IB_QPT_TUN_SMI:
1657 case MLX4_IB_QPT_PROXY_GSI:
1658 case MLX4_IB_QPT_TUN_GSI: return (mlx4_is_mfunc(dev->dev) ?
1659 MLX4_QP_ST_UD : -1);
1660 default: return -1;
1661 }
1662 }
1663
to_mlx4_access_flags(struct mlx4_ib_qp * qp,const struct ib_qp_attr * attr,int attr_mask)1664 static __be32 to_mlx4_access_flags(struct mlx4_ib_qp *qp, const struct ib_qp_attr *attr,
1665 int attr_mask)
1666 {
1667 u8 dest_rd_atomic;
1668 u32 access_flags;
1669 u32 hw_access_flags = 0;
1670
1671 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
1672 dest_rd_atomic = attr->max_dest_rd_atomic;
1673 else
1674 dest_rd_atomic = qp->resp_depth;
1675
1676 if (attr_mask & IB_QP_ACCESS_FLAGS)
1677 access_flags = attr->qp_access_flags;
1678 else
1679 access_flags = qp->atomic_rd_en;
1680
1681 if (!dest_rd_atomic)
1682 access_flags &= IB_ACCESS_REMOTE_WRITE;
1683
1684 if (access_flags & IB_ACCESS_REMOTE_READ)
1685 hw_access_flags |= MLX4_QP_BIT_RRE;
1686 if (access_flags & IB_ACCESS_REMOTE_ATOMIC)
1687 hw_access_flags |= MLX4_QP_BIT_RAE;
1688 if (access_flags & IB_ACCESS_REMOTE_WRITE)
1689 hw_access_flags |= MLX4_QP_BIT_RWE;
1690
1691 return cpu_to_be32(hw_access_flags);
1692 }
1693
store_sqp_attrs(struct mlx4_ib_sqp * sqp,const struct ib_qp_attr * attr,int attr_mask)1694 static void store_sqp_attrs(struct mlx4_ib_sqp *sqp, const struct ib_qp_attr *attr,
1695 int attr_mask)
1696 {
1697 if (attr_mask & IB_QP_PKEY_INDEX)
1698 sqp->pkey_index = attr->pkey_index;
1699 if (attr_mask & IB_QP_QKEY)
1700 sqp->qkey = attr->qkey;
1701 if (attr_mask & IB_QP_SQ_PSN)
1702 sqp->send_psn = attr->sq_psn;
1703 }
1704
mlx4_set_sched(struct mlx4_qp_path * path,u8 port)1705 static void mlx4_set_sched(struct mlx4_qp_path *path, u8 port)
1706 {
1707 path->sched_queue = (path->sched_queue & 0xbf) | ((port - 1) << 6);
1708 }
1709
_mlx4_set_path(struct mlx4_ib_dev * dev,const struct rdma_ah_attr * ah,u64 smac,u16 vlan_tag,struct mlx4_qp_path * path,struct mlx4_roce_smac_vlan_info * smac_info,u8 port)1710 static int _mlx4_set_path(struct mlx4_ib_dev *dev,
1711 const struct rdma_ah_attr *ah,
1712 u64 smac, u16 vlan_tag, struct mlx4_qp_path *path,
1713 struct mlx4_roce_smac_vlan_info *smac_info, u8 port)
1714 {
1715 int vidx;
1716 int smac_index;
1717 int err;
1718
1719 path->grh_mylmc = rdma_ah_get_path_bits(ah) & 0x7f;
1720 path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
1721 if (rdma_ah_get_static_rate(ah)) {
1722 path->static_rate = rdma_ah_get_static_rate(ah) +
1723 MLX4_STAT_RATE_OFFSET;
1724 while (path->static_rate > IB_RATE_2_5_GBPS + MLX4_STAT_RATE_OFFSET &&
1725 !(1 << path->static_rate & dev->dev->caps.stat_rate_support))
1726 --path->static_rate;
1727 } else
1728 path->static_rate = 0;
1729
1730 if (rdma_ah_get_ah_flags(ah) & IB_AH_GRH) {
1731 const struct ib_global_route *grh = rdma_ah_read_grh(ah);
1732 int real_sgid_index =
1733 mlx4_ib_gid_index_to_real_index(dev, grh->sgid_attr);
1734
1735 if (real_sgid_index < 0)
1736 return real_sgid_index;
1737 if (real_sgid_index >= dev->dev->caps.gid_table_len[port]) {
1738 pr_err("sgid_index (%u) too large. max is %d\n",
1739 real_sgid_index, dev->dev->caps.gid_table_len[port] - 1);
1740 return -1;
1741 }
1742
1743 path->grh_mylmc |= 1 << 7;
1744 path->mgid_index = real_sgid_index;
1745 path->hop_limit = grh->hop_limit;
1746 path->tclass_flowlabel =
1747 cpu_to_be32((grh->traffic_class << 20) |
1748 (grh->flow_label));
1749 memcpy(path->rgid, grh->dgid.raw, 16);
1750 }
1751
1752 if (ah->type == RDMA_AH_ATTR_TYPE_ROCE) {
1753 if (!(rdma_ah_get_ah_flags(ah) & IB_AH_GRH))
1754 return -1;
1755
1756 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1757 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 7) << 3);
1758
1759 path->feup |= MLX4_FEUP_FORCE_ETH_UP;
1760 if (vlan_tag < 0x1000) {
1761 if (smac_info->vid < 0x1000) {
1762 /* both valid vlan ids */
1763 if (smac_info->vid != vlan_tag) {
1764 /* different VIDs. unreg old and reg new */
1765 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1766 if (err)
1767 return err;
1768 smac_info->candidate_vid = vlan_tag;
1769 smac_info->candidate_vlan_index = vidx;
1770 smac_info->candidate_vlan_port = port;
1771 smac_info->update_vid = 1;
1772 path->vlan_index = vidx;
1773 } else {
1774 path->vlan_index = smac_info->vlan_index;
1775 }
1776 } else {
1777 /* no current vlan tag in qp */
1778 err = mlx4_register_vlan(dev->dev, port, vlan_tag, &vidx);
1779 if (err)
1780 return err;
1781 smac_info->candidate_vid = vlan_tag;
1782 smac_info->candidate_vlan_index = vidx;
1783 smac_info->candidate_vlan_port = port;
1784 smac_info->update_vid = 1;
1785 path->vlan_index = vidx;
1786 }
1787 path->feup |= MLX4_FVL_FORCE_ETH_VLAN;
1788 path->fl = 1 << 6;
1789 } else {
1790 /* have current vlan tag. unregister it at modify-qp success */
1791 if (smac_info->vid < 0x1000) {
1792 smac_info->candidate_vid = 0xFFFF;
1793 smac_info->update_vid = 1;
1794 }
1795 }
1796
1797 /* get smac_index for RoCE use.
1798 * If no smac was yet assigned, register one.
1799 * If one was already assigned, but the new mac differs,
1800 * unregister the old one and register the new one.
1801 */
1802 if ((!smac_info->smac && !smac_info->smac_port) ||
1803 smac_info->smac != smac) {
1804 /* register candidate now, unreg if needed, after success */
1805 smac_index = mlx4_register_mac(dev->dev, port, smac);
1806 if (smac_index >= 0) {
1807 smac_info->candidate_smac_index = smac_index;
1808 smac_info->candidate_smac = smac;
1809 smac_info->candidate_smac_port = port;
1810 } else {
1811 return -EINVAL;
1812 }
1813 } else {
1814 smac_index = smac_info->smac_index;
1815 }
1816 memcpy(path->dmac, ah->roce.dmac, 6);
1817 path->ackto = MLX4_IB_LINK_TYPE_ETH;
1818 /* put MAC table smac index for IBoE */
1819 path->grh_mylmc = (u8) (smac_index) | 0x80;
1820 } else {
1821 path->sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE |
1822 ((port - 1) << 6) | ((rdma_ah_get_sl(ah) & 0xf) << 2);
1823 }
1824
1825 return 0;
1826 }
1827
mlx4_set_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port,u16 vlan_id,u8 * smac)1828 static int mlx4_set_path(struct mlx4_ib_dev *dev, const struct ib_qp_attr *qp,
1829 enum ib_qp_attr_mask qp_attr_mask,
1830 struct mlx4_ib_qp *mqp,
1831 struct mlx4_qp_path *path, u8 port,
1832 u16 vlan_id, u8 *smac)
1833 {
1834 return _mlx4_set_path(dev, &qp->ah_attr,
1835 mlx4_mac_to_u64(smac),
1836 vlan_id,
1837 path, &mqp->pri, port);
1838 }
1839
mlx4_set_alt_path(struct mlx4_ib_dev * dev,const struct ib_qp_attr * qp,enum ib_qp_attr_mask qp_attr_mask,struct mlx4_ib_qp * mqp,struct mlx4_qp_path * path,u8 port)1840 static int mlx4_set_alt_path(struct mlx4_ib_dev *dev,
1841 const struct ib_qp_attr *qp,
1842 enum ib_qp_attr_mask qp_attr_mask,
1843 struct mlx4_ib_qp *mqp,
1844 struct mlx4_qp_path *path, u8 port)
1845 {
1846 return _mlx4_set_path(dev, &qp->alt_ah_attr,
1847 0,
1848 0xffff,
1849 path, &mqp->alt, port);
1850 }
1851
update_mcg_macs(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1852 static void update_mcg_macs(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1853 {
1854 struct mlx4_ib_gid_entry *ge, *tmp;
1855
1856 list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
1857 if (!ge->added && mlx4_ib_add_mc(dev, qp, &ge->gid)) {
1858 ge->added = 1;
1859 ge->port = qp->port;
1860 }
1861 }
1862 }
1863
handle_eth_ud_smac_index(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp,struct mlx4_qp_context * context)1864 static int handle_eth_ud_smac_index(struct mlx4_ib_dev *dev,
1865 struct mlx4_ib_qp *qp,
1866 struct mlx4_qp_context *context)
1867 {
1868 u64 u64_mac;
1869 int smac_index;
1870
1871 u64_mac = atomic64_read(&dev->iboe.mac[qp->port - 1]);
1872
1873 context->pri_path.sched_queue = MLX4_IB_DEFAULT_SCHED_QUEUE | ((qp->port - 1) << 6);
1874 if (!qp->pri.smac && !qp->pri.smac_port) {
1875 smac_index = mlx4_register_mac(dev->dev, qp->port, u64_mac);
1876 if (smac_index >= 0) {
1877 qp->pri.candidate_smac_index = smac_index;
1878 qp->pri.candidate_smac = u64_mac;
1879 qp->pri.candidate_smac_port = qp->port;
1880 context->pri_path.grh_mylmc = 0x80 | (u8) smac_index;
1881 } else {
1882 return -ENOENT;
1883 }
1884 }
1885 return 0;
1886 }
1887
create_qp_lb_counter(struct mlx4_ib_dev * dev,struct mlx4_ib_qp * qp)1888 static int create_qp_lb_counter(struct mlx4_ib_dev *dev, struct mlx4_ib_qp *qp)
1889 {
1890 struct counter_index *new_counter_index;
1891 int err;
1892 u32 tmp_idx;
1893
1894 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) !=
1895 IB_LINK_LAYER_ETHERNET ||
1896 !(qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK) ||
1897 !(dev->dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_LB_SRC_CHK))
1898 return 0;
1899
1900 err = mlx4_counter_alloc(dev->dev, &tmp_idx, MLX4_RES_USAGE_DRIVER);
1901 if (err)
1902 return err;
1903
1904 new_counter_index = kmalloc(sizeof(*new_counter_index), GFP_KERNEL);
1905 if (!new_counter_index) {
1906 mlx4_counter_free(dev->dev, tmp_idx);
1907 return -ENOMEM;
1908 }
1909
1910 new_counter_index->index = tmp_idx;
1911 new_counter_index->allocated = 1;
1912 qp->counter_index = new_counter_index;
1913
1914 mutex_lock(&dev->counters_table[qp->port - 1].mutex);
1915 list_add_tail(&new_counter_index->list,
1916 &dev->counters_table[qp->port - 1].counters_list);
1917 mutex_unlock(&dev->counters_table[qp->port - 1].mutex);
1918
1919 return 0;
1920 }
1921
1922 enum {
1923 MLX4_QPC_ROCE_MODE_1 = 0,
1924 MLX4_QPC_ROCE_MODE_2 = 2,
1925 MLX4_QPC_ROCE_MODE_UNDEFINED = 0xff
1926 };
1927
gid_type_to_qpc(enum ib_gid_type gid_type)1928 static u8 gid_type_to_qpc(enum ib_gid_type gid_type)
1929 {
1930 switch (gid_type) {
1931 case IB_GID_TYPE_ROCE:
1932 return MLX4_QPC_ROCE_MODE_1;
1933 case IB_GID_TYPE_ROCE_UDP_ENCAP:
1934 return MLX4_QPC_ROCE_MODE_2;
1935 default:
1936 return MLX4_QPC_ROCE_MODE_UNDEFINED;
1937 }
1938 }
1939
1940 /*
1941 * Go over all RSS QP's childes (WQs) and apply their HW state according to
1942 * their logic state if the RSS QP is the first RSS QP associated for the WQ.
1943 */
bringup_rss_rwqs(struct ib_rwq_ind_table * ind_tbl,u8 port_num)1944 static int bringup_rss_rwqs(struct ib_rwq_ind_table *ind_tbl, u8 port_num)
1945 {
1946 int err = 0;
1947 int i;
1948
1949 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
1950 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
1951 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1952
1953 mutex_lock(&wq->mutex);
1954
1955 /* Mlx4_ib restrictions:
1956 * WQ's is associated to a port according to the RSS QP it is
1957 * associates to.
1958 * In case the WQ is associated to a different port by another
1959 * RSS QP, return a failure.
1960 */
1961 if ((wq->rss_usecnt > 0) && (wq->port != port_num)) {
1962 err = -EINVAL;
1963 mutex_unlock(&wq->mutex);
1964 break;
1965 }
1966 wq->port = port_num;
1967 if ((wq->rss_usecnt == 0) && (ibwq->state == IB_WQS_RDY)) {
1968 err = _mlx4_ib_modify_wq(ibwq, IB_WQS_RDY);
1969 if (err) {
1970 mutex_unlock(&wq->mutex);
1971 break;
1972 }
1973 }
1974 wq->rss_usecnt++;
1975
1976 mutex_unlock(&wq->mutex);
1977 }
1978
1979 if (i && err) {
1980 int j;
1981
1982 for (j = (i - 1); j >= 0; j--) {
1983 struct ib_wq *ibwq = ind_tbl->ind_tbl[j];
1984 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
1985
1986 mutex_lock(&wq->mutex);
1987
1988 if ((wq->rss_usecnt == 1) &&
1989 (ibwq->state == IB_WQS_RDY))
1990 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
1991 pr_warn("failed to reverse WQN=0x%06x\n",
1992 ibwq->wq_num);
1993 wq->rss_usecnt--;
1994
1995 mutex_unlock(&wq->mutex);
1996 }
1997 }
1998
1999 return err;
2000 }
2001
bring_down_rss_rwqs(struct ib_rwq_ind_table * ind_tbl)2002 static void bring_down_rss_rwqs(struct ib_rwq_ind_table *ind_tbl)
2003 {
2004 int i;
2005
2006 for (i = 0; i < (1 << ind_tbl->log_ind_tbl_size); i++) {
2007 struct ib_wq *ibwq = ind_tbl->ind_tbl[i];
2008 struct mlx4_ib_qp *wq = to_mqp((struct ib_qp *)ibwq);
2009
2010 mutex_lock(&wq->mutex);
2011
2012 if ((wq->rss_usecnt == 1) && (ibwq->state == IB_WQS_RDY))
2013 if (_mlx4_ib_modify_wq(ibwq, IB_WQS_RESET))
2014 pr_warn("failed to reverse WQN=%x\n",
2015 ibwq->wq_num);
2016 wq->rss_usecnt--;
2017
2018 mutex_unlock(&wq->mutex);
2019 }
2020 }
2021
fill_qp_rss_context(struct mlx4_qp_context * context,struct mlx4_ib_qp * qp)2022 static void fill_qp_rss_context(struct mlx4_qp_context *context,
2023 struct mlx4_ib_qp *qp)
2024 {
2025 struct mlx4_rss_context *rss_context;
2026
2027 rss_context = (void *)context + offsetof(struct mlx4_qp_context,
2028 pri_path) + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
2029
2030 rss_context->base_qpn = cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz);
2031 rss_context->default_qpn =
2032 cpu_to_be32(qp->rss_ctx->base_qpn_tbl_sz & 0xffffff);
2033 if (qp->rss_ctx->flags & (MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6))
2034 rss_context->base_qpn_udp = rss_context->default_qpn;
2035 rss_context->flags = qp->rss_ctx->flags;
2036 /* Currently support just toeplitz */
2037 rss_context->hash_fn = MLX4_RSS_HASH_TOP;
2038
2039 memcpy(rss_context->rss_key, qp->rss_ctx->rss_key,
2040 MLX4_EN_RSS_KEY_SIZE);
2041 }
2042
__mlx4_ib_modify_qp(void * src,enum mlx4_ib_source_type src_type,const struct ib_qp_attr * attr,int attr_mask,enum ib_qp_state cur_state,enum ib_qp_state new_state)2043 static int __mlx4_ib_modify_qp(void *src, enum mlx4_ib_source_type src_type,
2044 const struct ib_qp_attr *attr, int attr_mask,
2045 enum ib_qp_state cur_state, enum ib_qp_state new_state)
2046 {
2047 struct ib_uobject *ibuobject;
2048 struct ib_srq *ibsrq;
2049 const struct ib_gid_attr *gid_attr = NULL;
2050 struct ib_rwq_ind_table *rwq_ind_tbl;
2051 enum ib_qp_type qp_type;
2052 struct mlx4_ib_dev *dev;
2053 struct mlx4_ib_qp *qp;
2054 struct mlx4_ib_pd *pd;
2055 struct mlx4_ib_cq *send_cq, *recv_cq;
2056 struct mlx4_qp_context *context;
2057 enum mlx4_qp_optpar optpar = 0;
2058 int sqd_event;
2059 int steer_qp = 0;
2060 int err = -EINVAL;
2061 int counter_index;
2062
2063 if (src_type == MLX4_IB_RWQ_SRC) {
2064 struct ib_wq *ibwq;
2065
2066 ibwq = (struct ib_wq *)src;
2067 ibuobject = ibwq->uobject;
2068 ibsrq = NULL;
2069 rwq_ind_tbl = NULL;
2070 qp_type = IB_QPT_RAW_PACKET;
2071 qp = to_mqp((struct ib_qp *)ibwq);
2072 dev = to_mdev(ibwq->device);
2073 pd = to_mpd(ibwq->pd);
2074 } else {
2075 struct ib_qp *ibqp;
2076
2077 ibqp = (struct ib_qp *)src;
2078 ibuobject = ibqp->uobject;
2079 ibsrq = ibqp->srq;
2080 rwq_ind_tbl = ibqp->rwq_ind_tbl;
2081 qp_type = ibqp->qp_type;
2082 qp = to_mqp(ibqp);
2083 dev = to_mdev(ibqp->device);
2084 pd = get_pd(qp);
2085 }
2086
2087 /* APM is not supported under RoCE */
2088 if (attr_mask & IB_QP_ALT_PATH &&
2089 rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2090 IB_LINK_LAYER_ETHERNET)
2091 return -ENOTSUPP;
2092
2093 context = kzalloc(sizeof *context, GFP_KERNEL);
2094 if (!context)
2095 return -ENOMEM;
2096
2097 context->flags = cpu_to_be32((to_mlx4_state(new_state) << 28) |
2098 (to_mlx4_st(dev, qp->mlx4_ib_qp_type) << 16));
2099
2100 if (!(attr_mask & IB_QP_PATH_MIG_STATE))
2101 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2102 else {
2103 optpar |= MLX4_QP_OPTPAR_PM_STATE;
2104 switch (attr->path_mig_state) {
2105 case IB_MIG_MIGRATED:
2106 context->flags |= cpu_to_be32(MLX4_QP_PM_MIGRATED << 11);
2107 break;
2108 case IB_MIG_REARM:
2109 context->flags |= cpu_to_be32(MLX4_QP_PM_REARM << 11);
2110 break;
2111 case IB_MIG_ARMED:
2112 context->flags |= cpu_to_be32(MLX4_QP_PM_ARMED << 11);
2113 break;
2114 }
2115 }
2116
2117 if (qp->inl_recv_sz)
2118 context->param3 |= cpu_to_be32(1 << 25);
2119
2120 if (qp->flags & MLX4_IB_QP_SCATTER_FCS)
2121 context->param3 |= cpu_to_be32(1 << 29);
2122
2123 if (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI)
2124 context->mtu_msgmax = (IB_MTU_4096 << 5) | 11;
2125 else if (qp_type == IB_QPT_RAW_PACKET)
2126 context->mtu_msgmax = (MLX4_RAW_QP_MTU << 5) | MLX4_RAW_QP_MSGMAX;
2127 else if (qp_type == IB_QPT_UD) {
2128 if (qp->flags & MLX4_IB_QP_LSO)
2129 context->mtu_msgmax = (IB_MTU_4096 << 5) |
2130 ilog2(dev->dev->caps.max_gso_sz);
2131 else
2132 context->mtu_msgmax = (IB_MTU_4096 << 5) | 13;
2133 } else if (attr_mask & IB_QP_PATH_MTU) {
2134 if (attr->path_mtu < IB_MTU_256 || attr->path_mtu > IB_MTU_4096) {
2135 pr_err("path MTU (%u) is invalid\n",
2136 attr->path_mtu);
2137 goto out;
2138 }
2139 context->mtu_msgmax = (attr->path_mtu << 5) |
2140 ilog2(dev->dev->caps.max_msg_sz);
2141 }
2142
2143 if (!rwq_ind_tbl) { /* PRM RSS receive side should be left zeros */
2144 if (qp->rq.wqe_cnt)
2145 context->rq_size_stride = ilog2(qp->rq.wqe_cnt) << 3;
2146 context->rq_size_stride |= qp->rq.wqe_shift - 4;
2147 }
2148
2149 if (qp->sq.wqe_cnt)
2150 context->sq_size_stride = ilog2(qp->sq.wqe_cnt) << 3;
2151 context->sq_size_stride |= qp->sq.wqe_shift - 4;
2152
2153 if (new_state == IB_QPS_RESET && qp->counter_index)
2154 mlx4_ib_free_qp_counter(dev, qp);
2155
2156 if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
2157 context->sq_size_stride |= !!qp->sq_no_prefetch << 7;
2158 context->xrcd = cpu_to_be32((u32) qp->xrcdn);
2159 if (qp_type == IB_QPT_RAW_PACKET)
2160 context->param3 |= cpu_to_be32(1 << 30);
2161 }
2162
2163 if (ibuobject)
2164 context->usr_page = cpu_to_be32(
2165 mlx4_to_hw_uar_index(dev->dev,
2166 to_mucontext(ibuobject->context)
2167 ->uar.index));
2168 else
2169 context->usr_page = cpu_to_be32(
2170 mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index));
2171
2172 if (attr_mask & IB_QP_DEST_QPN)
2173 context->remote_qpn = cpu_to_be32(attr->dest_qp_num);
2174
2175 if (attr_mask & IB_QP_PORT) {
2176 if (cur_state == IB_QPS_SQD && new_state == IB_QPS_SQD &&
2177 !(attr_mask & IB_QP_AV)) {
2178 mlx4_set_sched(&context->pri_path, attr->port_num);
2179 optpar |= MLX4_QP_OPTPAR_SCHED_QUEUE;
2180 }
2181 }
2182
2183 if (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR) {
2184 err = create_qp_lb_counter(dev, qp);
2185 if (err)
2186 goto out;
2187
2188 counter_index =
2189 dev->counters_table[qp->port - 1].default_counter;
2190 if (qp->counter_index)
2191 counter_index = qp->counter_index->index;
2192
2193 if (counter_index != -1) {
2194 context->pri_path.counter_index = counter_index;
2195 optpar |= MLX4_QP_OPTPAR_COUNTER_INDEX;
2196 if (qp->counter_index) {
2197 context->pri_path.fl |=
2198 MLX4_FL_ETH_SRC_CHECK_MC_LB;
2199 context->pri_path.vlan_control |=
2200 MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER;
2201 }
2202 } else
2203 context->pri_path.counter_index =
2204 MLX4_SINK_COUNTER_INDEX(dev->dev);
2205
2206 if (qp->flags & MLX4_IB_QP_NETIF) {
2207 mlx4_ib_steer_qp_reg(dev, qp, 1);
2208 steer_qp = 1;
2209 }
2210
2211 if (qp_type == IB_QPT_GSI) {
2212 enum ib_gid_type gid_type = qp->flags & MLX4_IB_ROCE_V2_GSI_QP ?
2213 IB_GID_TYPE_ROCE_UDP_ENCAP : IB_GID_TYPE_ROCE;
2214 u8 qpc_roce_mode = gid_type_to_qpc(gid_type);
2215
2216 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2217 }
2218 }
2219
2220 if (attr_mask & IB_QP_PKEY_INDEX) {
2221 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2222 context->pri_path.disable_pkey_check = 0x40;
2223 context->pri_path.pkey_index = attr->pkey_index;
2224 optpar |= MLX4_QP_OPTPAR_PKEY_INDEX;
2225 }
2226
2227 if (attr_mask & IB_QP_AV) {
2228 u8 port_num = mlx4_is_bonded(dev->dev) ? 1 :
2229 attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2230 u16 vlan = 0xffff;
2231 u8 smac[ETH_ALEN];
2232 int is_eth =
2233 rdma_cap_eth_ah(&dev->ib_dev, port_num) &&
2234 rdma_ah_get_ah_flags(&attr->ah_attr) & IB_AH_GRH;
2235
2236 if (is_eth) {
2237 gid_attr = attr->ah_attr.grh.sgid_attr;
2238 vlan = rdma_vlan_dev_vlan_id(gid_attr->ndev);
2239 memcpy(smac, gid_attr->ndev->dev_addr, ETH_ALEN);
2240 }
2241
2242 if (mlx4_set_path(dev, attr, attr_mask, qp, &context->pri_path,
2243 port_num, vlan, smac))
2244 goto out;
2245
2246 optpar |= (MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH |
2247 MLX4_QP_OPTPAR_SCHED_QUEUE);
2248
2249 if (is_eth &&
2250 (cur_state == IB_QPS_INIT && new_state == IB_QPS_RTR)) {
2251 u8 qpc_roce_mode = gid_type_to_qpc(gid_attr->gid_type);
2252
2253 if (qpc_roce_mode == MLX4_QPC_ROCE_MODE_UNDEFINED) {
2254 err = -EINVAL;
2255 goto out;
2256 }
2257 context->rlkey_roce_mode |= (qpc_roce_mode << 6);
2258 }
2259
2260 }
2261
2262 if (attr_mask & IB_QP_TIMEOUT) {
2263 context->pri_path.ackto |= attr->timeout << 3;
2264 optpar |= MLX4_QP_OPTPAR_ACK_TIMEOUT;
2265 }
2266
2267 if (attr_mask & IB_QP_ALT_PATH) {
2268 if (attr->alt_port_num == 0 ||
2269 attr->alt_port_num > dev->dev->caps.num_ports)
2270 goto out;
2271
2272 if (attr->alt_pkey_index >=
2273 dev->dev->caps.pkey_table_len[attr->alt_port_num])
2274 goto out;
2275
2276 if (mlx4_set_alt_path(dev, attr, attr_mask, qp,
2277 &context->alt_path,
2278 attr->alt_port_num))
2279 goto out;
2280
2281 context->alt_path.pkey_index = attr->alt_pkey_index;
2282 context->alt_path.ackto = attr->alt_timeout << 3;
2283 optpar |= MLX4_QP_OPTPAR_ALT_ADDR_PATH;
2284 }
2285
2286 context->pd = cpu_to_be32(pd->pdn);
2287
2288 if (!rwq_ind_tbl) {
2289 context->params1 = cpu_to_be32(MLX4_IB_ACK_REQ_FREQ << 28);
2290 get_cqs(qp, src_type, &send_cq, &recv_cq);
2291 } else { /* Set dummy CQs to be compatible with HV and PRM */
2292 send_cq = to_mcq(rwq_ind_tbl->ind_tbl[0]->cq);
2293 recv_cq = send_cq;
2294 }
2295 context->cqn_send = cpu_to_be32(send_cq->mcq.cqn);
2296 context->cqn_recv = cpu_to_be32(recv_cq->mcq.cqn);
2297
2298 /* Set "fast registration enabled" for all kernel QPs */
2299 if (!ibuobject)
2300 context->params1 |= cpu_to_be32(1 << 11);
2301
2302 if (attr_mask & IB_QP_RNR_RETRY) {
2303 context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
2304 optpar |= MLX4_QP_OPTPAR_RNR_RETRY;
2305 }
2306
2307 if (attr_mask & IB_QP_RETRY_CNT) {
2308 context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
2309 optpar |= MLX4_QP_OPTPAR_RETRY_COUNT;
2310 }
2311
2312 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2313 if (attr->max_rd_atomic)
2314 context->params1 |=
2315 cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
2316 optpar |= MLX4_QP_OPTPAR_SRA_MAX;
2317 }
2318
2319 if (attr_mask & IB_QP_SQ_PSN)
2320 context->next_send_psn = cpu_to_be32(attr->sq_psn);
2321
2322 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2323 if (attr->max_dest_rd_atomic)
2324 context->params2 |=
2325 cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
2326 optpar |= MLX4_QP_OPTPAR_RRA_MAX;
2327 }
2328
2329 if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
2330 context->params2 |= to_mlx4_access_flags(qp, attr, attr_mask);
2331 optpar |= MLX4_QP_OPTPAR_RWE | MLX4_QP_OPTPAR_RRE | MLX4_QP_OPTPAR_RAE;
2332 }
2333
2334 if (ibsrq)
2335 context->params2 |= cpu_to_be32(MLX4_QP_BIT_RIC);
2336
2337 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2338 context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
2339 optpar |= MLX4_QP_OPTPAR_RNR_TIMEOUT;
2340 }
2341 if (attr_mask & IB_QP_RQ_PSN)
2342 context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
2343
2344 /* proxy and tunnel qp qkeys will be changed in modify-qp wrappers */
2345 if (attr_mask & IB_QP_QKEY) {
2346 if (qp->mlx4_ib_qp_type &
2347 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))
2348 context->qkey = cpu_to_be32(IB_QP_SET_QKEY);
2349 else {
2350 if (mlx4_is_mfunc(dev->dev) &&
2351 !(qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV) &&
2352 (attr->qkey & MLX4_RESERVED_QKEY_MASK) ==
2353 MLX4_RESERVED_QKEY_BASE) {
2354 pr_err("Cannot use reserved QKEY"
2355 " 0x%x (range 0xffff0000..0xffffffff"
2356 " is reserved)\n", attr->qkey);
2357 err = -EINVAL;
2358 goto out;
2359 }
2360 context->qkey = cpu_to_be32(attr->qkey);
2361 }
2362 optpar |= MLX4_QP_OPTPAR_Q_KEY;
2363 }
2364
2365 if (ibsrq)
2366 context->srqn = cpu_to_be32(1 << 24 |
2367 to_msrq(ibsrq)->msrq.srqn);
2368
2369 if (qp->rq.wqe_cnt &&
2370 cur_state == IB_QPS_RESET &&
2371 new_state == IB_QPS_INIT)
2372 context->db_rec_addr = cpu_to_be64(qp->db.dma);
2373
2374 if (cur_state == IB_QPS_INIT &&
2375 new_state == IB_QPS_RTR &&
2376 (qp_type == IB_QPT_GSI || qp_type == IB_QPT_SMI ||
2377 qp_type == IB_QPT_UD || qp_type == IB_QPT_RAW_PACKET)) {
2378 context->pri_path.sched_queue = (qp->port - 1) << 6;
2379 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
2380 qp->mlx4_ib_qp_type &
2381 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER)) {
2382 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_QP0_SCHED_QUEUE;
2383 if (qp->mlx4_ib_qp_type != MLX4_IB_QPT_SMI)
2384 context->pri_path.fl = 0x80;
2385 } else {
2386 if (qp->mlx4_ib_qp_type & MLX4_IB_QPT_ANY_SRIOV)
2387 context->pri_path.fl = 0x80;
2388 context->pri_path.sched_queue |= MLX4_IB_DEFAULT_SCHED_QUEUE;
2389 }
2390 if (rdma_port_get_link_layer(&dev->ib_dev, qp->port) ==
2391 IB_LINK_LAYER_ETHERNET) {
2392 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI ||
2393 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI)
2394 context->pri_path.feup = 1 << 7; /* don't fsm */
2395 /* handle smac_index */
2396 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_UD ||
2397 qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI ||
2398 qp->mlx4_ib_qp_type == MLX4_IB_QPT_TUN_GSI) {
2399 err = handle_eth_ud_smac_index(dev, qp, context);
2400 if (err) {
2401 err = -EINVAL;
2402 goto out;
2403 }
2404 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_GSI)
2405 dev->qp1_proxy[qp->port - 1] = qp;
2406 }
2407 }
2408 }
2409
2410 if (qp_type == IB_QPT_RAW_PACKET) {
2411 context->pri_path.ackto = (context->pri_path.ackto & 0xf8) |
2412 MLX4_IB_LINK_TYPE_ETH;
2413 if (dev->dev->caps.tunnel_offload_mode == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) {
2414 /* set QP to receive both tunneled & non-tunneled packets */
2415 if (!rwq_ind_tbl)
2416 context->srqn = cpu_to_be32(7 << 28);
2417 }
2418 }
2419
2420 if (qp_type == IB_QPT_UD && (new_state == IB_QPS_RTR)) {
2421 int is_eth = rdma_port_get_link_layer(
2422 &dev->ib_dev, qp->port) ==
2423 IB_LINK_LAYER_ETHERNET;
2424 if (is_eth) {
2425 context->pri_path.ackto = MLX4_IB_LINK_TYPE_ETH;
2426 optpar |= MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH;
2427 }
2428 }
2429
2430 if (cur_state == IB_QPS_RTS && new_state == IB_QPS_SQD &&
2431 attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY && attr->en_sqd_async_notify)
2432 sqd_event = 1;
2433 else
2434 sqd_event = 0;
2435
2436 if (!ibuobject &&
2437 cur_state == IB_QPS_RESET &&
2438 new_state == IB_QPS_INIT)
2439 context->rlkey_roce_mode |= (1 << 4);
2440
2441 /*
2442 * Before passing a kernel QP to the HW, make sure that the
2443 * ownership bits of the send queue are set and the SQ
2444 * headroom is stamped so that the hardware doesn't start
2445 * processing stale work requests.
2446 */
2447 if (!ibuobject &&
2448 cur_state == IB_QPS_RESET &&
2449 new_state == IB_QPS_INIT) {
2450 struct mlx4_wqe_ctrl_seg *ctrl;
2451 int i;
2452
2453 for (i = 0; i < qp->sq.wqe_cnt; ++i) {
2454 ctrl = get_send_wqe(qp, i);
2455 ctrl->owner_opcode = cpu_to_be32(1 << 31);
2456 ctrl->qpn_vlan.fence_size =
2457 1 << (qp->sq.wqe_shift - 4);
2458 stamp_send_wqe(qp, i);
2459 }
2460 }
2461
2462 if (rwq_ind_tbl &&
2463 cur_state == IB_QPS_RESET &&
2464 new_state == IB_QPS_INIT) {
2465 fill_qp_rss_context(context, qp);
2466 context->flags |= cpu_to_be32(1 << MLX4_RSS_QPC_FLAG_OFFSET);
2467 }
2468
2469 err = mlx4_qp_modify(dev->dev, &qp->mtt, to_mlx4_state(cur_state),
2470 to_mlx4_state(new_state), context, optpar,
2471 sqd_event, &qp->mqp);
2472 if (err)
2473 goto out;
2474
2475 qp->state = new_state;
2476
2477 if (attr_mask & IB_QP_ACCESS_FLAGS)
2478 qp->atomic_rd_en = attr->qp_access_flags;
2479 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
2480 qp->resp_depth = attr->max_dest_rd_atomic;
2481 if (attr_mask & IB_QP_PORT) {
2482 qp->port = attr->port_num;
2483 update_mcg_macs(dev, qp);
2484 }
2485 if (attr_mask & IB_QP_ALT_PATH)
2486 qp->alt_port = attr->alt_port_num;
2487
2488 if (is_sqp(dev, qp))
2489 store_sqp_attrs(to_msqp(qp), attr, attr_mask);
2490
2491 /*
2492 * If we moved QP0 to RTR, bring the IB link up; if we moved
2493 * QP0 to RESET or ERROR, bring the link back down.
2494 */
2495 if (is_qp0(dev, qp)) {
2496 if (cur_state != IB_QPS_RTR && new_state == IB_QPS_RTR)
2497 if (mlx4_INIT_PORT(dev->dev, qp->port))
2498 pr_warn("INIT_PORT failed for port %d\n",
2499 qp->port);
2500
2501 if (cur_state != IB_QPS_RESET && cur_state != IB_QPS_ERR &&
2502 (new_state == IB_QPS_RESET || new_state == IB_QPS_ERR))
2503 mlx4_CLOSE_PORT(dev->dev, qp->port);
2504 }
2505
2506 /*
2507 * If we moved a kernel QP to RESET, clean up all old CQ
2508 * entries and reinitialize the QP.
2509 */
2510 if (new_state == IB_QPS_RESET) {
2511 if (!ibuobject) {
2512 mlx4_ib_cq_clean(recv_cq, qp->mqp.qpn,
2513 ibsrq ? to_msrq(ibsrq) : NULL);
2514 if (send_cq != recv_cq)
2515 mlx4_ib_cq_clean(send_cq, qp->mqp.qpn, NULL);
2516
2517 qp->rq.head = 0;
2518 qp->rq.tail = 0;
2519 qp->sq.head = 0;
2520 qp->sq.tail = 0;
2521 qp->sq_next_wqe = 0;
2522 if (qp->rq.wqe_cnt)
2523 *qp->db.db = 0;
2524
2525 if (qp->flags & MLX4_IB_QP_NETIF)
2526 mlx4_ib_steer_qp_reg(dev, qp, 0);
2527 }
2528 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port)) {
2529 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2530 qp->pri.smac = 0;
2531 qp->pri.smac_port = 0;
2532 }
2533 if (qp->alt.smac) {
2534 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2535 qp->alt.smac = 0;
2536 }
2537 if (qp->pri.vid < 0x1000) {
2538 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port, qp->pri.vid);
2539 qp->pri.vid = 0xFFFF;
2540 qp->pri.candidate_vid = 0xFFFF;
2541 qp->pri.update_vid = 0;
2542 }
2543
2544 if (qp->alt.vid < 0x1000) {
2545 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port, qp->alt.vid);
2546 qp->alt.vid = 0xFFFF;
2547 qp->alt.candidate_vid = 0xFFFF;
2548 qp->alt.update_vid = 0;
2549 }
2550 }
2551 out:
2552 if (err && qp->counter_index)
2553 mlx4_ib_free_qp_counter(dev, qp);
2554 if (err && steer_qp)
2555 mlx4_ib_steer_qp_reg(dev, qp, 0);
2556 kfree(context);
2557 if (qp->pri.candidate_smac ||
2558 (!qp->pri.candidate_smac && qp->pri.candidate_smac_port)) {
2559 if (err) {
2560 mlx4_unregister_mac(dev->dev, qp->pri.candidate_smac_port, qp->pri.candidate_smac);
2561 } else {
2562 if (qp->pri.smac || (!qp->pri.smac && qp->pri.smac_port))
2563 mlx4_unregister_mac(dev->dev, qp->pri.smac_port, qp->pri.smac);
2564 qp->pri.smac = qp->pri.candidate_smac;
2565 qp->pri.smac_index = qp->pri.candidate_smac_index;
2566 qp->pri.smac_port = qp->pri.candidate_smac_port;
2567 }
2568 qp->pri.candidate_smac = 0;
2569 qp->pri.candidate_smac_index = 0;
2570 qp->pri.candidate_smac_port = 0;
2571 }
2572 if (qp->alt.candidate_smac) {
2573 if (err) {
2574 mlx4_unregister_mac(dev->dev, qp->alt.candidate_smac_port, qp->alt.candidate_smac);
2575 } else {
2576 if (qp->alt.smac)
2577 mlx4_unregister_mac(dev->dev, qp->alt.smac_port, qp->alt.smac);
2578 qp->alt.smac = qp->alt.candidate_smac;
2579 qp->alt.smac_index = qp->alt.candidate_smac_index;
2580 qp->alt.smac_port = qp->alt.candidate_smac_port;
2581 }
2582 qp->alt.candidate_smac = 0;
2583 qp->alt.candidate_smac_index = 0;
2584 qp->alt.candidate_smac_port = 0;
2585 }
2586
2587 if (qp->pri.update_vid) {
2588 if (err) {
2589 if (qp->pri.candidate_vid < 0x1000)
2590 mlx4_unregister_vlan(dev->dev, qp->pri.candidate_vlan_port,
2591 qp->pri.candidate_vid);
2592 } else {
2593 if (qp->pri.vid < 0x1000)
2594 mlx4_unregister_vlan(dev->dev, qp->pri.vlan_port,
2595 qp->pri.vid);
2596 qp->pri.vid = qp->pri.candidate_vid;
2597 qp->pri.vlan_port = qp->pri.candidate_vlan_port;
2598 qp->pri.vlan_index = qp->pri.candidate_vlan_index;
2599 }
2600 qp->pri.candidate_vid = 0xFFFF;
2601 qp->pri.update_vid = 0;
2602 }
2603
2604 if (qp->alt.update_vid) {
2605 if (err) {
2606 if (qp->alt.candidate_vid < 0x1000)
2607 mlx4_unregister_vlan(dev->dev, qp->alt.candidate_vlan_port,
2608 qp->alt.candidate_vid);
2609 } else {
2610 if (qp->alt.vid < 0x1000)
2611 mlx4_unregister_vlan(dev->dev, qp->alt.vlan_port,
2612 qp->alt.vid);
2613 qp->alt.vid = qp->alt.candidate_vid;
2614 qp->alt.vlan_port = qp->alt.candidate_vlan_port;
2615 qp->alt.vlan_index = qp->alt.candidate_vlan_index;
2616 }
2617 qp->alt.candidate_vid = 0xFFFF;
2618 qp->alt.update_vid = 0;
2619 }
2620
2621 return err;
2622 }
2623
2624 enum {
2625 MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK = (IB_QP_STATE |
2626 IB_QP_PORT),
2627 };
2628
_mlx4_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2629 static int _mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2630 int attr_mask, struct ib_udata *udata)
2631 {
2632 enum rdma_link_layer ll = IB_LINK_LAYER_UNSPECIFIED;
2633 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
2634 struct mlx4_ib_qp *qp = to_mqp(ibqp);
2635 enum ib_qp_state cur_state, new_state;
2636 int err = -EINVAL;
2637 mutex_lock(&qp->mutex);
2638
2639 cur_state = attr_mask & IB_QP_CUR_STATE ? attr->cur_qp_state : qp->state;
2640 new_state = attr_mask & IB_QP_STATE ? attr->qp_state : cur_state;
2641
2642 if (cur_state != new_state || cur_state != IB_QPS_RESET) {
2643 int port = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2644 ll = rdma_port_get_link_layer(&dev->ib_dev, port);
2645 }
2646
2647 if (!ib_modify_qp_is_ok(cur_state, new_state, ibqp->qp_type,
2648 attr_mask, ll)) {
2649 pr_debug("qpn 0x%x: invalid attribute mask specified "
2650 "for transition %d to %d. qp_type %d,"
2651 " attr_mask 0x%x\n",
2652 ibqp->qp_num, cur_state, new_state,
2653 ibqp->qp_type, attr_mask);
2654 goto out;
2655 }
2656
2657 if (ibqp->rwq_ind_tbl) {
2658 if (!(((cur_state == IB_QPS_RESET) &&
2659 (new_state == IB_QPS_INIT)) ||
2660 ((cur_state == IB_QPS_INIT) &&
2661 (new_state == IB_QPS_RTR)))) {
2662 pr_debug("qpn 0x%x: RSS QP unsupported transition %d to %d\n",
2663 ibqp->qp_num, cur_state, new_state);
2664
2665 err = -EOPNOTSUPP;
2666 goto out;
2667 }
2668
2669 if (attr_mask & ~MLX4_IB_MODIFY_QP_RSS_SUP_ATTR_MSK) {
2670 pr_debug("qpn 0x%x: RSS QP unsupported attribute mask 0x%x for transition %d to %d\n",
2671 ibqp->qp_num, attr_mask, cur_state, new_state);
2672
2673 err = -EOPNOTSUPP;
2674 goto out;
2675 }
2676 }
2677
2678 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT)) {
2679 if ((cur_state == IB_QPS_RESET) && (new_state == IB_QPS_INIT)) {
2680 if ((ibqp->qp_type == IB_QPT_RC) ||
2681 (ibqp->qp_type == IB_QPT_UD) ||
2682 (ibqp->qp_type == IB_QPT_UC) ||
2683 (ibqp->qp_type == IB_QPT_RAW_PACKET) ||
2684 (ibqp->qp_type == IB_QPT_XRC_INI)) {
2685 attr->port_num = mlx4_ib_bond_next_port(dev);
2686 }
2687 } else {
2688 /* no sense in changing port_num
2689 * when ports are bonded */
2690 attr_mask &= ~IB_QP_PORT;
2691 }
2692 }
2693
2694 if ((attr_mask & IB_QP_PORT) &&
2695 (attr->port_num == 0 || attr->port_num > dev->num_ports)) {
2696 pr_debug("qpn 0x%x: invalid port number (%d) specified "
2697 "for transition %d to %d. qp_type %d\n",
2698 ibqp->qp_num, attr->port_num, cur_state,
2699 new_state, ibqp->qp_type);
2700 goto out;
2701 }
2702
2703 if ((attr_mask & IB_QP_PORT) && (ibqp->qp_type == IB_QPT_RAW_PACKET) &&
2704 (rdma_port_get_link_layer(&dev->ib_dev, attr->port_num) !=
2705 IB_LINK_LAYER_ETHERNET))
2706 goto out;
2707
2708 if (attr_mask & IB_QP_PKEY_INDEX) {
2709 int p = attr_mask & IB_QP_PORT ? attr->port_num : qp->port;
2710 if (attr->pkey_index >= dev->dev->caps.pkey_table_len[p]) {
2711 pr_debug("qpn 0x%x: invalid pkey index (%d) specified "
2712 "for transition %d to %d. qp_type %d\n",
2713 ibqp->qp_num, attr->pkey_index, cur_state,
2714 new_state, ibqp->qp_type);
2715 goto out;
2716 }
2717 }
2718
2719 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC &&
2720 attr->max_rd_atomic > dev->dev->caps.max_qp_init_rdma) {
2721 pr_debug("qpn 0x%x: max_rd_atomic (%d) too large. "
2722 "Transition %d to %d. qp_type %d\n",
2723 ibqp->qp_num, attr->max_rd_atomic, cur_state,
2724 new_state, ibqp->qp_type);
2725 goto out;
2726 }
2727
2728 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC &&
2729 attr->max_dest_rd_atomic > dev->dev->caps.max_qp_dest_rdma) {
2730 pr_debug("qpn 0x%x: max_dest_rd_atomic (%d) too large. "
2731 "Transition %d to %d. qp_type %d\n",
2732 ibqp->qp_num, attr->max_dest_rd_atomic, cur_state,
2733 new_state, ibqp->qp_type);
2734 goto out;
2735 }
2736
2737 if (cur_state == new_state && cur_state == IB_QPS_RESET) {
2738 err = 0;
2739 goto out;
2740 }
2741
2742 if (ibqp->rwq_ind_tbl && (new_state == IB_QPS_INIT)) {
2743 err = bringup_rss_rwqs(ibqp->rwq_ind_tbl, attr->port_num);
2744 if (err)
2745 goto out;
2746 }
2747
2748 err = __mlx4_ib_modify_qp(ibqp, MLX4_IB_QP_SRC, attr, attr_mask,
2749 cur_state, new_state);
2750
2751 if (ibqp->rwq_ind_tbl && err)
2752 bring_down_rss_rwqs(ibqp->rwq_ind_tbl);
2753
2754 if (mlx4_is_bonded(dev->dev) && (attr_mask & IB_QP_PORT))
2755 attr->port_num = 1;
2756
2757 out:
2758 mutex_unlock(&qp->mutex);
2759 return err;
2760 }
2761
mlx4_ib_modify_qp(struct ib_qp * ibqp,struct ib_qp_attr * attr,int attr_mask,struct ib_udata * udata)2762 int mlx4_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
2763 int attr_mask, struct ib_udata *udata)
2764 {
2765 struct mlx4_ib_qp *mqp = to_mqp(ibqp);
2766 int ret;
2767
2768 ret = _mlx4_ib_modify_qp(ibqp, attr, attr_mask, udata);
2769
2770 if (mqp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
2771 struct mlx4_ib_sqp *sqp = to_msqp(mqp);
2772 int err = 0;
2773
2774 if (sqp->roce_v2_gsi)
2775 err = ib_modify_qp(sqp->roce_v2_gsi, attr, attr_mask);
2776 if (err)
2777 pr_err("Failed to modify GSI QP for RoCEv2 (%d)\n",
2778 err);
2779 }
2780 return ret;
2781 }
2782
vf_get_qp0_qkey(struct mlx4_dev * dev,int qpn,u32 * qkey)2783 static int vf_get_qp0_qkey(struct mlx4_dev *dev, int qpn, u32 *qkey)
2784 {
2785 int i;
2786 for (i = 0; i < dev->caps.num_ports; i++) {
2787 if (qpn == dev->caps.spec_qps[i].qp0_proxy ||
2788 qpn == dev->caps.spec_qps[i].qp0_tunnel) {
2789 *qkey = dev->caps.spec_qps[i].qp0_qkey;
2790 return 0;
2791 }
2792 }
2793 return -EINVAL;
2794 }
2795
build_sriov_qp0_header(struct mlx4_ib_sqp * sqp,const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2796 static int build_sriov_qp0_header(struct mlx4_ib_sqp *sqp,
2797 const struct ib_ud_wr *wr,
2798 void *wqe, unsigned *mlx_seg_len)
2799 {
2800 struct mlx4_ib_dev *mdev = to_mdev(sqp->qp.ibqp.device);
2801 struct ib_device *ib_dev = &mdev->ib_dev;
2802 struct mlx4_wqe_mlx_seg *mlx = wqe;
2803 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2804 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2805 u16 pkey;
2806 u32 qkey;
2807 int send_size;
2808 int header_size;
2809 int spc;
2810 int err;
2811 int i;
2812
2813 if (wr->wr.opcode != IB_WR_SEND)
2814 return -EINVAL;
2815
2816 send_size = 0;
2817
2818 for (i = 0; i < wr->wr.num_sge; ++i)
2819 send_size += wr->wr.sg_list[i].length;
2820
2821 /* for proxy-qp0 sends, need to add in size of tunnel header */
2822 /* for tunnel-qp0 sends, tunnel header is already in s/g list */
2823 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER)
2824 send_size += sizeof (struct mlx4_ib_tunnel_header);
2825
2826 ib_ud_header_init(send_size, 1, 0, 0, 0, 0, 0, 0, &sqp->ud_header);
2827
2828 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_PROXY_SMI_OWNER) {
2829 sqp->ud_header.lrh.service_level =
2830 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
2831 sqp->ud_header.lrh.destination_lid =
2832 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2833 sqp->ud_header.lrh.source_lid =
2834 cpu_to_be16(ah->av.ib.g_slid & 0x7f);
2835 }
2836
2837 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
2838
2839 /* force loopback */
2840 mlx->flags |= cpu_to_be32(MLX4_WQE_MLX_VL15 | 0x1 | MLX4_WQE_MLX_SLR);
2841 mlx->rlid = sqp->ud_header.lrh.destination_lid;
2842
2843 sqp->ud_header.lrh.virtual_lane = 0;
2844 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
2845 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, 0, &pkey);
2846 if (err)
2847 return err;
2848 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
2849 if (sqp->qp.mlx4_ib_qp_type == MLX4_IB_QPT_TUN_SMI_OWNER)
2850 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
2851 else
2852 sqp->ud_header.bth.destination_qpn =
2853 cpu_to_be32(mdev->dev->caps.spec_qps[sqp->qp.port - 1].qp0_tunnel);
2854
2855 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
2856 if (mlx4_is_master(mdev->dev)) {
2857 if (mlx4_get_parav_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2858 return -EINVAL;
2859 } else {
2860 if (vf_get_qp0_qkey(mdev->dev, sqp->qp.mqp.qpn, &qkey))
2861 return -EINVAL;
2862 }
2863 sqp->ud_header.deth.qkey = cpu_to_be32(qkey);
2864 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.mqp.qpn);
2865
2866 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
2867 sqp->ud_header.immediate_present = 0;
2868
2869 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
2870
2871 /*
2872 * Inline data segments may not cross a 64 byte boundary. If
2873 * our UD header is bigger than the space available up to the
2874 * next 64 byte boundary in the WQE, use two inline data
2875 * segments to hold the UD header.
2876 */
2877 spc = MLX4_INLINE_ALIGN -
2878 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
2879 if (header_size <= spc) {
2880 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
2881 memcpy(inl + 1, sqp->header_buf, header_size);
2882 i = 1;
2883 } else {
2884 inl->byte_count = cpu_to_be32(1 << 31 | spc);
2885 memcpy(inl + 1, sqp->header_buf, spc);
2886
2887 inl = (void *) (inl + 1) + spc;
2888 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
2889 /*
2890 * Need a barrier here to make sure all the data is
2891 * visible before the byte_count field is set.
2892 * Otherwise the HCA prefetcher could grab the 64-byte
2893 * chunk with this inline segment and get a valid (!=
2894 * 0xffffffff) byte count but stale data, and end up
2895 * generating a packet with bad headers.
2896 *
2897 * The first inline segment's byte_count field doesn't
2898 * need a barrier, because it comes after a
2899 * control/MLX segment and therefore is at an offset
2900 * of 16 mod 64.
2901 */
2902 wmb();
2903 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
2904 i = 2;
2905 }
2906
2907 *mlx_seg_len =
2908 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
2909 return 0;
2910 }
2911
sl_to_vl(struct mlx4_ib_dev * dev,u8 sl,int port_num)2912 static u8 sl_to_vl(struct mlx4_ib_dev *dev, u8 sl, int port_num)
2913 {
2914 union sl2vl_tbl_to_u64 tmp_vltab;
2915 u8 vl;
2916
2917 if (sl > 15)
2918 return 0xf;
2919 tmp_vltab.sl64 = atomic64_read(&dev->sl2vl[port_num - 1]);
2920 vl = tmp_vltab.sl8[sl >> 1];
2921 if (sl & 1)
2922 vl &= 0x0f;
2923 else
2924 vl >>= 4;
2925 return vl;
2926 }
2927
fill_gid_by_hw_index(struct mlx4_ib_dev * ibdev,u8 port_num,int index,union ib_gid * gid,enum ib_gid_type * gid_type)2928 static int fill_gid_by_hw_index(struct mlx4_ib_dev *ibdev, u8 port_num,
2929 int index, union ib_gid *gid,
2930 enum ib_gid_type *gid_type)
2931 {
2932 struct mlx4_ib_iboe *iboe = &ibdev->iboe;
2933 struct mlx4_port_gid_table *port_gid_table;
2934 unsigned long flags;
2935
2936 port_gid_table = &iboe->gids[port_num - 1];
2937 spin_lock_irqsave(&iboe->lock, flags);
2938 memcpy(gid, &port_gid_table->gids[index].gid, sizeof(*gid));
2939 *gid_type = port_gid_table->gids[index].gid_type;
2940 spin_unlock_irqrestore(&iboe->lock, flags);
2941 if (rdma_is_zero_gid(gid))
2942 return -ENOENT;
2943
2944 return 0;
2945 }
2946
2947 #define MLX4_ROCEV2_QP1_SPORT 0xC000
build_mlx_header(struct mlx4_ib_sqp * sqp,const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)2948 static int build_mlx_header(struct mlx4_ib_sqp *sqp, const struct ib_ud_wr *wr,
2949 void *wqe, unsigned *mlx_seg_len)
2950 {
2951 struct ib_device *ib_dev = sqp->qp.ibqp.device;
2952 struct mlx4_ib_dev *ibdev = to_mdev(ib_dev);
2953 struct mlx4_wqe_mlx_seg *mlx = wqe;
2954 struct mlx4_wqe_ctrl_seg *ctrl = wqe;
2955 struct mlx4_wqe_inline_seg *inl = wqe + sizeof *mlx;
2956 struct mlx4_ib_ah *ah = to_mah(wr->ah);
2957 union ib_gid sgid;
2958 u16 pkey;
2959 int send_size;
2960 int header_size;
2961 int spc;
2962 int i;
2963 int err = 0;
2964 u16 vlan = 0xffff;
2965 bool is_eth;
2966 bool is_vlan = false;
2967 bool is_grh;
2968 bool is_udp = false;
2969 int ip_version = 0;
2970
2971 send_size = 0;
2972 for (i = 0; i < wr->wr.num_sge; ++i)
2973 send_size += wr->wr.sg_list[i].length;
2974
2975 is_eth = rdma_port_get_link_layer(sqp->qp.ibqp.device, sqp->qp.port) == IB_LINK_LAYER_ETHERNET;
2976 is_grh = mlx4_ib_ah_grh_present(ah);
2977 if (is_eth) {
2978 enum ib_gid_type gid_type;
2979 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
2980 /* When multi-function is enabled, the ib_core gid
2981 * indexes don't necessarily match the hw ones, so
2982 * we must use our own cache */
2983 err = mlx4_get_roce_gid_from_slave(to_mdev(ib_dev)->dev,
2984 be32_to_cpu(ah->av.ib.port_pd) >> 24,
2985 ah->av.ib.gid_index, &sgid.raw[0]);
2986 if (err)
2987 return err;
2988 } else {
2989 err = fill_gid_by_hw_index(ibdev, sqp->qp.port,
2990 ah->av.ib.gid_index,
2991 &sgid, &gid_type);
2992 if (!err) {
2993 is_udp = gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP;
2994 if (is_udp) {
2995 if (ipv6_addr_v4mapped((struct in6_addr *)&sgid))
2996 ip_version = 4;
2997 else
2998 ip_version = 6;
2999 is_grh = false;
3000 }
3001 } else {
3002 return err;
3003 }
3004 }
3005 if (ah->av.eth.vlan != cpu_to_be16(0xffff)) {
3006 vlan = be16_to_cpu(ah->av.eth.vlan) & 0x0fff;
3007 is_vlan = 1;
3008 }
3009 }
3010 err = ib_ud_header_init(send_size, !is_eth, is_eth, is_vlan, is_grh,
3011 ip_version, is_udp, 0, &sqp->ud_header);
3012 if (err)
3013 return err;
3014
3015 if (!is_eth) {
3016 sqp->ud_header.lrh.service_level =
3017 be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 28;
3018 sqp->ud_header.lrh.destination_lid = ah->av.ib.dlid;
3019 sqp->ud_header.lrh.source_lid = cpu_to_be16(ah->av.ib.g_slid & 0x7f);
3020 }
3021
3022 if (is_grh || (ip_version == 6)) {
3023 sqp->ud_header.grh.traffic_class =
3024 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3025 sqp->ud_header.grh.flow_label =
3026 ah->av.ib.sl_tclass_flowlabel & cpu_to_be32(0xfffff);
3027 sqp->ud_header.grh.hop_limit = ah->av.ib.hop_limit;
3028 if (is_eth) {
3029 memcpy(sqp->ud_header.grh.source_gid.raw, sgid.raw, 16);
3030 } else {
3031 if (mlx4_is_mfunc(to_mdev(ib_dev)->dev)) {
3032 /* When multi-function is enabled, the ib_core gid
3033 * indexes don't necessarily match the hw ones, so
3034 * we must use our own cache
3035 */
3036 sqp->ud_header.grh.source_gid.global.subnet_prefix =
3037 cpu_to_be64(atomic64_read(&(to_mdev(ib_dev)->sriov.
3038 demux[sqp->qp.port - 1].
3039 subnet_prefix)));
3040 sqp->ud_header.grh.source_gid.global.interface_id =
3041 to_mdev(ib_dev)->sriov.demux[sqp->qp.port - 1].
3042 guid_cache[ah->av.ib.gid_index];
3043 } else {
3044 sqp->ud_header.grh.source_gid =
3045 ah->ibah.sgid_attr->gid;
3046 }
3047 }
3048 memcpy(sqp->ud_header.grh.destination_gid.raw,
3049 ah->av.ib.dgid, 16);
3050 }
3051
3052 if (ip_version == 4) {
3053 sqp->ud_header.ip4.tos =
3054 (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 20) & 0xff;
3055 sqp->ud_header.ip4.id = 0;
3056 sqp->ud_header.ip4.frag_off = htons(IP_DF);
3057 sqp->ud_header.ip4.ttl = ah->av.eth.hop_limit;
3058
3059 memcpy(&sqp->ud_header.ip4.saddr,
3060 sgid.raw + 12, 4);
3061 memcpy(&sqp->ud_header.ip4.daddr, ah->av.ib.dgid + 12, 4);
3062 sqp->ud_header.ip4.check = ib_ud_ip4_csum(&sqp->ud_header);
3063 }
3064
3065 if (is_udp) {
3066 sqp->ud_header.udp.dport = htons(ROCE_V2_UDP_DPORT);
3067 sqp->ud_header.udp.sport = htons(MLX4_ROCEV2_QP1_SPORT);
3068 sqp->ud_header.udp.csum = 0;
3069 }
3070
3071 mlx->flags &= cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE);
3072
3073 if (!is_eth) {
3074 mlx->flags |= cpu_to_be32((!sqp->qp.ibqp.qp_num ? MLX4_WQE_MLX_VL15 : 0) |
3075 (sqp->ud_header.lrh.destination_lid ==
3076 IB_LID_PERMISSIVE ? MLX4_WQE_MLX_SLR : 0) |
3077 (sqp->ud_header.lrh.service_level << 8));
3078 if (ah->av.ib.port_pd & cpu_to_be32(0x80000000))
3079 mlx->flags |= cpu_to_be32(0x1); /* force loopback */
3080 mlx->rlid = sqp->ud_header.lrh.destination_lid;
3081 }
3082
3083 switch (wr->wr.opcode) {
3084 case IB_WR_SEND:
3085 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY;
3086 sqp->ud_header.immediate_present = 0;
3087 break;
3088 case IB_WR_SEND_WITH_IMM:
3089 sqp->ud_header.bth.opcode = IB_OPCODE_UD_SEND_ONLY_WITH_IMMEDIATE;
3090 sqp->ud_header.immediate_present = 1;
3091 sqp->ud_header.immediate_data = wr->wr.ex.imm_data;
3092 break;
3093 default:
3094 return -EINVAL;
3095 }
3096
3097 if (is_eth) {
3098 struct in6_addr in6;
3099 u16 ether_type;
3100 u16 pcp = (be32_to_cpu(ah->av.ib.sl_tclass_flowlabel) >> 29) << 13;
3101
3102 ether_type = (!is_udp) ? ETH_P_IBOE:
3103 (ip_version == 4 ? ETH_P_IP : ETH_P_IPV6);
3104
3105 mlx->sched_prio = cpu_to_be16(pcp);
3106
3107 ether_addr_copy(sqp->ud_header.eth.smac_h, ah->av.eth.s_mac);
3108 memcpy(sqp->ud_header.eth.dmac_h, ah->av.eth.mac, 6);
3109 memcpy(&ctrl->srcrb_flags16[0], ah->av.eth.mac, 2);
3110 memcpy(&ctrl->imm, ah->av.eth.mac + 2, 4);
3111 memcpy(&in6, sgid.raw, sizeof(in6));
3112
3113
3114 if (!memcmp(sqp->ud_header.eth.smac_h, sqp->ud_header.eth.dmac_h, 6))
3115 mlx->flags |= cpu_to_be32(MLX4_WQE_CTRL_FORCE_LOOPBACK);
3116 if (!is_vlan) {
3117 sqp->ud_header.eth.type = cpu_to_be16(ether_type);
3118 } else {
3119 sqp->ud_header.vlan.type = cpu_to_be16(ether_type);
3120 sqp->ud_header.vlan.tag = cpu_to_be16(vlan | pcp);
3121 }
3122 } else {
3123 sqp->ud_header.lrh.virtual_lane = !sqp->qp.ibqp.qp_num ? 15 :
3124 sl_to_vl(to_mdev(ib_dev),
3125 sqp->ud_header.lrh.service_level,
3126 sqp->qp.port);
3127 if (sqp->qp.ibqp.qp_num && sqp->ud_header.lrh.virtual_lane == 15)
3128 return -EINVAL;
3129 if (sqp->ud_header.lrh.destination_lid == IB_LID_PERMISSIVE)
3130 sqp->ud_header.lrh.source_lid = IB_LID_PERMISSIVE;
3131 }
3132 sqp->ud_header.bth.solicited_event = !!(wr->wr.send_flags & IB_SEND_SOLICITED);
3133 if (!sqp->qp.ibqp.qp_num)
3134 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, sqp->pkey_index,
3135 &pkey);
3136 else
3137 err = ib_get_cached_pkey(ib_dev, sqp->qp.port, wr->pkey_index,
3138 &pkey);
3139 if (err)
3140 return err;
3141
3142 sqp->ud_header.bth.pkey = cpu_to_be16(pkey);
3143 sqp->ud_header.bth.destination_qpn = cpu_to_be32(wr->remote_qpn);
3144 sqp->ud_header.bth.psn = cpu_to_be32((sqp->send_psn++) & ((1 << 24) - 1));
3145 sqp->ud_header.deth.qkey = cpu_to_be32(wr->remote_qkey & 0x80000000 ?
3146 sqp->qkey : wr->remote_qkey);
3147 sqp->ud_header.deth.source_qpn = cpu_to_be32(sqp->qp.ibqp.qp_num);
3148
3149 header_size = ib_ud_header_pack(&sqp->ud_header, sqp->header_buf);
3150
3151 if (0) {
3152 pr_err("built UD header of size %d:\n", header_size);
3153 for (i = 0; i < header_size / 4; ++i) {
3154 if (i % 8 == 0)
3155 pr_err(" [%02x] ", i * 4);
3156 pr_cont(" %08x",
3157 be32_to_cpu(((__be32 *) sqp->header_buf)[i]));
3158 if ((i + 1) % 8 == 0)
3159 pr_cont("\n");
3160 }
3161 pr_err("\n");
3162 }
3163
3164 /*
3165 * Inline data segments may not cross a 64 byte boundary. If
3166 * our UD header is bigger than the space available up to the
3167 * next 64 byte boundary in the WQE, use two inline data
3168 * segments to hold the UD header.
3169 */
3170 spc = MLX4_INLINE_ALIGN -
3171 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3172 if (header_size <= spc) {
3173 inl->byte_count = cpu_to_be32(1 << 31 | header_size);
3174 memcpy(inl + 1, sqp->header_buf, header_size);
3175 i = 1;
3176 } else {
3177 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3178 memcpy(inl + 1, sqp->header_buf, spc);
3179
3180 inl = (void *) (inl + 1) + spc;
3181 memcpy(inl + 1, sqp->header_buf + spc, header_size - spc);
3182 /*
3183 * Need a barrier here to make sure all the data is
3184 * visible before the byte_count field is set.
3185 * Otherwise the HCA prefetcher could grab the 64-byte
3186 * chunk with this inline segment and get a valid (!=
3187 * 0xffffffff) byte count but stale data, and end up
3188 * generating a packet with bad headers.
3189 *
3190 * The first inline segment's byte_count field doesn't
3191 * need a barrier, because it comes after a
3192 * control/MLX segment and therefore is at an offset
3193 * of 16 mod 64.
3194 */
3195 wmb();
3196 inl->byte_count = cpu_to_be32(1 << 31 | (header_size - spc));
3197 i = 2;
3198 }
3199
3200 *mlx_seg_len =
3201 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + header_size, 16);
3202 return 0;
3203 }
3204
mlx4_wq_overflow(struct mlx4_ib_wq * wq,int nreq,struct ib_cq * ib_cq)3205 static int mlx4_wq_overflow(struct mlx4_ib_wq *wq, int nreq, struct ib_cq *ib_cq)
3206 {
3207 unsigned cur;
3208 struct mlx4_ib_cq *cq;
3209
3210 cur = wq->head - wq->tail;
3211 if (likely(cur + nreq < wq->max_post))
3212 return 0;
3213
3214 cq = to_mcq(ib_cq);
3215 spin_lock(&cq->lock);
3216 cur = wq->head - wq->tail;
3217 spin_unlock(&cq->lock);
3218
3219 return cur + nreq >= wq->max_post;
3220 }
3221
convert_access(int acc)3222 static __be32 convert_access(int acc)
3223 {
3224 return (acc & IB_ACCESS_REMOTE_ATOMIC ?
3225 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC) : 0) |
3226 (acc & IB_ACCESS_REMOTE_WRITE ?
3227 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE) : 0) |
3228 (acc & IB_ACCESS_REMOTE_READ ?
3229 cpu_to_be32(MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ) : 0) |
3230 (acc & IB_ACCESS_LOCAL_WRITE ? cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_WRITE) : 0) |
3231 cpu_to_be32(MLX4_WQE_FMR_PERM_LOCAL_READ);
3232 }
3233
set_reg_seg(struct mlx4_wqe_fmr_seg * fseg,const struct ib_reg_wr * wr)3234 static void set_reg_seg(struct mlx4_wqe_fmr_seg *fseg,
3235 const struct ib_reg_wr *wr)
3236 {
3237 struct mlx4_ib_mr *mr = to_mmr(wr->mr);
3238
3239 fseg->flags = convert_access(wr->access);
3240 fseg->mem_key = cpu_to_be32(wr->key);
3241 fseg->buf_list = cpu_to_be64(mr->page_map);
3242 fseg->start_addr = cpu_to_be64(mr->ibmr.iova);
3243 fseg->reg_len = cpu_to_be64(mr->ibmr.length);
3244 fseg->offset = 0; /* XXX -- is this just for ZBVA? */
3245 fseg->page_size = cpu_to_be32(ilog2(mr->ibmr.page_size));
3246 fseg->reserved[0] = 0;
3247 fseg->reserved[1] = 0;
3248 }
3249
set_local_inv_seg(struct mlx4_wqe_local_inval_seg * iseg,u32 rkey)3250 static void set_local_inv_seg(struct mlx4_wqe_local_inval_seg *iseg, u32 rkey)
3251 {
3252 memset(iseg, 0, sizeof(*iseg));
3253 iseg->mem_key = cpu_to_be32(rkey);
3254 }
3255
set_raddr_seg(struct mlx4_wqe_raddr_seg * rseg,u64 remote_addr,u32 rkey)3256 static __always_inline void set_raddr_seg(struct mlx4_wqe_raddr_seg *rseg,
3257 u64 remote_addr, u32 rkey)
3258 {
3259 rseg->raddr = cpu_to_be64(remote_addr);
3260 rseg->rkey = cpu_to_be32(rkey);
3261 rseg->reserved = 0;
3262 }
3263
set_atomic_seg(struct mlx4_wqe_atomic_seg * aseg,const struct ib_atomic_wr * wr)3264 static void set_atomic_seg(struct mlx4_wqe_atomic_seg *aseg,
3265 const struct ib_atomic_wr *wr)
3266 {
3267 if (wr->wr.opcode == IB_WR_ATOMIC_CMP_AND_SWP) {
3268 aseg->swap_add = cpu_to_be64(wr->swap);
3269 aseg->compare = cpu_to_be64(wr->compare_add);
3270 } else if (wr->wr.opcode == IB_WR_MASKED_ATOMIC_FETCH_AND_ADD) {
3271 aseg->swap_add = cpu_to_be64(wr->compare_add);
3272 aseg->compare = cpu_to_be64(wr->compare_add_mask);
3273 } else {
3274 aseg->swap_add = cpu_to_be64(wr->compare_add);
3275 aseg->compare = 0;
3276 }
3277
3278 }
3279
set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg * aseg,const struct ib_atomic_wr * wr)3280 static void set_masked_atomic_seg(struct mlx4_wqe_masked_atomic_seg *aseg,
3281 const struct ib_atomic_wr *wr)
3282 {
3283 aseg->swap_add = cpu_to_be64(wr->swap);
3284 aseg->swap_add_mask = cpu_to_be64(wr->swap_mask);
3285 aseg->compare = cpu_to_be64(wr->compare_add);
3286 aseg->compare_mask = cpu_to_be64(wr->compare_add_mask);
3287 }
3288
set_datagram_seg(struct mlx4_wqe_datagram_seg * dseg,const struct ib_ud_wr * wr)3289 static void set_datagram_seg(struct mlx4_wqe_datagram_seg *dseg,
3290 const struct ib_ud_wr *wr)
3291 {
3292 memcpy(dseg->av, &to_mah(wr->ah)->av, sizeof (struct mlx4_av));
3293 dseg->dqpn = cpu_to_be32(wr->remote_qpn);
3294 dseg->qkey = cpu_to_be32(wr->remote_qkey);
3295 dseg->vlan = to_mah(wr->ah)->av.eth.vlan;
3296 memcpy(dseg->mac, to_mah(wr->ah)->av.eth.mac, 6);
3297 }
3298
set_tunnel_datagram_seg(struct mlx4_ib_dev * dev,struct mlx4_wqe_datagram_seg * dseg,const struct ib_ud_wr * wr,enum mlx4_ib_qp_type qpt)3299 static void set_tunnel_datagram_seg(struct mlx4_ib_dev *dev,
3300 struct mlx4_wqe_datagram_seg *dseg,
3301 const struct ib_ud_wr *wr,
3302 enum mlx4_ib_qp_type qpt)
3303 {
3304 union mlx4_ext_av *av = &to_mah(wr->ah)->av;
3305 struct mlx4_av sqp_av = {0};
3306 int port = *((u8 *) &av->ib.port_pd) & 0x3;
3307
3308 /* force loopback */
3309 sqp_av.port_pd = av->ib.port_pd | cpu_to_be32(0x80000000);
3310 sqp_av.g_slid = av->ib.g_slid & 0x7f; /* no GRH */
3311 sqp_av.sl_tclass_flowlabel = av->ib.sl_tclass_flowlabel &
3312 cpu_to_be32(0xf0000000);
3313
3314 memcpy(dseg->av, &sqp_av, sizeof (struct mlx4_av));
3315 if (qpt == MLX4_IB_QPT_PROXY_GSI)
3316 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp1_tunnel);
3317 else
3318 dseg->dqpn = cpu_to_be32(dev->dev->caps.spec_qps[port - 1].qp0_tunnel);
3319 /* Use QKEY from the QP context, which is set by master */
3320 dseg->qkey = cpu_to_be32(IB_QP_SET_QKEY);
3321 }
3322
build_tunnel_header(const struct ib_ud_wr * wr,void * wqe,unsigned * mlx_seg_len)3323 static void build_tunnel_header(const struct ib_ud_wr *wr, void *wqe,
3324 unsigned *mlx_seg_len)
3325 {
3326 struct mlx4_wqe_inline_seg *inl = wqe;
3327 struct mlx4_ib_tunnel_header hdr;
3328 struct mlx4_ib_ah *ah = to_mah(wr->ah);
3329 int spc;
3330 int i;
3331
3332 memcpy(&hdr.av, &ah->av, sizeof hdr.av);
3333 hdr.remote_qpn = cpu_to_be32(wr->remote_qpn);
3334 hdr.pkey_index = cpu_to_be16(wr->pkey_index);
3335 hdr.qkey = cpu_to_be32(wr->remote_qkey);
3336 memcpy(hdr.mac, ah->av.eth.mac, 6);
3337 hdr.vlan = ah->av.eth.vlan;
3338
3339 spc = MLX4_INLINE_ALIGN -
3340 ((unsigned long) (inl + 1) & (MLX4_INLINE_ALIGN - 1));
3341 if (sizeof (hdr) <= spc) {
3342 memcpy(inl + 1, &hdr, sizeof (hdr));
3343 wmb();
3344 inl->byte_count = cpu_to_be32(1 << 31 | sizeof (hdr));
3345 i = 1;
3346 } else {
3347 memcpy(inl + 1, &hdr, spc);
3348 wmb();
3349 inl->byte_count = cpu_to_be32(1 << 31 | spc);
3350
3351 inl = (void *) (inl + 1) + spc;
3352 memcpy(inl + 1, (void *) &hdr + spc, sizeof (hdr) - spc);
3353 wmb();
3354 inl->byte_count = cpu_to_be32(1 << 31 | (sizeof (hdr) - spc));
3355 i = 2;
3356 }
3357
3358 *mlx_seg_len =
3359 ALIGN(i * sizeof (struct mlx4_wqe_inline_seg) + sizeof (hdr), 16);
3360 }
3361
set_mlx_icrc_seg(void * dseg)3362 static void set_mlx_icrc_seg(void *dseg)
3363 {
3364 u32 *t = dseg;
3365 struct mlx4_wqe_inline_seg *iseg = dseg;
3366
3367 t[1] = 0;
3368
3369 /*
3370 * Need a barrier here before writing the byte_count field to
3371 * make sure that all the data is visible before the
3372 * byte_count field is set. Otherwise, if the segment begins
3373 * a new cacheline, the HCA prefetcher could grab the 64-byte
3374 * chunk and get a valid (!= * 0xffffffff) byte count but
3375 * stale data, and end up sending the wrong data.
3376 */
3377 wmb();
3378
3379 iseg->byte_count = cpu_to_be32((1 << 31) | 4);
3380 }
3381
set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)3382 static void set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3383 {
3384 dseg->lkey = cpu_to_be32(sg->lkey);
3385 dseg->addr = cpu_to_be64(sg->addr);
3386
3387 /*
3388 * Need a barrier here before writing the byte_count field to
3389 * make sure that all the data is visible before the
3390 * byte_count field is set. Otherwise, if the segment begins
3391 * a new cacheline, the HCA prefetcher could grab the 64-byte
3392 * chunk and get a valid (!= * 0xffffffff) byte count but
3393 * stale data, and end up sending the wrong data.
3394 */
3395 wmb();
3396
3397 dseg->byte_count = cpu_to_be32(sg->length);
3398 }
3399
__set_data_seg(struct mlx4_wqe_data_seg * dseg,struct ib_sge * sg)3400 static void __set_data_seg(struct mlx4_wqe_data_seg *dseg, struct ib_sge *sg)
3401 {
3402 dseg->byte_count = cpu_to_be32(sg->length);
3403 dseg->lkey = cpu_to_be32(sg->lkey);
3404 dseg->addr = cpu_to_be64(sg->addr);
3405 }
3406
build_lso_seg(struct mlx4_wqe_lso_seg * wqe,const struct ib_ud_wr * wr,struct mlx4_ib_qp * qp,unsigned * lso_seg_len,__be32 * lso_hdr_sz,__be32 * blh)3407 static int build_lso_seg(struct mlx4_wqe_lso_seg *wqe,
3408 const struct ib_ud_wr *wr, struct mlx4_ib_qp *qp,
3409 unsigned *lso_seg_len, __be32 *lso_hdr_sz, __be32 *blh)
3410 {
3411 unsigned halign = ALIGN(sizeof *wqe + wr->hlen, 16);
3412
3413 if (unlikely(halign > MLX4_IB_CACHE_LINE_SIZE))
3414 *blh = cpu_to_be32(1 << 6);
3415
3416 if (unlikely(!(qp->flags & MLX4_IB_QP_LSO) &&
3417 wr->wr.num_sge > qp->sq.max_gs - (halign >> 4)))
3418 return -EINVAL;
3419
3420 memcpy(wqe->header, wr->header, wr->hlen);
3421
3422 *lso_hdr_sz = cpu_to_be32(wr->mss << 16 | wr->hlen);
3423 *lso_seg_len = halign;
3424 return 0;
3425 }
3426
send_ieth(const struct ib_send_wr * wr)3427 static __be32 send_ieth(const struct ib_send_wr *wr)
3428 {
3429 switch (wr->opcode) {
3430 case IB_WR_SEND_WITH_IMM:
3431 case IB_WR_RDMA_WRITE_WITH_IMM:
3432 return wr->ex.imm_data;
3433
3434 case IB_WR_SEND_WITH_INV:
3435 return cpu_to_be32(wr->ex.invalidate_rkey);
3436
3437 default:
3438 return 0;
3439 }
3440 }
3441
add_zero_len_inline(void * wqe)3442 static void add_zero_len_inline(void *wqe)
3443 {
3444 struct mlx4_wqe_inline_seg *inl = wqe;
3445 memset(wqe, 0, 16);
3446 inl->byte_count = cpu_to_be32(1 << 31);
3447 }
3448
_mlx4_ib_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr,bool drain)3449 static int _mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3450 const struct ib_send_wr **bad_wr, bool drain)
3451 {
3452 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3453 void *wqe;
3454 struct mlx4_wqe_ctrl_seg *ctrl;
3455 struct mlx4_wqe_data_seg *dseg;
3456 unsigned long flags;
3457 int nreq;
3458 int err = 0;
3459 unsigned ind;
3460 int uninitialized_var(size);
3461 unsigned uninitialized_var(seglen);
3462 __be32 dummy;
3463 __be32 *lso_wqe;
3464 __be32 uninitialized_var(lso_hdr_sz);
3465 __be32 blh;
3466 int i;
3467 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3468
3469 if (qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI) {
3470 struct mlx4_ib_sqp *sqp = to_msqp(qp);
3471
3472 if (sqp->roce_v2_gsi) {
3473 struct mlx4_ib_ah *ah = to_mah(ud_wr(wr)->ah);
3474 enum ib_gid_type gid_type;
3475 union ib_gid gid;
3476
3477 if (!fill_gid_by_hw_index(mdev, sqp->qp.port,
3478 ah->av.ib.gid_index,
3479 &gid, &gid_type))
3480 qp = (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP) ?
3481 to_mqp(sqp->roce_v2_gsi) : qp;
3482 else
3483 pr_err("Failed to get gid at index %d. RoCEv2 will not work properly\n",
3484 ah->av.ib.gid_index);
3485 }
3486 }
3487
3488 spin_lock_irqsave(&qp->sq.lock, flags);
3489 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3490 !drain) {
3491 err = -EIO;
3492 *bad_wr = wr;
3493 nreq = 0;
3494 goto out;
3495 }
3496
3497 ind = qp->sq_next_wqe;
3498
3499 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3500 lso_wqe = &dummy;
3501 blh = 0;
3502
3503 if (mlx4_wq_overflow(&qp->sq, nreq, qp->ibqp.send_cq)) {
3504 err = -ENOMEM;
3505 *bad_wr = wr;
3506 goto out;
3507 }
3508
3509 if (unlikely(wr->num_sge > qp->sq.max_gs)) {
3510 err = -EINVAL;
3511 *bad_wr = wr;
3512 goto out;
3513 }
3514
3515 ctrl = wqe = get_send_wqe(qp, ind & (qp->sq.wqe_cnt - 1));
3516 qp->sq.wrid[(qp->sq.head + nreq) & (qp->sq.wqe_cnt - 1)] = wr->wr_id;
3517
3518 ctrl->srcrb_flags =
3519 (wr->send_flags & IB_SEND_SIGNALED ?
3520 cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) : 0) |
3521 (wr->send_flags & IB_SEND_SOLICITED ?
3522 cpu_to_be32(MLX4_WQE_CTRL_SOLICITED) : 0) |
3523 ((wr->send_flags & IB_SEND_IP_CSUM) ?
3524 cpu_to_be32(MLX4_WQE_CTRL_IP_CSUM |
3525 MLX4_WQE_CTRL_TCP_UDP_CSUM) : 0) |
3526 qp->sq_signal_bits;
3527
3528 ctrl->imm = send_ieth(wr);
3529
3530 wqe += sizeof *ctrl;
3531 size = sizeof *ctrl / 16;
3532
3533 switch (qp->mlx4_ib_qp_type) {
3534 case MLX4_IB_QPT_RC:
3535 case MLX4_IB_QPT_UC:
3536 switch (wr->opcode) {
3537 case IB_WR_ATOMIC_CMP_AND_SWP:
3538 case IB_WR_ATOMIC_FETCH_AND_ADD:
3539 case IB_WR_MASKED_ATOMIC_FETCH_AND_ADD:
3540 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3541 atomic_wr(wr)->rkey);
3542 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3543
3544 set_atomic_seg(wqe, atomic_wr(wr));
3545 wqe += sizeof (struct mlx4_wqe_atomic_seg);
3546
3547 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3548 sizeof (struct mlx4_wqe_atomic_seg)) / 16;
3549
3550 break;
3551
3552 case IB_WR_MASKED_ATOMIC_CMP_AND_SWP:
3553 set_raddr_seg(wqe, atomic_wr(wr)->remote_addr,
3554 atomic_wr(wr)->rkey);
3555 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3556
3557 set_masked_atomic_seg(wqe, atomic_wr(wr));
3558 wqe += sizeof (struct mlx4_wqe_masked_atomic_seg);
3559
3560 size += (sizeof (struct mlx4_wqe_raddr_seg) +
3561 sizeof (struct mlx4_wqe_masked_atomic_seg)) / 16;
3562
3563 break;
3564
3565 case IB_WR_RDMA_READ:
3566 case IB_WR_RDMA_WRITE:
3567 case IB_WR_RDMA_WRITE_WITH_IMM:
3568 set_raddr_seg(wqe, rdma_wr(wr)->remote_addr,
3569 rdma_wr(wr)->rkey);
3570 wqe += sizeof (struct mlx4_wqe_raddr_seg);
3571 size += sizeof (struct mlx4_wqe_raddr_seg) / 16;
3572 break;
3573
3574 case IB_WR_LOCAL_INV:
3575 ctrl->srcrb_flags |=
3576 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3577 set_local_inv_seg(wqe, wr->ex.invalidate_rkey);
3578 wqe += sizeof (struct mlx4_wqe_local_inval_seg);
3579 size += sizeof (struct mlx4_wqe_local_inval_seg) / 16;
3580 break;
3581
3582 case IB_WR_REG_MR:
3583 ctrl->srcrb_flags |=
3584 cpu_to_be32(MLX4_WQE_CTRL_STRONG_ORDER);
3585 set_reg_seg(wqe, reg_wr(wr));
3586 wqe += sizeof(struct mlx4_wqe_fmr_seg);
3587 size += sizeof(struct mlx4_wqe_fmr_seg) / 16;
3588 break;
3589
3590 default:
3591 /* No extra segments required for sends */
3592 break;
3593 }
3594 break;
3595
3596 case MLX4_IB_QPT_TUN_SMI_OWNER:
3597 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3598 ctrl, &seglen);
3599 if (unlikely(err)) {
3600 *bad_wr = wr;
3601 goto out;
3602 }
3603 wqe += seglen;
3604 size += seglen / 16;
3605 break;
3606 case MLX4_IB_QPT_TUN_SMI:
3607 case MLX4_IB_QPT_TUN_GSI:
3608 /* this is a UD qp used in MAD responses to slaves. */
3609 set_datagram_seg(wqe, ud_wr(wr));
3610 /* set the forced-loopback bit in the data seg av */
3611 *(__be32 *) wqe |= cpu_to_be32(0x80000000);
3612 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3613 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3614 break;
3615 case MLX4_IB_QPT_UD:
3616 set_datagram_seg(wqe, ud_wr(wr));
3617 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3618 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3619
3620 if (wr->opcode == IB_WR_LSO) {
3621 err = build_lso_seg(wqe, ud_wr(wr), qp, &seglen,
3622 &lso_hdr_sz, &blh);
3623 if (unlikely(err)) {
3624 *bad_wr = wr;
3625 goto out;
3626 }
3627 lso_wqe = (__be32 *) wqe;
3628 wqe += seglen;
3629 size += seglen / 16;
3630 }
3631 break;
3632
3633 case MLX4_IB_QPT_PROXY_SMI_OWNER:
3634 err = build_sriov_qp0_header(to_msqp(qp), ud_wr(wr),
3635 ctrl, &seglen);
3636 if (unlikely(err)) {
3637 *bad_wr = wr;
3638 goto out;
3639 }
3640 wqe += seglen;
3641 size += seglen / 16;
3642 /* to start tunnel header on a cache-line boundary */
3643 add_zero_len_inline(wqe);
3644 wqe += 16;
3645 size++;
3646 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3647 wqe += seglen;
3648 size += seglen / 16;
3649 break;
3650 case MLX4_IB_QPT_PROXY_SMI:
3651 case MLX4_IB_QPT_PROXY_GSI:
3652 /* If we are tunneling special qps, this is a UD qp.
3653 * In this case we first add a UD segment targeting
3654 * the tunnel qp, and then add a header with address
3655 * information */
3656 set_tunnel_datagram_seg(to_mdev(ibqp->device), wqe,
3657 ud_wr(wr),
3658 qp->mlx4_ib_qp_type);
3659 wqe += sizeof (struct mlx4_wqe_datagram_seg);
3660 size += sizeof (struct mlx4_wqe_datagram_seg) / 16;
3661 build_tunnel_header(ud_wr(wr), wqe, &seglen);
3662 wqe += seglen;
3663 size += seglen / 16;
3664 break;
3665
3666 case MLX4_IB_QPT_SMI:
3667 case MLX4_IB_QPT_GSI:
3668 err = build_mlx_header(to_msqp(qp), ud_wr(wr), ctrl,
3669 &seglen);
3670 if (unlikely(err)) {
3671 *bad_wr = wr;
3672 goto out;
3673 }
3674 wqe += seglen;
3675 size += seglen / 16;
3676 break;
3677
3678 default:
3679 break;
3680 }
3681
3682 /*
3683 * Write data segments in reverse order, so as to
3684 * overwrite cacheline stamp last within each
3685 * cacheline. This avoids issues with WQE
3686 * prefetching.
3687 */
3688
3689 dseg = wqe;
3690 dseg += wr->num_sge - 1;
3691 size += wr->num_sge * (sizeof (struct mlx4_wqe_data_seg) / 16);
3692
3693 /* Add one more inline data segment for ICRC for MLX sends */
3694 if (unlikely(qp->mlx4_ib_qp_type == MLX4_IB_QPT_SMI ||
3695 qp->mlx4_ib_qp_type == MLX4_IB_QPT_GSI ||
3696 qp->mlx4_ib_qp_type &
3697 (MLX4_IB_QPT_PROXY_SMI_OWNER | MLX4_IB_QPT_TUN_SMI_OWNER))) {
3698 set_mlx_icrc_seg(dseg + 1);
3699 size += sizeof (struct mlx4_wqe_data_seg) / 16;
3700 }
3701
3702 for (i = wr->num_sge - 1; i >= 0; --i, --dseg)
3703 set_data_seg(dseg, wr->sg_list + i);
3704
3705 /*
3706 * Possibly overwrite stamping in cacheline with LSO
3707 * segment only after making sure all data segments
3708 * are written.
3709 */
3710 wmb();
3711 *lso_wqe = lso_hdr_sz;
3712
3713 ctrl->qpn_vlan.fence_size = (wr->send_flags & IB_SEND_FENCE ?
3714 MLX4_WQE_CTRL_FENCE : 0) | size;
3715
3716 /*
3717 * Make sure descriptor is fully written before
3718 * setting ownership bit (because HW can start
3719 * executing as soon as we do).
3720 */
3721 wmb();
3722
3723 if (wr->opcode < 0 || wr->opcode >= ARRAY_SIZE(mlx4_ib_opcode)) {
3724 *bad_wr = wr;
3725 err = -EINVAL;
3726 goto out;
3727 }
3728
3729 ctrl->owner_opcode = mlx4_ib_opcode[wr->opcode] |
3730 (ind & qp->sq.wqe_cnt ? cpu_to_be32(1 << 31) : 0) | blh;
3731
3732 /*
3733 * We can improve latency by not stamping the last
3734 * send queue WQE until after ringing the doorbell, so
3735 * only stamp here if there are still more WQEs to post.
3736 */
3737 if (wr->next)
3738 stamp_send_wqe(qp, ind + qp->sq_spare_wqes);
3739 ind++;
3740 }
3741
3742 out:
3743 if (likely(nreq)) {
3744 qp->sq.head += nreq;
3745
3746 /*
3747 * Make sure that descriptors are written before
3748 * doorbell record.
3749 */
3750 wmb();
3751
3752 writel_relaxed(qp->doorbell_qpn,
3753 to_mdev(ibqp->device)->uar_map + MLX4_SEND_DOORBELL);
3754
3755 /*
3756 * Make sure doorbells don't leak out of SQ spinlock
3757 * and reach the HCA out of order.
3758 */
3759 mmiowb();
3760
3761 stamp_send_wqe(qp, ind + qp->sq_spare_wqes - 1);
3762
3763 qp->sq_next_wqe = ind;
3764 }
3765
3766 spin_unlock_irqrestore(&qp->sq.lock, flags);
3767
3768 return err;
3769 }
3770
mlx4_ib_post_send(struct ib_qp * ibqp,const struct ib_send_wr * wr,const struct ib_send_wr ** bad_wr)3771 int mlx4_ib_post_send(struct ib_qp *ibqp, const struct ib_send_wr *wr,
3772 const struct ib_send_wr **bad_wr)
3773 {
3774 return _mlx4_ib_post_send(ibqp, wr, bad_wr, false);
3775 }
3776
_mlx4_ib_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr,bool drain)3777 static int _mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3778 const struct ib_recv_wr **bad_wr, bool drain)
3779 {
3780 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3781 struct mlx4_wqe_data_seg *scat;
3782 unsigned long flags;
3783 int err = 0;
3784 int nreq;
3785 int ind;
3786 int max_gs;
3787 int i;
3788 struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
3789
3790 max_gs = qp->rq.max_gs;
3791 spin_lock_irqsave(&qp->rq.lock, flags);
3792
3793 if (mdev->dev->persist->state & MLX4_DEVICE_STATE_INTERNAL_ERROR &&
3794 !drain) {
3795 err = -EIO;
3796 *bad_wr = wr;
3797 nreq = 0;
3798 goto out;
3799 }
3800
3801 ind = qp->rq.head & (qp->rq.wqe_cnt - 1);
3802
3803 for (nreq = 0; wr; ++nreq, wr = wr->next) {
3804 if (mlx4_wq_overflow(&qp->rq, nreq, qp->ibqp.recv_cq)) {
3805 err = -ENOMEM;
3806 *bad_wr = wr;
3807 goto out;
3808 }
3809
3810 if (unlikely(wr->num_sge > qp->rq.max_gs)) {
3811 err = -EINVAL;
3812 *bad_wr = wr;
3813 goto out;
3814 }
3815
3816 scat = get_recv_wqe(qp, ind);
3817
3818 if (qp->mlx4_ib_qp_type & (MLX4_IB_QPT_PROXY_SMI_OWNER |
3819 MLX4_IB_QPT_PROXY_SMI | MLX4_IB_QPT_PROXY_GSI)) {
3820 ib_dma_sync_single_for_device(ibqp->device,
3821 qp->sqp_proxy_rcv[ind].map,
3822 sizeof (struct mlx4_ib_proxy_sqp_hdr),
3823 DMA_FROM_DEVICE);
3824 scat->byte_count =
3825 cpu_to_be32(sizeof (struct mlx4_ib_proxy_sqp_hdr));
3826 /* use dma lkey from upper layer entry */
3827 scat->lkey = cpu_to_be32(wr->sg_list->lkey);
3828 scat->addr = cpu_to_be64(qp->sqp_proxy_rcv[ind].map);
3829 scat++;
3830 max_gs--;
3831 }
3832
3833 for (i = 0; i < wr->num_sge; ++i)
3834 __set_data_seg(scat + i, wr->sg_list + i);
3835
3836 if (i < max_gs) {
3837 scat[i].byte_count = 0;
3838 scat[i].lkey = cpu_to_be32(MLX4_INVALID_LKEY);
3839 scat[i].addr = 0;
3840 }
3841
3842 qp->rq.wrid[ind] = wr->wr_id;
3843
3844 ind = (ind + 1) & (qp->rq.wqe_cnt - 1);
3845 }
3846
3847 out:
3848 if (likely(nreq)) {
3849 qp->rq.head += nreq;
3850
3851 /*
3852 * Make sure that descriptors are written before
3853 * doorbell record.
3854 */
3855 wmb();
3856
3857 *qp->db.db = cpu_to_be32(qp->rq.head & 0xffff);
3858 }
3859
3860 spin_unlock_irqrestore(&qp->rq.lock, flags);
3861
3862 return err;
3863 }
3864
mlx4_ib_post_recv(struct ib_qp * ibqp,const struct ib_recv_wr * wr,const struct ib_recv_wr ** bad_wr)3865 int mlx4_ib_post_recv(struct ib_qp *ibqp, const struct ib_recv_wr *wr,
3866 const struct ib_recv_wr **bad_wr)
3867 {
3868 return _mlx4_ib_post_recv(ibqp, wr, bad_wr, false);
3869 }
3870
to_ib_qp_state(enum mlx4_qp_state mlx4_state)3871 static inline enum ib_qp_state to_ib_qp_state(enum mlx4_qp_state mlx4_state)
3872 {
3873 switch (mlx4_state) {
3874 case MLX4_QP_STATE_RST: return IB_QPS_RESET;
3875 case MLX4_QP_STATE_INIT: return IB_QPS_INIT;
3876 case MLX4_QP_STATE_RTR: return IB_QPS_RTR;
3877 case MLX4_QP_STATE_RTS: return IB_QPS_RTS;
3878 case MLX4_QP_STATE_SQ_DRAINING:
3879 case MLX4_QP_STATE_SQD: return IB_QPS_SQD;
3880 case MLX4_QP_STATE_SQER: return IB_QPS_SQE;
3881 case MLX4_QP_STATE_ERR: return IB_QPS_ERR;
3882 default: return -1;
3883 }
3884 }
3885
to_ib_mig_state(int mlx4_mig_state)3886 static inline enum ib_mig_state to_ib_mig_state(int mlx4_mig_state)
3887 {
3888 switch (mlx4_mig_state) {
3889 case MLX4_QP_PM_ARMED: return IB_MIG_ARMED;
3890 case MLX4_QP_PM_REARM: return IB_MIG_REARM;
3891 case MLX4_QP_PM_MIGRATED: return IB_MIG_MIGRATED;
3892 default: return -1;
3893 }
3894 }
3895
to_ib_qp_access_flags(int mlx4_flags)3896 static int to_ib_qp_access_flags(int mlx4_flags)
3897 {
3898 int ib_flags = 0;
3899
3900 if (mlx4_flags & MLX4_QP_BIT_RRE)
3901 ib_flags |= IB_ACCESS_REMOTE_READ;
3902 if (mlx4_flags & MLX4_QP_BIT_RWE)
3903 ib_flags |= IB_ACCESS_REMOTE_WRITE;
3904 if (mlx4_flags & MLX4_QP_BIT_RAE)
3905 ib_flags |= IB_ACCESS_REMOTE_ATOMIC;
3906
3907 return ib_flags;
3908 }
3909
to_rdma_ah_attr(struct mlx4_ib_dev * ibdev,struct rdma_ah_attr * ah_attr,struct mlx4_qp_path * path)3910 static void to_rdma_ah_attr(struct mlx4_ib_dev *ibdev,
3911 struct rdma_ah_attr *ah_attr,
3912 struct mlx4_qp_path *path)
3913 {
3914 struct mlx4_dev *dev = ibdev->dev;
3915 u8 port_num = path->sched_queue & 0x40 ? 2 : 1;
3916
3917 memset(ah_attr, 0, sizeof(*ah_attr));
3918 if (port_num == 0 || port_num > dev->caps.num_ports)
3919 return;
3920 ah_attr->type = rdma_ah_find_type(&ibdev->ib_dev, port_num);
3921
3922 if (ah_attr->type == RDMA_AH_ATTR_TYPE_ROCE)
3923 rdma_ah_set_sl(ah_attr, ((path->sched_queue >> 3) & 0x7) |
3924 ((path->sched_queue & 4) << 1));
3925 else
3926 rdma_ah_set_sl(ah_attr, (path->sched_queue >> 2) & 0xf);
3927 rdma_ah_set_port_num(ah_attr, port_num);
3928
3929 rdma_ah_set_dlid(ah_attr, be16_to_cpu(path->rlid));
3930 rdma_ah_set_path_bits(ah_attr, path->grh_mylmc & 0x7f);
3931 rdma_ah_set_static_rate(ah_attr,
3932 path->static_rate ? path->static_rate - 5 : 0);
3933 if (path->grh_mylmc & (1 << 7)) {
3934 rdma_ah_set_grh(ah_attr, NULL,
3935 be32_to_cpu(path->tclass_flowlabel) & 0xfffff,
3936 path->mgid_index,
3937 path->hop_limit,
3938 (be32_to_cpu(path->tclass_flowlabel)
3939 >> 20) & 0xff);
3940 rdma_ah_set_dgid_raw(ah_attr, path->rgid);
3941 }
3942 }
3943
mlx4_ib_query_qp(struct ib_qp * ibqp,struct ib_qp_attr * qp_attr,int qp_attr_mask,struct ib_qp_init_attr * qp_init_attr)3944 int mlx4_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
3945 struct ib_qp_init_attr *qp_init_attr)
3946 {
3947 struct mlx4_ib_dev *dev = to_mdev(ibqp->device);
3948 struct mlx4_ib_qp *qp = to_mqp(ibqp);
3949 struct mlx4_qp_context context;
3950 int mlx4_state;
3951 int err = 0;
3952
3953 if (ibqp->rwq_ind_tbl)
3954 return -EOPNOTSUPP;
3955
3956 mutex_lock(&qp->mutex);
3957
3958 if (qp->state == IB_QPS_RESET) {
3959 qp_attr->qp_state = IB_QPS_RESET;
3960 goto done;
3961 }
3962
3963 err = mlx4_qp_query(dev->dev, &qp->mqp, &context);
3964 if (err) {
3965 err = -EINVAL;
3966 goto out;
3967 }
3968
3969 mlx4_state = be32_to_cpu(context.flags) >> 28;
3970
3971 qp->state = to_ib_qp_state(mlx4_state);
3972 qp_attr->qp_state = qp->state;
3973 qp_attr->path_mtu = context.mtu_msgmax >> 5;
3974 qp_attr->path_mig_state =
3975 to_ib_mig_state((be32_to_cpu(context.flags) >> 11) & 0x3);
3976 qp_attr->qkey = be32_to_cpu(context.qkey);
3977 qp_attr->rq_psn = be32_to_cpu(context.rnr_nextrecvpsn) & 0xffffff;
3978 qp_attr->sq_psn = be32_to_cpu(context.next_send_psn) & 0xffffff;
3979 qp_attr->dest_qp_num = be32_to_cpu(context.remote_qpn) & 0xffffff;
3980 qp_attr->qp_access_flags =
3981 to_ib_qp_access_flags(be32_to_cpu(context.params2));
3982
3983 if (qp->ibqp.qp_type == IB_QPT_RC || qp->ibqp.qp_type == IB_QPT_UC) {
3984 to_rdma_ah_attr(dev, &qp_attr->ah_attr, &context.pri_path);
3985 to_rdma_ah_attr(dev, &qp_attr->alt_ah_attr, &context.alt_path);
3986 qp_attr->alt_pkey_index = context.alt_path.pkey_index & 0x7f;
3987 qp_attr->alt_port_num =
3988 rdma_ah_get_port_num(&qp_attr->alt_ah_attr);
3989 }
3990
3991 qp_attr->pkey_index = context.pri_path.pkey_index & 0x7f;
3992 if (qp_attr->qp_state == IB_QPS_INIT)
3993 qp_attr->port_num = qp->port;
3994 else
3995 qp_attr->port_num = context.pri_path.sched_queue & 0x40 ? 2 : 1;
3996
3997 /* qp_attr->en_sqd_async_notify is only applicable in modify qp */
3998 qp_attr->sq_draining = mlx4_state == MLX4_QP_STATE_SQ_DRAINING;
3999
4000 qp_attr->max_rd_atomic = 1 << ((be32_to_cpu(context.params1) >> 21) & 0x7);
4001
4002 qp_attr->max_dest_rd_atomic =
4003 1 << ((be32_to_cpu(context.params2) >> 21) & 0x7);
4004 qp_attr->min_rnr_timer =
4005 (be32_to_cpu(context.rnr_nextrecvpsn) >> 24) & 0x1f;
4006 qp_attr->timeout = context.pri_path.ackto >> 3;
4007 qp_attr->retry_cnt = (be32_to_cpu(context.params1) >> 16) & 0x7;
4008 qp_attr->rnr_retry = (be32_to_cpu(context.params1) >> 13) & 0x7;
4009 qp_attr->alt_timeout = context.alt_path.ackto >> 3;
4010
4011 done:
4012 qp_attr->cur_qp_state = qp_attr->qp_state;
4013 qp_attr->cap.max_recv_wr = qp->rq.wqe_cnt;
4014 qp_attr->cap.max_recv_sge = qp->rq.max_gs;
4015
4016 if (!ibqp->uobject) {
4017 qp_attr->cap.max_send_wr = qp->sq.wqe_cnt;
4018 qp_attr->cap.max_send_sge = qp->sq.max_gs;
4019 } else {
4020 qp_attr->cap.max_send_wr = 0;
4021 qp_attr->cap.max_send_sge = 0;
4022 }
4023
4024 /*
4025 * We don't support inline sends for kernel QPs (yet), and we
4026 * don't know what userspace's value should be.
4027 */
4028 qp_attr->cap.max_inline_data = 0;
4029
4030 qp_init_attr->cap = qp_attr->cap;
4031
4032 qp_init_attr->create_flags = 0;
4033 if (qp->flags & MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK)
4034 qp_init_attr->create_flags |= IB_QP_CREATE_BLOCK_MULTICAST_LOOPBACK;
4035
4036 if (qp->flags & MLX4_IB_QP_LSO)
4037 qp_init_attr->create_flags |= IB_QP_CREATE_IPOIB_UD_LSO;
4038
4039 if (qp->flags & MLX4_IB_QP_NETIF)
4040 qp_init_attr->create_flags |= IB_QP_CREATE_NETIF_QP;
4041
4042 qp_init_attr->sq_sig_type =
4043 qp->sq_signal_bits == cpu_to_be32(MLX4_WQE_CTRL_CQ_UPDATE) ?
4044 IB_SIGNAL_ALL_WR : IB_SIGNAL_REQ_WR;
4045
4046 out:
4047 mutex_unlock(&qp->mutex);
4048 return err;
4049 }
4050
mlx4_ib_create_wq(struct ib_pd * pd,struct ib_wq_init_attr * init_attr,struct ib_udata * udata)4051 struct ib_wq *mlx4_ib_create_wq(struct ib_pd *pd,
4052 struct ib_wq_init_attr *init_attr,
4053 struct ib_udata *udata)
4054 {
4055 struct mlx4_ib_dev *dev;
4056 struct ib_qp_init_attr ib_qp_init_attr;
4057 struct mlx4_ib_qp *qp;
4058 struct mlx4_ib_create_wq ucmd;
4059 int err, required_cmd_sz;
4060
4061 if (!(udata && pd->uobject))
4062 return ERR_PTR(-EINVAL);
4063
4064 required_cmd_sz = offsetof(typeof(ucmd), comp_mask) +
4065 sizeof(ucmd.comp_mask);
4066 if (udata->inlen < required_cmd_sz) {
4067 pr_debug("invalid inlen\n");
4068 return ERR_PTR(-EINVAL);
4069 }
4070
4071 if (udata->inlen > sizeof(ucmd) &&
4072 !ib_is_udata_cleared(udata, sizeof(ucmd),
4073 udata->inlen - sizeof(ucmd))) {
4074 pr_debug("inlen is not supported\n");
4075 return ERR_PTR(-EOPNOTSUPP);
4076 }
4077
4078 if (udata->outlen)
4079 return ERR_PTR(-EOPNOTSUPP);
4080
4081 dev = to_mdev(pd->device);
4082
4083 if (init_attr->wq_type != IB_WQT_RQ) {
4084 pr_debug("unsupported wq type %d\n", init_attr->wq_type);
4085 return ERR_PTR(-EOPNOTSUPP);
4086 }
4087
4088 if (init_attr->create_flags & ~IB_WQ_FLAGS_SCATTER_FCS) {
4089 pr_debug("unsupported create_flags %u\n",
4090 init_attr->create_flags);
4091 return ERR_PTR(-EOPNOTSUPP);
4092 }
4093
4094 qp = kzalloc(sizeof(*qp), GFP_KERNEL);
4095 if (!qp)
4096 return ERR_PTR(-ENOMEM);
4097
4098 qp->pri.vid = 0xFFFF;
4099 qp->alt.vid = 0xFFFF;
4100
4101 memset(&ib_qp_init_attr, 0, sizeof(ib_qp_init_attr));
4102 ib_qp_init_attr.qp_context = init_attr->wq_context;
4103 ib_qp_init_attr.qp_type = IB_QPT_RAW_PACKET;
4104 ib_qp_init_attr.cap.max_recv_wr = init_attr->max_wr;
4105 ib_qp_init_attr.cap.max_recv_sge = init_attr->max_sge;
4106 ib_qp_init_attr.recv_cq = init_attr->cq;
4107 ib_qp_init_attr.send_cq = ib_qp_init_attr.recv_cq; /* Dummy CQ */
4108
4109 if (init_attr->create_flags & IB_WQ_FLAGS_SCATTER_FCS)
4110 ib_qp_init_attr.create_flags |= IB_QP_CREATE_SCATTER_FCS;
4111
4112 err = create_qp_common(dev, pd, MLX4_IB_RWQ_SRC, &ib_qp_init_attr,
4113 udata, 0, &qp);
4114 if (err) {
4115 kfree(qp);
4116 return ERR_PTR(err);
4117 }
4118
4119 qp->ibwq.event_handler = init_attr->event_handler;
4120 qp->ibwq.wq_num = qp->mqp.qpn;
4121 qp->ibwq.state = IB_WQS_RESET;
4122
4123 return &qp->ibwq;
4124 }
4125
ib_wq2qp_state(enum ib_wq_state state)4126 static int ib_wq2qp_state(enum ib_wq_state state)
4127 {
4128 switch (state) {
4129 case IB_WQS_RESET:
4130 return IB_QPS_RESET;
4131 case IB_WQS_RDY:
4132 return IB_QPS_RTR;
4133 default:
4134 return IB_QPS_ERR;
4135 }
4136 }
4137
_mlx4_ib_modify_wq(struct ib_wq * ibwq,enum ib_wq_state new_state)4138 static int _mlx4_ib_modify_wq(struct ib_wq *ibwq, enum ib_wq_state new_state)
4139 {
4140 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4141 enum ib_qp_state qp_cur_state;
4142 enum ib_qp_state qp_new_state;
4143 int attr_mask;
4144 int err;
4145
4146 /* ib_qp.state represents the WQ HW state while ib_wq.state represents
4147 * the WQ logic state.
4148 */
4149 qp_cur_state = qp->state;
4150 qp_new_state = ib_wq2qp_state(new_state);
4151
4152 if (ib_wq2qp_state(new_state) == qp_cur_state)
4153 return 0;
4154
4155 if (new_state == IB_WQS_RDY) {
4156 struct ib_qp_attr attr = {};
4157
4158 attr.port_num = qp->port;
4159 attr_mask = IB_QP_PORT;
4160
4161 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, &attr,
4162 attr_mask, IB_QPS_RESET, IB_QPS_INIT);
4163 if (err) {
4164 pr_debug("WQN=0x%06x failed to apply RST->INIT on the HW QP\n",
4165 ibwq->wq_num);
4166 return err;
4167 }
4168
4169 qp_cur_state = IB_QPS_INIT;
4170 }
4171
4172 attr_mask = 0;
4173 err = __mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL, attr_mask,
4174 qp_cur_state, qp_new_state);
4175
4176 if (err && (qp_cur_state == IB_QPS_INIT)) {
4177 qp_new_state = IB_QPS_RESET;
4178 if (__mlx4_ib_modify_qp(ibwq, MLX4_IB_RWQ_SRC, NULL,
4179 attr_mask, IB_QPS_INIT, IB_QPS_RESET)) {
4180 pr_warn("WQN=0x%06x failed with reverting HW's resources failure\n",
4181 ibwq->wq_num);
4182 qp_new_state = IB_QPS_INIT;
4183 }
4184 }
4185
4186 qp->state = qp_new_state;
4187
4188 return err;
4189 }
4190
mlx4_ib_modify_wq(struct ib_wq * ibwq,struct ib_wq_attr * wq_attr,u32 wq_attr_mask,struct ib_udata * udata)4191 int mlx4_ib_modify_wq(struct ib_wq *ibwq, struct ib_wq_attr *wq_attr,
4192 u32 wq_attr_mask, struct ib_udata *udata)
4193 {
4194 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4195 struct mlx4_ib_modify_wq ucmd = {};
4196 size_t required_cmd_sz;
4197 enum ib_wq_state cur_state, new_state;
4198 int err = 0;
4199
4200 required_cmd_sz = offsetof(typeof(ucmd), reserved) +
4201 sizeof(ucmd.reserved);
4202 if (udata->inlen < required_cmd_sz)
4203 return -EINVAL;
4204
4205 if (udata->inlen > sizeof(ucmd) &&
4206 !ib_is_udata_cleared(udata, sizeof(ucmd),
4207 udata->inlen - sizeof(ucmd)))
4208 return -EOPNOTSUPP;
4209
4210 if (ib_copy_from_udata(&ucmd, udata, min(sizeof(ucmd), udata->inlen)))
4211 return -EFAULT;
4212
4213 if (ucmd.comp_mask || ucmd.reserved)
4214 return -EOPNOTSUPP;
4215
4216 if (wq_attr_mask & IB_WQ_FLAGS)
4217 return -EOPNOTSUPP;
4218
4219 cur_state = wq_attr_mask & IB_WQ_CUR_STATE ? wq_attr->curr_wq_state :
4220 ibwq->state;
4221 new_state = wq_attr_mask & IB_WQ_STATE ? wq_attr->wq_state : cur_state;
4222
4223 if (cur_state < IB_WQS_RESET || cur_state > IB_WQS_ERR ||
4224 new_state < IB_WQS_RESET || new_state > IB_WQS_ERR)
4225 return -EINVAL;
4226
4227 if ((new_state == IB_WQS_RDY) && (cur_state == IB_WQS_ERR))
4228 return -EINVAL;
4229
4230 if ((new_state == IB_WQS_ERR) && (cur_state == IB_WQS_RESET))
4231 return -EINVAL;
4232
4233 /* Need to protect against the parent RSS which also may modify WQ
4234 * state.
4235 */
4236 mutex_lock(&qp->mutex);
4237
4238 /* Can update HW state only if a RSS QP has already associated to this
4239 * WQ, so we can apply its port on the WQ.
4240 */
4241 if (qp->rss_usecnt)
4242 err = _mlx4_ib_modify_wq(ibwq, new_state);
4243
4244 if (!err)
4245 ibwq->state = new_state;
4246
4247 mutex_unlock(&qp->mutex);
4248
4249 return err;
4250 }
4251
mlx4_ib_destroy_wq(struct ib_wq * ibwq)4252 int mlx4_ib_destroy_wq(struct ib_wq *ibwq)
4253 {
4254 struct mlx4_ib_dev *dev = to_mdev(ibwq->device);
4255 struct mlx4_ib_qp *qp = to_mqp((struct ib_qp *)ibwq);
4256
4257 if (qp->counter_index)
4258 mlx4_ib_free_qp_counter(dev, qp);
4259
4260 destroy_qp_common(dev, qp, MLX4_IB_RWQ_SRC, 1);
4261
4262 kfree(qp);
4263
4264 return 0;
4265 }
4266
4267 struct ib_rwq_ind_table
mlx4_ib_create_rwq_ind_table(struct ib_device * device,struct ib_rwq_ind_table_init_attr * init_attr,struct ib_udata * udata)4268 *mlx4_ib_create_rwq_ind_table(struct ib_device *device,
4269 struct ib_rwq_ind_table_init_attr *init_attr,
4270 struct ib_udata *udata)
4271 {
4272 struct ib_rwq_ind_table *rwq_ind_table;
4273 struct mlx4_ib_create_rwq_ind_tbl_resp resp = {};
4274 unsigned int ind_tbl_size = 1 << init_attr->log_ind_tbl_size;
4275 unsigned int base_wqn;
4276 size_t min_resp_len;
4277 int i;
4278 int err;
4279
4280 if (udata->inlen > 0 &&
4281 !ib_is_udata_cleared(udata, 0,
4282 udata->inlen))
4283 return ERR_PTR(-EOPNOTSUPP);
4284
4285 min_resp_len = offsetof(typeof(resp), reserved) + sizeof(resp.reserved);
4286 if (udata->outlen && udata->outlen < min_resp_len)
4287 return ERR_PTR(-EINVAL);
4288
4289 if (ind_tbl_size >
4290 device->attrs.rss_caps.max_rwq_indirection_table_size) {
4291 pr_debug("log_ind_tbl_size = %d is bigger than supported = %d\n",
4292 ind_tbl_size,
4293 device->attrs.rss_caps.max_rwq_indirection_table_size);
4294 return ERR_PTR(-EINVAL);
4295 }
4296
4297 base_wqn = init_attr->ind_tbl[0]->wq_num;
4298
4299 if (base_wqn % ind_tbl_size) {
4300 pr_debug("WQN=0x%x isn't aligned with indirection table size\n",
4301 base_wqn);
4302 return ERR_PTR(-EINVAL);
4303 }
4304
4305 for (i = 1; i < ind_tbl_size; i++) {
4306 if (++base_wqn != init_attr->ind_tbl[i]->wq_num) {
4307 pr_debug("indirection table's WQNs aren't consecutive\n");
4308 return ERR_PTR(-EINVAL);
4309 }
4310 }
4311
4312 rwq_ind_table = kzalloc(sizeof(*rwq_ind_table), GFP_KERNEL);
4313 if (!rwq_ind_table)
4314 return ERR_PTR(-ENOMEM);
4315
4316 if (udata->outlen) {
4317 resp.response_length = offsetof(typeof(resp), response_length) +
4318 sizeof(resp.response_length);
4319 err = ib_copy_to_udata(udata, &resp, resp.response_length);
4320 if (err)
4321 goto err;
4322 }
4323
4324 return rwq_ind_table;
4325
4326 err:
4327 kfree(rwq_ind_table);
4328 return ERR_PTR(err);
4329 }
4330
mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table * ib_rwq_ind_tbl)4331 int mlx4_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
4332 {
4333 kfree(ib_rwq_ind_tbl);
4334 return 0;
4335 }
4336
4337 struct mlx4_ib_drain_cqe {
4338 struct ib_cqe cqe;
4339 struct completion done;
4340 };
4341
mlx4_ib_drain_qp_done(struct ib_cq * cq,struct ib_wc * wc)4342 static void mlx4_ib_drain_qp_done(struct ib_cq *cq, struct ib_wc *wc)
4343 {
4344 struct mlx4_ib_drain_cqe *cqe = container_of(wc->wr_cqe,
4345 struct mlx4_ib_drain_cqe,
4346 cqe);
4347
4348 complete(&cqe->done);
4349 }
4350
4351 /* This function returns only once the drained WR was completed */
handle_drain_completion(struct ib_cq * cq,struct mlx4_ib_drain_cqe * sdrain,struct mlx4_ib_dev * dev)4352 static void handle_drain_completion(struct ib_cq *cq,
4353 struct mlx4_ib_drain_cqe *sdrain,
4354 struct mlx4_ib_dev *dev)
4355 {
4356 struct mlx4_dev *mdev = dev->dev;
4357
4358 if (cq->poll_ctx == IB_POLL_DIRECT) {
4359 while (wait_for_completion_timeout(&sdrain->done, HZ / 10) <= 0)
4360 ib_process_cq_direct(cq, -1);
4361 return;
4362 }
4363
4364 if (mdev->persist->state == MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4365 struct mlx4_ib_cq *mcq = to_mcq(cq);
4366 bool triggered = false;
4367 unsigned long flags;
4368
4369 spin_lock_irqsave(&dev->reset_flow_resource_lock, flags);
4370 /* Make sure that the CQ handler won't run if wasn't run yet */
4371 if (!mcq->mcq.reset_notify_added)
4372 mcq->mcq.reset_notify_added = 1;
4373 else
4374 triggered = true;
4375 spin_unlock_irqrestore(&dev->reset_flow_resource_lock, flags);
4376
4377 if (triggered) {
4378 /* Wait for any scheduled/running task to be ended */
4379 switch (cq->poll_ctx) {
4380 case IB_POLL_SOFTIRQ:
4381 irq_poll_disable(&cq->iop);
4382 irq_poll_enable(&cq->iop);
4383 break;
4384 case IB_POLL_WORKQUEUE:
4385 cancel_work_sync(&cq->work);
4386 break;
4387 default:
4388 WARN_ON_ONCE(1);
4389 }
4390 }
4391
4392 /* Run the CQ handler - this makes sure that the drain WR will
4393 * be processed if wasn't processed yet.
4394 */
4395 mcq->mcq.comp(&mcq->mcq);
4396 }
4397
4398 wait_for_completion(&sdrain->done);
4399 }
4400
mlx4_ib_drain_sq(struct ib_qp * qp)4401 void mlx4_ib_drain_sq(struct ib_qp *qp)
4402 {
4403 struct ib_cq *cq = qp->send_cq;
4404 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4405 struct mlx4_ib_drain_cqe sdrain;
4406 const struct ib_send_wr *bad_swr;
4407 struct ib_rdma_wr swr = {
4408 .wr = {
4409 .next = NULL,
4410 { .wr_cqe = &sdrain.cqe, },
4411 .opcode = IB_WR_RDMA_WRITE,
4412 },
4413 };
4414 int ret;
4415 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4416 struct mlx4_dev *mdev = dev->dev;
4417
4418 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4419 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4420 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4421 return;
4422 }
4423
4424 sdrain.cqe.done = mlx4_ib_drain_qp_done;
4425 init_completion(&sdrain.done);
4426
4427 ret = _mlx4_ib_post_send(qp, &swr.wr, &bad_swr, true);
4428 if (ret) {
4429 WARN_ONCE(ret, "failed to drain send queue: %d\n", ret);
4430 return;
4431 }
4432
4433 handle_drain_completion(cq, &sdrain, dev);
4434 }
4435
mlx4_ib_drain_rq(struct ib_qp * qp)4436 void mlx4_ib_drain_rq(struct ib_qp *qp)
4437 {
4438 struct ib_cq *cq = qp->recv_cq;
4439 struct ib_qp_attr attr = { .qp_state = IB_QPS_ERR };
4440 struct mlx4_ib_drain_cqe rdrain;
4441 struct ib_recv_wr rwr = {};
4442 const struct ib_recv_wr *bad_rwr;
4443 int ret;
4444 struct mlx4_ib_dev *dev = to_mdev(qp->device);
4445 struct mlx4_dev *mdev = dev->dev;
4446
4447 ret = ib_modify_qp(qp, &attr, IB_QP_STATE);
4448 if (ret && mdev->persist->state != MLX4_DEVICE_STATE_INTERNAL_ERROR) {
4449 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4450 return;
4451 }
4452
4453 rwr.wr_cqe = &rdrain.cqe;
4454 rdrain.cqe.done = mlx4_ib_drain_qp_done;
4455 init_completion(&rdrain.done);
4456
4457 ret = _mlx4_ib_post_recv(qp, &rwr, &bad_rwr, true);
4458 if (ret) {
4459 WARN_ONCE(ret, "failed to drain recv queue: %d\n", ret);
4460 return;
4461 }
4462
4463 handle_drain_completion(cq, &rdrain, dev);
4464 }
4465