1 /*
2 * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <rdma/ib_umem.h>
34 #include <rdma/ib_umem_odp.h>
35 #include <linux/kernel.h>
36
37 #include "mlx5_ib.h"
38 #include "cmd.h"
39
40 #define MAX_PREFETCH_LEN (4*1024*1024U)
41
42 /* Timeout in ms to wait for an active mmu notifier to complete when handling
43 * a pagefault. */
44 #define MMU_NOTIFIER_TIMEOUT 1000
45
46 #define MLX5_IMR_MTT_BITS (30 - PAGE_SHIFT)
47 #define MLX5_IMR_MTT_SHIFT (MLX5_IMR_MTT_BITS + PAGE_SHIFT)
48 #define MLX5_IMR_MTT_ENTRIES BIT_ULL(MLX5_IMR_MTT_BITS)
49 #define MLX5_IMR_MTT_SIZE BIT_ULL(MLX5_IMR_MTT_SHIFT)
50 #define MLX5_IMR_MTT_MASK (~(MLX5_IMR_MTT_SIZE - 1))
51
52 #define MLX5_KSM_PAGE_SHIFT MLX5_IMR_MTT_SHIFT
53
54 static u64 mlx5_imr_ksm_entries;
55
check_parent(struct ib_umem_odp * odp,struct mlx5_ib_mr * parent)56 static int check_parent(struct ib_umem_odp *odp,
57 struct mlx5_ib_mr *parent)
58 {
59 struct mlx5_ib_mr *mr = odp->private;
60
61 return mr && mr->parent == parent && !odp->dying;
62 }
63
odp_next(struct ib_umem_odp * odp)64 static struct ib_umem_odp *odp_next(struct ib_umem_odp *odp)
65 {
66 struct mlx5_ib_mr *mr = odp->private, *parent = mr->parent;
67 struct ib_ucontext *ctx = odp->umem->context;
68 struct rb_node *rb;
69
70 down_read(&ctx->umem_rwsem);
71 while (1) {
72 rb = rb_next(&odp->interval_tree.rb);
73 if (!rb)
74 goto not_found;
75 odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb);
76 if (check_parent(odp, parent))
77 goto end;
78 }
79 not_found:
80 odp = NULL;
81 end:
82 up_read(&ctx->umem_rwsem);
83 return odp;
84 }
85
odp_lookup(struct ib_ucontext * ctx,u64 start,u64 length,struct mlx5_ib_mr * parent)86 static struct ib_umem_odp *odp_lookup(struct ib_ucontext *ctx,
87 u64 start, u64 length,
88 struct mlx5_ib_mr *parent)
89 {
90 struct ib_umem_odp *odp;
91 struct rb_node *rb;
92
93 down_read(&ctx->umem_rwsem);
94 odp = rbt_ib_umem_lookup(&ctx->umem_tree, start, length);
95 if (!odp)
96 goto end;
97
98 while (1) {
99 if (check_parent(odp, parent))
100 goto end;
101 rb = rb_next(&odp->interval_tree.rb);
102 if (!rb)
103 goto not_found;
104 odp = rb_entry(rb, struct ib_umem_odp, interval_tree.rb);
105 if (ib_umem_start(odp->umem) > start + length)
106 goto not_found;
107 }
108 not_found:
109 odp = NULL;
110 end:
111 up_read(&ctx->umem_rwsem);
112 return odp;
113 }
114
mlx5_odp_populate_klm(struct mlx5_klm * pklm,size_t offset,size_t nentries,struct mlx5_ib_mr * mr,int flags)115 void mlx5_odp_populate_klm(struct mlx5_klm *pklm, size_t offset,
116 size_t nentries, struct mlx5_ib_mr *mr, int flags)
117 {
118 struct ib_pd *pd = mr->ibmr.pd;
119 struct ib_ucontext *ctx = pd->uobject->context;
120 struct mlx5_ib_dev *dev = to_mdev(pd->device);
121 struct ib_umem_odp *odp;
122 unsigned long va;
123 int i;
124
125 if (flags & MLX5_IB_UPD_XLT_ZAP) {
126 for (i = 0; i < nentries; i++, pklm++) {
127 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
128 pklm->key = cpu_to_be32(dev->null_mkey);
129 pklm->va = 0;
130 }
131 return;
132 }
133
134 odp = odp_lookup(ctx, offset * MLX5_IMR_MTT_SIZE,
135 nentries * MLX5_IMR_MTT_SIZE, mr);
136
137 for (i = 0; i < nentries; i++, pklm++) {
138 pklm->bcount = cpu_to_be32(MLX5_IMR_MTT_SIZE);
139 va = (offset + i) * MLX5_IMR_MTT_SIZE;
140 if (odp && odp->umem->address == va) {
141 struct mlx5_ib_mr *mtt = odp->private;
142
143 pklm->key = cpu_to_be32(mtt->ibmr.lkey);
144 odp = odp_next(odp);
145 } else {
146 pklm->key = cpu_to_be32(dev->null_mkey);
147 }
148 mlx5_ib_dbg(dev, "[%d] va %lx key %x\n",
149 i, va, be32_to_cpu(pklm->key));
150 }
151 }
152
mr_leaf_free_action(struct work_struct * work)153 static void mr_leaf_free_action(struct work_struct *work)
154 {
155 struct ib_umem_odp *odp = container_of(work, struct ib_umem_odp, work);
156 int idx = ib_umem_start(odp->umem) >> MLX5_IMR_MTT_SHIFT;
157 struct mlx5_ib_mr *mr = odp->private, *imr = mr->parent;
158
159 mr->parent = NULL;
160 synchronize_srcu(&mr->dev->mr_srcu);
161
162 ib_umem_release(odp->umem);
163 if (imr->live)
164 mlx5_ib_update_xlt(imr, idx, 1, 0,
165 MLX5_IB_UPD_XLT_INDIRECT |
166 MLX5_IB_UPD_XLT_ATOMIC);
167 mlx5_mr_cache_free(mr->dev, mr);
168
169 if (atomic_dec_and_test(&imr->num_leaf_free))
170 wake_up(&imr->q_leaf_free);
171 }
172
mlx5_ib_invalidate_range(struct ib_umem * umem,unsigned long start,unsigned long end)173 void mlx5_ib_invalidate_range(struct ib_umem *umem, unsigned long start,
174 unsigned long end)
175 {
176 struct mlx5_ib_mr *mr;
177 const u64 umr_block_mask = (MLX5_UMR_MTT_ALIGNMENT /
178 sizeof(struct mlx5_mtt)) - 1;
179 u64 idx = 0, blk_start_idx = 0;
180 int in_block = 0;
181 u64 addr;
182
183 if (!umem || !umem->odp_data) {
184 pr_err("invalidation called on NULL umem or non-ODP umem\n");
185 return;
186 }
187
188 mr = umem->odp_data->private;
189
190 if (!mr || !mr->ibmr.pd)
191 return;
192
193 start = max_t(u64, ib_umem_start(umem), start);
194 end = min_t(u64, ib_umem_end(umem), end);
195
196 /*
197 * Iteration one - zap the HW's MTTs. The notifiers_count ensures that
198 * while we are doing the invalidation, no page fault will attempt to
199 * overwrite the same MTTs. Concurent invalidations might race us,
200 * but they will write 0s as well, so no difference in the end result.
201 */
202
203 for (addr = start; addr < end; addr += BIT(umem->page_shift)) {
204 idx = (addr - ib_umem_start(umem)) >> umem->page_shift;
205 /*
206 * Strive to write the MTTs in chunks, but avoid overwriting
207 * non-existing MTTs. The huristic here can be improved to
208 * estimate the cost of another UMR vs. the cost of bigger
209 * UMR.
210 */
211 if (umem->odp_data->dma_list[idx] &
212 (ODP_READ_ALLOWED_BIT | ODP_WRITE_ALLOWED_BIT)) {
213 if (!in_block) {
214 blk_start_idx = idx;
215 in_block = 1;
216 }
217 } else {
218 u64 umr_offset = idx & umr_block_mask;
219
220 if (in_block && umr_offset == 0) {
221 mlx5_ib_update_xlt(mr, blk_start_idx,
222 idx - blk_start_idx, 0,
223 MLX5_IB_UPD_XLT_ZAP |
224 MLX5_IB_UPD_XLT_ATOMIC);
225 in_block = 0;
226 }
227 }
228 }
229 if (in_block)
230 mlx5_ib_update_xlt(mr, blk_start_idx,
231 idx - blk_start_idx + 1, 0,
232 MLX5_IB_UPD_XLT_ZAP |
233 MLX5_IB_UPD_XLT_ATOMIC);
234 /*
235 * We are now sure that the device will not access the
236 * memory. We can safely unmap it, and mark it as dirty if
237 * needed.
238 */
239
240 ib_umem_odp_unmap_dma_pages(umem, start, end);
241
242 if (unlikely(!umem->npages && mr->parent &&
243 !umem->odp_data->dying)) {
244 WRITE_ONCE(umem->odp_data->dying, 1);
245 atomic_inc(&mr->parent->num_leaf_free);
246 schedule_work(&umem->odp_data->work);
247 }
248 }
249
mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev * dev)250 void mlx5_ib_internal_fill_odp_caps(struct mlx5_ib_dev *dev)
251 {
252 struct ib_odp_caps *caps = &dev->odp_caps;
253
254 memset(caps, 0, sizeof(*caps));
255
256 if (!MLX5_CAP_GEN(dev->mdev, pg))
257 return;
258
259 caps->general_caps = IB_ODP_SUPPORT;
260
261 if (MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
262 dev->odp_max_size = U64_MAX;
263 else
264 dev->odp_max_size = BIT_ULL(MLX5_MAX_UMR_SHIFT + PAGE_SHIFT);
265
266 if (MLX5_CAP_ODP(dev->mdev, ud_odp_caps.send))
267 caps->per_transport_caps.ud_odp_caps |= IB_ODP_SUPPORT_SEND;
268
269 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.send))
270 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_SEND;
271
272 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.receive))
273 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_RECV;
274
275 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.write))
276 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_WRITE;
277
278 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.read))
279 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_READ;
280
281 if (MLX5_CAP_ODP(dev->mdev, rc_odp_caps.atomic))
282 caps->per_transport_caps.rc_odp_caps |= IB_ODP_SUPPORT_ATOMIC;
283
284 if (MLX5_CAP_GEN(dev->mdev, fixed_buffer_size) &&
285 MLX5_CAP_GEN(dev->mdev, null_mkey) &&
286 MLX5_CAP_GEN(dev->mdev, umr_extended_translation_offset))
287 caps->general_caps |= IB_ODP_SUPPORT_IMPLICIT;
288
289 return;
290 }
291
mlx5_ib_page_fault_resume(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault,int error)292 static void mlx5_ib_page_fault_resume(struct mlx5_ib_dev *dev,
293 struct mlx5_pagefault *pfault,
294 int error)
295 {
296 int wq_num = pfault->event_subtype == MLX5_PFAULT_SUBTYPE_WQE ?
297 pfault->wqe.wq_num : pfault->token;
298 int ret = mlx5_core_page_fault_resume(dev->mdev,
299 pfault->token,
300 wq_num,
301 pfault->type,
302 error);
303 if (ret)
304 mlx5_ib_err(dev, "Failed to resolve the page fault on WQ 0x%x\n",
305 wq_num);
306 }
307
implicit_mr_alloc(struct ib_pd * pd,struct ib_umem * umem,bool ksm,int access_flags)308 static struct mlx5_ib_mr *implicit_mr_alloc(struct ib_pd *pd,
309 struct ib_umem *umem,
310 bool ksm, int access_flags)
311 {
312 struct mlx5_ib_dev *dev = to_mdev(pd->device);
313 struct mlx5_ib_mr *mr;
314 int err;
315
316 mr = mlx5_mr_cache_alloc(dev, ksm ? MLX5_IMR_KSM_CACHE_ENTRY :
317 MLX5_IMR_MTT_CACHE_ENTRY);
318
319 if (IS_ERR(mr))
320 return mr;
321
322 mr->ibmr.pd = pd;
323
324 mr->dev = dev;
325 mr->access_flags = access_flags;
326 mr->mmkey.iova = 0;
327 mr->umem = umem;
328
329 if (ksm) {
330 err = mlx5_ib_update_xlt(mr, 0,
331 mlx5_imr_ksm_entries,
332 MLX5_KSM_PAGE_SHIFT,
333 MLX5_IB_UPD_XLT_INDIRECT |
334 MLX5_IB_UPD_XLT_ZAP |
335 MLX5_IB_UPD_XLT_ENABLE);
336
337 } else {
338 err = mlx5_ib_update_xlt(mr, 0,
339 MLX5_IMR_MTT_ENTRIES,
340 PAGE_SHIFT,
341 MLX5_IB_UPD_XLT_ZAP |
342 MLX5_IB_UPD_XLT_ENABLE |
343 MLX5_IB_UPD_XLT_ATOMIC);
344 }
345
346 if (err)
347 goto fail;
348
349 mr->ibmr.lkey = mr->mmkey.key;
350 mr->ibmr.rkey = mr->mmkey.key;
351
352 mr->live = 1;
353
354 mlx5_ib_dbg(dev, "key %x dev %p mr %p\n",
355 mr->mmkey.key, dev->mdev, mr);
356
357 return mr;
358
359 fail:
360 mlx5_ib_err(dev, "Failed to register MKEY %d\n", err);
361 mlx5_mr_cache_free(dev, mr);
362
363 return ERR_PTR(err);
364 }
365
implicit_mr_get_data(struct mlx5_ib_mr * mr,u64 io_virt,size_t bcnt)366 static struct ib_umem_odp *implicit_mr_get_data(struct mlx5_ib_mr *mr,
367 u64 io_virt, size_t bcnt)
368 {
369 struct ib_ucontext *ctx = mr->ibmr.pd->uobject->context;
370 struct mlx5_ib_dev *dev = to_mdev(mr->ibmr.pd->device);
371 struct ib_umem_odp *odp, *result = NULL;
372 u64 addr = io_virt & MLX5_IMR_MTT_MASK;
373 int nentries = 0, start_idx = 0, ret;
374 struct mlx5_ib_mr *mtt;
375 struct ib_umem *umem;
376
377 mutex_lock(&mr->umem->odp_data->umem_mutex);
378 odp = odp_lookup(ctx, addr, 1, mr);
379
380 mlx5_ib_dbg(dev, "io_virt:%llx bcnt:%zx addr:%llx odp:%p\n",
381 io_virt, bcnt, addr, odp);
382
383 next_mr:
384 if (likely(odp)) {
385 if (nentries)
386 nentries++;
387 } else {
388 umem = ib_alloc_odp_umem(ctx, addr, MLX5_IMR_MTT_SIZE);
389 if (IS_ERR(umem)) {
390 mutex_unlock(&mr->umem->odp_data->umem_mutex);
391 return ERR_CAST(umem);
392 }
393
394 mtt = implicit_mr_alloc(mr->ibmr.pd, umem, 0, mr->access_flags);
395 if (IS_ERR(mtt)) {
396 mutex_unlock(&mr->umem->odp_data->umem_mutex);
397 ib_umem_release(umem);
398 return ERR_CAST(mtt);
399 }
400
401 odp = umem->odp_data;
402 odp->private = mtt;
403 mtt->umem = umem;
404 mtt->mmkey.iova = addr;
405 mtt->parent = mr;
406 INIT_WORK(&odp->work, mr_leaf_free_action);
407
408 if (!nentries)
409 start_idx = addr >> MLX5_IMR_MTT_SHIFT;
410 nentries++;
411 }
412
413 /* Return first odp if region not covered by single one */
414 if (likely(!result))
415 result = odp;
416
417 addr += MLX5_IMR_MTT_SIZE;
418 if (unlikely(addr < io_virt + bcnt)) {
419 odp = odp_next(odp);
420 if (odp && odp->umem->address != addr)
421 odp = NULL;
422 goto next_mr;
423 }
424
425 if (unlikely(nentries)) {
426 ret = mlx5_ib_update_xlt(mr, start_idx, nentries, 0,
427 MLX5_IB_UPD_XLT_INDIRECT |
428 MLX5_IB_UPD_XLT_ATOMIC);
429 if (ret) {
430 mlx5_ib_err(dev, "Failed to update PAS\n");
431 result = ERR_PTR(ret);
432 }
433 }
434
435 mutex_unlock(&mr->umem->odp_data->umem_mutex);
436 return result;
437 }
438
mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd * pd,int access_flags)439 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
440 int access_flags)
441 {
442 struct ib_ucontext *ctx = pd->ibpd.uobject->context;
443 struct mlx5_ib_mr *imr;
444 struct ib_umem *umem;
445
446 umem = ib_umem_get(ctx, 0, 0, IB_ACCESS_ON_DEMAND, 0);
447 if (IS_ERR(umem))
448 return ERR_CAST(umem);
449
450 imr = implicit_mr_alloc(&pd->ibpd, umem, 1, access_flags);
451 if (IS_ERR(imr)) {
452 ib_umem_release(umem);
453 return ERR_CAST(imr);
454 }
455
456 imr->umem = umem;
457 init_waitqueue_head(&imr->q_leaf_free);
458 atomic_set(&imr->num_leaf_free, 0);
459
460 return imr;
461 }
462
mr_leaf_free(struct ib_umem * umem,u64 start,u64 end,void * cookie)463 static int mr_leaf_free(struct ib_umem *umem, u64 start,
464 u64 end, void *cookie)
465 {
466 struct mlx5_ib_mr *mr = umem->odp_data->private, *imr = cookie;
467
468 if (mr->parent != imr)
469 return 0;
470
471 ib_umem_odp_unmap_dma_pages(umem,
472 ib_umem_start(umem),
473 ib_umem_end(umem));
474
475 if (umem->odp_data->dying)
476 return 0;
477
478 WRITE_ONCE(umem->odp_data->dying, 1);
479 atomic_inc(&imr->num_leaf_free);
480 schedule_work(&umem->odp_data->work);
481
482 return 0;
483 }
484
mlx5_ib_free_implicit_mr(struct mlx5_ib_mr * imr)485 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *imr)
486 {
487 struct ib_ucontext *ctx = imr->ibmr.pd->uobject->context;
488
489 down_read(&ctx->umem_rwsem);
490 rbt_ib_umem_for_each_in_range(&ctx->umem_tree, 0, ULLONG_MAX,
491 mr_leaf_free, true, imr);
492 up_read(&ctx->umem_rwsem);
493
494 wait_event(imr->q_leaf_free, !atomic_read(&imr->num_leaf_free));
495 }
496
pagefault_mr(struct mlx5_ib_dev * dev,struct mlx5_ib_mr * mr,u64 io_virt,size_t bcnt,u32 * bytes_mapped)497 static int pagefault_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr,
498 u64 io_virt, size_t bcnt, u32 *bytes_mapped)
499 {
500 u64 access_mask;
501 int npages = 0, page_shift, np;
502 u64 start_idx, page_mask;
503 struct ib_umem_odp *odp;
504 int current_seq;
505 size_t size;
506 int ret;
507
508 if (!mr->umem->odp_data->page_list) {
509 odp = implicit_mr_get_data(mr, io_virt, bcnt);
510
511 if (IS_ERR(odp))
512 return PTR_ERR(odp);
513 mr = odp->private;
514
515 } else {
516 odp = mr->umem->odp_data;
517 }
518
519 next_mr:
520 size = min_t(size_t, bcnt, ib_umem_end(odp->umem) - io_virt);
521
522 page_shift = mr->umem->page_shift;
523 page_mask = ~(BIT(page_shift) - 1);
524 start_idx = (io_virt - (mr->mmkey.iova & page_mask)) >> page_shift;
525 access_mask = ODP_READ_ALLOWED_BIT;
526
527 if (mr->umem->writable)
528 access_mask |= ODP_WRITE_ALLOWED_BIT;
529
530 current_seq = READ_ONCE(odp->notifiers_seq);
531 /*
532 * Ensure the sequence number is valid for some time before we call
533 * gup.
534 */
535 smp_rmb();
536
537 ret = ib_umem_odp_map_dma_pages(mr->umem, io_virt, size,
538 access_mask, current_seq);
539
540 if (ret < 0)
541 goto out;
542
543 np = ret;
544
545 mutex_lock(&odp->umem_mutex);
546 if (!ib_umem_mmu_notifier_retry(mr->umem, current_seq)) {
547 /*
548 * No need to check whether the MTTs really belong to
549 * this MR, since ib_umem_odp_map_dma_pages already
550 * checks this.
551 */
552 ret = mlx5_ib_update_xlt(mr, start_idx, np,
553 page_shift, MLX5_IB_UPD_XLT_ATOMIC);
554 } else {
555 ret = -EAGAIN;
556 }
557 mutex_unlock(&odp->umem_mutex);
558
559 if (ret < 0) {
560 if (ret != -EAGAIN)
561 mlx5_ib_err(dev, "Failed to update mkey page tables\n");
562 goto out;
563 }
564
565 if (bytes_mapped) {
566 u32 new_mappings = (np << page_shift) -
567 (io_virt - round_down(io_virt, 1 << page_shift));
568 *bytes_mapped += min_t(u32, new_mappings, size);
569 }
570
571 npages += np << (page_shift - PAGE_SHIFT);
572 bcnt -= size;
573
574 if (unlikely(bcnt)) {
575 struct ib_umem_odp *next;
576
577 io_virt += size;
578 next = odp_next(odp);
579 if (unlikely(!next || next->umem->address != io_virt)) {
580 mlx5_ib_dbg(dev, "next implicit leaf removed at 0x%llx. got %p\n",
581 io_virt, next);
582 return -EAGAIN;
583 }
584 odp = next;
585 mr = odp->private;
586 goto next_mr;
587 }
588
589 return npages;
590
591 out:
592 if (ret == -EAGAIN) {
593 if (mr->parent || !odp->dying) {
594 unsigned long timeout =
595 msecs_to_jiffies(MMU_NOTIFIER_TIMEOUT);
596
597 if (!wait_for_completion_timeout(
598 &odp->notifier_completion,
599 timeout)) {
600 mlx5_ib_warn(dev, "timeout waiting for mmu notifier. seq %d against %d\n",
601 current_seq, odp->notifiers_seq);
602 }
603 } else {
604 /* The MR is being killed, kill the QP as well. */
605 ret = -EFAULT;
606 }
607 }
608
609 return ret;
610 }
611
612 struct pf_frame {
613 struct pf_frame *next;
614 u32 key;
615 u64 io_virt;
616 size_t bcnt;
617 int depth;
618 };
619
620 /*
621 * Handle a single data segment in a page-fault WQE or RDMA region.
622 *
623 * Returns number of OS pages retrieved on success. The caller may continue to
624 * the next data segment.
625 * Can return the following error codes:
626 * -EAGAIN to designate a temporary error. The caller will abort handling the
627 * page fault and resolve it.
628 * -EFAULT when there's an error mapping the requested pages. The caller will
629 * abort the page fault handling.
630 */
pagefault_single_data_segment(struct mlx5_ib_dev * dev,u32 key,u64 io_virt,size_t bcnt,u32 * bytes_committed,u32 * bytes_mapped)631 static int pagefault_single_data_segment(struct mlx5_ib_dev *dev,
632 u32 key, u64 io_virt, size_t bcnt,
633 u32 *bytes_committed,
634 u32 *bytes_mapped)
635 {
636 int npages = 0, srcu_key, ret, i, outlen, cur_outlen = 0, depth = 0;
637 struct pf_frame *head = NULL, *frame;
638 struct mlx5_core_mkey *mmkey;
639 struct mlx5_ib_mw *mw;
640 struct mlx5_ib_mr *mr;
641 struct mlx5_klm *pklm;
642 u32 *out = NULL;
643 size_t offset;
644
645 srcu_key = srcu_read_lock(&dev->mr_srcu);
646
647 io_virt += *bytes_committed;
648 bcnt -= *bytes_committed;
649
650 next_mr:
651 mmkey = __mlx5_mr_lookup(dev->mdev, mlx5_base_mkey(key));
652 if (!mmkey || mmkey->key != key) {
653 mlx5_ib_dbg(dev, "failed to find mkey %x\n", key);
654 ret = -EFAULT;
655 goto srcu_unlock;
656 }
657
658 switch (mmkey->type) {
659 case MLX5_MKEY_MR:
660 mr = container_of(mmkey, struct mlx5_ib_mr, mmkey);
661 if (!mr->live || !mr->ibmr.pd) {
662 mlx5_ib_dbg(dev, "got dead MR\n");
663 ret = -EFAULT;
664 goto srcu_unlock;
665 }
666
667 ret = pagefault_mr(dev, mr, io_virt, bcnt, bytes_mapped);
668 if (ret < 0)
669 goto srcu_unlock;
670
671 npages += ret;
672 ret = 0;
673 break;
674
675 case MLX5_MKEY_MW:
676 mw = container_of(mmkey, struct mlx5_ib_mw, mmkey);
677
678 if (depth >= MLX5_CAP_GEN(dev->mdev, max_indirection)) {
679 mlx5_ib_dbg(dev, "indirection level exceeded\n");
680 ret = -EFAULT;
681 goto srcu_unlock;
682 }
683
684 outlen = MLX5_ST_SZ_BYTES(query_mkey_out) +
685 sizeof(*pklm) * (mw->ndescs - 2);
686
687 if (outlen > cur_outlen) {
688 kfree(out);
689 out = kzalloc(outlen, GFP_KERNEL);
690 if (!out) {
691 ret = -ENOMEM;
692 goto srcu_unlock;
693 }
694 cur_outlen = outlen;
695 }
696
697 pklm = (struct mlx5_klm *)MLX5_ADDR_OF(query_mkey_out, out,
698 bsf0_klm0_pas_mtt0_1);
699
700 ret = mlx5_core_query_mkey(dev->mdev, &mw->mmkey, out, outlen);
701 if (ret)
702 goto srcu_unlock;
703
704 offset = io_virt - MLX5_GET64(query_mkey_out, out,
705 memory_key_mkey_entry.start_addr);
706
707 for (i = 0; bcnt && i < mw->ndescs; i++, pklm++) {
708 if (offset >= be32_to_cpu(pklm->bcount)) {
709 offset -= be32_to_cpu(pklm->bcount);
710 continue;
711 }
712
713 frame = kzalloc(sizeof(*frame), GFP_KERNEL);
714 if (!frame) {
715 ret = -ENOMEM;
716 goto srcu_unlock;
717 }
718
719 frame->key = be32_to_cpu(pklm->key);
720 frame->io_virt = be64_to_cpu(pklm->va) + offset;
721 frame->bcnt = min_t(size_t, bcnt,
722 be32_to_cpu(pklm->bcount) - offset);
723 frame->depth = depth + 1;
724 frame->next = head;
725 head = frame;
726
727 bcnt -= frame->bcnt;
728 offset = 0;
729 }
730 break;
731
732 default:
733 mlx5_ib_dbg(dev, "wrong mkey type %d\n", mmkey->type);
734 ret = -EFAULT;
735 goto srcu_unlock;
736 }
737
738 if (head) {
739 frame = head;
740 head = frame->next;
741
742 key = frame->key;
743 io_virt = frame->io_virt;
744 bcnt = frame->bcnt;
745 depth = frame->depth;
746 kfree(frame);
747
748 goto next_mr;
749 }
750
751 srcu_unlock:
752 while (head) {
753 frame = head;
754 head = frame->next;
755 kfree(frame);
756 }
757 kfree(out);
758
759 srcu_read_unlock(&dev->mr_srcu, srcu_key);
760 *bytes_committed = 0;
761 return ret ? ret : npages;
762 }
763
764 /**
765 * Parse a series of data segments for page fault handling.
766 *
767 * @qp the QP on which the fault occurred.
768 * @pfault contains page fault information.
769 * @wqe points at the first data segment in the WQE.
770 * @wqe_end points after the end of the WQE.
771 * @bytes_mapped receives the number of bytes that the function was able to
772 * map. This allows the caller to decide intelligently whether
773 * enough memory was mapped to resolve the page fault
774 * successfully (e.g. enough for the next MTU, or the entire
775 * WQE).
776 * @total_wqe_bytes receives the total data size of this WQE in bytes (minus
777 * the committed bytes).
778 *
779 * Returns the number of pages loaded if positive, zero for an empty WQE, or a
780 * negative error code.
781 */
pagefault_data_segments(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault,struct mlx5_ib_qp * qp,void * wqe,void * wqe_end,u32 * bytes_mapped,u32 * total_wqe_bytes,int receive_queue)782 static int pagefault_data_segments(struct mlx5_ib_dev *dev,
783 struct mlx5_pagefault *pfault,
784 struct mlx5_ib_qp *qp, void *wqe,
785 void *wqe_end, u32 *bytes_mapped,
786 u32 *total_wqe_bytes, int receive_queue)
787 {
788 int ret = 0, npages = 0;
789 u64 io_virt;
790 u32 key;
791 u32 byte_count;
792 size_t bcnt;
793 int inline_segment;
794
795 /* Skip SRQ next-WQE segment. */
796 if (receive_queue && qp->ibqp.srq)
797 wqe += sizeof(struct mlx5_wqe_srq_next_seg);
798
799 if (bytes_mapped)
800 *bytes_mapped = 0;
801 if (total_wqe_bytes)
802 *total_wqe_bytes = 0;
803
804 while (wqe < wqe_end) {
805 struct mlx5_wqe_data_seg *dseg = wqe;
806
807 io_virt = be64_to_cpu(dseg->addr);
808 key = be32_to_cpu(dseg->lkey);
809 byte_count = be32_to_cpu(dseg->byte_count);
810 inline_segment = !!(byte_count & MLX5_INLINE_SEG);
811 bcnt = byte_count & ~MLX5_INLINE_SEG;
812
813 if (inline_segment) {
814 bcnt = bcnt & MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK;
815 wqe += ALIGN(sizeof(struct mlx5_wqe_inline_seg) + bcnt,
816 16);
817 } else {
818 wqe += sizeof(*dseg);
819 }
820
821 /* receive WQE end of sg list. */
822 if (receive_queue && bcnt == 0 && key == MLX5_INVALID_LKEY &&
823 io_virt == 0)
824 break;
825
826 if (!inline_segment && total_wqe_bytes) {
827 *total_wqe_bytes += bcnt - min_t(size_t, bcnt,
828 pfault->bytes_committed);
829 }
830
831 /* A zero length data segment designates a length of 2GB. */
832 if (bcnt == 0)
833 bcnt = 1U << 31;
834
835 if (inline_segment || bcnt <= pfault->bytes_committed) {
836 pfault->bytes_committed -=
837 min_t(size_t, bcnt,
838 pfault->bytes_committed);
839 continue;
840 }
841
842 ret = pagefault_single_data_segment(dev, key, io_virt, bcnt,
843 &pfault->bytes_committed,
844 bytes_mapped);
845 if (ret < 0)
846 break;
847 npages += ret;
848 }
849
850 return ret < 0 ? ret : npages;
851 }
852
853 static const u32 mlx5_ib_odp_opcode_cap[] = {
854 [MLX5_OPCODE_SEND] = IB_ODP_SUPPORT_SEND,
855 [MLX5_OPCODE_SEND_IMM] = IB_ODP_SUPPORT_SEND,
856 [MLX5_OPCODE_SEND_INVAL] = IB_ODP_SUPPORT_SEND,
857 [MLX5_OPCODE_RDMA_WRITE] = IB_ODP_SUPPORT_WRITE,
858 [MLX5_OPCODE_RDMA_WRITE_IMM] = IB_ODP_SUPPORT_WRITE,
859 [MLX5_OPCODE_RDMA_READ] = IB_ODP_SUPPORT_READ,
860 [MLX5_OPCODE_ATOMIC_CS] = IB_ODP_SUPPORT_ATOMIC,
861 [MLX5_OPCODE_ATOMIC_FA] = IB_ODP_SUPPORT_ATOMIC,
862 };
863
864 /*
865 * Parse initiator WQE. Advances the wqe pointer to point at the
866 * scatter-gather list, and set wqe_end to the end of the WQE.
867 */
mlx5_ib_mr_initiator_pfault_handler(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault,struct mlx5_ib_qp * qp,void ** wqe,void ** wqe_end,int wqe_length)868 static int mlx5_ib_mr_initiator_pfault_handler(
869 struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
870 struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
871 {
872 struct mlx5_wqe_ctrl_seg *ctrl = *wqe;
873 u16 wqe_index = pfault->wqe.wqe_index;
874 u32 transport_caps;
875 struct mlx5_base_av *av;
876 unsigned ds, opcode;
877 #if defined(DEBUG)
878 u32 ctrl_wqe_index, ctrl_qpn;
879 #endif
880 u32 qpn = qp->trans_qp.base.mqp.qpn;
881
882 ds = be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_DS_MASK;
883 if (ds * MLX5_WQE_DS_UNITS > wqe_length) {
884 mlx5_ib_err(dev, "Unable to read the complete WQE. ds = 0x%x, ret = 0x%x\n",
885 ds, wqe_length);
886 return -EFAULT;
887 }
888
889 if (ds == 0) {
890 mlx5_ib_err(dev, "Got WQE with zero DS. wqe_index=%x, qpn=%x\n",
891 wqe_index, qpn);
892 return -EFAULT;
893 }
894
895 #if defined(DEBUG)
896 ctrl_wqe_index = (be32_to_cpu(ctrl->opmod_idx_opcode) &
897 MLX5_WQE_CTRL_WQE_INDEX_MASK) >>
898 MLX5_WQE_CTRL_WQE_INDEX_SHIFT;
899 if (wqe_index != ctrl_wqe_index) {
900 mlx5_ib_err(dev, "Got WQE with invalid wqe_index. wqe_index=0x%x, qpn=0x%x ctrl->wqe_index=0x%x\n",
901 wqe_index, qpn,
902 ctrl_wqe_index);
903 return -EFAULT;
904 }
905
906 ctrl_qpn = (be32_to_cpu(ctrl->qpn_ds) & MLX5_WQE_CTRL_QPN_MASK) >>
907 MLX5_WQE_CTRL_QPN_SHIFT;
908 if (qpn != ctrl_qpn) {
909 mlx5_ib_err(dev, "Got WQE with incorrect QP number. wqe_index=0x%x, qpn=0x%x ctrl->qpn=0x%x\n",
910 wqe_index, qpn,
911 ctrl_qpn);
912 return -EFAULT;
913 }
914 #endif /* DEBUG */
915
916 *wqe_end = *wqe + ds * MLX5_WQE_DS_UNITS;
917 *wqe += sizeof(*ctrl);
918
919 opcode = be32_to_cpu(ctrl->opmod_idx_opcode) &
920 MLX5_WQE_CTRL_OPCODE_MASK;
921
922 switch (qp->ibqp.qp_type) {
923 case IB_QPT_RC:
924 transport_caps = dev->odp_caps.per_transport_caps.rc_odp_caps;
925 break;
926 case IB_QPT_UD:
927 transport_caps = dev->odp_caps.per_transport_caps.ud_odp_caps;
928 break;
929 default:
930 mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport 0x%x\n",
931 qp->ibqp.qp_type);
932 return -EFAULT;
933 }
934
935 if (unlikely(opcode >= ARRAY_SIZE(mlx5_ib_odp_opcode_cap) ||
936 !(transport_caps & mlx5_ib_odp_opcode_cap[opcode]))) {
937 mlx5_ib_err(dev, "ODP fault on QP of an unsupported opcode 0x%x\n",
938 opcode);
939 return -EFAULT;
940 }
941
942 if (qp->ibqp.qp_type != IB_QPT_RC) {
943 av = *wqe;
944 if (av->dqp_dct & cpu_to_be32(MLX5_EXTENDED_UD_AV))
945 *wqe += sizeof(struct mlx5_av);
946 else
947 *wqe += sizeof(struct mlx5_base_av);
948 }
949
950 switch (opcode) {
951 case MLX5_OPCODE_RDMA_WRITE:
952 case MLX5_OPCODE_RDMA_WRITE_IMM:
953 case MLX5_OPCODE_RDMA_READ:
954 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
955 break;
956 case MLX5_OPCODE_ATOMIC_CS:
957 case MLX5_OPCODE_ATOMIC_FA:
958 *wqe += sizeof(struct mlx5_wqe_raddr_seg);
959 *wqe += sizeof(struct mlx5_wqe_atomic_seg);
960 break;
961 }
962
963 return 0;
964 }
965
966 /*
967 * Parse responder WQE. Advances the wqe pointer to point at the
968 * scatter-gather list, and set wqe_end to the end of the WQE.
969 */
mlx5_ib_mr_responder_pfault_handler(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault,struct mlx5_ib_qp * qp,void ** wqe,void ** wqe_end,int wqe_length)970 static int mlx5_ib_mr_responder_pfault_handler(
971 struct mlx5_ib_dev *dev, struct mlx5_pagefault *pfault,
972 struct mlx5_ib_qp *qp, void **wqe, void **wqe_end, int wqe_length)
973 {
974 struct mlx5_ib_wq *wq = &qp->rq;
975 int wqe_size = 1 << wq->wqe_shift;
976
977 if (qp->ibqp.srq) {
978 mlx5_ib_err(dev, "ODP fault on SRQ is not supported\n");
979 return -EFAULT;
980 }
981
982 if (qp->wq_sig) {
983 mlx5_ib_err(dev, "ODP fault with WQE signatures is not supported\n");
984 return -EFAULT;
985 }
986
987 if (wqe_size > wqe_length) {
988 mlx5_ib_err(dev, "Couldn't read all of the receive WQE's content\n");
989 return -EFAULT;
990 }
991
992 switch (qp->ibqp.qp_type) {
993 case IB_QPT_RC:
994 if (!(dev->odp_caps.per_transport_caps.rc_odp_caps &
995 IB_ODP_SUPPORT_RECV))
996 goto invalid_transport_or_opcode;
997 break;
998 default:
999 invalid_transport_or_opcode:
1000 mlx5_ib_err(dev, "ODP fault on QP of an unsupported transport. transport: 0x%x\n",
1001 qp->ibqp.qp_type);
1002 return -EFAULT;
1003 }
1004
1005 *wqe_end = *wqe + wqe_size;
1006
1007 return 0;
1008 }
1009
mlx5_ib_odp_find_qp(struct mlx5_ib_dev * dev,u32 wq_num)1010 static struct mlx5_ib_qp *mlx5_ib_odp_find_qp(struct mlx5_ib_dev *dev,
1011 u32 wq_num)
1012 {
1013 struct mlx5_core_qp *mqp = __mlx5_qp_lookup(dev->mdev, wq_num);
1014
1015 if (!mqp) {
1016 mlx5_ib_err(dev, "QPN 0x%6x not found\n", wq_num);
1017 return NULL;
1018 }
1019
1020 return to_mibqp(mqp);
1021 }
1022
mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault)1023 static void mlx5_ib_mr_wqe_pfault_handler(struct mlx5_ib_dev *dev,
1024 struct mlx5_pagefault *pfault)
1025 {
1026 int ret;
1027 void *wqe, *wqe_end;
1028 u32 bytes_mapped, total_wqe_bytes;
1029 char *buffer = NULL;
1030 int resume_with_error = 1;
1031 u16 wqe_index = pfault->wqe.wqe_index;
1032 int requestor = pfault->type & MLX5_PFAULT_REQUESTOR;
1033 struct mlx5_ib_qp *qp;
1034
1035 buffer = (char *)__get_free_page(GFP_KERNEL);
1036 if (!buffer) {
1037 mlx5_ib_err(dev, "Error allocating memory for IO page fault handling.\n");
1038 goto resolve_page_fault;
1039 }
1040
1041 qp = mlx5_ib_odp_find_qp(dev, pfault->wqe.wq_num);
1042 if (!qp)
1043 goto resolve_page_fault;
1044
1045 ret = mlx5_ib_read_user_wqe(qp, requestor, wqe_index, buffer,
1046 PAGE_SIZE, &qp->trans_qp.base);
1047 if (ret < 0) {
1048 mlx5_ib_err(dev, "Failed reading a WQE following page fault, error=%d, wqe_index=%x, qpn=%x\n",
1049 ret, wqe_index, pfault->token);
1050 goto resolve_page_fault;
1051 }
1052
1053 wqe = buffer;
1054 if (requestor)
1055 ret = mlx5_ib_mr_initiator_pfault_handler(dev, pfault, qp, &wqe,
1056 &wqe_end, ret);
1057 else
1058 ret = mlx5_ib_mr_responder_pfault_handler(dev, pfault, qp, &wqe,
1059 &wqe_end, ret);
1060 if (ret < 0)
1061 goto resolve_page_fault;
1062
1063 if (wqe >= wqe_end) {
1064 mlx5_ib_err(dev, "ODP fault on invalid WQE.\n");
1065 goto resolve_page_fault;
1066 }
1067
1068 ret = pagefault_data_segments(dev, pfault, qp, wqe, wqe_end,
1069 &bytes_mapped, &total_wqe_bytes,
1070 !requestor);
1071 if (ret == -EAGAIN) {
1072 resume_with_error = 0;
1073 goto resolve_page_fault;
1074 } else if (ret < 0 || total_wqe_bytes > bytes_mapped) {
1075 goto resolve_page_fault;
1076 }
1077
1078 resume_with_error = 0;
1079 resolve_page_fault:
1080 mlx5_ib_page_fault_resume(dev, pfault, resume_with_error);
1081 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x resume_with_error=%d, type: 0x%x\n",
1082 pfault->wqe.wq_num, resume_with_error,
1083 pfault->type);
1084 free_page((unsigned long)buffer);
1085 }
1086
pages_in_range(u64 address,u32 length)1087 static int pages_in_range(u64 address, u32 length)
1088 {
1089 return (ALIGN(address + length, PAGE_SIZE) -
1090 (address & PAGE_MASK)) >> PAGE_SHIFT;
1091 }
1092
mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev * dev,struct mlx5_pagefault * pfault)1093 static void mlx5_ib_mr_rdma_pfault_handler(struct mlx5_ib_dev *dev,
1094 struct mlx5_pagefault *pfault)
1095 {
1096 u64 address;
1097 u32 length;
1098 u32 prefetch_len = pfault->bytes_committed;
1099 int prefetch_activated = 0;
1100 u32 rkey = pfault->rdma.r_key;
1101 int ret;
1102
1103 /* The RDMA responder handler handles the page fault in two parts.
1104 * First it brings the necessary pages for the current packet
1105 * (and uses the pfault context), and then (after resuming the QP)
1106 * prefetches more pages. The second operation cannot use the pfault
1107 * context and therefore uses the dummy_pfault context allocated on
1108 * the stack */
1109 pfault->rdma.rdma_va += pfault->bytes_committed;
1110 pfault->rdma.rdma_op_len -= min(pfault->bytes_committed,
1111 pfault->rdma.rdma_op_len);
1112 pfault->bytes_committed = 0;
1113
1114 address = pfault->rdma.rdma_va;
1115 length = pfault->rdma.rdma_op_len;
1116
1117 /* For some operations, the hardware cannot tell the exact message
1118 * length, and in those cases it reports zero. Use prefetch
1119 * logic. */
1120 if (length == 0) {
1121 prefetch_activated = 1;
1122 length = pfault->rdma.packet_size;
1123 prefetch_len = min(MAX_PREFETCH_LEN, prefetch_len);
1124 }
1125
1126 ret = pagefault_single_data_segment(dev, rkey, address, length,
1127 &pfault->bytes_committed, NULL);
1128 if (ret == -EAGAIN) {
1129 /* We're racing with an invalidation, don't prefetch */
1130 prefetch_activated = 0;
1131 } else if (ret < 0 || pages_in_range(address, length) > ret) {
1132 mlx5_ib_page_fault_resume(dev, pfault, 1);
1133 if (ret != -ENOENT)
1134 mlx5_ib_dbg(dev, "PAGE FAULT error %d. QP 0x%x, type: 0x%x\n",
1135 ret, pfault->token, pfault->type);
1136 return;
1137 }
1138
1139 mlx5_ib_page_fault_resume(dev, pfault, 0);
1140 mlx5_ib_dbg(dev, "PAGE FAULT completed. QP 0x%x, type: 0x%x, prefetch_activated: %d\n",
1141 pfault->token, pfault->type,
1142 prefetch_activated);
1143
1144 /* At this point, there might be a new pagefault already arriving in
1145 * the eq, switch to the dummy pagefault for the rest of the
1146 * processing. We're still OK with the objects being alive as the
1147 * work-queue is being fenced. */
1148
1149 if (prefetch_activated) {
1150 u32 bytes_committed = 0;
1151
1152 ret = pagefault_single_data_segment(dev, rkey, address,
1153 prefetch_len,
1154 &bytes_committed, NULL);
1155 if (ret < 0 && ret != -EAGAIN) {
1156 mlx5_ib_dbg(dev, "Prefetch failed. ret: %d, QP 0x%x, address: 0x%.16llx, length = 0x%.16x\n",
1157 ret, pfault->token, address, prefetch_len);
1158 }
1159 }
1160 }
1161
mlx5_ib_pfault(struct mlx5_core_dev * mdev,void * context,struct mlx5_pagefault * pfault)1162 void mlx5_ib_pfault(struct mlx5_core_dev *mdev, void *context,
1163 struct mlx5_pagefault *pfault)
1164 {
1165 struct mlx5_ib_dev *dev = context;
1166 u8 event_subtype = pfault->event_subtype;
1167
1168 switch (event_subtype) {
1169 case MLX5_PFAULT_SUBTYPE_WQE:
1170 mlx5_ib_mr_wqe_pfault_handler(dev, pfault);
1171 break;
1172 case MLX5_PFAULT_SUBTYPE_RDMA:
1173 mlx5_ib_mr_rdma_pfault_handler(dev, pfault);
1174 break;
1175 default:
1176 mlx5_ib_err(dev, "Invalid page fault event subtype: 0x%x\n",
1177 event_subtype);
1178 mlx5_ib_page_fault_resume(dev, pfault, 1);
1179 }
1180 }
1181
mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent * ent)1182 void mlx5_odp_init_mr_cache_entry(struct mlx5_cache_ent *ent)
1183 {
1184 if (!(ent->dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT))
1185 return;
1186
1187 switch (ent->order - 2) {
1188 case MLX5_IMR_MTT_CACHE_ENTRY:
1189 ent->page = PAGE_SHIFT;
1190 ent->xlt = MLX5_IMR_MTT_ENTRIES *
1191 sizeof(struct mlx5_mtt) /
1192 MLX5_IB_UMR_OCTOWORD;
1193 ent->access_mode = MLX5_MKC_ACCESS_MODE_MTT;
1194 ent->limit = 0;
1195 break;
1196
1197 case MLX5_IMR_KSM_CACHE_ENTRY:
1198 ent->page = MLX5_KSM_PAGE_SHIFT;
1199 ent->xlt = mlx5_imr_ksm_entries *
1200 sizeof(struct mlx5_klm) /
1201 MLX5_IB_UMR_OCTOWORD;
1202 ent->access_mode = MLX5_MKC_ACCESS_MODE_KSM;
1203 ent->limit = 0;
1204 break;
1205 }
1206 }
1207
mlx5_ib_odp_init_one(struct mlx5_ib_dev * dev)1208 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *dev)
1209 {
1210 int ret;
1211
1212 if (dev->odp_caps.general_caps & IB_ODP_SUPPORT_IMPLICIT) {
1213 ret = mlx5_cmd_null_mkey(dev->mdev, &dev->null_mkey);
1214 if (ret) {
1215 mlx5_ib_err(dev, "Error getting null_mkey %d\n", ret);
1216 return ret;
1217 }
1218 }
1219
1220 return 0;
1221 }
1222
mlx5_ib_odp_init(void)1223 int mlx5_ib_odp_init(void)
1224 {
1225 mlx5_imr_ksm_entries = BIT_ULL(get_order(TASK_SIZE) -
1226 MLX5_IMR_MTT_BITS);
1227
1228 return 0;
1229 }
1230
1231