1 /*
2 * Copyright (c) 2012 - 2018 Intel Corporation. All rights reserved.
3 * Copyright (c) 2006 - 2012 QLogic Corporation. All rights reserved.
4 * Copyright (c) 2005, 2006 PathScale, Inc. All rights reserved.
5 *
6 * This software is available to you under a choice of one of two
7 * licenses. You may choose to be licensed under the terms of the GNU
8 * General Public License (GPL) Version 2, available from the file
9 * COPYING in the main directory of this source tree, or the
10 * OpenIB.org BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or
13 * without modification, are permitted provided that the following
14 * conditions are met:
15 *
16 * - Redistributions of source code must retain the above
17 * copyright notice, this list of conditions and the following
18 * disclaimer.
19 *
20 * - Redistributions in binary form must reproduce the above
21 * copyright notice, this list of conditions and the following
22 * disclaimer in the documentation and/or other materials
23 * provided with the distribution.
24 *
25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32 * SOFTWARE.
33 */
34
35 #include <rdma/ib_mad.h>
36 #include <rdma/ib_user_verbs.h>
37 #include <linux/io.h>
38 #include <linux/module.h>
39 #include <linux/utsname.h>
40 #include <linux/rculist.h>
41 #include <linux/mm.h>
42 #include <linux/random.h>
43 #include <linux/vmalloc.h>
44 #include <rdma/rdma_vt.h>
45
46 #include "qib.h"
47 #include "qib_common.h"
48
49 static unsigned int ib_qib_qp_table_size = 256;
50 module_param_named(qp_table_size, ib_qib_qp_table_size, uint, S_IRUGO);
51 MODULE_PARM_DESC(qp_table_size, "QP table size");
52
53 static unsigned int qib_lkey_table_size = 16;
54 module_param_named(lkey_table_size, qib_lkey_table_size, uint,
55 S_IRUGO);
56 MODULE_PARM_DESC(lkey_table_size,
57 "LKEY table size in bits (2^n, 1 <= n <= 23)");
58
59 static unsigned int ib_qib_max_pds = 0xFFFF;
60 module_param_named(max_pds, ib_qib_max_pds, uint, S_IRUGO);
61 MODULE_PARM_DESC(max_pds,
62 "Maximum number of protection domains to support");
63
64 static unsigned int ib_qib_max_ahs = 0xFFFF;
65 module_param_named(max_ahs, ib_qib_max_ahs, uint, S_IRUGO);
66 MODULE_PARM_DESC(max_ahs, "Maximum number of address handles to support");
67
68 unsigned int ib_qib_max_cqes = 0x2FFFF;
69 module_param_named(max_cqes, ib_qib_max_cqes, uint, S_IRUGO);
70 MODULE_PARM_DESC(max_cqes,
71 "Maximum number of completion queue entries to support");
72
73 unsigned int ib_qib_max_cqs = 0x1FFFF;
74 module_param_named(max_cqs, ib_qib_max_cqs, uint, S_IRUGO);
75 MODULE_PARM_DESC(max_cqs, "Maximum number of completion queues to support");
76
77 unsigned int ib_qib_max_qp_wrs = 0x3FFF;
78 module_param_named(max_qp_wrs, ib_qib_max_qp_wrs, uint, S_IRUGO);
79 MODULE_PARM_DESC(max_qp_wrs, "Maximum number of QP WRs to support");
80
81 unsigned int ib_qib_max_qps = 16384;
82 module_param_named(max_qps, ib_qib_max_qps, uint, S_IRUGO);
83 MODULE_PARM_DESC(max_qps, "Maximum number of QPs to support");
84
85 unsigned int ib_qib_max_sges = 0x60;
86 module_param_named(max_sges, ib_qib_max_sges, uint, S_IRUGO);
87 MODULE_PARM_DESC(max_sges, "Maximum number of SGEs to support");
88
89 unsigned int ib_qib_max_mcast_grps = 16384;
90 module_param_named(max_mcast_grps, ib_qib_max_mcast_grps, uint, S_IRUGO);
91 MODULE_PARM_DESC(max_mcast_grps,
92 "Maximum number of multicast groups to support");
93
94 unsigned int ib_qib_max_mcast_qp_attached = 16;
95 module_param_named(max_mcast_qp_attached, ib_qib_max_mcast_qp_attached,
96 uint, S_IRUGO);
97 MODULE_PARM_DESC(max_mcast_qp_attached,
98 "Maximum number of attached QPs to support");
99
100 unsigned int ib_qib_max_srqs = 1024;
101 module_param_named(max_srqs, ib_qib_max_srqs, uint, S_IRUGO);
102 MODULE_PARM_DESC(max_srqs, "Maximum number of SRQs to support");
103
104 unsigned int ib_qib_max_srq_sges = 128;
105 module_param_named(max_srq_sges, ib_qib_max_srq_sges, uint, S_IRUGO);
106 MODULE_PARM_DESC(max_srq_sges, "Maximum number of SRQ SGEs to support");
107
108 unsigned int ib_qib_max_srq_wrs = 0x1FFFF;
109 module_param_named(max_srq_wrs, ib_qib_max_srq_wrs, uint, S_IRUGO);
110 MODULE_PARM_DESC(max_srq_wrs, "Maximum number of SRQ WRs support");
111
112 static unsigned int ib_qib_disable_sma;
113 module_param_named(disable_sma, ib_qib_disable_sma, uint, S_IWUSR | S_IRUGO);
114 MODULE_PARM_DESC(disable_sma, "Disable the SMA");
115
116 /*
117 * Translate ib_wr_opcode into ib_wc_opcode.
118 */
119 const enum ib_wc_opcode ib_qib_wc_opcode[] = {
120 [IB_WR_RDMA_WRITE] = IB_WC_RDMA_WRITE,
121 [IB_WR_RDMA_WRITE_WITH_IMM] = IB_WC_RDMA_WRITE,
122 [IB_WR_SEND] = IB_WC_SEND,
123 [IB_WR_SEND_WITH_IMM] = IB_WC_SEND,
124 [IB_WR_RDMA_READ] = IB_WC_RDMA_READ,
125 [IB_WR_ATOMIC_CMP_AND_SWP] = IB_WC_COMP_SWAP,
126 [IB_WR_ATOMIC_FETCH_AND_ADD] = IB_WC_FETCH_ADD
127 };
128
129 /*
130 * System image GUID.
131 */
132 __be64 ib_qib_sys_image_guid;
133
134 /**
135 * qib_copy_sge - copy data to SGE memory
136 * @ss: the SGE state
137 * @data: the data to copy
138 * @length: the length of the data
139 */
qib_copy_sge(struct rvt_sge_state * ss,void * data,u32 length,int release)140 void qib_copy_sge(struct rvt_sge_state *ss, void *data, u32 length, int release)
141 {
142 struct rvt_sge *sge = &ss->sge;
143
144 while (length) {
145 u32 len = rvt_get_sge_length(sge, length);
146
147 WARN_ON_ONCE(len == 0);
148 memcpy(sge->vaddr, data, len);
149 rvt_update_sge(ss, len, release);
150 data += len;
151 length -= len;
152 }
153 }
154
155 /*
156 * Count the number of DMA descriptors needed to send length bytes of data.
157 * Don't modify the qib_sge_state to get the count.
158 * Return zero if any of the segments is not aligned.
159 */
qib_count_sge(struct rvt_sge_state * ss,u32 length)160 static u32 qib_count_sge(struct rvt_sge_state *ss, u32 length)
161 {
162 struct rvt_sge *sg_list = ss->sg_list;
163 struct rvt_sge sge = ss->sge;
164 u8 num_sge = ss->num_sge;
165 u32 ndesc = 1; /* count the header */
166
167 while (length) {
168 u32 len = sge.length;
169
170 if (len > length)
171 len = length;
172 if (len > sge.sge_length)
173 len = sge.sge_length;
174 BUG_ON(len == 0);
175 if (((long) sge.vaddr & (sizeof(u32) - 1)) ||
176 (len != length && (len & (sizeof(u32) - 1)))) {
177 ndesc = 0;
178 break;
179 }
180 ndesc++;
181 sge.vaddr += len;
182 sge.length -= len;
183 sge.sge_length -= len;
184 if (sge.sge_length == 0) {
185 if (--num_sge)
186 sge = *sg_list++;
187 } else if (sge.length == 0 && sge.mr->lkey) {
188 if (++sge.n >= RVT_SEGSZ) {
189 if (++sge.m >= sge.mr->mapsz)
190 break;
191 sge.n = 0;
192 }
193 sge.vaddr =
194 sge.mr->map[sge.m]->segs[sge.n].vaddr;
195 sge.length =
196 sge.mr->map[sge.m]->segs[sge.n].length;
197 }
198 length -= len;
199 }
200 return ndesc;
201 }
202
203 /*
204 * Copy from the SGEs to the data buffer.
205 */
qib_copy_from_sge(void * data,struct rvt_sge_state * ss,u32 length)206 static void qib_copy_from_sge(void *data, struct rvt_sge_state *ss, u32 length)
207 {
208 struct rvt_sge *sge = &ss->sge;
209
210 while (length) {
211 u32 len = sge->length;
212
213 if (len > length)
214 len = length;
215 if (len > sge->sge_length)
216 len = sge->sge_length;
217 BUG_ON(len == 0);
218 memcpy(data, sge->vaddr, len);
219 sge->vaddr += len;
220 sge->length -= len;
221 sge->sge_length -= len;
222 if (sge->sge_length == 0) {
223 if (--ss->num_sge)
224 *sge = *ss->sg_list++;
225 } else if (sge->length == 0 && sge->mr->lkey) {
226 if (++sge->n >= RVT_SEGSZ) {
227 if (++sge->m >= sge->mr->mapsz)
228 break;
229 sge->n = 0;
230 }
231 sge->vaddr =
232 sge->mr->map[sge->m]->segs[sge->n].vaddr;
233 sge->length =
234 sge->mr->map[sge->m]->segs[sge->n].length;
235 }
236 data += len;
237 length -= len;
238 }
239 }
240
241 /**
242 * qib_qp_rcv - processing an incoming packet on a QP
243 * @rcd: the context pointer
244 * @hdr: the packet header
245 * @has_grh: true if the packet has a GRH
246 * @data: the packet data
247 * @tlen: the packet length
248 * @qp: the QP the packet came on
249 *
250 * This is called from qib_ib_rcv() to process an incoming packet
251 * for the given QP.
252 * Called at interrupt level.
253 */
qib_qp_rcv(struct qib_ctxtdata * rcd,struct ib_header * hdr,int has_grh,void * data,u32 tlen,struct rvt_qp * qp)254 static void qib_qp_rcv(struct qib_ctxtdata *rcd, struct ib_header *hdr,
255 int has_grh, void *data, u32 tlen, struct rvt_qp *qp)
256 {
257 struct qib_ibport *ibp = &rcd->ppd->ibport_data;
258
259 spin_lock(&qp->r_lock);
260
261 /* Check for valid receive state. */
262 if (!(ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK)) {
263 ibp->rvp.n_pkt_drops++;
264 goto unlock;
265 }
266
267 switch (qp->ibqp.qp_type) {
268 case IB_QPT_SMI:
269 case IB_QPT_GSI:
270 if (ib_qib_disable_sma)
271 break;
272 /* FALLTHROUGH */
273 case IB_QPT_UD:
274 qib_ud_rcv(ibp, hdr, has_grh, data, tlen, qp);
275 break;
276
277 case IB_QPT_RC:
278 qib_rc_rcv(rcd, hdr, has_grh, data, tlen, qp);
279 break;
280
281 case IB_QPT_UC:
282 qib_uc_rcv(ibp, hdr, has_grh, data, tlen, qp);
283 break;
284
285 default:
286 break;
287 }
288
289 unlock:
290 spin_unlock(&qp->r_lock);
291 }
292
293 /**
294 * qib_ib_rcv - process an incoming packet
295 * @rcd: the context pointer
296 * @rhdr: the header of the packet
297 * @data: the packet payload
298 * @tlen: the packet length
299 *
300 * This is called from qib_kreceive() to process an incoming packet at
301 * interrupt level. Tlen is the length of the header + data + CRC in bytes.
302 */
qib_ib_rcv(struct qib_ctxtdata * rcd,void * rhdr,void * data,u32 tlen)303 void qib_ib_rcv(struct qib_ctxtdata *rcd, void *rhdr, void *data, u32 tlen)
304 {
305 struct qib_pportdata *ppd = rcd->ppd;
306 struct qib_ibport *ibp = &ppd->ibport_data;
307 struct ib_header *hdr = rhdr;
308 struct qib_devdata *dd = ppd->dd;
309 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
310 struct ib_other_headers *ohdr;
311 struct rvt_qp *qp;
312 u32 qp_num;
313 int lnh;
314 u8 opcode;
315 u16 lid;
316
317 /* 24 == LRH+BTH+CRC */
318 if (unlikely(tlen < 24))
319 goto drop;
320
321 /* Check for a valid destination LID (see ch. 7.11.1). */
322 lid = be16_to_cpu(hdr->lrh[1]);
323 if (lid < be16_to_cpu(IB_MULTICAST_LID_BASE)) {
324 lid &= ~((1 << ppd->lmc) - 1);
325 if (unlikely(lid != ppd->lid))
326 goto drop;
327 }
328
329 /* Check for GRH */
330 lnh = be16_to_cpu(hdr->lrh[0]) & 3;
331 if (lnh == QIB_LRH_BTH)
332 ohdr = &hdr->u.oth;
333 else if (lnh == QIB_LRH_GRH) {
334 u32 vtf;
335
336 ohdr = &hdr->u.l.oth;
337 if (hdr->u.l.grh.next_hdr != IB_GRH_NEXT_HDR)
338 goto drop;
339 vtf = be32_to_cpu(hdr->u.l.grh.version_tclass_flow);
340 if ((vtf >> IB_GRH_VERSION_SHIFT) != IB_GRH_VERSION)
341 goto drop;
342 } else
343 goto drop;
344
345 opcode = (be32_to_cpu(ohdr->bth[0]) >> 24) & 0x7f;
346 #ifdef CONFIG_DEBUG_FS
347 rcd->opstats->stats[opcode].n_bytes += tlen;
348 rcd->opstats->stats[opcode].n_packets++;
349 #endif
350
351 /* Get the destination QP number. */
352 qp_num = be32_to_cpu(ohdr->bth[1]) & RVT_QPN_MASK;
353 if (qp_num == QIB_MULTICAST_QPN) {
354 struct rvt_mcast *mcast;
355 struct rvt_mcast_qp *p;
356
357 if (lnh != QIB_LRH_GRH)
358 goto drop;
359 mcast = rvt_mcast_find(&ibp->rvp, &hdr->u.l.grh.dgid, lid);
360 if (mcast == NULL)
361 goto drop;
362 this_cpu_inc(ibp->pmastats->n_multicast_rcv);
363 rcu_read_lock();
364 list_for_each_entry_rcu(p, &mcast->qp_list, list)
365 qib_qp_rcv(rcd, hdr, 1, data, tlen, p->qp);
366 rcu_read_unlock();
367 /*
368 * Notify rvt_multicast_detach() if it is waiting for us
369 * to finish.
370 */
371 if (atomic_dec_return(&mcast->refcount) <= 1)
372 wake_up(&mcast->wait);
373 } else {
374 rcu_read_lock();
375 qp = rvt_lookup_qpn(rdi, &ibp->rvp, qp_num);
376 if (!qp) {
377 rcu_read_unlock();
378 goto drop;
379 }
380 this_cpu_inc(ibp->pmastats->n_unicast_rcv);
381 qib_qp_rcv(rcd, hdr, lnh == QIB_LRH_GRH, data, tlen, qp);
382 rcu_read_unlock();
383 }
384 return;
385
386 drop:
387 ibp->rvp.n_pkt_drops++;
388 }
389
390 /*
391 * This is called from a timer to check for QPs
392 * which need kernel memory in order to send a packet.
393 */
mem_timer(struct timer_list * t)394 static void mem_timer(struct timer_list *t)
395 {
396 struct qib_ibdev *dev = from_timer(dev, t, mem_timer);
397 struct list_head *list = &dev->memwait;
398 struct rvt_qp *qp = NULL;
399 struct qib_qp_priv *priv = NULL;
400 unsigned long flags;
401
402 spin_lock_irqsave(&dev->rdi.pending_lock, flags);
403 if (!list_empty(list)) {
404 priv = list_entry(list->next, struct qib_qp_priv, iowait);
405 qp = priv->owner;
406 list_del_init(&priv->iowait);
407 rvt_get_qp(qp);
408 if (!list_empty(list))
409 mod_timer(&dev->mem_timer, jiffies + 1);
410 }
411 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
412
413 if (qp) {
414 spin_lock_irqsave(&qp->s_lock, flags);
415 if (qp->s_flags & RVT_S_WAIT_KMEM) {
416 qp->s_flags &= ~RVT_S_WAIT_KMEM;
417 qib_schedule_send(qp);
418 }
419 spin_unlock_irqrestore(&qp->s_lock, flags);
420 rvt_put_qp(qp);
421 }
422 }
423
424 #ifdef __LITTLE_ENDIAN
get_upper_bits(u32 data,u32 shift)425 static inline u32 get_upper_bits(u32 data, u32 shift)
426 {
427 return data >> shift;
428 }
429
set_upper_bits(u32 data,u32 shift)430 static inline u32 set_upper_bits(u32 data, u32 shift)
431 {
432 return data << shift;
433 }
434
clear_upper_bytes(u32 data,u32 n,u32 off)435 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
436 {
437 data <<= ((sizeof(u32) - n) * BITS_PER_BYTE);
438 data >>= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
439 return data;
440 }
441 #else
get_upper_bits(u32 data,u32 shift)442 static inline u32 get_upper_bits(u32 data, u32 shift)
443 {
444 return data << shift;
445 }
446
set_upper_bits(u32 data,u32 shift)447 static inline u32 set_upper_bits(u32 data, u32 shift)
448 {
449 return data >> shift;
450 }
451
clear_upper_bytes(u32 data,u32 n,u32 off)452 static inline u32 clear_upper_bytes(u32 data, u32 n, u32 off)
453 {
454 data >>= ((sizeof(u32) - n) * BITS_PER_BYTE);
455 data <<= ((sizeof(u32) - n - off) * BITS_PER_BYTE);
456 return data;
457 }
458 #endif
459
copy_io(u32 __iomem * piobuf,struct rvt_sge_state * ss,u32 length,unsigned flush_wc)460 static void copy_io(u32 __iomem *piobuf, struct rvt_sge_state *ss,
461 u32 length, unsigned flush_wc)
462 {
463 u32 extra = 0;
464 u32 data = 0;
465 u32 last;
466
467 while (1) {
468 u32 len = ss->sge.length;
469 u32 off;
470
471 if (len > length)
472 len = length;
473 if (len > ss->sge.sge_length)
474 len = ss->sge.sge_length;
475 BUG_ON(len == 0);
476 /* If the source address is not aligned, try to align it. */
477 off = (unsigned long)ss->sge.vaddr & (sizeof(u32) - 1);
478 if (off) {
479 u32 *addr = (u32 *)((unsigned long)ss->sge.vaddr &
480 ~(sizeof(u32) - 1));
481 u32 v = get_upper_bits(*addr, off * BITS_PER_BYTE);
482 u32 y;
483
484 y = sizeof(u32) - off;
485 if (len > y)
486 len = y;
487 if (len + extra >= sizeof(u32)) {
488 data |= set_upper_bits(v, extra *
489 BITS_PER_BYTE);
490 len = sizeof(u32) - extra;
491 if (len == length) {
492 last = data;
493 break;
494 }
495 __raw_writel(data, piobuf);
496 piobuf++;
497 extra = 0;
498 data = 0;
499 } else {
500 /* Clear unused upper bytes */
501 data |= clear_upper_bytes(v, len, extra);
502 if (len == length) {
503 last = data;
504 break;
505 }
506 extra += len;
507 }
508 } else if (extra) {
509 /* Source address is aligned. */
510 u32 *addr = (u32 *) ss->sge.vaddr;
511 int shift = extra * BITS_PER_BYTE;
512 int ushift = 32 - shift;
513 u32 l = len;
514
515 while (l >= sizeof(u32)) {
516 u32 v = *addr;
517
518 data |= set_upper_bits(v, shift);
519 __raw_writel(data, piobuf);
520 data = get_upper_bits(v, ushift);
521 piobuf++;
522 addr++;
523 l -= sizeof(u32);
524 }
525 /*
526 * We still have 'extra' number of bytes leftover.
527 */
528 if (l) {
529 u32 v = *addr;
530
531 if (l + extra >= sizeof(u32)) {
532 data |= set_upper_bits(v, shift);
533 len -= l + extra - sizeof(u32);
534 if (len == length) {
535 last = data;
536 break;
537 }
538 __raw_writel(data, piobuf);
539 piobuf++;
540 extra = 0;
541 data = 0;
542 } else {
543 /* Clear unused upper bytes */
544 data |= clear_upper_bytes(v, l, extra);
545 if (len == length) {
546 last = data;
547 break;
548 }
549 extra += l;
550 }
551 } else if (len == length) {
552 last = data;
553 break;
554 }
555 } else if (len == length) {
556 u32 w;
557
558 /*
559 * Need to round up for the last dword in the
560 * packet.
561 */
562 w = (len + 3) >> 2;
563 qib_pio_copy(piobuf, ss->sge.vaddr, w - 1);
564 piobuf += w - 1;
565 last = ((u32 *) ss->sge.vaddr)[w - 1];
566 break;
567 } else {
568 u32 w = len >> 2;
569
570 qib_pio_copy(piobuf, ss->sge.vaddr, w);
571 piobuf += w;
572
573 extra = len & (sizeof(u32) - 1);
574 if (extra) {
575 u32 v = ((u32 *) ss->sge.vaddr)[w];
576
577 /* Clear unused upper bytes */
578 data = clear_upper_bytes(v, extra, 0);
579 }
580 }
581 rvt_update_sge(ss, len, false);
582 length -= len;
583 }
584 /* Update address before sending packet. */
585 rvt_update_sge(ss, length, false);
586 if (flush_wc) {
587 /* must flush early everything before trigger word */
588 qib_flush_wc();
589 __raw_writel(last, piobuf);
590 /* be sure trigger word is written */
591 qib_flush_wc();
592 } else
593 __raw_writel(last, piobuf);
594 }
595
__get_txreq(struct qib_ibdev * dev,struct rvt_qp * qp)596 static noinline struct qib_verbs_txreq *__get_txreq(struct qib_ibdev *dev,
597 struct rvt_qp *qp)
598 {
599 struct qib_qp_priv *priv = qp->priv;
600 struct qib_verbs_txreq *tx;
601 unsigned long flags;
602
603 spin_lock_irqsave(&qp->s_lock, flags);
604 spin_lock(&dev->rdi.pending_lock);
605
606 if (!list_empty(&dev->txreq_free)) {
607 struct list_head *l = dev->txreq_free.next;
608
609 list_del(l);
610 spin_unlock(&dev->rdi.pending_lock);
611 spin_unlock_irqrestore(&qp->s_lock, flags);
612 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
613 } else {
614 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK &&
615 list_empty(&priv->iowait)) {
616 dev->n_txwait++;
617 qp->s_flags |= RVT_S_WAIT_TX;
618 list_add_tail(&priv->iowait, &dev->txwait);
619 }
620 qp->s_flags &= ~RVT_S_BUSY;
621 spin_unlock(&dev->rdi.pending_lock);
622 spin_unlock_irqrestore(&qp->s_lock, flags);
623 tx = ERR_PTR(-EBUSY);
624 }
625 return tx;
626 }
627
get_txreq(struct qib_ibdev * dev,struct rvt_qp * qp)628 static inline struct qib_verbs_txreq *get_txreq(struct qib_ibdev *dev,
629 struct rvt_qp *qp)
630 {
631 struct qib_verbs_txreq *tx;
632 unsigned long flags;
633
634 spin_lock_irqsave(&dev->rdi.pending_lock, flags);
635 /* assume the list non empty */
636 if (likely(!list_empty(&dev->txreq_free))) {
637 struct list_head *l = dev->txreq_free.next;
638
639 list_del(l);
640 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
641 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
642 } else {
643 /* call slow path to get the extra lock */
644 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
645 tx = __get_txreq(dev, qp);
646 }
647 return tx;
648 }
649
qib_put_txreq(struct qib_verbs_txreq * tx)650 void qib_put_txreq(struct qib_verbs_txreq *tx)
651 {
652 struct qib_ibdev *dev;
653 struct rvt_qp *qp;
654 struct qib_qp_priv *priv;
655 unsigned long flags;
656
657 qp = tx->qp;
658 dev = to_idev(qp->ibqp.device);
659
660 if (tx->mr) {
661 rvt_put_mr(tx->mr);
662 tx->mr = NULL;
663 }
664 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF) {
665 tx->txreq.flags &= ~QIB_SDMA_TXREQ_F_FREEBUF;
666 dma_unmap_single(&dd_from_dev(dev)->pcidev->dev,
667 tx->txreq.addr, tx->hdr_dwords << 2,
668 DMA_TO_DEVICE);
669 kfree(tx->align_buf);
670 }
671
672 spin_lock_irqsave(&dev->rdi.pending_lock, flags);
673
674 /* Put struct back on free list */
675 list_add(&tx->txreq.list, &dev->txreq_free);
676
677 if (!list_empty(&dev->txwait)) {
678 /* Wake up first QP wanting a free struct */
679 priv = list_entry(dev->txwait.next, struct qib_qp_priv,
680 iowait);
681 qp = priv->owner;
682 list_del_init(&priv->iowait);
683 rvt_get_qp(qp);
684 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
685
686 spin_lock_irqsave(&qp->s_lock, flags);
687 if (qp->s_flags & RVT_S_WAIT_TX) {
688 qp->s_flags &= ~RVT_S_WAIT_TX;
689 qib_schedule_send(qp);
690 }
691 spin_unlock_irqrestore(&qp->s_lock, flags);
692
693 rvt_put_qp(qp);
694 } else
695 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
696 }
697
698 /*
699 * This is called when there are send DMA descriptors that might be
700 * available.
701 *
702 * This is called with ppd->sdma_lock held.
703 */
qib_verbs_sdma_desc_avail(struct qib_pportdata * ppd,unsigned avail)704 void qib_verbs_sdma_desc_avail(struct qib_pportdata *ppd, unsigned avail)
705 {
706 struct rvt_qp *qp;
707 struct qib_qp_priv *qpp, *nqpp;
708 struct rvt_qp *qps[20];
709 struct qib_ibdev *dev;
710 unsigned i, n;
711
712 n = 0;
713 dev = &ppd->dd->verbs_dev;
714 spin_lock(&dev->rdi.pending_lock);
715
716 /* Search wait list for first QP wanting DMA descriptors. */
717 list_for_each_entry_safe(qpp, nqpp, &dev->dmawait, iowait) {
718 qp = qpp->owner;
719 if (qp->port_num != ppd->port)
720 continue;
721 if (n == ARRAY_SIZE(qps))
722 break;
723 if (qpp->s_tx->txreq.sg_count > avail)
724 break;
725 avail -= qpp->s_tx->txreq.sg_count;
726 list_del_init(&qpp->iowait);
727 rvt_get_qp(qp);
728 qps[n++] = qp;
729 }
730
731 spin_unlock(&dev->rdi.pending_lock);
732
733 for (i = 0; i < n; i++) {
734 qp = qps[i];
735 spin_lock(&qp->s_lock);
736 if (qp->s_flags & RVT_S_WAIT_DMA_DESC) {
737 qp->s_flags &= ~RVT_S_WAIT_DMA_DESC;
738 qib_schedule_send(qp);
739 }
740 spin_unlock(&qp->s_lock);
741 rvt_put_qp(qp);
742 }
743 }
744
745 /*
746 * This is called with ppd->sdma_lock held.
747 */
sdma_complete(struct qib_sdma_txreq * cookie,int status)748 static void sdma_complete(struct qib_sdma_txreq *cookie, int status)
749 {
750 struct qib_verbs_txreq *tx =
751 container_of(cookie, struct qib_verbs_txreq, txreq);
752 struct rvt_qp *qp = tx->qp;
753 struct qib_qp_priv *priv = qp->priv;
754
755 spin_lock(&qp->s_lock);
756 if (tx->wqe)
757 qib_send_complete(qp, tx->wqe, IB_WC_SUCCESS);
758 else if (qp->ibqp.qp_type == IB_QPT_RC) {
759 struct ib_header *hdr;
760
761 if (tx->txreq.flags & QIB_SDMA_TXREQ_F_FREEBUF)
762 hdr = &tx->align_buf->hdr;
763 else {
764 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
765
766 hdr = &dev->pio_hdrs[tx->hdr_inx].hdr;
767 }
768 qib_rc_send_complete(qp, hdr);
769 }
770 if (atomic_dec_and_test(&priv->s_dma_busy)) {
771 if (qp->state == IB_QPS_RESET)
772 wake_up(&priv->wait_dma);
773 else if (qp->s_flags & RVT_S_WAIT_DMA) {
774 qp->s_flags &= ~RVT_S_WAIT_DMA;
775 qib_schedule_send(qp);
776 }
777 }
778 spin_unlock(&qp->s_lock);
779
780 qib_put_txreq(tx);
781 }
782
wait_kmem(struct qib_ibdev * dev,struct rvt_qp * qp)783 static int wait_kmem(struct qib_ibdev *dev, struct rvt_qp *qp)
784 {
785 struct qib_qp_priv *priv = qp->priv;
786 unsigned long flags;
787 int ret = 0;
788
789 spin_lock_irqsave(&qp->s_lock, flags);
790 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
791 spin_lock(&dev->rdi.pending_lock);
792 if (list_empty(&priv->iowait)) {
793 if (list_empty(&dev->memwait))
794 mod_timer(&dev->mem_timer, jiffies + 1);
795 qp->s_flags |= RVT_S_WAIT_KMEM;
796 list_add_tail(&priv->iowait, &dev->memwait);
797 }
798 spin_unlock(&dev->rdi.pending_lock);
799 qp->s_flags &= ~RVT_S_BUSY;
800 ret = -EBUSY;
801 }
802 spin_unlock_irqrestore(&qp->s_lock, flags);
803
804 return ret;
805 }
806
qib_verbs_send_dma(struct rvt_qp * qp,struct ib_header * hdr,u32 hdrwords,struct rvt_sge_state * ss,u32 len,u32 plen,u32 dwords)807 static int qib_verbs_send_dma(struct rvt_qp *qp, struct ib_header *hdr,
808 u32 hdrwords, struct rvt_sge_state *ss, u32 len,
809 u32 plen, u32 dwords)
810 {
811 struct qib_qp_priv *priv = qp->priv;
812 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
813 struct qib_devdata *dd = dd_from_dev(dev);
814 struct qib_ibport *ibp = to_iport(qp->ibqp.device, qp->port_num);
815 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
816 struct qib_verbs_txreq *tx;
817 struct qib_pio_header *phdr;
818 u32 control;
819 u32 ndesc;
820 int ret;
821
822 tx = priv->s_tx;
823 if (tx) {
824 priv->s_tx = NULL;
825 /* resend previously constructed packet */
826 ret = qib_sdma_verbs_send(ppd, tx->ss, tx->dwords, tx);
827 goto bail;
828 }
829
830 tx = get_txreq(dev, qp);
831 if (IS_ERR(tx))
832 goto bail_tx;
833
834 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
835 be16_to_cpu(hdr->lrh[0]) >> 12);
836 tx->qp = qp;
837 tx->wqe = qp->s_wqe;
838 tx->mr = qp->s_rdma_mr;
839 if (qp->s_rdma_mr)
840 qp->s_rdma_mr = NULL;
841 tx->txreq.callback = sdma_complete;
842 if (dd->flags & QIB_HAS_SDMA_TIMEOUT)
843 tx->txreq.flags = QIB_SDMA_TXREQ_F_HEADTOHOST;
844 else
845 tx->txreq.flags = QIB_SDMA_TXREQ_F_INTREQ;
846 if (plen + 1 > dd->piosize2kmax_dwords)
847 tx->txreq.flags |= QIB_SDMA_TXREQ_F_USELARGEBUF;
848
849 if (len) {
850 /*
851 * Don't try to DMA if it takes more descriptors than
852 * the queue holds.
853 */
854 ndesc = qib_count_sge(ss, len);
855 if (ndesc >= ppd->sdma_descq_cnt)
856 ndesc = 0;
857 } else
858 ndesc = 1;
859 if (ndesc) {
860 phdr = &dev->pio_hdrs[tx->hdr_inx];
861 phdr->pbc[0] = cpu_to_le32(plen);
862 phdr->pbc[1] = cpu_to_le32(control);
863 memcpy(&phdr->hdr, hdr, hdrwords << 2);
864 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEDESC;
865 tx->txreq.sg_count = ndesc;
866 tx->txreq.addr = dev->pio_hdrs_phys +
867 tx->hdr_inx * sizeof(struct qib_pio_header);
868 tx->hdr_dwords = hdrwords + 2; /* add PBC length */
869 ret = qib_sdma_verbs_send(ppd, ss, dwords, tx);
870 goto bail;
871 }
872
873 /* Allocate a buffer and copy the header and payload to it. */
874 tx->hdr_dwords = plen + 1;
875 phdr = kmalloc(tx->hdr_dwords << 2, GFP_ATOMIC);
876 if (!phdr)
877 goto err_tx;
878 phdr->pbc[0] = cpu_to_le32(plen);
879 phdr->pbc[1] = cpu_to_le32(control);
880 memcpy(&phdr->hdr, hdr, hdrwords << 2);
881 qib_copy_from_sge((u32 *) &phdr->hdr + hdrwords, ss, len);
882
883 tx->txreq.addr = dma_map_single(&dd->pcidev->dev, phdr,
884 tx->hdr_dwords << 2, DMA_TO_DEVICE);
885 if (dma_mapping_error(&dd->pcidev->dev, tx->txreq.addr))
886 goto map_err;
887 tx->align_buf = phdr;
888 tx->txreq.flags |= QIB_SDMA_TXREQ_F_FREEBUF;
889 tx->txreq.sg_count = 1;
890 ret = qib_sdma_verbs_send(ppd, NULL, 0, tx);
891 goto unaligned;
892
893 map_err:
894 kfree(phdr);
895 err_tx:
896 qib_put_txreq(tx);
897 ret = wait_kmem(dev, qp);
898 unaligned:
899 ibp->rvp.n_unaligned++;
900 bail:
901 return ret;
902 bail_tx:
903 ret = PTR_ERR(tx);
904 goto bail;
905 }
906
907 /*
908 * If we are now in the error state, return zero to flush the
909 * send work request.
910 */
no_bufs_available(struct rvt_qp * qp)911 static int no_bufs_available(struct rvt_qp *qp)
912 {
913 struct qib_qp_priv *priv = qp->priv;
914 struct qib_ibdev *dev = to_idev(qp->ibqp.device);
915 struct qib_devdata *dd;
916 unsigned long flags;
917 int ret = 0;
918
919 /*
920 * Note that as soon as want_buffer() is called and
921 * possibly before it returns, qib_ib_piobufavail()
922 * could be called. Therefore, put QP on the I/O wait list before
923 * enabling the PIO avail interrupt.
924 */
925 spin_lock_irqsave(&qp->s_lock, flags);
926 if (ib_rvt_state_ops[qp->state] & RVT_PROCESS_RECV_OK) {
927 spin_lock(&dev->rdi.pending_lock);
928 if (list_empty(&priv->iowait)) {
929 dev->n_piowait++;
930 qp->s_flags |= RVT_S_WAIT_PIO;
931 list_add_tail(&priv->iowait, &dev->piowait);
932 dd = dd_from_dev(dev);
933 dd->f_wantpiobuf_intr(dd, 1);
934 }
935 spin_unlock(&dev->rdi.pending_lock);
936 qp->s_flags &= ~RVT_S_BUSY;
937 ret = -EBUSY;
938 }
939 spin_unlock_irqrestore(&qp->s_lock, flags);
940 return ret;
941 }
942
qib_verbs_send_pio(struct rvt_qp * qp,struct ib_header * ibhdr,u32 hdrwords,struct rvt_sge_state * ss,u32 len,u32 plen,u32 dwords)943 static int qib_verbs_send_pio(struct rvt_qp *qp, struct ib_header *ibhdr,
944 u32 hdrwords, struct rvt_sge_state *ss, u32 len,
945 u32 plen, u32 dwords)
946 {
947 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
948 struct qib_pportdata *ppd = dd->pport + qp->port_num - 1;
949 u32 *hdr = (u32 *) ibhdr;
950 u32 __iomem *piobuf_orig;
951 u32 __iomem *piobuf;
952 u64 pbc;
953 unsigned long flags;
954 unsigned flush_wc;
955 u32 control;
956 u32 pbufn;
957
958 control = dd->f_setpbc_control(ppd, plen, qp->s_srate,
959 be16_to_cpu(ibhdr->lrh[0]) >> 12);
960 pbc = ((u64) control << 32) | plen;
961 piobuf = dd->f_getsendbuf(ppd, pbc, &pbufn);
962 if (unlikely(piobuf == NULL))
963 return no_bufs_available(qp);
964
965 /*
966 * Write the pbc.
967 * We have to flush after the PBC for correctness on some cpus
968 * or WC buffer can be written out of order.
969 */
970 writeq(pbc, piobuf);
971 piobuf_orig = piobuf;
972 piobuf += 2;
973
974 flush_wc = dd->flags & QIB_PIO_FLUSH_WC;
975 if (len == 0) {
976 /*
977 * If there is just the header portion, must flush before
978 * writing last word of header for correctness, and after
979 * the last header word (trigger word).
980 */
981 if (flush_wc) {
982 qib_flush_wc();
983 qib_pio_copy(piobuf, hdr, hdrwords - 1);
984 qib_flush_wc();
985 __raw_writel(hdr[hdrwords - 1], piobuf + hdrwords - 1);
986 qib_flush_wc();
987 } else
988 qib_pio_copy(piobuf, hdr, hdrwords);
989 goto done;
990 }
991
992 if (flush_wc)
993 qib_flush_wc();
994 qib_pio_copy(piobuf, hdr, hdrwords);
995 piobuf += hdrwords;
996
997 /* The common case is aligned and contained in one segment. */
998 if (likely(ss->num_sge == 1 && len <= ss->sge.length &&
999 !((unsigned long)ss->sge.vaddr & (sizeof(u32) - 1)))) {
1000 u32 *addr = (u32 *) ss->sge.vaddr;
1001
1002 /* Update address before sending packet. */
1003 rvt_update_sge(ss, len, false);
1004 if (flush_wc) {
1005 qib_pio_copy(piobuf, addr, dwords - 1);
1006 /* must flush early everything before trigger word */
1007 qib_flush_wc();
1008 __raw_writel(addr[dwords - 1], piobuf + dwords - 1);
1009 /* be sure trigger word is written */
1010 qib_flush_wc();
1011 } else
1012 qib_pio_copy(piobuf, addr, dwords);
1013 goto done;
1014 }
1015 copy_io(piobuf, ss, len, flush_wc);
1016 done:
1017 if (dd->flags & QIB_USE_SPCL_TRIG) {
1018 u32 spcl_off = (pbufn >= dd->piobcnt2k) ? 2047 : 1023;
1019
1020 qib_flush_wc();
1021 __raw_writel(0xaebecede, piobuf_orig + spcl_off);
1022 }
1023 qib_sendbuf_done(dd, pbufn);
1024 if (qp->s_rdma_mr) {
1025 rvt_put_mr(qp->s_rdma_mr);
1026 qp->s_rdma_mr = NULL;
1027 }
1028 if (qp->s_wqe) {
1029 spin_lock_irqsave(&qp->s_lock, flags);
1030 qib_send_complete(qp, qp->s_wqe, IB_WC_SUCCESS);
1031 spin_unlock_irqrestore(&qp->s_lock, flags);
1032 } else if (qp->ibqp.qp_type == IB_QPT_RC) {
1033 spin_lock_irqsave(&qp->s_lock, flags);
1034 qib_rc_send_complete(qp, ibhdr);
1035 spin_unlock_irqrestore(&qp->s_lock, flags);
1036 }
1037 return 0;
1038 }
1039
1040 /**
1041 * qib_verbs_send - send a packet
1042 * @qp: the QP to send on
1043 * @hdr: the packet header
1044 * @hdrwords: the number of 32-bit words in the header
1045 * @ss: the SGE to send
1046 * @len: the length of the packet in bytes
1047 *
1048 * Return zero if packet is sent or queued OK.
1049 * Return non-zero and clear qp->s_flags RVT_S_BUSY otherwise.
1050 */
qib_verbs_send(struct rvt_qp * qp,struct ib_header * hdr,u32 hdrwords,struct rvt_sge_state * ss,u32 len)1051 int qib_verbs_send(struct rvt_qp *qp, struct ib_header *hdr,
1052 u32 hdrwords, struct rvt_sge_state *ss, u32 len)
1053 {
1054 struct qib_devdata *dd = dd_from_ibdev(qp->ibqp.device);
1055 u32 plen;
1056 int ret;
1057 u32 dwords = (len + 3) >> 2;
1058
1059 /*
1060 * Calculate the send buffer trigger address.
1061 * The +1 counts for the pbc control dword following the pbc length.
1062 */
1063 plen = hdrwords + dwords + 1;
1064
1065 /*
1066 * VL15 packets (IB_QPT_SMI) will always use PIO, so we
1067 * can defer SDMA restart until link goes ACTIVE without
1068 * worrying about just how we got there.
1069 */
1070 if (qp->ibqp.qp_type == IB_QPT_SMI ||
1071 !(dd->flags & QIB_HAS_SEND_DMA))
1072 ret = qib_verbs_send_pio(qp, hdr, hdrwords, ss, len,
1073 plen, dwords);
1074 else
1075 ret = qib_verbs_send_dma(qp, hdr, hdrwords, ss, len,
1076 plen, dwords);
1077
1078 return ret;
1079 }
1080
qib_snapshot_counters(struct qib_pportdata * ppd,u64 * swords,u64 * rwords,u64 * spkts,u64 * rpkts,u64 * xmit_wait)1081 int qib_snapshot_counters(struct qib_pportdata *ppd, u64 *swords,
1082 u64 *rwords, u64 *spkts, u64 *rpkts,
1083 u64 *xmit_wait)
1084 {
1085 int ret;
1086 struct qib_devdata *dd = ppd->dd;
1087
1088 if (!(dd->flags & QIB_PRESENT)) {
1089 /* no hardware, freeze, etc. */
1090 ret = -EINVAL;
1091 goto bail;
1092 }
1093 *swords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDSEND);
1094 *rwords = dd->f_portcntr(ppd, QIBPORTCNTR_WORDRCV);
1095 *spkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTSEND);
1096 *rpkts = dd->f_portcntr(ppd, QIBPORTCNTR_PKTRCV);
1097 *xmit_wait = dd->f_portcntr(ppd, QIBPORTCNTR_SENDSTALL);
1098
1099 ret = 0;
1100
1101 bail:
1102 return ret;
1103 }
1104
1105 /**
1106 * qib_get_counters - get various chip counters
1107 * @dd: the qlogic_ib device
1108 * @cntrs: counters are placed here
1109 *
1110 * Return the counters needed by recv_pma_get_portcounters().
1111 */
qib_get_counters(struct qib_pportdata * ppd,struct qib_verbs_counters * cntrs)1112 int qib_get_counters(struct qib_pportdata *ppd,
1113 struct qib_verbs_counters *cntrs)
1114 {
1115 int ret;
1116
1117 if (!(ppd->dd->flags & QIB_PRESENT)) {
1118 /* no hardware, freeze, etc. */
1119 ret = -EINVAL;
1120 goto bail;
1121 }
1122 cntrs->symbol_error_counter =
1123 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBSYMBOLERR);
1124 cntrs->link_error_recovery_counter =
1125 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKERRRECOV);
1126 /*
1127 * The link downed counter counts when the other side downs the
1128 * connection. We add in the number of times we downed the link
1129 * due to local link integrity errors to compensate.
1130 */
1131 cntrs->link_downed_counter =
1132 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_IBLINKDOWN);
1133 cntrs->port_rcv_errors =
1134 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXDROPPKT) +
1135 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVOVFL) +
1136 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERR_RLEN) +
1137 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_INVALIDRLEN) +
1138 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLINK) +
1139 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRICRC) +
1140 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRVCRC) +
1141 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_ERRLPCRC) +
1142 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_BADFORMAT);
1143 cntrs->port_rcv_errors +=
1144 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXLOCALPHYERR);
1145 cntrs->port_rcv_errors +=
1146 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RXVLERR);
1147 cntrs->port_rcv_remphys_errors =
1148 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_RCVEBP);
1149 cntrs->port_xmit_discards =
1150 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_UNSUPVL);
1151 cntrs->port_xmit_data = ppd->dd->f_portcntr(ppd,
1152 QIBPORTCNTR_WORDSEND);
1153 cntrs->port_rcv_data = ppd->dd->f_portcntr(ppd,
1154 QIBPORTCNTR_WORDRCV);
1155 cntrs->port_xmit_packets = ppd->dd->f_portcntr(ppd,
1156 QIBPORTCNTR_PKTSEND);
1157 cntrs->port_rcv_packets = ppd->dd->f_portcntr(ppd,
1158 QIBPORTCNTR_PKTRCV);
1159 cntrs->local_link_integrity_errors =
1160 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_LLI);
1161 cntrs->excessive_buffer_overrun_errors =
1162 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_EXCESSBUFOVFL);
1163 cntrs->vl15_dropped =
1164 ppd->dd->f_portcntr(ppd, QIBPORTCNTR_VL15PKTDROP);
1165
1166 ret = 0;
1167
1168 bail:
1169 return ret;
1170 }
1171
1172 /**
1173 * qib_ib_piobufavail - callback when a PIO buffer is available
1174 * @dd: the device pointer
1175 *
1176 * This is called from qib_intr() at interrupt level when a PIO buffer is
1177 * available after qib_verbs_send() returned an error that no buffers were
1178 * available. Disable the interrupt if there are no more QPs waiting.
1179 */
qib_ib_piobufavail(struct qib_devdata * dd)1180 void qib_ib_piobufavail(struct qib_devdata *dd)
1181 {
1182 struct qib_ibdev *dev = &dd->verbs_dev;
1183 struct list_head *list;
1184 struct rvt_qp *qps[5];
1185 struct rvt_qp *qp;
1186 unsigned long flags;
1187 unsigned i, n;
1188 struct qib_qp_priv *priv;
1189
1190 list = &dev->piowait;
1191 n = 0;
1192
1193 /*
1194 * Note: checking that the piowait list is empty and clearing
1195 * the buffer available interrupt needs to be atomic or we
1196 * could end up with QPs on the wait list with the interrupt
1197 * disabled.
1198 */
1199 spin_lock_irqsave(&dev->rdi.pending_lock, flags);
1200 while (!list_empty(list)) {
1201 if (n == ARRAY_SIZE(qps))
1202 goto full;
1203 priv = list_entry(list->next, struct qib_qp_priv, iowait);
1204 qp = priv->owner;
1205 list_del_init(&priv->iowait);
1206 rvt_get_qp(qp);
1207 qps[n++] = qp;
1208 }
1209 dd->f_wantpiobuf_intr(dd, 0);
1210 full:
1211 spin_unlock_irqrestore(&dev->rdi.pending_lock, flags);
1212
1213 for (i = 0; i < n; i++) {
1214 qp = qps[i];
1215
1216 spin_lock_irqsave(&qp->s_lock, flags);
1217 if (qp->s_flags & RVT_S_WAIT_PIO) {
1218 qp->s_flags &= ~RVT_S_WAIT_PIO;
1219 qib_schedule_send(qp);
1220 }
1221 spin_unlock_irqrestore(&qp->s_lock, flags);
1222
1223 /* Notify qib_destroy_qp() if it is waiting. */
1224 rvt_put_qp(qp);
1225 }
1226 }
1227
qib_query_port(struct rvt_dev_info * rdi,u8 port_num,struct ib_port_attr * props)1228 static int qib_query_port(struct rvt_dev_info *rdi, u8 port_num,
1229 struct ib_port_attr *props)
1230 {
1231 struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi);
1232 struct qib_devdata *dd = dd_from_dev(ibdev);
1233 struct qib_pportdata *ppd = &dd->pport[port_num - 1];
1234 enum ib_mtu mtu;
1235 u16 lid = ppd->lid;
1236
1237 /* props being zeroed by the caller, avoid zeroing it here */
1238 props->lid = lid ? lid : be16_to_cpu(IB_LID_PERMISSIVE);
1239 props->lmc = ppd->lmc;
1240 props->state = dd->f_iblink_state(ppd->lastibcstat);
1241 props->phys_state = dd->f_ibphys_portstate(ppd->lastibcstat);
1242 props->gid_tbl_len = QIB_GUIDS_PER_PORT;
1243 props->active_width = ppd->link_width_active;
1244 /* See rate_show() */
1245 props->active_speed = ppd->link_speed_active;
1246 props->max_vl_num = qib_num_vls(ppd->vls_supported);
1247
1248 props->max_mtu = qib_ibmtu ? qib_ibmtu : IB_MTU_4096;
1249 switch (ppd->ibmtu) {
1250 case 4096:
1251 mtu = IB_MTU_4096;
1252 break;
1253 case 2048:
1254 mtu = IB_MTU_2048;
1255 break;
1256 case 1024:
1257 mtu = IB_MTU_1024;
1258 break;
1259 case 512:
1260 mtu = IB_MTU_512;
1261 break;
1262 case 256:
1263 mtu = IB_MTU_256;
1264 break;
1265 default:
1266 mtu = IB_MTU_2048;
1267 }
1268 props->active_mtu = mtu;
1269
1270 return 0;
1271 }
1272
qib_modify_device(struct ib_device * device,int device_modify_mask,struct ib_device_modify * device_modify)1273 static int qib_modify_device(struct ib_device *device,
1274 int device_modify_mask,
1275 struct ib_device_modify *device_modify)
1276 {
1277 struct qib_devdata *dd = dd_from_ibdev(device);
1278 unsigned i;
1279 int ret;
1280
1281 if (device_modify_mask & ~(IB_DEVICE_MODIFY_SYS_IMAGE_GUID |
1282 IB_DEVICE_MODIFY_NODE_DESC)) {
1283 ret = -EOPNOTSUPP;
1284 goto bail;
1285 }
1286
1287 if (device_modify_mask & IB_DEVICE_MODIFY_NODE_DESC) {
1288 memcpy(device->node_desc, device_modify->node_desc,
1289 IB_DEVICE_NODE_DESC_MAX);
1290 for (i = 0; i < dd->num_pports; i++) {
1291 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1292
1293 qib_node_desc_chg(ibp);
1294 }
1295 }
1296
1297 if (device_modify_mask & IB_DEVICE_MODIFY_SYS_IMAGE_GUID) {
1298 ib_qib_sys_image_guid =
1299 cpu_to_be64(device_modify->sys_image_guid);
1300 for (i = 0; i < dd->num_pports; i++) {
1301 struct qib_ibport *ibp = &dd->pport[i].ibport_data;
1302
1303 qib_sys_guid_chg(ibp);
1304 }
1305 }
1306
1307 ret = 0;
1308
1309 bail:
1310 return ret;
1311 }
1312
qib_shut_down_port(struct rvt_dev_info * rdi,u8 port_num)1313 static int qib_shut_down_port(struct rvt_dev_info *rdi, u8 port_num)
1314 {
1315 struct qib_ibdev *ibdev = container_of(rdi, struct qib_ibdev, rdi);
1316 struct qib_devdata *dd = dd_from_dev(ibdev);
1317 struct qib_pportdata *ppd = &dd->pport[port_num - 1];
1318
1319 qib_set_linkstate(ppd, QIB_IB_LINKDOWN);
1320
1321 return 0;
1322 }
1323
qib_get_guid_be(struct rvt_dev_info * rdi,struct rvt_ibport * rvp,int guid_index,__be64 * guid)1324 static int qib_get_guid_be(struct rvt_dev_info *rdi, struct rvt_ibport *rvp,
1325 int guid_index, __be64 *guid)
1326 {
1327 struct qib_ibport *ibp = container_of(rvp, struct qib_ibport, rvp);
1328 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1329
1330 if (guid_index == 0)
1331 *guid = ppd->guid;
1332 else if (guid_index < QIB_GUIDS_PER_PORT)
1333 *guid = ibp->guids[guid_index - 1];
1334 else
1335 return -EINVAL;
1336
1337 return 0;
1338 }
1339
qib_check_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr)1340 int qib_check_ah(struct ib_device *ibdev, struct rdma_ah_attr *ah_attr)
1341 {
1342 if (rdma_ah_get_sl(ah_attr) > 15)
1343 return -EINVAL;
1344
1345 if (rdma_ah_get_dlid(ah_attr) == 0)
1346 return -EINVAL;
1347 if (rdma_ah_get_dlid(ah_attr) >=
1348 be16_to_cpu(IB_MULTICAST_LID_BASE) &&
1349 rdma_ah_get_dlid(ah_attr) !=
1350 be16_to_cpu(IB_LID_PERMISSIVE) &&
1351 !(rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH))
1352 return -EINVAL;
1353
1354 return 0;
1355 }
1356
qib_notify_new_ah(struct ib_device * ibdev,struct rdma_ah_attr * ah_attr,struct rvt_ah * ah)1357 static void qib_notify_new_ah(struct ib_device *ibdev,
1358 struct rdma_ah_attr *ah_attr,
1359 struct rvt_ah *ah)
1360 {
1361 struct qib_ibport *ibp;
1362 struct qib_pportdata *ppd;
1363
1364 /*
1365 * Do not trust reading anything from rvt_ah at this point as it is not
1366 * done being setup. We can however modify things which we need to set.
1367 */
1368
1369 ibp = to_iport(ibdev, rdma_ah_get_port_num(ah_attr));
1370 ppd = ppd_from_ibp(ibp);
1371 ah->vl = ibp->sl_to_vl[rdma_ah_get_sl(&ah->attr)];
1372 ah->log_pmtu = ilog2(ppd->ibmtu);
1373 }
1374
qib_create_qp0_ah(struct qib_ibport * ibp,u16 dlid)1375 struct ib_ah *qib_create_qp0_ah(struct qib_ibport *ibp, u16 dlid)
1376 {
1377 struct rdma_ah_attr attr;
1378 struct ib_ah *ah = ERR_PTR(-EINVAL);
1379 struct rvt_qp *qp0;
1380 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1381 struct qib_devdata *dd = dd_from_ppd(ppd);
1382 u8 port_num = ppd->port;
1383
1384 memset(&attr, 0, sizeof(attr));
1385 attr.type = rdma_ah_find_type(&dd->verbs_dev.rdi.ibdev, port_num);
1386 rdma_ah_set_dlid(&attr, dlid);
1387 rdma_ah_set_port_num(&attr, port_num);
1388 rcu_read_lock();
1389 qp0 = rcu_dereference(ibp->rvp.qp[0]);
1390 if (qp0)
1391 ah = rdma_create_ah(qp0->ibqp.pd, &attr);
1392 rcu_read_unlock();
1393 return ah;
1394 }
1395
1396 /**
1397 * qib_get_npkeys - return the size of the PKEY table for context 0
1398 * @dd: the qlogic_ib device
1399 */
qib_get_npkeys(struct qib_devdata * dd)1400 unsigned qib_get_npkeys(struct qib_devdata *dd)
1401 {
1402 return ARRAY_SIZE(dd->rcd[0]->pkeys);
1403 }
1404
1405 /*
1406 * Return the indexed PKEY from the port PKEY table.
1407 * No need to validate rcd[ctxt]; the port is setup if we are here.
1408 */
qib_get_pkey(struct qib_ibport * ibp,unsigned index)1409 unsigned qib_get_pkey(struct qib_ibport *ibp, unsigned index)
1410 {
1411 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1412 struct qib_devdata *dd = ppd->dd;
1413 unsigned ctxt = ppd->hw_pidx;
1414 unsigned ret;
1415
1416 /* dd->rcd null if mini_init or some init failures */
1417 if (!dd->rcd || index >= ARRAY_SIZE(dd->rcd[ctxt]->pkeys))
1418 ret = 0;
1419 else
1420 ret = dd->rcd[ctxt]->pkeys[index];
1421
1422 return ret;
1423 }
1424
init_ibport(struct qib_pportdata * ppd)1425 static void init_ibport(struct qib_pportdata *ppd)
1426 {
1427 struct qib_verbs_counters cntrs;
1428 struct qib_ibport *ibp = &ppd->ibport_data;
1429
1430 spin_lock_init(&ibp->rvp.lock);
1431 /* Set the prefix to the default value (see ch. 4.1.1) */
1432 ibp->rvp.gid_prefix = IB_DEFAULT_GID_PREFIX;
1433 ibp->rvp.sm_lid = be16_to_cpu(IB_LID_PERMISSIVE);
1434 ibp->rvp.port_cap_flags = IB_PORT_SYS_IMAGE_GUID_SUP |
1435 IB_PORT_CLIENT_REG_SUP | IB_PORT_SL_MAP_SUP |
1436 IB_PORT_TRAP_SUP | IB_PORT_AUTO_MIGR_SUP |
1437 IB_PORT_DR_NOTICE_SUP | IB_PORT_CAP_MASK_NOTICE_SUP |
1438 IB_PORT_OTHER_LOCAL_CHANGES_SUP;
1439 if (ppd->dd->flags & QIB_HAS_LINK_LATENCY)
1440 ibp->rvp.port_cap_flags |= IB_PORT_LINK_LATENCY_SUP;
1441 ibp->rvp.pma_counter_select[0] = IB_PMA_PORT_XMIT_DATA;
1442 ibp->rvp.pma_counter_select[1] = IB_PMA_PORT_RCV_DATA;
1443 ibp->rvp.pma_counter_select[2] = IB_PMA_PORT_XMIT_PKTS;
1444 ibp->rvp.pma_counter_select[3] = IB_PMA_PORT_RCV_PKTS;
1445 ibp->rvp.pma_counter_select[4] = IB_PMA_PORT_XMIT_WAIT;
1446
1447 /* Snapshot current HW counters to "clear" them. */
1448 qib_get_counters(ppd, &cntrs);
1449 ibp->z_symbol_error_counter = cntrs.symbol_error_counter;
1450 ibp->z_link_error_recovery_counter =
1451 cntrs.link_error_recovery_counter;
1452 ibp->z_link_downed_counter = cntrs.link_downed_counter;
1453 ibp->z_port_rcv_errors = cntrs.port_rcv_errors;
1454 ibp->z_port_rcv_remphys_errors = cntrs.port_rcv_remphys_errors;
1455 ibp->z_port_xmit_discards = cntrs.port_xmit_discards;
1456 ibp->z_port_xmit_data = cntrs.port_xmit_data;
1457 ibp->z_port_rcv_data = cntrs.port_rcv_data;
1458 ibp->z_port_xmit_packets = cntrs.port_xmit_packets;
1459 ibp->z_port_rcv_packets = cntrs.port_rcv_packets;
1460 ibp->z_local_link_integrity_errors =
1461 cntrs.local_link_integrity_errors;
1462 ibp->z_excessive_buffer_overrun_errors =
1463 cntrs.excessive_buffer_overrun_errors;
1464 ibp->z_vl15_dropped = cntrs.vl15_dropped;
1465 RCU_INIT_POINTER(ibp->rvp.qp[0], NULL);
1466 RCU_INIT_POINTER(ibp->rvp.qp[1], NULL);
1467 }
1468
1469 /**
1470 * qib_fill_device_attr - Fill in rvt dev info device attributes.
1471 * @dd: the device data structure
1472 */
qib_fill_device_attr(struct qib_devdata * dd)1473 static void qib_fill_device_attr(struct qib_devdata *dd)
1474 {
1475 struct rvt_dev_info *rdi = &dd->verbs_dev.rdi;
1476
1477 memset(&rdi->dparms.props, 0, sizeof(rdi->dparms.props));
1478
1479 rdi->dparms.props.max_pd = ib_qib_max_pds;
1480 rdi->dparms.props.max_ah = ib_qib_max_ahs;
1481 rdi->dparms.props.device_cap_flags = IB_DEVICE_BAD_PKEY_CNTR |
1482 IB_DEVICE_BAD_QKEY_CNTR | IB_DEVICE_SHUTDOWN_PORT |
1483 IB_DEVICE_SYS_IMAGE_GUID | IB_DEVICE_RC_RNR_NAK_GEN |
1484 IB_DEVICE_PORT_ACTIVE_EVENT | IB_DEVICE_SRQ_RESIZE;
1485 rdi->dparms.props.page_size_cap = PAGE_SIZE;
1486 rdi->dparms.props.vendor_id =
1487 QIB_SRC_OUI_1 << 16 | QIB_SRC_OUI_2 << 8 | QIB_SRC_OUI_3;
1488 rdi->dparms.props.vendor_part_id = dd->deviceid;
1489 rdi->dparms.props.hw_ver = dd->minrev;
1490 rdi->dparms.props.sys_image_guid = ib_qib_sys_image_guid;
1491 rdi->dparms.props.max_mr_size = ~0ULL;
1492 rdi->dparms.props.max_qp = ib_qib_max_qps;
1493 rdi->dparms.props.max_qp_wr = ib_qib_max_qp_wrs;
1494 rdi->dparms.props.max_send_sge = ib_qib_max_sges;
1495 rdi->dparms.props.max_recv_sge = ib_qib_max_sges;
1496 rdi->dparms.props.max_sge_rd = ib_qib_max_sges;
1497 rdi->dparms.props.max_cq = ib_qib_max_cqs;
1498 rdi->dparms.props.max_cqe = ib_qib_max_cqes;
1499 rdi->dparms.props.max_ah = ib_qib_max_ahs;
1500 rdi->dparms.props.max_map_per_fmr = 32767;
1501 rdi->dparms.props.max_qp_rd_atom = QIB_MAX_RDMA_ATOMIC;
1502 rdi->dparms.props.max_qp_init_rd_atom = 255;
1503 rdi->dparms.props.max_srq = ib_qib_max_srqs;
1504 rdi->dparms.props.max_srq_wr = ib_qib_max_srq_wrs;
1505 rdi->dparms.props.max_srq_sge = ib_qib_max_srq_sges;
1506 rdi->dparms.props.atomic_cap = IB_ATOMIC_GLOB;
1507 rdi->dparms.props.max_pkeys = qib_get_npkeys(dd);
1508 rdi->dparms.props.max_mcast_grp = ib_qib_max_mcast_grps;
1509 rdi->dparms.props.max_mcast_qp_attach = ib_qib_max_mcast_qp_attached;
1510 rdi->dparms.props.max_total_mcast_qp_attach =
1511 rdi->dparms.props.max_mcast_qp_attach *
1512 rdi->dparms.props.max_mcast_grp;
1513 /* post send table */
1514 dd->verbs_dev.rdi.post_parms = qib_post_parms;
1515 }
1516
1517 /**
1518 * qib_register_ib_device - register our device with the infiniband core
1519 * @dd: the device data structure
1520 * Return the allocated qib_ibdev pointer or NULL on error.
1521 */
qib_register_ib_device(struct qib_devdata * dd)1522 int qib_register_ib_device(struct qib_devdata *dd)
1523 {
1524 struct qib_ibdev *dev = &dd->verbs_dev;
1525 struct ib_device *ibdev = &dev->rdi.ibdev;
1526 struct qib_pportdata *ppd = dd->pport;
1527 unsigned i, ctxt;
1528 int ret;
1529
1530 get_random_bytes(&dev->qp_rnd, sizeof(dev->qp_rnd));
1531 for (i = 0; i < dd->num_pports; i++)
1532 init_ibport(ppd + i);
1533
1534 /* Only need to initialize non-zero fields. */
1535 timer_setup(&dev->mem_timer, mem_timer, 0);
1536
1537 INIT_LIST_HEAD(&dev->piowait);
1538 INIT_LIST_HEAD(&dev->dmawait);
1539 INIT_LIST_HEAD(&dev->txwait);
1540 INIT_LIST_HEAD(&dev->memwait);
1541 INIT_LIST_HEAD(&dev->txreq_free);
1542
1543 if (ppd->sdma_descq_cnt) {
1544 dev->pio_hdrs = dma_alloc_coherent(&dd->pcidev->dev,
1545 ppd->sdma_descq_cnt *
1546 sizeof(struct qib_pio_header),
1547 &dev->pio_hdrs_phys,
1548 GFP_KERNEL);
1549 if (!dev->pio_hdrs) {
1550 ret = -ENOMEM;
1551 goto err_hdrs;
1552 }
1553 }
1554
1555 for (i = 0; i < ppd->sdma_descq_cnt; i++) {
1556 struct qib_verbs_txreq *tx;
1557
1558 tx = kzalloc(sizeof(*tx), GFP_KERNEL);
1559 if (!tx) {
1560 ret = -ENOMEM;
1561 goto err_tx;
1562 }
1563 tx->hdr_inx = i;
1564 list_add(&tx->txreq.list, &dev->txreq_free);
1565 }
1566
1567 /*
1568 * The system image GUID is supposed to be the same for all
1569 * IB HCAs in a single system but since there can be other
1570 * device types in the system, we can't be sure this is unique.
1571 */
1572 if (!ib_qib_sys_image_guid)
1573 ib_qib_sys_image_guid = ppd->guid;
1574
1575 ibdev->owner = THIS_MODULE;
1576 ibdev->node_guid = ppd->guid;
1577 ibdev->phys_port_cnt = dd->num_pports;
1578 ibdev->dev.parent = &dd->pcidev->dev;
1579 ibdev->modify_device = qib_modify_device;
1580 ibdev->process_mad = qib_process_mad;
1581
1582 snprintf(ibdev->node_desc, sizeof(ibdev->node_desc),
1583 "Intel Infiniband HCA %s", init_utsname()->nodename);
1584
1585 /*
1586 * Fill in rvt info object.
1587 */
1588 dd->verbs_dev.rdi.driver_f.port_callback = qib_create_port_files;
1589 dd->verbs_dev.rdi.driver_f.get_pci_dev = qib_get_pci_dev;
1590 dd->verbs_dev.rdi.driver_f.check_ah = qib_check_ah;
1591 dd->verbs_dev.rdi.driver_f.check_send_wqe = qib_check_send_wqe;
1592 dd->verbs_dev.rdi.driver_f.notify_new_ah = qib_notify_new_ah;
1593 dd->verbs_dev.rdi.driver_f.alloc_qpn = qib_alloc_qpn;
1594 dd->verbs_dev.rdi.driver_f.qp_priv_alloc = qib_qp_priv_alloc;
1595 dd->verbs_dev.rdi.driver_f.qp_priv_free = qib_qp_priv_free;
1596 dd->verbs_dev.rdi.driver_f.free_all_qps = qib_free_all_qps;
1597 dd->verbs_dev.rdi.driver_f.notify_qp_reset = qib_notify_qp_reset;
1598 dd->verbs_dev.rdi.driver_f.do_send = qib_do_send;
1599 dd->verbs_dev.rdi.driver_f.schedule_send = qib_schedule_send;
1600 dd->verbs_dev.rdi.driver_f.quiesce_qp = qib_quiesce_qp;
1601 dd->verbs_dev.rdi.driver_f.stop_send_queue = qib_stop_send_queue;
1602 dd->verbs_dev.rdi.driver_f.flush_qp_waiters = qib_flush_qp_waiters;
1603 dd->verbs_dev.rdi.driver_f.notify_error_qp = qib_notify_error_qp;
1604 dd->verbs_dev.rdi.driver_f.notify_restart_rc = qib_restart_rc;
1605 dd->verbs_dev.rdi.driver_f.mtu_to_path_mtu = qib_mtu_to_path_mtu;
1606 dd->verbs_dev.rdi.driver_f.mtu_from_qp = qib_mtu_from_qp;
1607 dd->verbs_dev.rdi.driver_f.get_pmtu_from_attr = qib_get_pmtu_from_attr;
1608 dd->verbs_dev.rdi.driver_f.schedule_send_no_lock = _qib_schedule_send;
1609 dd->verbs_dev.rdi.driver_f.query_port_state = qib_query_port;
1610 dd->verbs_dev.rdi.driver_f.shut_down_port = qib_shut_down_port;
1611 dd->verbs_dev.rdi.driver_f.cap_mask_chg = qib_cap_mask_chg;
1612 dd->verbs_dev.rdi.driver_f.notify_create_mad_agent =
1613 qib_notify_create_mad_agent;
1614 dd->verbs_dev.rdi.driver_f.notify_free_mad_agent =
1615 qib_notify_free_mad_agent;
1616
1617 dd->verbs_dev.rdi.dparms.max_rdma_atomic = QIB_MAX_RDMA_ATOMIC;
1618 dd->verbs_dev.rdi.driver_f.get_guid_be = qib_get_guid_be;
1619 dd->verbs_dev.rdi.dparms.lkey_table_size = qib_lkey_table_size;
1620 dd->verbs_dev.rdi.dparms.qp_table_size = ib_qib_qp_table_size;
1621 dd->verbs_dev.rdi.dparms.qpn_start = 1;
1622 dd->verbs_dev.rdi.dparms.qpn_res_start = QIB_KD_QP;
1623 dd->verbs_dev.rdi.dparms.qpn_res_end = QIB_KD_QP; /* Reserve one QP */
1624 dd->verbs_dev.rdi.dparms.qpn_inc = 1;
1625 dd->verbs_dev.rdi.dparms.qos_shift = 1;
1626 dd->verbs_dev.rdi.dparms.psn_mask = QIB_PSN_MASK;
1627 dd->verbs_dev.rdi.dparms.psn_shift = QIB_PSN_SHIFT;
1628 dd->verbs_dev.rdi.dparms.psn_modify_mask = QIB_PSN_MASK;
1629 dd->verbs_dev.rdi.dparms.nports = dd->num_pports;
1630 dd->verbs_dev.rdi.dparms.npkeys = qib_get_npkeys(dd);
1631 dd->verbs_dev.rdi.dparms.node = dd->assigned_node_id;
1632 dd->verbs_dev.rdi.dparms.core_cap_flags = RDMA_CORE_PORT_IBA_IB;
1633 dd->verbs_dev.rdi.dparms.max_mad_size = IB_MGMT_MAD_SIZE;
1634
1635 qib_fill_device_attr(dd);
1636
1637 ppd = dd->pport;
1638 for (i = 0; i < dd->num_pports; i++, ppd++) {
1639 ctxt = ppd->hw_pidx;
1640 rvt_init_port(&dd->verbs_dev.rdi,
1641 &ppd->ibport_data.rvp,
1642 i,
1643 dd->rcd[ctxt]->pkeys);
1644 }
1645
1646 ret = rvt_register_device(&dd->verbs_dev.rdi, RDMA_DRIVER_QIB);
1647 if (ret)
1648 goto err_tx;
1649
1650 ret = qib_verbs_register_sysfs(dd);
1651 if (ret)
1652 goto err_class;
1653
1654 return ret;
1655
1656 err_class:
1657 rvt_unregister_device(&dd->verbs_dev.rdi);
1658 err_tx:
1659 while (!list_empty(&dev->txreq_free)) {
1660 struct list_head *l = dev->txreq_free.next;
1661 struct qib_verbs_txreq *tx;
1662
1663 list_del(l);
1664 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
1665 kfree(tx);
1666 }
1667 if (ppd->sdma_descq_cnt)
1668 dma_free_coherent(&dd->pcidev->dev,
1669 ppd->sdma_descq_cnt *
1670 sizeof(struct qib_pio_header),
1671 dev->pio_hdrs, dev->pio_hdrs_phys);
1672 err_hdrs:
1673 qib_dev_err(dd, "cannot register verbs: %d!\n", -ret);
1674 return ret;
1675 }
1676
qib_unregister_ib_device(struct qib_devdata * dd)1677 void qib_unregister_ib_device(struct qib_devdata *dd)
1678 {
1679 struct qib_ibdev *dev = &dd->verbs_dev;
1680
1681 qib_verbs_unregister_sysfs(dd);
1682
1683 rvt_unregister_device(&dd->verbs_dev.rdi);
1684
1685 if (!list_empty(&dev->piowait))
1686 qib_dev_err(dd, "piowait list not empty!\n");
1687 if (!list_empty(&dev->dmawait))
1688 qib_dev_err(dd, "dmawait list not empty!\n");
1689 if (!list_empty(&dev->txwait))
1690 qib_dev_err(dd, "txwait list not empty!\n");
1691 if (!list_empty(&dev->memwait))
1692 qib_dev_err(dd, "memwait list not empty!\n");
1693
1694 del_timer_sync(&dev->mem_timer);
1695 while (!list_empty(&dev->txreq_free)) {
1696 struct list_head *l = dev->txreq_free.next;
1697 struct qib_verbs_txreq *tx;
1698
1699 list_del(l);
1700 tx = list_entry(l, struct qib_verbs_txreq, txreq.list);
1701 kfree(tx);
1702 }
1703 if (dd->pport->sdma_descq_cnt)
1704 dma_free_coherent(&dd->pcidev->dev,
1705 dd->pport->sdma_descq_cnt *
1706 sizeof(struct qib_pio_header),
1707 dev->pio_hdrs, dev->pio_hdrs_phys);
1708 }
1709
1710 /**
1711 * _qib_schedule_send - schedule progress
1712 * @qp - the qp
1713 *
1714 * This schedules progress w/o regard to the s_flags.
1715 *
1716 * It is only used in post send, which doesn't hold
1717 * the s_lock.
1718 */
_qib_schedule_send(struct rvt_qp * qp)1719 void _qib_schedule_send(struct rvt_qp *qp)
1720 {
1721 struct qib_ibport *ibp =
1722 to_iport(qp->ibqp.device, qp->port_num);
1723 struct qib_pportdata *ppd = ppd_from_ibp(ibp);
1724 struct qib_qp_priv *priv = qp->priv;
1725
1726 queue_work(ppd->qib_wq, &priv->s_work);
1727 }
1728
1729 /**
1730 * qib_schedule_send - schedule progress
1731 * @qp - the qp
1732 *
1733 * This schedules qp progress. The s_lock
1734 * should be held.
1735 */
qib_schedule_send(struct rvt_qp * qp)1736 void qib_schedule_send(struct rvt_qp *qp)
1737 {
1738 if (qib_send_ok(qp))
1739 _qib_schedule_send(qp);
1740 }
1741