1 /*
2 * Driver for Analog Devices ADV748X video decoder and HDMI receiver
3 *
4 * Copyright (C) 2017 Renesas Electronics Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * Authors:
12 * Koji Matsuoka <koji.matsuoka.xm@renesas.com>
13 * Niklas Söderlund <niklas.soderlund@ragnatech.se>
14 * Kieran Bingham <kieran.bingham@ideasonboard.com>
15 *
16 * The ADV748x range of receivers have the following configurations:
17 *
18 * Analog HDMI MHL 4-Lane 1-Lane
19 * In In CSI CSI
20 * ADV7480 X X X
21 * ADV7481 X X X X X
22 * ADV7482 X X X X
23 */
24
25 #include <linux/i2c.h>
26
27 #ifndef _ADV748X_H_
28 #define _ADV748X_H_
29
30 enum adv748x_page {
31 ADV748X_PAGE_IO,
32 ADV748X_PAGE_DPLL,
33 ADV748X_PAGE_CP,
34 ADV748X_PAGE_HDMI,
35 ADV748X_PAGE_EDID,
36 ADV748X_PAGE_REPEATER,
37 ADV748X_PAGE_INFOFRAME,
38 ADV748X_PAGE_CBUS,
39 ADV748X_PAGE_CEC,
40 ADV748X_PAGE_SDP,
41 ADV748X_PAGE_TXB,
42 ADV748X_PAGE_TXA,
43 ADV748X_PAGE_MAX,
44
45 /* Fake pages for register sequences */
46 ADV748X_PAGE_WAIT, /* Wait x msec */
47 ADV748X_PAGE_EOR, /* End Mark */
48 };
49
50 /**
51 * enum adv748x_ports - Device tree port number definitions
52 *
53 * The ADV748X ports define the mapping between subdevices
54 * and the device tree specification
55 */
56 enum adv748x_ports {
57 ADV748X_PORT_AIN0 = 0,
58 ADV748X_PORT_AIN1 = 1,
59 ADV748X_PORT_AIN2 = 2,
60 ADV748X_PORT_AIN3 = 3,
61 ADV748X_PORT_AIN4 = 4,
62 ADV748X_PORT_AIN5 = 5,
63 ADV748X_PORT_AIN6 = 6,
64 ADV748X_PORT_AIN7 = 7,
65 ADV748X_PORT_HDMI = 8,
66 ADV748X_PORT_TTL = 9,
67 ADV748X_PORT_TXA = 10,
68 ADV748X_PORT_TXB = 11,
69 ADV748X_PORT_MAX = 12,
70 };
71
72 enum adv748x_csi2_pads {
73 ADV748X_CSI2_SINK,
74 ADV748X_CSI2_SOURCE,
75 ADV748X_CSI2_NR_PADS,
76 };
77
78 /* CSI2 transmitters can have 2 internal connections, HDMI/AFE */
79 #define ADV748X_CSI2_MAX_SUBDEVS 2
80
81 struct adv748x_csi2 {
82 struct adv748x_state *state;
83 struct v4l2_mbus_framefmt format;
84 unsigned int page;
85 unsigned int port;
86
87 struct media_pad pads[ADV748X_CSI2_NR_PADS];
88 struct v4l2_ctrl_handler ctrl_hdl;
89 struct v4l2_ctrl *pixel_rate;
90 struct v4l2_subdev sd;
91 };
92
93 #define notifier_to_csi2(n) container_of(n, struct adv748x_csi2, notifier)
94 #define adv748x_sd_to_csi2(sd) container_of(sd, struct adv748x_csi2, sd)
95 #define is_tx_enabled(_tx) ((_tx)->state->endpoints[(_tx)->port] != NULL)
96
97 enum adv748x_hdmi_pads {
98 ADV748X_HDMI_SINK,
99 ADV748X_HDMI_SOURCE,
100 ADV748X_HDMI_NR_PADS,
101 };
102
103 struct adv748x_hdmi {
104 struct media_pad pads[ADV748X_HDMI_NR_PADS];
105 struct v4l2_ctrl_handler ctrl_hdl;
106 struct v4l2_subdev sd;
107 struct v4l2_mbus_framefmt format;
108
109 struct v4l2_dv_timings timings;
110 struct v4l2_fract aspect_ratio;
111
112 struct {
113 u8 edid[512];
114 u32 present;
115 unsigned int blocks;
116 } edid;
117 };
118
119 #define adv748x_ctrl_to_hdmi(ctrl) \
120 container_of(ctrl->handler, struct adv748x_hdmi, ctrl_hdl)
121 #define adv748x_sd_to_hdmi(sd) container_of(sd, struct adv748x_hdmi, sd)
122
123 enum adv748x_afe_pads {
124 ADV748X_AFE_SINK_AIN0,
125 ADV748X_AFE_SINK_AIN1,
126 ADV748X_AFE_SINK_AIN2,
127 ADV748X_AFE_SINK_AIN3,
128 ADV748X_AFE_SINK_AIN4,
129 ADV748X_AFE_SINK_AIN5,
130 ADV748X_AFE_SINK_AIN6,
131 ADV748X_AFE_SINK_AIN7,
132 ADV748X_AFE_SOURCE,
133 ADV748X_AFE_NR_PADS,
134 };
135
136 struct adv748x_afe {
137 struct media_pad pads[ADV748X_AFE_NR_PADS];
138 struct v4l2_ctrl_handler ctrl_hdl;
139 struct v4l2_subdev sd;
140 struct v4l2_mbus_framefmt format;
141
142 bool streaming;
143 v4l2_std_id curr_norm;
144 unsigned int input;
145 };
146
147 #define adv748x_ctrl_to_afe(ctrl) \
148 container_of(ctrl->handler, struct adv748x_afe, ctrl_hdl)
149 #define adv748x_sd_to_afe(sd) container_of(sd, struct adv748x_afe, sd)
150
151 /**
152 * struct adv748x_state - State of ADV748X
153 * @dev: (OF) device
154 * @client: I2C client
155 * @mutex: protect global state
156 *
157 * @endpoints: parsed device node endpoints for each port
158 *
159 * @i2c_addresses I2C Page addresses
160 * @i2c_clients I2C clients for the page accesses
161 * @regmap regmap configuration pages.
162 *
163 * @hdmi: state of HDMI receiver context
164 * @afe: state of AFE receiver context
165 * @txa: state of TXA transmitter context
166 * @txb: state of TXB transmitter context
167 */
168 struct adv748x_state {
169 struct device *dev;
170 struct i2c_client *client;
171 struct mutex mutex;
172
173 struct device_node *endpoints[ADV748X_PORT_MAX];
174
175 struct i2c_client *i2c_clients[ADV748X_PAGE_MAX];
176 struct regmap *regmap[ADV748X_PAGE_MAX];
177
178 struct adv748x_hdmi hdmi;
179 struct adv748x_afe afe;
180 struct adv748x_csi2 txa;
181 struct adv748x_csi2 txb;
182 };
183
184 #define adv748x_hdmi_to_state(h) container_of(h, struct adv748x_state, hdmi)
185 #define adv748x_afe_to_state(a) container_of(a, struct adv748x_state, afe)
186
187 #define adv_err(a, fmt, arg...) dev_err(a->dev, fmt, ##arg)
188 #define adv_info(a, fmt, arg...) dev_info(a->dev, fmt, ##arg)
189 #define adv_dbg(a, fmt, arg...) dev_dbg(a->dev, fmt, ##arg)
190
191 /* Register Mappings */
192
193 /* IO Map */
194 #define ADV748X_IO_PD 0x00 /* power down controls */
195 #define ADV748X_IO_PD_RX_EN BIT(6)
196
197 #define ADV748X_IO_REG_04 0x04
198 #define ADV748X_IO_REG_04_FORCE_FR BIT(0) /* Force CP free-run */
199
200 #define ADV748X_IO_DATAPATH 0x03 /* datapath cntrl */
201 #define ADV748X_IO_DATAPATH_VFREQ_M 0x70
202 #define ADV748X_IO_DATAPATH_VFREQ_SHIFT 4
203
204 #define ADV748X_IO_VID_STD 0x05
205
206 #define ADV748X_IO_10 0x10 /* io_reg_10 */
207 #define ADV748X_IO_10_CSI4_EN BIT(7)
208 #define ADV748X_IO_10_CSI1_EN BIT(6)
209 #define ADV748X_IO_10_PIX_OUT_EN BIT(5)
210
211 #define ADV748X_IO_CHIP_REV_ID_1 0xdf
212 #define ADV748X_IO_CHIP_REV_ID_2 0xe0
213
214 #define ADV748X_IO_SLAVE_ADDR_BASE 0xf2
215
216 /* HDMI RX Map */
217 #define ADV748X_HDMI_LW1 0x07 /* line width_1 */
218 #define ADV748X_HDMI_LW1_VERT_FILTER BIT(7)
219 #define ADV748X_HDMI_LW1_DE_REGEN BIT(5)
220 #define ADV748X_HDMI_LW1_WIDTH_MASK 0x1fff
221
222 #define ADV748X_HDMI_F0H1 0x09 /* field0 height_1 */
223 #define ADV748X_HDMI_F0H1_HEIGHT_MASK 0x1fff
224
225 #define ADV748X_HDMI_F1H1 0x0b /* field1 height_1 */
226 #define ADV748X_HDMI_F1H1_INTERLACED BIT(5)
227
228 #define ADV748X_HDMI_HFRONT_PORCH 0x20 /* hsync_front_porch_1 */
229 #define ADV748X_HDMI_HFRONT_PORCH_MASK 0x1fff
230
231 #define ADV748X_HDMI_HSYNC_WIDTH 0x22 /* hsync_pulse_width_1 */
232 #define ADV748X_HDMI_HSYNC_WIDTH_MASK 0x1fff
233
234 #define ADV748X_HDMI_HBACK_PORCH 0x24 /* hsync_back_porch_1 */
235 #define ADV748X_HDMI_HBACK_PORCH_MASK 0x1fff
236
237 #define ADV748X_HDMI_VFRONT_PORCH 0x2a /* field0_vs_front_porch_1 */
238 #define ADV748X_HDMI_VFRONT_PORCH_MASK 0x3fff
239
240 #define ADV748X_HDMI_VSYNC_WIDTH 0x2e /* field0_vs_pulse_width_1 */
241 #define ADV748X_HDMI_VSYNC_WIDTH_MASK 0x3fff
242
243 #define ADV748X_HDMI_VBACK_PORCH 0x32 /* field0_vs_back_porch_1 */
244 #define ADV748X_HDMI_VBACK_PORCH_MASK 0x3fff
245
246 #define ADV748X_HDMI_TMDS_1 0x51 /* hdmi_reg_51 */
247 #define ADV748X_HDMI_TMDS_2 0x52 /* hdmi_reg_52 */
248
249 /* HDMI RX Repeater Map */
250 #define ADV748X_REPEATER_EDID_SZ 0x70 /* primary_edid_size */
251 #define ADV748X_REPEATER_EDID_SZ_SHIFT 4
252
253 #define ADV748X_REPEATER_EDID_CTL 0x74 /* hdcp edid controls */
254 #define ADV748X_REPEATER_EDID_CTL_EN BIT(0) /* man_edid_a_enable */
255
256 /* SDP Main Map */
257 #define ADV748X_SDP_INSEL 0x00 /* user_map_rw_reg_00 */
258
259 #define ADV748X_SDP_VID_SEL 0x02 /* user_map_rw_reg_02 */
260 #define ADV748X_SDP_VID_SEL_MASK 0xf0
261 #define ADV748X_SDP_VID_SEL_SHIFT 4
262
263 /* Contrast - Unsigned*/
264 #define ADV748X_SDP_CON 0x08 /* user_map_rw_reg_08 */
265 #define ADV748X_SDP_CON_MIN 0
266 #define ADV748X_SDP_CON_DEF 128
267 #define ADV748X_SDP_CON_MAX 255
268
269 /* Brightness - Signed */
270 #define ADV748X_SDP_BRI 0x0a /* user_map_rw_reg_0a */
271 #define ADV748X_SDP_BRI_MIN -128
272 #define ADV748X_SDP_BRI_DEF 0
273 #define ADV748X_SDP_BRI_MAX 127
274
275 /* Hue - Signed, inverted*/
276 #define ADV748X_SDP_HUE 0x0b /* user_map_rw_reg_0b */
277 #define ADV748X_SDP_HUE_MIN -127
278 #define ADV748X_SDP_HUE_DEF 0
279 #define ADV748X_SDP_HUE_MAX 128
280
281 /* Test Patterns / Default Values */
282 #define ADV748X_SDP_DEF 0x0c /* user_map_rw_reg_0c */
283 #define ADV748X_SDP_DEF_VAL_EN BIT(0) /* Force free run mode */
284 #define ADV748X_SDP_DEF_VAL_AUTO_EN BIT(1) /* Free run when no signal */
285
286 #define ADV748X_SDP_MAP_SEL 0x0e /* user_map_rw_reg_0e */
287 #define ADV748X_SDP_MAP_SEL_RO_MAIN 1
288
289 /* Free run pattern select */
290 #define ADV748X_SDP_FRP 0x14
291 #define ADV748X_SDP_FRP_MASK GENMASK(3, 1)
292
293 /* Saturation */
294 #define ADV748X_SDP_SD_SAT_U 0xe3 /* user_map_rw_reg_e3 */
295 #define ADV748X_SDP_SD_SAT_V 0xe4 /* user_map_rw_reg_e4 */
296 #define ADV748X_SDP_SAT_MIN 0
297 #define ADV748X_SDP_SAT_DEF 128
298 #define ADV748X_SDP_SAT_MAX 255
299
300 /* SDP RO Main Map */
301 #define ADV748X_SDP_RO_10 0x10
302 #define ADV748X_SDP_RO_10_IN_LOCK BIT(0)
303
304 /* CP Map */
305 #define ADV748X_CP_PAT_GEN 0x37 /* int_pat_gen_1 */
306 #define ADV748X_CP_PAT_GEN_EN BIT(7)
307
308 /* Contrast Control - Unsigned */
309 #define ADV748X_CP_CON 0x3a /* contrast_cntrl */
310 #define ADV748X_CP_CON_MIN 0 /* Minimum contrast */
311 #define ADV748X_CP_CON_DEF 128 /* Default */
312 #define ADV748X_CP_CON_MAX 255 /* Maximum contrast */
313
314 /* Saturation Control - Unsigned */
315 #define ADV748X_CP_SAT 0x3b /* saturation_cntrl */
316 #define ADV748X_CP_SAT_MIN 0 /* Minimum saturation */
317 #define ADV748X_CP_SAT_DEF 128 /* Default */
318 #define ADV748X_CP_SAT_MAX 255 /* Maximum saturation */
319
320 /* Brightness Control - Signed */
321 #define ADV748X_CP_BRI 0x3c /* brightness_cntrl */
322 #define ADV748X_CP_BRI_MIN -128 /* Luma is -512d */
323 #define ADV748X_CP_BRI_DEF 0 /* Luma is 0 */
324 #define ADV748X_CP_BRI_MAX 127 /* Luma is 508d */
325
326 /* Hue Control */
327 #define ADV748X_CP_HUE 0x3d /* hue_cntrl */
328 #define ADV748X_CP_HUE_MIN 0 /* -90 degree */
329 #define ADV748X_CP_HUE_DEF 0 /* -90 degree */
330 #define ADV748X_CP_HUE_MAX 255 /* +90 degree */
331
332 #define ADV748X_CP_VID_ADJ 0x3e /* vid_adj_0 */
333 #define ADV748X_CP_VID_ADJ_ENABLE BIT(7) /* Enable colour controls */
334
335 #define ADV748X_CP_DE_POS_HIGH 0x8b /* de_pos_adj_6 */
336 #define ADV748X_CP_DE_POS_HIGH_SET BIT(6)
337 #define ADV748X_CP_DE_POS_END_LOW 0x8c /* de_pos_adj_7 */
338 #define ADV748X_CP_DE_POS_START_LOW 0x8d /* de_pos_adj_8 */
339
340 #define ADV748X_CP_VID_ADJ_2 0x91
341 #define ADV748X_CP_VID_ADJ_2_INTERLACED BIT(6)
342 #define ADV748X_CP_VID_ADJ_2_INTERLACED_3D BIT(4)
343
344 #define ADV748X_CP_CLMP_POS 0xc9 /* clmp_pos_cntrl_4 */
345 #define ADV748X_CP_CLMP_POS_DIS_AUTO BIT(0) /* dis_auto_param_buff */
346
347 /* CSI : TXA/TXB Maps */
348 #define ADV748X_CSI_VC_REF 0x0d /* csi_tx_top_reg_0d */
349 #define ADV748X_CSI_VC_REF_SHIFT 6
350
351 #define ADV748X_CSI_FS_AS_LS 0x1e /* csi_tx_top_reg_1e */
352 #define ADV748X_CSI_FS_AS_LS_UNKNOWN BIT(6) /* Undocumented bit */
353
354 /* Register handling */
355
356 int adv748x_read(struct adv748x_state *state, u8 addr, u8 reg);
357 int adv748x_write(struct adv748x_state *state, u8 page, u8 reg, u8 value);
358 int adv748x_write_block(struct adv748x_state *state, int client_page,
359 unsigned int init_reg, const void *val,
360 size_t val_len);
361
362 #define io_read(s, r) adv748x_read(s, ADV748X_PAGE_IO, r)
363 #define io_write(s, r, v) adv748x_write(s, ADV748X_PAGE_IO, r, v)
364 #define io_clrset(s, r, m, v) io_write(s, r, (io_read(s, r) & ~(m)) | (v))
365
366 #define hdmi_read(s, r) adv748x_read(s, ADV748X_PAGE_HDMI, r)
367 #define hdmi_read16(s, r, m) (((hdmi_read(s, r) << 8) | hdmi_read(s, (r)+1)) & (m))
368 #define hdmi_write(s, r, v) adv748x_write(s, ADV748X_PAGE_HDMI, r, v)
369
370 #define repeater_read(s, r) adv748x_read(s, ADV748X_PAGE_REPEATER, r)
371 #define repeater_write(s, r, v) adv748x_write(s, ADV748X_PAGE_REPEATER, r, v)
372
373 #define sdp_read(s, r) adv748x_read(s, ADV748X_PAGE_SDP, r)
374 #define sdp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_SDP, r, v)
375 #define sdp_clrset(s, r, m, v) sdp_write(s, r, (sdp_read(s, r) & ~(m)) | (v))
376
377 #define cp_read(s, r) adv748x_read(s, ADV748X_PAGE_CP, r)
378 #define cp_write(s, r, v) adv748x_write(s, ADV748X_PAGE_CP, r, v)
379 #define cp_clrset(s, r, m, v) cp_write(s, r, (cp_read(s, r) & ~(m)) | (v))
380
381 #define txa_read(s, r) adv748x_read(s, ADV748X_PAGE_TXA, r)
382 #define txb_read(s, r) adv748x_read(s, ADV748X_PAGE_TXB, r)
383
384 #define tx_read(t, r) adv748x_read(t->state, t->page, r)
385 #define tx_write(t, r, v) adv748x_write(t->state, t->page, r, v)
386
adv748x_get_remote_sd(struct media_pad * pad)387 static inline struct v4l2_subdev *adv748x_get_remote_sd(struct media_pad *pad)
388 {
389 pad = media_entity_remote_pad(pad);
390 if (!pad)
391 return NULL;
392
393 return media_entity_to_v4l2_subdev(pad->entity);
394 }
395
396 void adv748x_subdev_init(struct v4l2_subdev *sd, struct adv748x_state *state,
397 const struct v4l2_subdev_ops *ops, u32 function,
398 const char *ident);
399
400 int adv748x_register_subdevs(struct adv748x_state *state,
401 struct v4l2_device *v4l2_dev);
402
403 int adv748x_txa_power(struct adv748x_state *state, bool on);
404 int adv748x_txb_power(struct adv748x_state *state, bool on);
405
406 int adv748x_afe_init(struct adv748x_afe *afe);
407 void adv748x_afe_cleanup(struct adv748x_afe *afe);
408
409 int adv748x_csi2_init(struct adv748x_state *state, struct adv748x_csi2 *tx);
410 void adv748x_csi2_cleanup(struct adv748x_csi2 *tx);
411 int adv748x_csi2_set_pixelrate(struct v4l2_subdev *sd, s64 rate);
412
413 int adv748x_hdmi_init(struct adv748x_hdmi *hdmi);
414 void adv748x_hdmi_cleanup(struct adv748x_hdmi *hdmi);
415
416 #endif /* _ADV748X_H_ */
417