1 /*
2 * Copyright (C) 2007-2010 Texas Instruments Inc
3 * Copyright (C) 2007 MontaVista Software, Inc.
4 *
5 * Andy Lowe (alowe@mvista.com), MontaVista Software
6 * - Initial version
7 * Murali Karicheri (mkaricheri@gmail.com), Texas Instruments Ltd.
8 * - ported to sub device interface
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation version 2.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 */
20 #include <linux/module.h>
21 #include <linux/mod_devicetable.h>
22 #include <linux/kernel.h>
23 #include <linux/interrupt.h>
24 #include <linux/platform_device.h>
25 #include <linux/clk.h>
26 #include <linux/slab.h>
27
28 #ifdef CONFIG_ARCH_DAVINCI
29 #include <mach/cputype.h>
30 #include <mach/hardware.h>
31 #endif
32
33 #include <media/davinci/vpss.h>
34 #include <media/v4l2-device.h>
35 #include <media/davinci/vpbe_types.h>
36 #include <media/davinci/vpbe_osd.h>
37
38 #include <linux/io.h>
39 #include "vpbe_osd_regs.h"
40
41 #define MODULE_NAME "davinci-vpbe-osd"
42
43 static const struct platform_device_id vpbe_osd_devtype[] = {
44 {
45 .name = DM644X_VPBE_OSD_SUBDEV_NAME,
46 .driver_data = VPBE_VERSION_1,
47 }, {
48 .name = DM365_VPBE_OSD_SUBDEV_NAME,
49 .driver_data = VPBE_VERSION_2,
50 }, {
51 .name = DM355_VPBE_OSD_SUBDEV_NAME,
52 .driver_data = VPBE_VERSION_3,
53 },
54 {
55 /* sentinel */
56 }
57 };
58
59 MODULE_DEVICE_TABLE(platform, vpbe_osd_devtype);
60
61 /* register access routines */
osd_read(struct osd_state * sd,u32 offset)62 static inline u32 osd_read(struct osd_state *sd, u32 offset)
63 {
64 struct osd_state *osd = sd;
65
66 return readl(osd->osd_base + offset);
67 }
68
osd_write(struct osd_state * sd,u32 val,u32 offset)69 static inline u32 osd_write(struct osd_state *sd, u32 val, u32 offset)
70 {
71 struct osd_state *osd = sd;
72
73 writel(val, osd->osd_base + offset);
74
75 return val;
76 }
77
osd_set(struct osd_state * sd,u32 mask,u32 offset)78 static inline u32 osd_set(struct osd_state *sd, u32 mask, u32 offset)
79 {
80 struct osd_state *osd = sd;
81
82 void __iomem *addr = osd->osd_base + offset;
83 u32 val = readl(addr) | mask;
84
85 writel(val, addr);
86
87 return val;
88 }
89
osd_clear(struct osd_state * sd,u32 mask,u32 offset)90 static inline u32 osd_clear(struct osd_state *sd, u32 mask, u32 offset)
91 {
92 struct osd_state *osd = sd;
93
94 void __iomem *addr = osd->osd_base + offset;
95 u32 val = readl(addr) & ~mask;
96
97 writel(val, addr);
98
99 return val;
100 }
101
osd_modify(struct osd_state * sd,u32 mask,u32 val,u32 offset)102 static inline u32 osd_modify(struct osd_state *sd, u32 mask, u32 val,
103 u32 offset)
104 {
105 struct osd_state *osd = sd;
106
107 void __iomem *addr = osd->osd_base + offset;
108 u32 new_val = (readl(addr) & ~mask) | (val & mask);
109
110 writel(new_val, addr);
111
112 return new_val;
113 }
114
115 /* define some macros for layer and pixfmt classification */
116 #define is_osd_win(layer) (((layer) == WIN_OSD0) || ((layer) == WIN_OSD1))
117 #define is_vid_win(layer) (((layer) == WIN_VID0) || ((layer) == WIN_VID1))
118 #define is_rgb_pixfmt(pixfmt) \
119 (((pixfmt) == PIXFMT_RGB565) || ((pixfmt) == PIXFMT_RGB888))
120 #define is_yc_pixfmt(pixfmt) \
121 (((pixfmt) == PIXFMT_YCBCRI) || ((pixfmt) == PIXFMT_YCRCBI) || \
122 ((pixfmt) == PIXFMT_NV12))
123 #define MAX_WIN_SIZE OSD_VIDWIN0XP_V0X
124 #define MAX_LINE_LENGTH (OSD_VIDWIN0OFST_V0LO << 5)
125
126 /**
127 * _osd_dm6446_vid0_pingpong() - field inversion fix for DM6446
128 * @sd: ptr to struct osd_state
129 * @field_inversion: inversion flag
130 * @fb_base_phys: frame buffer address
131 * @lconfig: ptr to layer config
132 *
133 * This routine implements a workaround for the field signal inversion silicon
134 * erratum described in Advisory 1.3.8 for the DM6446. The fb_base_phys and
135 * lconfig parameters apply to the vid0 window. This routine should be called
136 * whenever the vid0 layer configuration or start address is modified, or when
137 * the OSD field inversion setting is modified.
138 * Returns: 1 if the ping-pong buffers need to be toggled in the vsync isr, or
139 * 0 otherwise
140 */
_osd_dm6446_vid0_pingpong(struct osd_state * sd,int field_inversion,unsigned long fb_base_phys,const struct osd_layer_config * lconfig)141 static int _osd_dm6446_vid0_pingpong(struct osd_state *sd,
142 int field_inversion,
143 unsigned long fb_base_phys,
144 const struct osd_layer_config *lconfig)
145 {
146 struct osd_platform_data *pdata;
147
148 pdata = (struct osd_platform_data *)sd->dev->platform_data;
149 if (pdata != NULL && pdata->field_inv_wa_enable) {
150
151 if (!field_inversion || !lconfig->interlaced) {
152 osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
153 osd_write(sd, fb_base_phys & ~0x1F, OSD_PPVWIN0ADR);
154 osd_modify(sd, OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, 0,
155 OSD_MISCCTL);
156 return 0;
157 } else {
158 unsigned miscctl = OSD_MISCCTL_PPRV;
159
160 osd_write(sd,
161 (fb_base_phys & ~0x1F) - lconfig->line_length,
162 OSD_VIDWIN0ADR);
163 osd_write(sd,
164 (fb_base_phys & ~0x1F) + lconfig->line_length,
165 OSD_PPVWIN0ADR);
166 osd_modify(sd,
167 OSD_MISCCTL_PPSW | OSD_MISCCTL_PPRV, miscctl,
168 OSD_MISCCTL);
169
170 return 1;
171 }
172 }
173
174 return 0;
175 }
176
_osd_set_field_inversion(struct osd_state * sd,int enable)177 static void _osd_set_field_inversion(struct osd_state *sd, int enable)
178 {
179 unsigned fsinv = 0;
180
181 if (enable)
182 fsinv = OSD_MODE_FSINV;
183
184 osd_modify(sd, OSD_MODE_FSINV, fsinv, OSD_MODE);
185 }
186
_osd_set_blink_attribute(struct osd_state * sd,int enable,enum osd_blink_interval blink)187 static void _osd_set_blink_attribute(struct osd_state *sd, int enable,
188 enum osd_blink_interval blink)
189 {
190 u32 osdatrmd = 0;
191
192 if (enable) {
193 osdatrmd |= OSD_OSDATRMD_BLNK;
194 osdatrmd |= blink << OSD_OSDATRMD_BLNKINT_SHIFT;
195 }
196 /* caller must ensure that OSD1 is configured in attribute mode */
197 osd_modify(sd, OSD_OSDATRMD_BLNKINT | OSD_OSDATRMD_BLNK, osdatrmd,
198 OSD_OSDATRMD);
199 }
200
_osd_set_rom_clut(struct osd_state * sd,enum osd_rom_clut rom_clut)201 static void _osd_set_rom_clut(struct osd_state *sd,
202 enum osd_rom_clut rom_clut)
203 {
204 if (rom_clut == ROM_CLUT0)
205 osd_clear(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
206 else
207 osd_set(sd, OSD_MISCCTL_RSEL, OSD_MISCCTL);
208 }
209
_osd_set_palette_map(struct osd_state * sd,enum osd_win_layer osdwin,unsigned char pixel_value,unsigned char clut_index,enum osd_pix_format pixfmt)210 static void _osd_set_palette_map(struct osd_state *sd,
211 enum osd_win_layer osdwin,
212 unsigned char pixel_value,
213 unsigned char clut_index,
214 enum osd_pix_format pixfmt)
215 {
216 static const int map_2bpp[] = { 0, 5, 10, 15 };
217 static const int map_1bpp[] = { 0, 15 };
218 int bmp_offset;
219 int bmp_shift;
220 int bmp_mask;
221 int bmp_reg;
222
223 switch (pixfmt) {
224 case PIXFMT_1BPP:
225 bmp_reg = map_1bpp[pixel_value & 0x1];
226 break;
227 case PIXFMT_2BPP:
228 bmp_reg = map_2bpp[pixel_value & 0x3];
229 break;
230 case PIXFMT_4BPP:
231 bmp_reg = pixel_value & 0xf;
232 break;
233 default:
234 return;
235 }
236
237 switch (osdwin) {
238 case OSDWIN_OSD0:
239 bmp_offset = OSD_W0BMP01 + (bmp_reg >> 1) * sizeof(u32);
240 break;
241 case OSDWIN_OSD1:
242 bmp_offset = OSD_W1BMP01 + (bmp_reg >> 1) * sizeof(u32);
243 break;
244 default:
245 return;
246 }
247
248 if (bmp_reg & 1) {
249 bmp_shift = 8;
250 bmp_mask = 0xff << 8;
251 } else {
252 bmp_shift = 0;
253 bmp_mask = 0xff;
254 }
255
256 osd_modify(sd, bmp_mask, clut_index << bmp_shift, bmp_offset);
257 }
258
_osd_set_rec601_attenuation(struct osd_state * sd,enum osd_win_layer osdwin,int enable)259 static void _osd_set_rec601_attenuation(struct osd_state *sd,
260 enum osd_win_layer osdwin, int enable)
261 {
262 switch (osdwin) {
263 case OSDWIN_OSD0:
264 osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
265 enable ? OSD_OSDWIN0MD_ATN0E : 0,
266 OSD_OSDWIN0MD);
267 if (sd->vpbe_type == VPBE_VERSION_1)
268 osd_modify(sd, OSD_OSDWIN0MD_ATN0E,
269 enable ? OSD_OSDWIN0MD_ATN0E : 0,
270 OSD_OSDWIN0MD);
271 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
272 (sd->vpbe_type == VPBE_VERSION_2))
273 osd_modify(sd, OSD_EXTMODE_ATNOSD0EN,
274 enable ? OSD_EXTMODE_ATNOSD0EN : 0,
275 OSD_EXTMODE);
276 break;
277 case OSDWIN_OSD1:
278 osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
279 enable ? OSD_OSDWIN1MD_ATN1E : 0,
280 OSD_OSDWIN1MD);
281 if (sd->vpbe_type == VPBE_VERSION_1)
282 osd_modify(sd, OSD_OSDWIN1MD_ATN1E,
283 enable ? OSD_OSDWIN1MD_ATN1E : 0,
284 OSD_OSDWIN1MD);
285 else if ((sd->vpbe_type == VPBE_VERSION_3) ||
286 (sd->vpbe_type == VPBE_VERSION_2))
287 osd_modify(sd, OSD_EXTMODE_ATNOSD1EN,
288 enable ? OSD_EXTMODE_ATNOSD1EN : 0,
289 OSD_EXTMODE);
290 break;
291 }
292 }
293
_osd_set_blending_factor(struct osd_state * sd,enum osd_win_layer osdwin,enum osd_blending_factor blend)294 static void _osd_set_blending_factor(struct osd_state *sd,
295 enum osd_win_layer osdwin,
296 enum osd_blending_factor blend)
297 {
298 switch (osdwin) {
299 case OSDWIN_OSD0:
300 osd_modify(sd, OSD_OSDWIN0MD_BLND0,
301 blend << OSD_OSDWIN0MD_BLND0_SHIFT, OSD_OSDWIN0MD);
302 break;
303 case OSDWIN_OSD1:
304 osd_modify(sd, OSD_OSDWIN1MD_BLND1,
305 blend << OSD_OSDWIN1MD_BLND1_SHIFT, OSD_OSDWIN1MD);
306 break;
307 }
308 }
309
_osd_enable_rgb888_pixblend(struct osd_state * sd,enum osd_win_layer osdwin)310 static void _osd_enable_rgb888_pixblend(struct osd_state *sd,
311 enum osd_win_layer osdwin)
312 {
313
314 osd_modify(sd, OSD_MISCCTL_BLDSEL, 0, OSD_MISCCTL);
315 switch (osdwin) {
316 case OSDWIN_OSD0:
317 osd_modify(sd, OSD_EXTMODE_OSD0BLDCHR,
318 OSD_EXTMODE_OSD0BLDCHR, OSD_EXTMODE);
319 break;
320 case OSDWIN_OSD1:
321 osd_modify(sd, OSD_EXTMODE_OSD1BLDCHR,
322 OSD_EXTMODE_OSD1BLDCHR, OSD_EXTMODE);
323 break;
324 }
325 }
326
_osd_enable_color_key(struct osd_state * sd,enum osd_win_layer osdwin,unsigned colorkey,enum osd_pix_format pixfmt)327 static void _osd_enable_color_key(struct osd_state *sd,
328 enum osd_win_layer osdwin,
329 unsigned colorkey,
330 enum osd_pix_format pixfmt)
331 {
332 switch (pixfmt) {
333 case PIXFMT_1BPP:
334 case PIXFMT_2BPP:
335 case PIXFMT_4BPP:
336 case PIXFMT_8BPP:
337 if (sd->vpbe_type == VPBE_VERSION_3) {
338 switch (osdwin) {
339 case OSDWIN_OSD0:
340 osd_modify(sd, OSD_TRANSPBMPIDX_BMP0,
341 colorkey <<
342 OSD_TRANSPBMPIDX_BMP0_SHIFT,
343 OSD_TRANSPBMPIDX);
344 break;
345 case OSDWIN_OSD1:
346 osd_modify(sd, OSD_TRANSPBMPIDX_BMP1,
347 colorkey <<
348 OSD_TRANSPBMPIDX_BMP1_SHIFT,
349 OSD_TRANSPBMPIDX);
350 break;
351 }
352 }
353 break;
354 case PIXFMT_RGB565:
355 if (sd->vpbe_type == VPBE_VERSION_1)
356 osd_write(sd, colorkey & OSD_TRANSPVAL_RGBTRANS,
357 OSD_TRANSPVAL);
358 else if (sd->vpbe_type == VPBE_VERSION_3)
359 osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
360 OSD_TRANSPVALL);
361 break;
362 case PIXFMT_YCBCRI:
363 case PIXFMT_YCRCBI:
364 if (sd->vpbe_type == VPBE_VERSION_3)
365 osd_modify(sd, OSD_TRANSPVALU_Y, colorkey,
366 OSD_TRANSPVALU);
367 break;
368 case PIXFMT_RGB888:
369 if (sd->vpbe_type == VPBE_VERSION_3) {
370 osd_write(sd, colorkey & OSD_TRANSPVALL_RGBL,
371 OSD_TRANSPVALL);
372 osd_modify(sd, OSD_TRANSPVALU_RGBU, colorkey >> 16,
373 OSD_TRANSPVALU);
374 }
375 break;
376 default:
377 break;
378 }
379
380 switch (osdwin) {
381 case OSDWIN_OSD0:
382 osd_set(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
383 break;
384 case OSDWIN_OSD1:
385 osd_set(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
386 break;
387 }
388 }
389
_osd_disable_color_key(struct osd_state * sd,enum osd_win_layer osdwin)390 static void _osd_disable_color_key(struct osd_state *sd,
391 enum osd_win_layer osdwin)
392 {
393 switch (osdwin) {
394 case OSDWIN_OSD0:
395 osd_clear(sd, OSD_OSDWIN0MD_TE0, OSD_OSDWIN0MD);
396 break;
397 case OSDWIN_OSD1:
398 osd_clear(sd, OSD_OSDWIN1MD_TE1, OSD_OSDWIN1MD);
399 break;
400 }
401 }
402
_osd_set_osd_clut(struct osd_state * sd,enum osd_win_layer osdwin,enum osd_clut clut)403 static void _osd_set_osd_clut(struct osd_state *sd,
404 enum osd_win_layer osdwin,
405 enum osd_clut clut)
406 {
407 u32 winmd = 0;
408
409 switch (osdwin) {
410 case OSDWIN_OSD0:
411 if (clut == RAM_CLUT)
412 winmd |= OSD_OSDWIN0MD_CLUTS0;
413 osd_modify(sd, OSD_OSDWIN0MD_CLUTS0, winmd, OSD_OSDWIN0MD);
414 break;
415 case OSDWIN_OSD1:
416 if (clut == RAM_CLUT)
417 winmd |= OSD_OSDWIN1MD_CLUTS1;
418 osd_modify(sd, OSD_OSDWIN1MD_CLUTS1, winmd, OSD_OSDWIN1MD);
419 break;
420 }
421 }
422
_osd_set_zoom(struct osd_state * sd,enum osd_layer layer,enum osd_zoom_factor h_zoom,enum osd_zoom_factor v_zoom)423 static void _osd_set_zoom(struct osd_state *sd, enum osd_layer layer,
424 enum osd_zoom_factor h_zoom,
425 enum osd_zoom_factor v_zoom)
426 {
427 u32 winmd = 0;
428
429 switch (layer) {
430 case WIN_OSD0:
431 winmd |= (h_zoom << OSD_OSDWIN0MD_OHZ0_SHIFT);
432 winmd |= (v_zoom << OSD_OSDWIN0MD_OVZ0_SHIFT);
433 osd_modify(sd, OSD_OSDWIN0MD_OHZ0 | OSD_OSDWIN0MD_OVZ0, winmd,
434 OSD_OSDWIN0MD);
435 break;
436 case WIN_VID0:
437 winmd |= (h_zoom << OSD_VIDWINMD_VHZ0_SHIFT);
438 winmd |= (v_zoom << OSD_VIDWINMD_VVZ0_SHIFT);
439 osd_modify(sd, OSD_VIDWINMD_VHZ0 | OSD_VIDWINMD_VVZ0, winmd,
440 OSD_VIDWINMD);
441 break;
442 case WIN_OSD1:
443 winmd |= (h_zoom << OSD_OSDWIN1MD_OHZ1_SHIFT);
444 winmd |= (v_zoom << OSD_OSDWIN1MD_OVZ1_SHIFT);
445 osd_modify(sd, OSD_OSDWIN1MD_OHZ1 | OSD_OSDWIN1MD_OVZ1, winmd,
446 OSD_OSDWIN1MD);
447 break;
448 case WIN_VID1:
449 winmd |= (h_zoom << OSD_VIDWINMD_VHZ1_SHIFT);
450 winmd |= (v_zoom << OSD_VIDWINMD_VVZ1_SHIFT);
451 osd_modify(sd, OSD_VIDWINMD_VHZ1 | OSD_VIDWINMD_VVZ1, winmd,
452 OSD_VIDWINMD);
453 break;
454 }
455 }
456
_osd_disable_layer(struct osd_state * sd,enum osd_layer layer)457 static void _osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
458 {
459 switch (layer) {
460 case WIN_OSD0:
461 osd_clear(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
462 break;
463 case WIN_VID0:
464 osd_clear(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
465 break;
466 case WIN_OSD1:
467 /* disable attribute mode as well as disabling the window */
468 osd_clear(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
469 OSD_OSDWIN1MD);
470 break;
471 case WIN_VID1:
472 osd_clear(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
473 break;
474 }
475 }
476
osd_disable_layer(struct osd_state * sd,enum osd_layer layer)477 static void osd_disable_layer(struct osd_state *sd, enum osd_layer layer)
478 {
479 struct osd_state *osd = sd;
480 struct osd_window_state *win = &osd->win[layer];
481 unsigned long flags;
482
483 spin_lock_irqsave(&osd->lock, flags);
484
485 if (!win->is_enabled) {
486 spin_unlock_irqrestore(&osd->lock, flags);
487 return;
488 }
489 win->is_enabled = 0;
490
491 _osd_disable_layer(sd, layer);
492
493 spin_unlock_irqrestore(&osd->lock, flags);
494 }
495
_osd_enable_attribute_mode(struct osd_state * sd)496 static void _osd_enable_attribute_mode(struct osd_state *sd)
497 {
498 /* enable attribute mode for OSD1 */
499 osd_set(sd, OSD_OSDWIN1MD_OASW, OSD_OSDWIN1MD);
500 }
501
_osd_enable_layer(struct osd_state * sd,enum osd_layer layer)502 static void _osd_enable_layer(struct osd_state *sd, enum osd_layer layer)
503 {
504 switch (layer) {
505 case WIN_OSD0:
506 osd_set(sd, OSD_OSDWIN0MD_OACT0, OSD_OSDWIN0MD);
507 break;
508 case WIN_VID0:
509 osd_set(sd, OSD_VIDWINMD_ACT0, OSD_VIDWINMD);
510 break;
511 case WIN_OSD1:
512 /* enable OSD1 and disable attribute mode */
513 osd_modify(sd, OSD_OSDWIN1MD_OASW | OSD_OSDWIN1MD_OACT1,
514 OSD_OSDWIN1MD_OACT1, OSD_OSDWIN1MD);
515 break;
516 case WIN_VID1:
517 osd_set(sd, OSD_VIDWINMD_ACT1, OSD_VIDWINMD);
518 break;
519 }
520 }
521
osd_enable_layer(struct osd_state * sd,enum osd_layer layer,int otherwin)522 static int osd_enable_layer(struct osd_state *sd, enum osd_layer layer,
523 int otherwin)
524 {
525 struct osd_state *osd = sd;
526 struct osd_window_state *win = &osd->win[layer];
527 struct osd_layer_config *cfg = &win->lconfig;
528 unsigned long flags;
529
530 spin_lock_irqsave(&osd->lock, flags);
531
532 /*
533 * use otherwin flag to know this is the other vid window
534 * in YUV420 mode, if is, skip this check
535 */
536 if (!otherwin && (!win->is_allocated ||
537 !win->fb_base_phys ||
538 !cfg->line_length ||
539 !cfg->xsize ||
540 !cfg->ysize)) {
541 spin_unlock_irqrestore(&osd->lock, flags);
542 return -1;
543 }
544
545 if (win->is_enabled) {
546 spin_unlock_irqrestore(&osd->lock, flags);
547 return 0;
548 }
549 win->is_enabled = 1;
550
551 if (cfg->pixfmt != PIXFMT_OSD_ATTR)
552 _osd_enable_layer(sd, layer);
553 else {
554 _osd_enable_attribute_mode(sd);
555 _osd_set_blink_attribute(sd, osd->is_blinking, osd->blink);
556 }
557
558 spin_unlock_irqrestore(&osd->lock, flags);
559
560 return 0;
561 }
562
563 #define OSD_SRC_ADDR_HIGH4 0x7800000
564 #define OSD_SRC_ADDR_HIGH7 0x7F0000
565 #define OSD_SRCADD_OFSET_SFT 23
566 #define OSD_SRCADD_ADD_SFT 16
567 #define OSD_WINADL_MASK 0xFFFF
568 #define OSD_WINOFST_MASK 0x1000
569 #define VPBE_REG_BASE 0x80000000
570
_osd_start_layer(struct osd_state * sd,enum osd_layer layer,unsigned long fb_base_phys,unsigned long cbcr_ofst)571 static void _osd_start_layer(struct osd_state *sd, enum osd_layer layer,
572 unsigned long fb_base_phys,
573 unsigned long cbcr_ofst)
574 {
575
576 if (sd->vpbe_type == VPBE_VERSION_1) {
577 switch (layer) {
578 case WIN_OSD0:
579 osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN0ADR);
580 break;
581 case WIN_VID0:
582 osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN0ADR);
583 break;
584 case WIN_OSD1:
585 osd_write(sd, fb_base_phys & ~0x1F, OSD_OSDWIN1ADR);
586 break;
587 case WIN_VID1:
588 osd_write(sd, fb_base_phys & ~0x1F, OSD_VIDWIN1ADR);
589 break;
590 }
591 } else if (sd->vpbe_type == VPBE_VERSION_3) {
592 unsigned long fb_offset_32 =
593 (fb_base_phys - VPBE_REG_BASE) >> 5;
594
595 switch (layer) {
596 case WIN_OSD0:
597 osd_modify(sd, OSD_OSDWINADH_O0AH,
598 fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
599 OSD_OSDWINADH_O0AH_SHIFT),
600 OSD_OSDWINADH);
601 osd_write(sd, fb_offset_32 & OSD_OSDWIN0ADL_O0AL,
602 OSD_OSDWIN0ADL);
603 break;
604 case WIN_VID0:
605 osd_modify(sd, OSD_VIDWINADH_V0AH,
606 fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
607 OSD_VIDWINADH_V0AH_SHIFT),
608 OSD_VIDWINADH);
609 osd_write(sd, fb_offset_32 & OSD_VIDWIN0ADL_V0AL,
610 OSD_VIDWIN0ADL);
611 break;
612 case WIN_OSD1:
613 osd_modify(sd, OSD_OSDWINADH_O1AH,
614 fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
615 OSD_OSDWINADH_O1AH_SHIFT),
616 OSD_OSDWINADH);
617 osd_write(sd, fb_offset_32 & OSD_OSDWIN1ADL_O1AL,
618 OSD_OSDWIN1ADL);
619 break;
620 case WIN_VID1:
621 osd_modify(sd, OSD_VIDWINADH_V1AH,
622 fb_offset_32 >> (OSD_SRCADD_ADD_SFT -
623 OSD_VIDWINADH_V1AH_SHIFT),
624 OSD_VIDWINADH);
625 osd_write(sd, fb_offset_32 & OSD_VIDWIN1ADL_V1AL,
626 OSD_VIDWIN1ADL);
627 break;
628 }
629 } else if (sd->vpbe_type == VPBE_VERSION_2) {
630 struct osd_window_state *win = &sd->win[layer];
631 unsigned long fb_offset_32, cbcr_offset_32;
632
633 fb_offset_32 = fb_base_phys - VPBE_REG_BASE;
634 if (cbcr_ofst)
635 cbcr_offset_32 = cbcr_ofst;
636 else
637 cbcr_offset_32 = win->lconfig.line_length *
638 win->lconfig.ysize;
639 cbcr_offset_32 += fb_offset_32;
640 fb_offset_32 = fb_offset_32 >> 5;
641 cbcr_offset_32 = cbcr_offset_32 >> 5;
642 /*
643 * DM365: start address is 27-bit long address b26 - b23 are
644 * in offset register b12 - b9, and * bit 26 has to be '1'
645 */
646 if (win->lconfig.pixfmt == PIXFMT_NV12) {
647 switch (layer) {
648 case WIN_VID0:
649 case WIN_VID1:
650 /* Y is in VID0 */
651 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
652 ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
653 (OSD_SRCADD_OFSET_SFT -
654 OSD_WINOFST_AH_SHIFT)) |
655 OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
656 osd_modify(sd, OSD_VIDWINADH_V0AH,
657 (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
658 (OSD_SRCADD_ADD_SFT -
659 OSD_VIDWINADH_V0AH_SHIFT),
660 OSD_VIDWINADH);
661 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
662 OSD_VIDWIN0ADL);
663 /* CbCr is in VID1 */
664 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
665 ((cbcr_offset_32 &
666 OSD_SRC_ADDR_HIGH4) >>
667 (OSD_SRCADD_OFSET_SFT -
668 OSD_WINOFST_AH_SHIFT)) |
669 OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
670 osd_modify(sd, OSD_VIDWINADH_V1AH,
671 (cbcr_offset_32 &
672 OSD_SRC_ADDR_HIGH7) >>
673 (OSD_SRCADD_ADD_SFT -
674 OSD_VIDWINADH_V1AH_SHIFT),
675 OSD_VIDWINADH);
676 osd_write(sd, cbcr_offset_32 & OSD_WINADL_MASK,
677 OSD_VIDWIN1ADL);
678 break;
679 default:
680 break;
681 }
682 }
683
684 switch (layer) {
685 case WIN_OSD0:
686 osd_modify(sd, OSD_OSDWIN0OFST_O0AH,
687 ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
688 (OSD_SRCADD_OFSET_SFT -
689 OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
690 OSD_OSDWIN0OFST);
691 osd_modify(sd, OSD_OSDWINADH_O0AH,
692 (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
693 (OSD_SRCADD_ADD_SFT -
694 OSD_OSDWINADH_O0AH_SHIFT), OSD_OSDWINADH);
695 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
696 OSD_OSDWIN0ADL);
697 break;
698 case WIN_VID0:
699 if (win->lconfig.pixfmt != PIXFMT_NV12) {
700 osd_modify(sd, OSD_VIDWIN0OFST_V0AH,
701 ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
702 (OSD_SRCADD_OFSET_SFT -
703 OSD_WINOFST_AH_SHIFT)) |
704 OSD_WINOFST_MASK, OSD_VIDWIN0OFST);
705 osd_modify(sd, OSD_VIDWINADH_V0AH,
706 (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
707 (OSD_SRCADD_ADD_SFT -
708 OSD_VIDWINADH_V0AH_SHIFT),
709 OSD_VIDWINADH);
710 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
711 OSD_VIDWIN0ADL);
712 }
713 break;
714 case WIN_OSD1:
715 osd_modify(sd, OSD_OSDWIN1OFST_O1AH,
716 ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
717 (OSD_SRCADD_OFSET_SFT -
718 OSD_WINOFST_AH_SHIFT)) | OSD_WINOFST_MASK,
719 OSD_OSDWIN1OFST);
720 osd_modify(sd, OSD_OSDWINADH_O1AH,
721 (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
722 (OSD_SRCADD_ADD_SFT -
723 OSD_OSDWINADH_O1AH_SHIFT),
724 OSD_OSDWINADH);
725 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
726 OSD_OSDWIN1ADL);
727 break;
728 case WIN_VID1:
729 if (win->lconfig.pixfmt != PIXFMT_NV12) {
730 osd_modify(sd, OSD_VIDWIN1OFST_V1AH,
731 ((fb_offset_32 & OSD_SRC_ADDR_HIGH4) >>
732 (OSD_SRCADD_OFSET_SFT -
733 OSD_WINOFST_AH_SHIFT)) |
734 OSD_WINOFST_MASK, OSD_VIDWIN1OFST);
735 osd_modify(sd, OSD_VIDWINADH_V1AH,
736 (fb_offset_32 & OSD_SRC_ADDR_HIGH7) >>
737 (OSD_SRCADD_ADD_SFT -
738 OSD_VIDWINADH_V1AH_SHIFT),
739 OSD_VIDWINADH);
740 osd_write(sd, fb_offset_32 & OSD_WINADL_MASK,
741 OSD_VIDWIN1ADL);
742 }
743 break;
744 }
745 }
746 }
747
osd_start_layer(struct osd_state * sd,enum osd_layer layer,unsigned long fb_base_phys,unsigned long cbcr_ofst)748 static void osd_start_layer(struct osd_state *sd, enum osd_layer layer,
749 unsigned long fb_base_phys,
750 unsigned long cbcr_ofst)
751 {
752 struct osd_state *osd = sd;
753 struct osd_window_state *win = &osd->win[layer];
754 struct osd_layer_config *cfg = &win->lconfig;
755 unsigned long flags;
756
757 spin_lock_irqsave(&osd->lock, flags);
758
759 win->fb_base_phys = fb_base_phys & ~0x1F;
760 _osd_start_layer(sd, layer, fb_base_phys, cbcr_ofst);
761
762 if (layer == WIN_VID0) {
763 osd->pingpong =
764 _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
765 win->fb_base_phys,
766 cfg);
767 }
768
769 spin_unlock_irqrestore(&osd->lock, flags);
770 }
771
osd_get_layer_config(struct osd_state * sd,enum osd_layer layer,struct osd_layer_config * lconfig)772 static void osd_get_layer_config(struct osd_state *sd, enum osd_layer layer,
773 struct osd_layer_config *lconfig)
774 {
775 struct osd_state *osd = sd;
776 struct osd_window_state *win = &osd->win[layer];
777 unsigned long flags;
778
779 spin_lock_irqsave(&osd->lock, flags);
780
781 *lconfig = win->lconfig;
782
783 spin_unlock_irqrestore(&osd->lock, flags);
784 }
785
786 /**
787 * try_layer_config() - Try a specific configuration for the layer
788 * @sd: ptr to struct osd_state
789 * @layer: layer to configure
790 * @lconfig: layer configuration to try
791 *
792 * If the requested lconfig is completely rejected and the value of lconfig on
793 * exit is the current lconfig, then try_layer_config() returns 1. Otherwise,
794 * try_layer_config() returns 0. A return value of 0 does not necessarily mean
795 * that the value of lconfig on exit is identical to the value of lconfig on
796 * entry, but merely that it represents a change from the current lconfig.
797 */
try_layer_config(struct osd_state * sd,enum osd_layer layer,struct osd_layer_config * lconfig)798 static int try_layer_config(struct osd_state *sd, enum osd_layer layer,
799 struct osd_layer_config *lconfig)
800 {
801 struct osd_state *osd = sd;
802 struct osd_window_state *win = &osd->win[layer];
803 int bad_config = 0;
804
805 /* verify that the pixel format is compatible with the layer */
806 switch (lconfig->pixfmt) {
807 case PIXFMT_1BPP:
808 case PIXFMT_2BPP:
809 case PIXFMT_4BPP:
810 case PIXFMT_8BPP:
811 case PIXFMT_RGB565:
812 if (osd->vpbe_type == VPBE_VERSION_1)
813 bad_config = !is_vid_win(layer);
814 break;
815 case PIXFMT_YCBCRI:
816 case PIXFMT_YCRCBI:
817 bad_config = !is_vid_win(layer);
818 break;
819 case PIXFMT_RGB888:
820 if (osd->vpbe_type == VPBE_VERSION_1)
821 bad_config = !is_vid_win(layer);
822 else if ((osd->vpbe_type == VPBE_VERSION_3) ||
823 (osd->vpbe_type == VPBE_VERSION_2))
824 bad_config = !is_osd_win(layer);
825 break;
826 case PIXFMT_NV12:
827 if (osd->vpbe_type != VPBE_VERSION_2)
828 bad_config = 1;
829 else
830 bad_config = is_osd_win(layer);
831 break;
832 case PIXFMT_OSD_ATTR:
833 bad_config = (layer != WIN_OSD1);
834 break;
835 default:
836 bad_config = 1;
837 break;
838 }
839 if (bad_config) {
840 /*
841 * The requested pixel format is incompatible with the layer,
842 * so keep the current layer configuration.
843 */
844 *lconfig = win->lconfig;
845 return bad_config;
846 }
847
848 /* DM6446: */
849 /* only one OSD window at a time can use RGB pixel formats */
850 if ((osd->vpbe_type == VPBE_VERSION_1) &&
851 is_osd_win(layer) && is_rgb_pixfmt(lconfig->pixfmt)) {
852 enum osd_pix_format pixfmt;
853
854 if (layer == WIN_OSD0)
855 pixfmt = osd->win[WIN_OSD1].lconfig.pixfmt;
856 else
857 pixfmt = osd->win[WIN_OSD0].lconfig.pixfmt;
858
859 if (is_rgb_pixfmt(pixfmt)) {
860 /*
861 * The other OSD window is already configured for an
862 * RGB, so keep the current layer configuration.
863 */
864 *lconfig = win->lconfig;
865 return 1;
866 }
867 }
868
869 /* DM6446: only one video window at a time can use RGB888 */
870 if ((osd->vpbe_type == VPBE_VERSION_1) && is_vid_win(layer) &&
871 lconfig->pixfmt == PIXFMT_RGB888) {
872 enum osd_pix_format pixfmt;
873
874 if (layer == WIN_VID0)
875 pixfmt = osd->win[WIN_VID1].lconfig.pixfmt;
876 else
877 pixfmt = osd->win[WIN_VID0].lconfig.pixfmt;
878
879 if (pixfmt == PIXFMT_RGB888) {
880 /*
881 * The other video window is already configured for
882 * RGB888, so keep the current layer configuration.
883 */
884 *lconfig = win->lconfig;
885 return 1;
886 }
887 }
888
889 /* window dimensions must be non-zero */
890 if (!lconfig->line_length || !lconfig->xsize || !lconfig->ysize) {
891 *lconfig = win->lconfig;
892 return 1;
893 }
894
895 /* round line_length up to a multiple of 32 */
896 lconfig->line_length = ((lconfig->line_length + 31) / 32) * 32;
897 lconfig->line_length =
898 min(lconfig->line_length, (unsigned)MAX_LINE_LENGTH);
899 lconfig->xsize = min(lconfig->xsize, (unsigned)MAX_WIN_SIZE);
900 lconfig->ysize = min(lconfig->ysize, (unsigned)MAX_WIN_SIZE);
901 lconfig->xpos = min(lconfig->xpos, (unsigned)MAX_WIN_SIZE);
902 lconfig->ypos = min(lconfig->ypos, (unsigned)MAX_WIN_SIZE);
903 lconfig->interlaced = (lconfig->interlaced != 0);
904 if (lconfig->interlaced) {
905 /* ysize and ypos must be even for interlaced displays */
906 lconfig->ysize &= ~1;
907 lconfig->ypos &= ~1;
908 }
909
910 return 0;
911 }
912
_osd_disable_vid_rgb888(struct osd_state * sd)913 static void _osd_disable_vid_rgb888(struct osd_state *sd)
914 {
915 /*
916 * The DM6446 supports RGB888 pixel format in a single video window.
917 * This routine disables RGB888 pixel format for both video windows.
918 * The caller must ensure that neither video window is currently
919 * configured for RGB888 pixel format.
920 */
921 if (sd->vpbe_type == VPBE_VERSION_1)
922 osd_clear(sd, OSD_MISCCTL_RGBEN, OSD_MISCCTL);
923 }
924
_osd_enable_vid_rgb888(struct osd_state * sd,enum osd_layer layer)925 static void _osd_enable_vid_rgb888(struct osd_state *sd,
926 enum osd_layer layer)
927 {
928 /*
929 * The DM6446 supports RGB888 pixel format in a single video window.
930 * This routine enables RGB888 pixel format for the specified video
931 * window. The caller must ensure that the other video window is not
932 * currently configured for RGB888 pixel format, as this routine will
933 * disable RGB888 pixel format for the other window.
934 */
935 if (sd->vpbe_type == VPBE_VERSION_1) {
936 if (layer == WIN_VID0)
937 osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
938 OSD_MISCCTL_RGBEN, OSD_MISCCTL);
939 else if (layer == WIN_VID1)
940 osd_modify(sd, OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
941 OSD_MISCCTL_RGBEN | OSD_MISCCTL_RGBWIN,
942 OSD_MISCCTL);
943 }
944 }
945
_osd_set_cbcr_order(struct osd_state * sd,enum osd_pix_format pixfmt)946 static void _osd_set_cbcr_order(struct osd_state *sd,
947 enum osd_pix_format pixfmt)
948 {
949 /*
950 * The caller must ensure that all windows using YC pixfmt use the same
951 * Cb/Cr order.
952 */
953 if (pixfmt == PIXFMT_YCBCRI)
954 osd_clear(sd, OSD_MODE_CS, OSD_MODE);
955 else if (pixfmt == PIXFMT_YCRCBI)
956 osd_set(sd, OSD_MODE_CS, OSD_MODE);
957 }
958
_osd_set_layer_config(struct osd_state * sd,enum osd_layer layer,const struct osd_layer_config * lconfig)959 static void _osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
960 const struct osd_layer_config *lconfig)
961 {
962 u32 winmd = 0, winmd_mask = 0, bmw = 0;
963
964 _osd_set_cbcr_order(sd, lconfig->pixfmt);
965
966 switch (layer) {
967 case WIN_OSD0:
968 if (sd->vpbe_type == VPBE_VERSION_1) {
969 winmd_mask |= OSD_OSDWIN0MD_RGB0E;
970 if (lconfig->pixfmt == PIXFMT_RGB565)
971 winmd |= OSD_OSDWIN0MD_RGB0E;
972 } else if ((sd->vpbe_type == VPBE_VERSION_3) ||
973 (sd->vpbe_type == VPBE_VERSION_2)) {
974 winmd_mask |= OSD_OSDWIN0MD_BMP0MD;
975 switch (lconfig->pixfmt) {
976 case PIXFMT_RGB565:
977 winmd |= (1 <<
978 OSD_OSDWIN0MD_BMP0MD_SHIFT);
979 break;
980 case PIXFMT_RGB888:
981 winmd |= (2 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
982 _osd_enable_rgb888_pixblend(sd, OSDWIN_OSD0);
983 break;
984 case PIXFMT_YCBCRI:
985 case PIXFMT_YCRCBI:
986 winmd |= (3 << OSD_OSDWIN0MD_BMP0MD_SHIFT);
987 break;
988 default:
989 break;
990 }
991 }
992
993 winmd_mask |= OSD_OSDWIN0MD_BMW0 | OSD_OSDWIN0MD_OFF0;
994
995 switch (lconfig->pixfmt) {
996 case PIXFMT_1BPP:
997 bmw = 0;
998 break;
999 case PIXFMT_2BPP:
1000 bmw = 1;
1001 break;
1002 case PIXFMT_4BPP:
1003 bmw = 2;
1004 break;
1005 case PIXFMT_8BPP:
1006 bmw = 3;
1007 break;
1008 default:
1009 break;
1010 }
1011 winmd |= (bmw << OSD_OSDWIN0MD_BMW0_SHIFT);
1012
1013 if (lconfig->interlaced)
1014 winmd |= OSD_OSDWIN0MD_OFF0;
1015
1016 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN0MD);
1017 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN0OFST);
1018 osd_write(sd, lconfig->xpos, OSD_OSDWIN0XP);
1019 osd_write(sd, lconfig->xsize, OSD_OSDWIN0XL);
1020 if (lconfig->interlaced) {
1021 osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN0YP);
1022 osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN0YL);
1023 } else {
1024 osd_write(sd, lconfig->ypos, OSD_OSDWIN0YP);
1025 osd_write(sd, lconfig->ysize, OSD_OSDWIN0YL);
1026 }
1027 break;
1028 case WIN_VID0:
1029 winmd_mask |= OSD_VIDWINMD_VFF0;
1030 if (lconfig->interlaced)
1031 winmd |= OSD_VIDWINMD_VFF0;
1032
1033 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1034 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN0OFST);
1035 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1036 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1037 /*
1038 * For YUV420P format the register contents are
1039 * duplicated in both VID registers
1040 */
1041 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1042 (lconfig->pixfmt == PIXFMT_NV12)) {
1043 /* other window also */
1044 if (lconfig->interlaced) {
1045 winmd_mask |= OSD_VIDWINMD_VFF1;
1046 winmd |= OSD_VIDWINMD_VFF1;
1047 osd_modify(sd, winmd_mask, winmd,
1048 OSD_VIDWINMD);
1049 }
1050
1051 osd_modify(sd, OSD_MISCCTL_S420D,
1052 OSD_MISCCTL_S420D, OSD_MISCCTL);
1053 osd_write(sd, lconfig->line_length >> 5,
1054 OSD_VIDWIN1OFST);
1055 osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1056 osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1057 /*
1058 * if NV21 pixfmt and line length not 32B
1059 * aligned (e.g. NTSC), Need to set window
1060 * X pixel size to be 32B aligned as well
1061 */
1062 if (lconfig->xsize % 32) {
1063 osd_write(sd,
1064 ((lconfig->xsize + 31) & ~31),
1065 OSD_VIDWIN1XL);
1066 osd_write(sd,
1067 ((lconfig->xsize + 31) & ~31),
1068 OSD_VIDWIN0XL);
1069 }
1070 } else if ((sd->vpbe_type == VPBE_VERSION_2) &&
1071 (lconfig->pixfmt != PIXFMT_NV12)) {
1072 osd_modify(sd, OSD_MISCCTL_S420D, ~OSD_MISCCTL_S420D,
1073 OSD_MISCCTL);
1074 }
1075
1076 if (lconfig->interlaced) {
1077 osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN0YP);
1078 osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN0YL);
1079 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1080 lconfig->pixfmt == PIXFMT_NV12) {
1081 osd_write(sd, lconfig->ypos >> 1,
1082 OSD_VIDWIN1YP);
1083 osd_write(sd, lconfig->ysize >> 1,
1084 OSD_VIDWIN1YL);
1085 }
1086 } else {
1087 osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1088 osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1089 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1090 lconfig->pixfmt == PIXFMT_NV12) {
1091 osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1092 osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1093 }
1094 }
1095 break;
1096 case WIN_OSD1:
1097 /*
1098 * The caller must ensure that OSD1 is disabled prior to
1099 * switching from a normal mode to attribute mode or from
1100 * attribute mode to a normal mode.
1101 */
1102 if (lconfig->pixfmt == PIXFMT_OSD_ATTR) {
1103 if (sd->vpbe_type == VPBE_VERSION_1) {
1104 winmd_mask |= OSD_OSDWIN1MD_ATN1E |
1105 OSD_OSDWIN1MD_RGB1E | OSD_OSDWIN1MD_CLUTS1 |
1106 OSD_OSDWIN1MD_BLND1 | OSD_OSDWIN1MD_TE1;
1107 } else {
1108 winmd_mask |= OSD_OSDWIN1MD_BMP1MD |
1109 OSD_OSDWIN1MD_CLUTS1 | OSD_OSDWIN1MD_BLND1 |
1110 OSD_OSDWIN1MD_TE1;
1111 }
1112 } else {
1113 if (sd->vpbe_type == VPBE_VERSION_1) {
1114 winmd_mask |= OSD_OSDWIN1MD_RGB1E;
1115 if (lconfig->pixfmt == PIXFMT_RGB565)
1116 winmd |= OSD_OSDWIN1MD_RGB1E;
1117 } else if ((sd->vpbe_type == VPBE_VERSION_3)
1118 || (sd->vpbe_type == VPBE_VERSION_2)) {
1119 winmd_mask |= OSD_OSDWIN1MD_BMP1MD;
1120 switch (lconfig->pixfmt) {
1121 case PIXFMT_RGB565:
1122 winmd |=
1123 (1 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1124 break;
1125 case PIXFMT_RGB888:
1126 winmd |=
1127 (2 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1128 _osd_enable_rgb888_pixblend(sd,
1129 OSDWIN_OSD1);
1130 break;
1131 case PIXFMT_YCBCRI:
1132 case PIXFMT_YCRCBI:
1133 winmd |=
1134 (3 << OSD_OSDWIN1MD_BMP1MD_SHIFT);
1135 break;
1136 default:
1137 break;
1138 }
1139 }
1140
1141 winmd_mask |= OSD_OSDWIN1MD_BMW1;
1142 switch (lconfig->pixfmt) {
1143 case PIXFMT_1BPP:
1144 bmw = 0;
1145 break;
1146 case PIXFMT_2BPP:
1147 bmw = 1;
1148 break;
1149 case PIXFMT_4BPP:
1150 bmw = 2;
1151 break;
1152 case PIXFMT_8BPP:
1153 bmw = 3;
1154 break;
1155 default:
1156 break;
1157 }
1158 winmd |= (bmw << OSD_OSDWIN1MD_BMW1_SHIFT);
1159 }
1160
1161 winmd_mask |= OSD_OSDWIN1MD_OFF1;
1162 if (lconfig->interlaced)
1163 winmd |= OSD_OSDWIN1MD_OFF1;
1164
1165 osd_modify(sd, winmd_mask, winmd, OSD_OSDWIN1MD);
1166 osd_write(sd, lconfig->line_length >> 5, OSD_OSDWIN1OFST);
1167 osd_write(sd, lconfig->xpos, OSD_OSDWIN1XP);
1168 osd_write(sd, lconfig->xsize, OSD_OSDWIN1XL);
1169 if (lconfig->interlaced) {
1170 osd_write(sd, lconfig->ypos >> 1, OSD_OSDWIN1YP);
1171 osd_write(sd, lconfig->ysize >> 1, OSD_OSDWIN1YL);
1172 } else {
1173 osd_write(sd, lconfig->ypos, OSD_OSDWIN1YP);
1174 osd_write(sd, lconfig->ysize, OSD_OSDWIN1YL);
1175 }
1176 break;
1177 case WIN_VID1:
1178 winmd_mask |= OSD_VIDWINMD_VFF1;
1179 if (lconfig->interlaced)
1180 winmd |= OSD_VIDWINMD_VFF1;
1181
1182 osd_modify(sd, winmd_mask, winmd, OSD_VIDWINMD);
1183 osd_write(sd, lconfig->line_length >> 5, OSD_VIDWIN1OFST);
1184 osd_write(sd, lconfig->xpos, OSD_VIDWIN1XP);
1185 osd_write(sd, lconfig->xsize, OSD_VIDWIN1XL);
1186 /*
1187 * For YUV420P format the register contents are
1188 * duplicated in both VID registers
1189 */
1190 if (sd->vpbe_type == VPBE_VERSION_2) {
1191 if (lconfig->pixfmt == PIXFMT_NV12) {
1192 /* other window also */
1193 if (lconfig->interlaced) {
1194 winmd_mask |= OSD_VIDWINMD_VFF0;
1195 winmd |= OSD_VIDWINMD_VFF0;
1196 osd_modify(sd, winmd_mask, winmd,
1197 OSD_VIDWINMD);
1198 }
1199 osd_modify(sd, OSD_MISCCTL_S420D,
1200 OSD_MISCCTL_S420D, OSD_MISCCTL);
1201 osd_write(sd, lconfig->line_length >> 5,
1202 OSD_VIDWIN0OFST);
1203 osd_write(sd, lconfig->xpos, OSD_VIDWIN0XP);
1204 osd_write(sd, lconfig->xsize, OSD_VIDWIN0XL);
1205 } else {
1206 osd_modify(sd, OSD_MISCCTL_S420D,
1207 ~OSD_MISCCTL_S420D, OSD_MISCCTL);
1208 }
1209 }
1210
1211 if (lconfig->interlaced) {
1212 osd_write(sd, lconfig->ypos >> 1, OSD_VIDWIN1YP);
1213 osd_write(sd, lconfig->ysize >> 1, OSD_VIDWIN1YL);
1214 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1215 lconfig->pixfmt == PIXFMT_NV12) {
1216 osd_write(sd, lconfig->ypos >> 1,
1217 OSD_VIDWIN0YP);
1218 osd_write(sd, lconfig->ysize >> 1,
1219 OSD_VIDWIN0YL);
1220 }
1221 } else {
1222 osd_write(sd, lconfig->ypos, OSD_VIDWIN1YP);
1223 osd_write(sd, lconfig->ysize, OSD_VIDWIN1YL);
1224 if ((sd->vpbe_type == VPBE_VERSION_2) &&
1225 lconfig->pixfmt == PIXFMT_NV12) {
1226 osd_write(sd, lconfig->ypos, OSD_VIDWIN0YP);
1227 osd_write(sd, lconfig->ysize, OSD_VIDWIN0YL);
1228 }
1229 }
1230 break;
1231 }
1232 }
1233
osd_set_layer_config(struct osd_state * sd,enum osd_layer layer,struct osd_layer_config * lconfig)1234 static int osd_set_layer_config(struct osd_state *sd, enum osd_layer layer,
1235 struct osd_layer_config *lconfig)
1236 {
1237 struct osd_state *osd = sd;
1238 struct osd_window_state *win = &osd->win[layer];
1239 struct osd_layer_config *cfg = &win->lconfig;
1240 unsigned long flags;
1241 int reject_config;
1242
1243 spin_lock_irqsave(&osd->lock, flags);
1244
1245 reject_config = try_layer_config(sd, layer, lconfig);
1246 if (reject_config) {
1247 spin_unlock_irqrestore(&osd->lock, flags);
1248 return reject_config;
1249 }
1250
1251 /* update the current Cb/Cr order */
1252 if (is_yc_pixfmt(lconfig->pixfmt))
1253 osd->yc_pixfmt = lconfig->pixfmt;
1254
1255 /*
1256 * If we are switching OSD1 from normal mode to attribute mode or from
1257 * attribute mode to normal mode, then we must disable the window.
1258 */
1259 if (layer == WIN_OSD1) {
1260 if (((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1261 (cfg->pixfmt != PIXFMT_OSD_ATTR)) ||
1262 ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1263 (cfg->pixfmt == PIXFMT_OSD_ATTR))) {
1264 win->is_enabled = 0;
1265 _osd_disable_layer(sd, layer);
1266 }
1267 }
1268
1269 _osd_set_layer_config(sd, layer, lconfig);
1270
1271 if (layer == WIN_OSD1) {
1272 struct osd_osdwin_state *osdwin_state =
1273 &osd->osdwin[OSDWIN_OSD1];
1274
1275 if ((lconfig->pixfmt != PIXFMT_OSD_ATTR) &&
1276 (cfg->pixfmt == PIXFMT_OSD_ATTR)) {
1277 /*
1278 * We just switched OSD1 from attribute mode to normal
1279 * mode, so we must initialize the CLUT select, the
1280 * blend factor, transparency colorkey enable, and
1281 * attenuation enable (DM6446 only) bits in the
1282 * OSDWIN1MD register.
1283 */
1284 _osd_set_osd_clut(sd, OSDWIN_OSD1,
1285 osdwin_state->clut);
1286 _osd_set_blending_factor(sd, OSDWIN_OSD1,
1287 osdwin_state->blend);
1288 if (osdwin_state->colorkey_blending) {
1289 _osd_enable_color_key(sd, OSDWIN_OSD1,
1290 osdwin_state->
1291 colorkey,
1292 lconfig->pixfmt);
1293 } else
1294 _osd_disable_color_key(sd, OSDWIN_OSD1);
1295 _osd_set_rec601_attenuation(sd, OSDWIN_OSD1,
1296 osdwin_state->
1297 rec601_attenuation);
1298 } else if ((lconfig->pixfmt == PIXFMT_OSD_ATTR) &&
1299 (cfg->pixfmt != PIXFMT_OSD_ATTR)) {
1300 /*
1301 * We just switched OSD1 from normal mode to attribute
1302 * mode, so we must initialize the blink enable and
1303 * blink interval bits in the OSDATRMD register.
1304 */
1305 _osd_set_blink_attribute(sd, osd->is_blinking,
1306 osd->blink);
1307 }
1308 }
1309
1310 /*
1311 * If we just switched to a 1-, 2-, or 4-bits-per-pixel bitmap format
1312 * then configure a default palette map.
1313 */
1314 if ((lconfig->pixfmt != cfg->pixfmt) &&
1315 ((lconfig->pixfmt == PIXFMT_1BPP) ||
1316 (lconfig->pixfmt == PIXFMT_2BPP) ||
1317 (lconfig->pixfmt == PIXFMT_4BPP))) {
1318 enum osd_win_layer osdwin =
1319 ((layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1);
1320 struct osd_osdwin_state *osdwin_state =
1321 &osd->osdwin[osdwin];
1322 unsigned char clut_index;
1323 unsigned char clut_entries = 0;
1324
1325 switch (lconfig->pixfmt) {
1326 case PIXFMT_1BPP:
1327 clut_entries = 2;
1328 break;
1329 case PIXFMT_2BPP:
1330 clut_entries = 4;
1331 break;
1332 case PIXFMT_4BPP:
1333 clut_entries = 16;
1334 break;
1335 default:
1336 break;
1337 }
1338 /*
1339 * The default palette map maps the pixel value to the clut
1340 * index, i.e. pixel value 0 maps to clut entry 0, pixel value
1341 * 1 maps to clut entry 1, etc.
1342 */
1343 for (clut_index = 0; clut_index < 16; clut_index++) {
1344 osdwin_state->palette_map[clut_index] = clut_index;
1345 if (clut_index < clut_entries) {
1346 _osd_set_palette_map(sd, osdwin, clut_index,
1347 clut_index,
1348 lconfig->pixfmt);
1349 }
1350 }
1351 }
1352
1353 *cfg = *lconfig;
1354 /* DM6446: configure the RGB888 enable and window selection */
1355 if (osd->win[WIN_VID0].lconfig.pixfmt == PIXFMT_RGB888)
1356 _osd_enable_vid_rgb888(sd, WIN_VID0);
1357 else if (osd->win[WIN_VID1].lconfig.pixfmt == PIXFMT_RGB888)
1358 _osd_enable_vid_rgb888(sd, WIN_VID1);
1359 else
1360 _osd_disable_vid_rgb888(sd);
1361
1362 if (layer == WIN_VID0) {
1363 osd->pingpong =
1364 _osd_dm6446_vid0_pingpong(sd, osd->field_inversion,
1365 win->fb_base_phys,
1366 cfg);
1367 }
1368
1369 spin_unlock_irqrestore(&osd->lock, flags);
1370
1371 return 0;
1372 }
1373
osd_init_layer(struct osd_state * sd,enum osd_layer layer)1374 static void osd_init_layer(struct osd_state *sd, enum osd_layer layer)
1375 {
1376 struct osd_state *osd = sd;
1377 struct osd_window_state *win = &osd->win[layer];
1378 enum osd_win_layer osdwin;
1379 struct osd_osdwin_state *osdwin_state;
1380 struct osd_layer_config *cfg = &win->lconfig;
1381 unsigned long flags;
1382
1383 spin_lock_irqsave(&osd->lock, flags);
1384
1385 win->is_enabled = 0;
1386 _osd_disable_layer(sd, layer);
1387
1388 win->h_zoom = ZOOM_X1;
1389 win->v_zoom = ZOOM_X1;
1390 _osd_set_zoom(sd, layer, win->h_zoom, win->v_zoom);
1391
1392 win->fb_base_phys = 0;
1393 _osd_start_layer(sd, layer, win->fb_base_phys, 0);
1394
1395 cfg->line_length = 0;
1396 cfg->xsize = 0;
1397 cfg->ysize = 0;
1398 cfg->xpos = 0;
1399 cfg->ypos = 0;
1400 cfg->interlaced = 0;
1401 switch (layer) {
1402 case WIN_OSD0:
1403 case WIN_OSD1:
1404 osdwin = (layer == WIN_OSD0) ? OSDWIN_OSD0 : OSDWIN_OSD1;
1405 osdwin_state = &osd->osdwin[osdwin];
1406 /*
1407 * Other code relies on the fact that OSD windows default to a
1408 * bitmap pixel format when they are deallocated, so don't
1409 * change this default pixel format.
1410 */
1411 cfg->pixfmt = PIXFMT_8BPP;
1412 _osd_set_layer_config(sd, layer, cfg);
1413 osdwin_state->clut = RAM_CLUT;
1414 _osd_set_osd_clut(sd, osdwin, osdwin_state->clut);
1415 osdwin_state->colorkey_blending = 0;
1416 _osd_disable_color_key(sd, osdwin);
1417 osdwin_state->blend = OSD_8_VID_0;
1418 _osd_set_blending_factor(sd, osdwin, osdwin_state->blend);
1419 osdwin_state->rec601_attenuation = 0;
1420 _osd_set_rec601_attenuation(sd, osdwin,
1421 osdwin_state->
1422 rec601_attenuation);
1423 if (osdwin == OSDWIN_OSD1) {
1424 osd->is_blinking = 0;
1425 osd->blink = BLINK_X1;
1426 }
1427 break;
1428 case WIN_VID0:
1429 case WIN_VID1:
1430 cfg->pixfmt = osd->yc_pixfmt;
1431 _osd_set_layer_config(sd, layer, cfg);
1432 break;
1433 }
1434
1435 spin_unlock_irqrestore(&osd->lock, flags);
1436 }
1437
osd_release_layer(struct osd_state * sd,enum osd_layer layer)1438 static void osd_release_layer(struct osd_state *sd, enum osd_layer layer)
1439 {
1440 struct osd_state *osd = sd;
1441 struct osd_window_state *win = &osd->win[layer];
1442 unsigned long flags;
1443
1444 spin_lock_irqsave(&osd->lock, flags);
1445
1446 if (!win->is_allocated) {
1447 spin_unlock_irqrestore(&osd->lock, flags);
1448 return;
1449 }
1450
1451 spin_unlock_irqrestore(&osd->lock, flags);
1452 osd_init_layer(sd, layer);
1453 spin_lock_irqsave(&osd->lock, flags);
1454
1455 win->is_allocated = 0;
1456
1457 spin_unlock_irqrestore(&osd->lock, flags);
1458 }
1459
osd_request_layer(struct osd_state * sd,enum osd_layer layer)1460 static int osd_request_layer(struct osd_state *sd, enum osd_layer layer)
1461 {
1462 struct osd_state *osd = sd;
1463 struct osd_window_state *win = &osd->win[layer];
1464 unsigned long flags;
1465
1466 spin_lock_irqsave(&osd->lock, flags);
1467
1468 if (win->is_allocated) {
1469 spin_unlock_irqrestore(&osd->lock, flags);
1470 return -1;
1471 }
1472 win->is_allocated = 1;
1473
1474 spin_unlock_irqrestore(&osd->lock, flags);
1475
1476 return 0;
1477 }
1478
_osd_init(struct osd_state * sd)1479 static void _osd_init(struct osd_state *sd)
1480 {
1481 osd_write(sd, 0, OSD_MODE);
1482 osd_write(sd, 0, OSD_VIDWINMD);
1483 osd_write(sd, 0, OSD_OSDWIN0MD);
1484 osd_write(sd, 0, OSD_OSDWIN1MD);
1485 osd_write(sd, 0, OSD_RECTCUR);
1486 osd_write(sd, 0, OSD_MISCCTL);
1487 if (sd->vpbe_type == VPBE_VERSION_3) {
1488 osd_write(sd, 0, OSD_VBNDRY);
1489 osd_write(sd, 0, OSD_EXTMODE);
1490 osd_write(sd, OSD_MISCCTL_DMANG, OSD_MISCCTL);
1491 }
1492 }
1493
osd_set_left_margin(struct osd_state * sd,u32 val)1494 static void osd_set_left_margin(struct osd_state *sd, u32 val)
1495 {
1496 osd_write(sd, val, OSD_BASEPX);
1497 }
1498
osd_set_top_margin(struct osd_state * sd,u32 val)1499 static void osd_set_top_margin(struct osd_state *sd, u32 val)
1500 {
1501 osd_write(sd, val, OSD_BASEPY);
1502 }
1503
osd_initialize(struct osd_state * osd)1504 static int osd_initialize(struct osd_state *osd)
1505 {
1506 if (osd == NULL)
1507 return -ENODEV;
1508 _osd_init(osd);
1509
1510 /* set default Cb/Cr order */
1511 osd->yc_pixfmt = PIXFMT_YCBCRI;
1512
1513 if (osd->vpbe_type == VPBE_VERSION_3) {
1514 /*
1515 * ROM CLUT1 on the DM355 is similar (identical?) to ROM CLUT0
1516 * on the DM6446, so make ROM_CLUT1 the default on the DM355.
1517 */
1518 osd->rom_clut = ROM_CLUT1;
1519 }
1520
1521 _osd_set_field_inversion(osd, osd->field_inversion);
1522 _osd_set_rom_clut(osd, osd->rom_clut);
1523
1524 osd_init_layer(osd, WIN_OSD0);
1525 osd_init_layer(osd, WIN_VID0);
1526 osd_init_layer(osd, WIN_OSD1);
1527 osd_init_layer(osd, WIN_VID1);
1528
1529 return 0;
1530 }
1531
1532 static const struct vpbe_osd_ops osd_ops = {
1533 .initialize = osd_initialize,
1534 .request_layer = osd_request_layer,
1535 .release_layer = osd_release_layer,
1536 .enable_layer = osd_enable_layer,
1537 .disable_layer = osd_disable_layer,
1538 .set_layer_config = osd_set_layer_config,
1539 .get_layer_config = osd_get_layer_config,
1540 .start_layer = osd_start_layer,
1541 .set_left_margin = osd_set_left_margin,
1542 .set_top_margin = osd_set_top_margin,
1543 };
1544
osd_probe(struct platform_device * pdev)1545 static int osd_probe(struct platform_device *pdev)
1546 {
1547 const struct platform_device_id *pdev_id;
1548 struct osd_state *osd;
1549 struct resource *res;
1550
1551 pdev_id = platform_get_device_id(pdev);
1552 if (!pdev_id)
1553 return -EINVAL;
1554
1555 osd = devm_kzalloc(&pdev->dev, sizeof(struct osd_state), GFP_KERNEL);
1556 if (osd == NULL)
1557 return -ENOMEM;
1558
1559
1560 osd->dev = &pdev->dev;
1561 osd->vpbe_type = pdev_id->driver_data;
1562
1563 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1564 osd->osd_base = devm_ioremap_resource(&pdev->dev, res);
1565 if (IS_ERR(osd->osd_base))
1566 return PTR_ERR(osd->osd_base);
1567
1568 osd->osd_base_phys = res->start;
1569 osd->osd_size = resource_size(res);
1570 spin_lock_init(&osd->lock);
1571 osd->ops = osd_ops;
1572 platform_set_drvdata(pdev, osd);
1573 dev_notice(osd->dev, "OSD sub device probe success\n");
1574
1575 return 0;
1576 }
1577
osd_remove(struct platform_device * pdev)1578 static int osd_remove(struct platform_device *pdev)
1579 {
1580 return 0;
1581 }
1582
1583 static struct platform_driver osd_driver = {
1584 .probe = osd_probe,
1585 .remove = osd_remove,
1586 .driver = {
1587 .name = MODULE_NAME,
1588 },
1589 .id_table = vpbe_osd_devtype
1590 };
1591
1592 module_platform_driver(osd_driver);
1593
1594 MODULE_LICENSE("GPL");
1595 MODULE_DESCRIPTION("DaVinci OSD Manager Driver");
1596 MODULE_AUTHOR("Texas Instruments");
1597