1 /*
2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Jacob Chen <jacob-chen@iotwrt.com>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/pm_runtime.h>
16
17 #include "rga-hw.h"
18 #include "rga.h"
19
20 enum e_rga_start_pos {
21 LT = 0,
22 LB = 1,
23 RT = 2,
24 RB = 3,
25 };
26
27 struct rga_addr_offset {
28 unsigned int y_off;
29 unsigned int u_off;
30 unsigned int v_off;
31 };
32
33 struct rga_corners_addr_offset {
34 struct rga_addr_offset left_top;
35 struct rga_addr_offset right_top;
36 struct rga_addr_offset left_bottom;
37 struct rga_addr_offset right_bottom;
38 };
39
rga_get_scaling(unsigned int src,unsigned int dst)40 static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
41 {
42 /*
43 * The rga hw scaling factor is a normalized inverse of the
44 * scaling factor.
45 * For example: When source width is 100 and destination width is 200
46 * (scaling of 2x), then the hw factor is NC * 100 / 200.
47 * The normalization factor (NC) is 2^16 = 0x10000.
48 */
49
50 return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
51 }
52
53 static struct rga_corners_addr_offset
rga_get_addr_offset(struct rga_frame * frm,unsigned int x,unsigned int y,unsigned int w,unsigned int h)54 rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
55 unsigned int w, unsigned int h)
56 {
57 struct rga_corners_addr_offset offsets;
58 struct rga_addr_offset *lt, *lb, *rt, *rb;
59 unsigned int x_div = 0,
60 y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
61
62 lt = &offsets.left_top;
63 lb = &offsets.left_bottom;
64 rt = &offsets.right_top;
65 rb = &offsets.right_bottom;
66
67 x_div = frm->fmt->x_div;
68 y_div = frm->fmt->y_div;
69 uv_factor = frm->fmt->uv_factor;
70 uv_stride = frm->stride / x_div;
71 pixel_width = frm->stride / frm->width;
72
73 lt->y_off = y * frm->stride + x * pixel_width;
74 lt->u_off =
75 frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
76 lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
77
78 lb->y_off = lt->y_off + (h - 1) * frm->stride;
79 lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
80 lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
81
82 rt->y_off = lt->y_off + (w - 1) * pixel_width;
83 rt->u_off = lt->u_off + w / x_div - 1;
84 rt->v_off = lt->v_off + w / x_div - 1;
85
86 rb->y_off = lb->y_off + (w - 1) * pixel_width;
87 rb->u_off = lb->u_off + w / x_div - 1;
88 rb->v_off = lb->v_off + w / x_div - 1;
89
90 return offsets;
91 }
92
rga_lookup_draw_pos(struct rga_corners_addr_offset * offsets,u32 rotate_mode,u32 mirr_mode)93 static struct rga_addr_offset *rga_lookup_draw_pos(struct
94 rga_corners_addr_offset
95 * offsets, u32 rotate_mode,
96 u32 mirr_mode)
97 {
98 static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
99 {
100 LT, RT, LB, RB,
101 },
102 {
103 RT, LT, RB, LB,
104 },
105 {
106 RB, LB, RT, LT,
107 },
108 {
109 LB, RB, LT, RT,
110 },
111 };
112
113 if (!offsets)
114 return NULL;
115
116 switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
117 case LT:
118 return &offsets->left_top;
119 case LB:
120 return &offsets->left_bottom;
121 case RT:
122 return &offsets->right_top;
123 case RB:
124 return &offsets->right_bottom;
125 }
126
127 return NULL;
128 }
129
rga_cmd_set_src_addr(struct rga_ctx * ctx,void * mmu_pages)130 static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
131 {
132 struct rockchip_rga *rga = ctx->rga;
133 u32 *dest = rga->cmdbuf_virt;
134 unsigned int reg;
135
136 reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
137 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
138
139 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
140 dest[reg >> 2] |= 0x7;
141 }
142
rga_cmd_set_src1_addr(struct rga_ctx * ctx,void * mmu_pages)143 static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
144 {
145 struct rockchip_rga *rga = ctx->rga;
146 u32 *dest = rga->cmdbuf_virt;
147 unsigned int reg;
148
149 reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
150 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
151
152 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
153 dest[reg >> 2] |= 0x7 << 4;
154 }
155
rga_cmd_set_dst_addr(struct rga_ctx * ctx,void * mmu_pages)156 static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
157 {
158 struct rockchip_rga *rga = ctx->rga;
159 u32 *dest = rga->cmdbuf_virt;
160 unsigned int reg;
161
162 reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
163 dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
164
165 reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
166 dest[reg >> 2] |= 0x7 << 8;
167 }
168
rga_cmd_set_trans_info(struct rga_ctx * ctx)169 static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
170 {
171 struct rockchip_rga *rga = ctx->rga;
172 u32 *dest = rga->cmdbuf_virt;
173 unsigned int scale_dst_w, scale_dst_h;
174 unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
175 union rga_src_info src_info;
176 union rga_dst_info dst_info;
177 union rga_src_x_factor x_factor;
178 union rga_src_y_factor y_factor;
179 union rga_src_vir_info src_vir_info;
180 union rga_src_act_info src_act_info;
181 union rga_dst_vir_info dst_vir_info;
182 union rga_dst_act_info dst_act_info;
183
184 struct rga_addr_offset *dst_offset;
185 struct rga_corners_addr_offset offsets;
186 struct rga_corners_addr_offset src_offsets;
187
188 src_h = ctx->in.crop.height;
189 src_w = ctx->in.crop.width;
190 src_x = ctx->in.crop.left;
191 src_y = ctx->in.crop.top;
192 dst_h = ctx->out.crop.height;
193 dst_w = ctx->out.crop.width;
194 dst_x = ctx->out.crop.left;
195 dst_y = ctx->out.crop.top;
196
197 src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
198 dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
199 x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
200 y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
201 src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
202 src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
203 dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
204 dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
205
206 src_info.data.format = ctx->in.fmt->hw_format;
207 src_info.data.swap = ctx->in.fmt->color_swap;
208 dst_info.data.format = ctx->out.fmt->hw_format;
209 dst_info.data.swap = ctx->out.fmt->color_swap;
210
211 /*
212 * CSC mode must only be set when the colorspace families differ between
213 * input and output. It must remain unset (zeroed) if both are the same.
214 */
215
216 if (RGA_COLOR_FMT_IS_YUV(ctx->in.fmt->hw_format) &&
217 RGA_COLOR_FMT_IS_RGB(ctx->out.fmt->hw_format)) {
218 switch (ctx->in.colorspace) {
219 case V4L2_COLORSPACE_REC709:
220 src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
221 break;
222 default:
223 src_info.data.csc_mode = RGA_SRC_CSC_MODE_BT601_R0;
224 break;
225 }
226 }
227
228 if (RGA_COLOR_FMT_IS_RGB(ctx->in.fmt->hw_format) &&
229 RGA_COLOR_FMT_IS_YUV(ctx->out.fmt->hw_format)) {
230 switch (ctx->out.colorspace) {
231 case V4L2_COLORSPACE_REC709:
232 dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
233 break;
234 default:
235 dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
236 break;
237 }
238 }
239
240 if (ctx->vflip)
241 src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
242
243 if (ctx->hflip)
244 src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
245
246 switch (ctx->rotate) {
247 case 90:
248 src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
249 break;
250 case 180:
251 src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
252 break;
253 case 270:
254 src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
255 break;
256 default:
257 src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
258 break;
259 }
260
261 /*
262 * Cacluate the up/down scaling mode/factor.
263 *
264 * RGA used to scale the picture first, and then rotate second,
265 * so we need to swap the w/h when rotate degree is 90/270.
266 */
267 if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
268 src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
269 if (rga->version.major == 0 || rga->version.minor == 0) {
270 if (dst_w == src_h)
271 src_h -= 8;
272 if (abs(src_w - dst_h) < 16)
273 src_w -= 16;
274 }
275
276 scale_dst_h = dst_w;
277 scale_dst_w = dst_h;
278 } else {
279 scale_dst_w = dst_w;
280 scale_dst_h = dst_h;
281 }
282
283 if (src_w == scale_dst_w) {
284 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
285 x_factor.val = 0;
286 } else if (src_w > scale_dst_w) {
287 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
288 x_factor.data.down_scale_factor =
289 rga_get_scaling(src_w, scale_dst_w) + 1;
290 } else {
291 src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
292 x_factor.data.up_scale_factor =
293 rga_get_scaling(src_w - 1, scale_dst_w - 1);
294 }
295
296 if (src_h == scale_dst_h) {
297 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
298 y_factor.val = 0;
299 } else if (src_h > scale_dst_h) {
300 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
301 y_factor.data.down_scale_factor =
302 rga_get_scaling(src_h, scale_dst_h) + 1;
303 } else {
304 src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
305 y_factor.data.up_scale_factor =
306 rga_get_scaling(src_h - 1, scale_dst_h - 1);
307 }
308
309 /*
310 * Cacluate the framebuffer virtual strides and active size,
311 * note that the step of vir_stride / vir_width is 4 byte words
312 */
313 src_vir_info.data.vir_stride = ctx->in.stride >> 2;
314 src_vir_info.data.vir_width = ctx->in.stride >> 2;
315
316 src_act_info.data.act_height = src_h - 1;
317 src_act_info.data.act_width = src_w - 1;
318
319 dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
320 dst_act_info.data.act_height = dst_h - 1;
321 dst_act_info.data.act_width = dst_w - 1;
322
323 /*
324 * Cacluate the source framebuffer base address with offset pixel.
325 */
326 src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
327 src_w, src_h);
328
329 /*
330 * Configure the dest framebuffer base address with pixel offset.
331 */
332 offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
333 dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
334 src_info.data.mir_mode);
335
336 dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
337 src_offsets.left_top.y_off;
338 dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
339 src_offsets.left_top.u_off;
340 dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
341 src_offsets.left_top.v_off;
342
343 dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
344 dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
345 dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
346 dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
347
348 dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
349
350 dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
351 dst_offset->y_off;
352 dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
353 dst_offset->u_off;
354 dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
355 dst_offset->v_off;
356
357 dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
358 dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
359
360 dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
361 }
362
rga_cmd_set_mode(struct rga_ctx * ctx)363 static void rga_cmd_set_mode(struct rga_ctx *ctx)
364 {
365 struct rockchip_rga *rga = ctx->rga;
366 u32 *dest = rga->cmdbuf_virt;
367 union rga_mode_ctrl mode;
368 union rga_alpha_ctrl0 alpha_ctrl0;
369 union rga_alpha_ctrl1 alpha_ctrl1;
370
371 mode.val = 0;
372 alpha_ctrl0.val = 0;
373 alpha_ctrl1.val = 0;
374
375 mode.data.gradient_sat = 1;
376 mode.data.render = RGA_MODE_RENDER_BITBLT;
377 mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
378
379 /* disable alpha blending */
380 dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
381 dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
382
383 dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
384 }
385
rga_cmd_set(struct rga_ctx * ctx)386 static void rga_cmd_set(struct rga_ctx *ctx)
387 {
388 struct rockchip_rga *rga = ctx->rga;
389
390 memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
391
392 rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
393 /*
394 * Due to hardware bug,
395 * src1 mmu also should be configured when using alpha blending.
396 */
397 rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
398
399 rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
400 rga_cmd_set_mode(ctx);
401
402 rga_cmd_set_trans_info(ctx);
403
404 rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
405
406 /* sync CMD buf for RGA */
407 dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
408 PAGE_SIZE, DMA_BIDIRECTIONAL);
409 }
410
rga_hw_start(struct rockchip_rga * rga)411 void rga_hw_start(struct rockchip_rga *rga)
412 {
413 struct rga_ctx *ctx = rga->curr;
414
415 rga_cmd_set(ctx);
416
417 rga_write(rga, RGA_SYS_CTRL, 0x00);
418
419 rga_write(rga, RGA_SYS_CTRL, 0x22);
420
421 rga_write(rga, RGA_INT, 0x600);
422
423 rga_write(rga, RGA_CMD_CTRL, 0x1);
424 }
425