1 /*
2 * GPMC support functions
3 *
4 * Copyright (C) 2005-2006 Nokia Corporation
5 *
6 * Author: Juha Yrjola
7 *
8 * Copyright (C) 2009 Texas Instruments
9 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15 #include <linux/irq.h>
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/err.h>
19 #include <linux/clk.h>
20 #include <linux/ioport.h>
21 #include <linux/spinlock.h>
22 #include <linux/io.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
25 #include <linux/interrupt.h>
26 #include <linux/irqdomain.h>
27 #include <linux/platform_device.h>
28 #include <linux/of.h>
29 #include <linux/of_address.h>
30 #include <linux/of_device.h>
31 #include <linux/of_platform.h>
32 #include <linux/omap-gpmc.h>
33 #include <linux/pm_runtime.h>
34
35 #include <linux/platform_data/mtd-nand-omap2.h>
36
37 #include <asm/mach-types.h>
38
39 #define DEVICE_NAME "omap-gpmc"
40
41 /* GPMC register offsets */
42 #define GPMC_REVISION 0x00
43 #define GPMC_SYSCONFIG 0x10
44 #define GPMC_SYSSTATUS 0x14
45 #define GPMC_IRQSTATUS 0x18
46 #define GPMC_IRQENABLE 0x1c
47 #define GPMC_TIMEOUT_CONTROL 0x40
48 #define GPMC_ERR_ADDRESS 0x44
49 #define GPMC_ERR_TYPE 0x48
50 #define GPMC_CONFIG 0x50
51 #define GPMC_STATUS 0x54
52 #define GPMC_PREFETCH_CONFIG1 0x1e0
53 #define GPMC_PREFETCH_CONFIG2 0x1e4
54 #define GPMC_PREFETCH_CONTROL 0x1ec
55 #define GPMC_PREFETCH_STATUS 0x1f0
56 #define GPMC_ECC_CONFIG 0x1f4
57 #define GPMC_ECC_CONTROL 0x1f8
58 #define GPMC_ECC_SIZE_CONFIG 0x1fc
59 #define GPMC_ECC1_RESULT 0x200
60 #define GPMC_ECC_BCH_RESULT_0 0x240 /* not available on OMAP2 */
61 #define GPMC_ECC_BCH_RESULT_1 0x244 /* not available on OMAP2 */
62 #define GPMC_ECC_BCH_RESULT_2 0x248 /* not available on OMAP2 */
63 #define GPMC_ECC_BCH_RESULT_3 0x24c /* not available on OMAP2 */
64 #define GPMC_ECC_BCH_RESULT_4 0x300 /* not available on OMAP2 */
65 #define GPMC_ECC_BCH_RESULT_5 0x304 /* not available on OMAP2 */
66 #define GPMC_ECC_BCH_RESULT_6 0x308 /* not available on OMAP2 */
67
68 /* GPMC ECC control settings */
69 #define GPMC_ECC_CTRL_ECCCLEAR 0x100
70 #define GPMC_ECC_CTRL_ECCDISABLE 0x000
71 #define GPMC_ECC_CTRL_ECCREG1 0x001
72 #define GPMC_ECC_CTRL_ECCREG2 0x002
73 #define GPMC_ECC_CTRL_ECCREG3 0x003
74 #define GPMC_ECC_CTRL_ECCREG4 0x004
75 #define GPMC_ECC_CTRL_ECCREG5 0x005
76 #define GPMC_ECC_CTRL_ECCREG6 0x006
77 #define GPMC_ECC_CTRL_ECCREG7 0x007
78 #define GPMC_ECC_CTRL_ECCREG8 0x008
79 #define GPMC_ECC_CTRL_ECCREG9 0x009
80
81 #define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
82
83 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS BIT(0)
84
85 #define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
86 #define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
87 #define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
88 #define GPMC_CONFIG4_WEEXTRADELAY BIT(23)
89 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN BIT(6)
90 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN BIT(7)
91
92 #define GPMC_CS0_OFFSET 0x60
93 #define GPMC_CS_SIZE 0x30
94 #define GPMC_BCH_SIZE 0x10
95
96 /*
97 * The first 1MB of GPMC address space is typically mapped to
98 * the internal ROM. Never allocate the first page, to
99 * facilitate bug detection; even if we didn't boot from ROM.
100 * As GPMC minimum partition size is 16MB we can only start from
101 * there.
102 */
103 #define GPMC_MEM_START 0x1000000
104 #define GPMC_MEM_END 0x3FFFFFFF
105
106 #define GPMC_CHUNK_SHIFT 24 /* 16 MB */
107 #define GPMC_SECTION_SHIFT 28 /* 128 MB */
108
109 #define CS_NUM_SHIFT 24
110 #define ENABLE_PREFETCH (0x1 << 7)
111 #define DMA_MPU_MODE 2
112
113 #define GPMC_REVISION_MAJOR(l) ((l >> 4) & 0xf)
114 #define GPMC_REVISION_MINOR(l) (l & 0xf)
115
116 #define GPMC_HAS_WR_ACCESS 0x1
117 #define GPMC_HAS_WR_DATA_MUX_BUS 0x2
118 #define GPMC_HAS_MUX_AAD 0x4
119
120 #define GPMC_NR_WAITPINS 4
121
122 #define GPMC_CS_CONFIG1 0x00
123 #define GPMC_CS_CONFIG2 0x04
124 #define GPMC_CS_CONFIG3 0x08
125 #define GPMC_CS_CONFIG4 0x0c
126 #define GPMC_CS_CONFIG5 0x10
127 #define GPMC_CS_CONFIG6 0x14
128 #define GPMC_CS_CONFIG7 0x18
129 #define GPMC_CS_NAND_COMMAND 0x1c
130 #define GPMC_CS_NAND_ADDRESS 0x20
131 #define GPMC_CS_NAND_DATA 0x24
132
133 /* Control Commands */
134 #define GPMC_CONFIG_RDY_BSY 0x00000001
135 #define GPMC_CONFIG_DEV_SIZE 0x00000002
136 #define GPMC_CONFIG_DEV_TYPE 0x00000003
137
138 #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
139 #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
140 #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
141 #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
142 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
143 #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
144 #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
145 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
146 /** CLKACTIVATIONTIME Max Ticks */
147 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
148 #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
149 /** ATTACHEDDEVICEPAGELENGTH Max Value */
150 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
151 #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
152 #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
153 #define GPMC_CONFIG1_WAIT_MON_TIME(val) ((val & 3) << 18)
154 /** WAITMONITORINGTIME Max Ticks */
155 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX 2
156 #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
157 #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
158 #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
159 /** DEVICESIZE Max Value */
160 #define GPMC_CONFIG1_DEVICESIZE_MAX 1
161 #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
162 #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
163 #define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
164 #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
165 #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
166 #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
167 #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
168 #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
169 #define GPMC_CONFIG7_CSVALID (1 << 6)
170
171 #define GPMC_CONFIG7_BASEADDRESS_MASK 0x3f
172 #define GPMC_CONFIG7_CSVALID_MASK BIT(6)
173 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
174 #define GPMC_CONFIG7_MASKADDRESS_MASK (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
175 /* All CONFIG7 bits except reserved bits */
176 #define GPMC_CONFIG7_MASK (GPMC_CONFIG7_BASEADDRESS_MASK | \
177 GPMC_CONFIG7_CSVALID_MASK | \
178 GPMC_CONFIG7_MASKADDRESS_MASK)
179
180 #define GPMC_DEVICETYPE_NOR 0
181 #define GPMC_DEVICETYPE_NAND 2
182 #define GPMC_CONFIG_WRITEPROTECT 0x00000010
183 #define WR_RD_PIN_MONITORING 0x00600000
184
185 /* ECC commands */
186 #define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
187 #define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
188 #define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
189
190 #define GPMC_NR_NAND_IRQS 2 /* number of NAND specific IRQs */
191
192 enum gpmc_clk_domain {
193 GPMC_CD_FCLK,
194 GPMC_CD_CLK
195 };
196
197 struct gpmc_cs_data {
198 const char *name;
199
200 #define GPMC_CS_RESERVED (1 << 0)
201 u32 flags;
202
203 struct resource mem;
204 };
205
206 /* Structure to save gpmc cs context */
207 struct gpmc_cs_config {
208 u32 config1;
209 u32 config2;
210 u32 config3;
211 u32 config4;
212 u32 config5;
213 u32 config6;
214 u32 config7;
215 int is_valid;
216 };
217
218 /*
219 * Structure to save/restore gpmc context
220 * to support core off on OMAP3
221 */
222 struct omap3_gpmc_regs {
223 u32 sysconfig;
224 u32 irqenable;
225 u32 timeout_ctrl;
226 u32 config;
227 u32 prefetch_config1;
228 u32 prefetch_config2;
229 u32 prefetch_control;
230 struct gpmc_cs_config cs_context[GPMC_CS_NUM];
231 };
232
233 struct gpmc_device {
234 struct device *dev;
235 int irq;
236 struct irq_chip irq_chip;
237 struct gpio_chip gpio_chip;
238 int nirqs;
239 };
240
241 static struct irq_domain *gpmc_irq_domain;
242
243 static struct resource gpmc_mem_root;
244 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
245 static DEFINE_SPINLOCK(gpmc_mem_lock);
246 /* Define chip-selects as reserved by default until probe completes */
247 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
248 static unsigned int gpmc_nr_waitpins;
249 static resource_size_t phys_base, mem_size;
250 static unsigned gpmc_capability;
251 static void __iomem *gpmc_base;
252
253 static struct clk *gpmc_l3_clk;
254
255 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
256
gpmc_write_reg(int idx,u32 val)257 static void gpmc_write_reg(int idx, u32 val)
258 {
259 writel_relaxed(val, gpmc_base + idx);
260 }
261
gpmc_read_reg(int idx)262 static u32 gpmc_read_reg(int idx)
263 {
264 return readl_relaxed(gpmc_base + idx);
265 }
266
gpmc_cs_write_reg(int cs,int idx,u32 val)267 void gpmc_cs_write_reg(int cs, int idx, u32 val)
268 {
269 void __iomem *reg_addr;
270
271 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
272 writel_relaxed(val, reg_addr);
273 }
274
gpmc_cs_read_reg(int cs,int idx)275 static u32 gpmc_cs_read_reg(int cs, int idx)
276 {
277 void __iomem *reg_addr;
278
279 reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
280 return readl_relaxed(reg_addr);
281 }
282
283 /* TODO: Add support for gpmc_fck to clock framework and use it */
gpmc_get_fclk_period(void)284 static unsigned long gpmc_get_fclk_period(void)
285 {
286 unsigned long rate = clk_get_rate(gpmc_l3_clk);
287
288 rate /= 1000;
289 rate = 1000000000 / rate; /* In picoseconds */
290
291 return rate;
292 }
293
294 /**
295 * gpmc_get_clk_period - get period of selected clock domain in ps
296 * @cs Chip Select Region.
297 * @cd Clock Domain.
298 *
299 * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
300 * prior to calling this function with GPMC_CD_CLK.
301 */
gpmc_get_clk_period(int cs,enum gpmc_clk_domain cd)302 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
303 {
304
305 unsigned long tick_ps = gpmc_get_fclk_period();
306 u32 l;
307 int div;
308
309 switch (cd) {
310 case GPMC_CD_CLK:
311 /* get current clk divider */
312 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
313 div = (l & 0x03) + 1;
314 /* get GPMC_CLK period */
315 tick_ps *= div;
316 break;
317 case GPMC_CD_FCLK:
318 /* FALL-THROUGH */
319 default:
320 break;
321 }
322
323 return tick_ps;
324
325 }
326
gpmc_ns_to_clk_ticks(unsigned int time_ns,int cs,enum gpmc_clk_domain cd)327 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
328 enum gpmc_clk_domain cd)
329 {
330 unsigned long tick_ps;
331
332 /* Calculate in picosecs to yield more exact results */
333 tick_ps = gpmc_get_clk_period(cs, cd);
334
335 return (time_ns * 1000 + tick_ps - 1) / tick_ps;
336 }
337
gpmc_ns_to_ticks(unsigned int time_ns)338 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
339 {
340 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
341 }
342
gpmc_ps_to_ticks(unsigned int time_ps)343 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
344 {
345 unsigned long tick_ps;
346
347 /* Calculate in picosecs to yield more exact results */
348 tick_ps = gpmc_get_fclk_period();
349
350 return (time_ps + tick_ps - 1) / tick_ps;
351 }
352
gpmc_clk_ticks_to_ns(unsigned int ticks,int cs,enum gpmc_clk_domain cd)353 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
354 enum gpmc_clk_domain cd)
355 {
356 return ticks * gpmc_get_clk_period(cs, cd) / 1000;
357 }
358
gpmc_ticks_to_ns(unsigned int ticks)359 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
360 {
361 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
362 }
363
gpmc_ticks_to_ps(unsigned int ticks)364 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
365 {
366 return ticks * gpmc_get_fclk_period();
367 }
368
gpmc_round_ps_to_ticks(unsigned int time_ps)369 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
370 {
371 unsigned long ticks = gpmc_ps_to_ticks(time_ps);
372
373 return ticks * gpmc_get_fclk_period();
374 }
375
gpmc_cs_modify_reg(int cs,int reg,u32 mask,bool value)376 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
377 {
378 u32 l;
379
380 l = gpmc_cs_read_reg(cs, reg);
381 if (value)
382 l |= mask;
383 else
384 l &= ~mask;
385 gpmc_cs_write_reg(cs, reg, l);
386 }
387
gpmc_cs_bool_timings(int cs,const struct gpmc_bool_timings * p)388 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
389 {
390 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
391 GPMC_CONFIG1_TIME_PARA_GRAN,
392 p->time_para_granularity);
393 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
394 GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
395 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
396 GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
397 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
398 GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
399 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
400 GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
401 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
402 GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
403 p->cycle2cyclesamecsen);
404 gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
405 GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
406 p->cycle2cyclediffcsen);
407 }
408
409 #ifdef CONFIG_OMAP_GPMC_DEBUG
410 /**
411 * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
412 * @cs: Chip Select Region
413 * @reg: GPMC_CS_CONFIGn register offset.
414 * @st_bit: Start Bit
415 * @end_bit: End Bit. Must be >= @st_bit.
416 * @ma:x Maximum parameter value (before optional @shift).
417 * If 0, maximum is as high as @st_bit and @end_bit allow.
418 * @name: DTS node name, w/o "gpmc,"
419 * @cd: Clock Domain of timing parameter.
420 * @shift: Parameter value left shifts @shift, which is then printed instead of value.
421 * @raw: Raw Format Option.
422 * raw format: gpmc,name = <value>
423 * tick format: gpmc,name = <value> /‍* x ns -- y ns; x ticks *‍/
424 * Where x ns -- y ns result in the same tick value.
425 * When @max is exceeded, "invalid" is printed inside comment.
426 * @noval: Parameter values equal to 0 are not printed.
427 * @return: Specified timing parameter (after optional @shift).
428 *
429 */
get_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,const char * name,const enum gpmc_clk_domain cd,int shift,bool raw,bool noval)430 static int get_gpmc_timing_reg(
431 /* timing specifiers */
432 int cs, int reg, int st_bit, int end_bit, int max,
433 const char *name, const enum gpmc_clk_domain cd,
434 /* value transform */
435 int shift,
436 /* format specifiers */
437 bool raw, bool noval)
438 {
439 u32 l;
440 int nr_bits;
441 int mask;
442 bool invalid;
443
444 l = gpmc_cs_read_reg(cs, reg);
445 nr_bits = end_bit - st_bit + 1;
446 mask = (1 << nr_bits) - 1;
447 l = (l >> st_bit) & mask;
448 if (!max)
449 max = mask;
450 invalid = l > max;
451 if (shift)
452 l = (shift << l);
453 if (noval && (l == 0))
454 return 0;
455 if (!raw) {
456 /* DTS tick format for timings in ns */
457 unsigned int time_ns;
458 unsigned int time_ns_min = 0;
459
460 if (l)
461 time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
462 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
463 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
464 name, time_ns, time_ns_min, time_ns, l,
465 invalid ? "; invalid " : " ");
466 } else {
467 /* raw format */
468 pr_info("gpmc,%s = <%u>;%s\n", name, l,
469 invalid ? " /* invalid */" : "");
470 }
471
472 return l;
473 }
474
475 #define GPMC_PRINT_CONFIG(cs, config) \
476 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
477 gpmc_cs_read_reg(cs, config))
478 #define GPMC_GET_RAW(reg, st, end, field) \
479 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
480 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
481 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
482 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
483 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
484 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
485 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
486 #define GPMC_GET_TICKS(reg, st, end, field) \
487 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
488 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
489 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
490 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
491 get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
492
gpmc_show_regs(int cs,const char * desc)493 static void gpmc_show_regs(int cs, const char *desc)
494 {
495 pr_info("gpmc cs%i %s:\n", cs, desc);
496 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
497 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
498 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
499 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
500 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
501 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
502 }
503
504 /*
505 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
506 * see commit c9fb809.
507 */
gpmc_cs_show_timings(int cs,const char * desc)508 static void gpmc_cs_show_timings(int cs, const char *desc)
509 {
510 gpmc_show_regs(cs, desc);
511
512 pr_info("gpmc cs%i access configuration:\n", cs);
513 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
514 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
515 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
516 GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
517 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
518 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
519 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
520 GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
521 GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
522 "burst-length");
523 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
524 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
525 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
526 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
527 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
528
529 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
530
531 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
532
533 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
534 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
535
536 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
537 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
538
539 pr_info("gpmc cs%i timings configuration:\n", cs);
540 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
541 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
542 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
543
544 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
545 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
546 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
547 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
548 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
549 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
550 "adv-aad-mux-rd-off-ns");
551 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
552 "adv-aad-mux-wr-off-ns");
553 }
554
555 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
556 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
557 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
558 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 4, 6, "oe-aad-mux-on-ns");
559 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
560 }
561 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
562 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
563
564 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
565 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
566 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
567
568 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
569
570 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
571 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
572
573 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
574 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
575 "wait-monitoring-ns", GPMC_CD_CLK);
576 GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
577 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
578 "clk-activation-ns", GPMC_CD_FCLK);
579
580 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
581 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
582 }
583 #else
gpmc_cs_show_timings(int cs,const char * desc)584 static inline void gpmc_cs_show_timings(int cs, const char *desc)
585 {
586 }
587 #endif
588
589 /**
590 * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
591 * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
592 * prior to calling this function with @cd equal to GPMC_CD_CLK.
593 *
594 * @cs: Chip Select Region.
595 * @reg: GPMC_CS_CONFIGn register offset.
596 * @st_bit: Start Bit
597 * @end_bit: End Bit. Must be >= @st_bit.
598 * @max: Maximum parameter value.
599 * If 0, maximum is as high as @st_bit and @end_bit allow.
600 * @time: Timing parameter in ns.
601 * @cd: Timing parameter clock domain.
602 * @name: Timing parameter name.
603 * @return: 0 on success, -1 on error.
604 */
set_gpmc_timing_reg(int cs,int reg,int st_bit,int end_bit,int max,int time,enum gpmc_clk_domain cd,const char * name)605 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
606 int time, enum gpmc_clk_domain cd, const char *name)
607 {
608 u32 l;
609 int ticks, mask, nr_bits;
610
611 if (time == 0)
612 ticks = 0;
613 else
614 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
615 nr_bits = end_bit - st_bit + 1;
616 mask = (1 << nr_bits) - 1;
617
618 if (!max)
619 max = mask;
620
621 if (ticks > max) {
622 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
623 __func__, cs, name, time, ticks, max);
624
625 return -1;
626 }
627
628 l = gpmc_cs_read_reg(cs, reg);
629 #ifdef CONFIG_OMAP_GPMC_DEBUG
630 pr_info(
631 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
632 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
633 (l >> st_bit) & mask, time);
634 #endif
635 l &= ~(mask << st_bit);
636 l |= ticks << st_bit;
637 gpmc_cs_write_reg(cs, reg, l);
638
639 return 0;
640 }
641
642 #define GPMC_SET_ONE_CD_MAX(reg, st, end, max, field, cd) \
643 if (set_gpmc_timing_reg(cs, (reg), (st), (end), (max), \
644 t->field, (cd), #field) < 0) \
645 return -1
646
647 #define GPMC_SET_ONE(reg, st, end, field) \
648 GPMC_SET_ONE_CD_MAX(reg, st, end, 0, field, GPMC_CD_FCLK)
649
650 /**
651 * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
652 * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
653 * read --> don't sample bus too early
654 * write --> data is longer on bus
655 *
656 * Formula:
657 * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
658 * / waitmonitoring_ticks)
659 * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
660 * div <= 0 check.
661 *
662 * @wait_monitoring: WAITMONITORINGTIME in ns.
663 * @return: -1 on failure to scale, else proper divider > 0.
664 */
gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)665 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
666 {
667
668 int div = gpmc_ns_to_ticks(wait_monitoring);
669
670 div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
671 div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
672
673 if (div > 4)
674 return -1;
675 if (div <= 0)
676 div = 1;
677
678 return div;
679
680 }
681
682 /**
683 * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
684 * @sync_clk: GPMC_CLK period in ps.
685 * @return: Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
686 * Else, returns -1.
687 */
gpmc_calc_divider(unsigned int sync_clk)688 int gpmc_calc_divider(unsigned int sync_clk)
689 {
690 int div = gpmc_ps_to_ticks(sync_clk);
691
692 if (div > 4)
693 return -1;
694 if (div <= 0)
695 div = 1;
696
697 return div;
698 }
699
700 /**
701 * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
702 * @cs: Chip Select Region.
703 * @t: GPMC timing parameters.
704 * @s: GPMC timing settings.
705 * @return: 0 on success, -1 on error.
706 */
gpmc_cs_set_timings(int cs,const struct gpmc_timings * t,const struct gpmc_settings * s)707 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
708 const struct gpmc_settings *s)
709 {
710 int div;
711 u32 l;
712
713 div = gpmc_calc_divider(t->sync_clk);
714 if (div < 0)
715 return div;
716
717 /*
718 * See if we need to change the divider for waitmonitoringtime.
719 *
720 * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
721 * pure asynchronous accesses, i.e. both read and write asynchronous.
722 * However, only do so if WAITMONITORINGTIME is actually used, i.e.
723 * either WAITREADMONITORING or WAITWRITEMONITORING is set.
724 *
725 * This statement must not change div to scale async WAITMONITORINGTIME
726 * to protect mixed synchronous and asynchronous accesses.
727 *
728 * We raise an error later if WAITMONITORINGTIME does not fit.
729 */
730 if (!s->sync_read && !s->sync_write &&
731 (s->wait_on_read || s->wait_on_write)
732 ) {
733
734 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
735 if (div < 0) {
736 pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
737 __func__,
738 t->wait_monitoring
739 );
740 return -1;
741 }
742 }
743
744 GPMC_SET_ONE(GPMC_CS_CONFIG2, 0, 3, cs_on);
745 GPMC_SET_ONE(GPMC_CS_CONFIG2, 8, 12, cs_rd_off);
746 GPMC_SET_ONE(GPMC_CS_CONFIG2, 16, 20, cs_wr_off);
747
748 GPMC_SET_ONE(GPMC_CS_CONFIG3, 0, 3, adv_on);
749 GPMC_SET_ONE(GPMC_CS_CONFIG3, 8, 12, adv_rd_off);
750 GPMC_SET_ONE(GPMC_CS_CONFIG3, 16, 20, adv_wr_off);
751 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
752 GPMC_SET_ONE(GPMC_CS_CONFIG3, 4, 6, adv_aad_mux_on);
753 GPMC_SET_ONE(GPMC_CS_CONFIG3, 24, 26, adv_aad_mux_rd_off);
754 GPMC_SET_ONE(GPMC_CS_CONFIG3, 28, 30, adv_aad_mux_wr_off);
755 }
756
757 GPMC_SET_ONE(GPMC_CS_CONFIG4, 0, 3, oe_on);
758 GPMC_SET_ONE(GPMC_CS_CONFIG4, 8, 12, oe_off);
759 if (gpmc_capability & GPMC_HAS_MUX_AAD) {
760 GPMC_SET_ONE(GPMC_CS_CONFIG4, 4, 6, oe_aad_mux_on);
761 GPMC_SET_ONE(GPMC_CS_CONFIG4, 13, 15, oe_aad_mux_off);
762 }
763 GPMC_SET_ONE(GPMC_CS_CONFIG4, 16, 19, we_on);
764 GPMC_SET_ONE(GPMC_CS_CONFIG4, 24, 28, we_off);
765
766 GPMC_SET_ONE(GPMC_CS_CONFIG5, 0, 4, rd_cycle);
767 GPMC_SET_ONE(GPMC_CS_CONFIG5, 8, 12, wr_cycle);
768 GPMC_SET_ONE(GPMC_CS_CONFIG5, 16, 20, access);
769
770 GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
771
772 GPMC_SET_ONE(GPMC_CS_CONFIG6, 0, 3, bus_turnaround);
773 GPMC_SET_ONE(GPMC_CS_CONFIG6, 8, 11, cycle2cycle_delay);
774
775 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
776 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
777 if (gpmc_capability & GPMC_HAS_WR_ACCESS)
778 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
779
780 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
781 l &= ~0x03;
782 l |= (div - 1);
783 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
784
785 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
786 GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
787 wait_monitoring, GPMC_CD_CLK);
788 GPMC_SET_ONE_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
789 GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
790 clk_activation, GPMC_CD_FCLK);
791
792 #ifdef CONFIG_OMAP_GPMC_DEBUG
793 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
794 cs, (div * gpmc_get_fclk_period()) / 1000, div);
795 #endif
796
797 gpmc_cs_bool_timings(cs, &t->bool_timings);
798 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
799
800 return 0;
801 }
802
gpmc_cs_set_memconf(int cs,u32 base,u32 size)803 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
804 {
805 u32 l;
806 u32 mask;
807
808 /*
809 * Ensure that base address is aligned on a
810 * boundary equal to or greater than size.
811 */
812 if (base & (size - 1))
813 return -EINVAL;
814
815 base >>= GPMC_CHUNK_SHIFT;
816 mask = (1 << GPMC_SECTION_SHIFT) - size;
817 mask >>= GPMC_CHUNK_SHIFT;
818 mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
819
820 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
821 l &= ~GPMC_CONFIG7_MASK;
822 l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
823 l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
824 l |= GPMC_CONFIG7_CSVALID;
825 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
826
827 return 0;
828 }
829
gpmc_cs_enable_mem(int cs)830 static void gpmc_cs_enable_mem(int cs)
831 {
832 u32 l;
833
834 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
835 l |= GPMC_CONFIG7_CSVALID;
836 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
837 }
838
gpmc_cs_disable_mem(int cs)839 static void gpmc_cs_disable_mem(int cs)
840 {
841 u32 l;
842
843 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
844 l &= ~GPMC_CONFIG7_CSVALID;
845 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
846 }
847
gpmc_cs_get_memconf(int cs,u32 * base,u32 * size)848 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
849 {
850 u32 l;
851 u32 mask;
852
853 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
854 *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
855 mask = (l >> 8) & 0x0f;
856 *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
857 }
858
gpmc_cs_mem_enabled(int cs)859 static int gpmc_cs_mem_enabled(int cs)
860 {
861 u32 l;
862
863 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
864 return l & GPMC_CONFIG7_CSVALID;
865 }
866
gpmc_cs_set_reserved(int cs,int reserved)867 static void gpmc_cs_set_reserved(int cs, int reserved)
868 {
869 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
870
871 gpmc->flags |= GPMC_CS_RESERVED;
872 }
873
gpmc_cs_reserved(int cs)874 static bool gpmc_cs_reserved(int cs)
875 {
876 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
877
878 return gpmc->flags & GPMC_CS_RESERVED;
879 }
880
gpmc_cs_set_name(int cs,const char * name)881 static void gpmc_cs_set_name(int cs, const char *name)
882 {
883 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
884
885 gpmc->name = name;
886 }
887
gpmc_cs_get_name(int cs)888 static const char *gpmc_cs_get_name(int cs)
889 {
890 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
891
892 return gpmc->name;
893 }
894
gpmc_mem_align(unsigned long size)895 static unsigned long gpmc_mem_align(unsigned long size)
896 {
897 int order;
898
899 size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
900 order = GPMC_CHUNK_SHIFT - 1;
901 do {
902 size >>= 1;
903 order++;
904 } while (size);
905 size = 1 << order;
906 return size;
907 }
908
gpmc_cs_insert_mem(int cs,unsigned long base,unsigned long size)909 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
910 {
911 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
912 struct resource *res = &gpmc->mem;
913 int r;
914
915 size = gpmc_mem_align(size);
916 spin_lock(&gpmc_mem_lock);
917 res->start = base;
918 res->end = base + size - 1;
919 r = request_resource(&gpmc_mem_root, res);
920 spin_unlock(&gpmc_mem_lock);
921
922 return r;
923 }
924
gpmc_cs_delete_mem(int cs)925 static int gpmc_cs_delete_mem(int cs)
926 {
927 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
928 struct resource *res = &gpmc->mem;
929 int r;
930
931 spin_lock(&gpmc_mem_lock);
932 r = release_resource(res);
933 res->start = 0;
934 res->end = 0;
935 spin_unlock(&gpmc_mem_lock);
936
937 return r;
938 }
939
940 /**
941 * gpmc_cs_remap - remaps a chip-select physical base address
942 * @cs: chip-select to remap
943 * @base: physical base address to re-map chip-select to
944 *
945 * Re-maps a chip-select to a new physical base address specified by
946 * "base". Returns 0 on success and appropriate negative error code
947 * on failure.
948 */
gpmc_cs_remap(int cs,u32 base)949 static int gpmc_cs_remap(int cs, u32 base)
950 {
951 int ret;
952 u32 old_base, size;
953
954 if (cs >= gpmc_cs_num) {
955 pr_err("%s: requested chip-select is disabled\n", __func__);
956 return -ENODEV;
957 }
958
959 /*
960 * Make sure we ignore any device offsets from the GPMC partition
961 * allocated for the chip select and that the new base confirms
962 * to the GPMC 16MB minimum granularity.
963 */
964 base &= ~(SZ_16M - 1);
965
966 gpmc_cs_get_memconf(cs, &old_base, &size);
967 if (base == old_base)
968 return 0;
969
970 ret = gpmc_cs_delete_mem(cs);
971 if (ret < 0)
972 return ret;
973
974 ret = gpmc_cs_insert_mem(cs, base, size);
975 if (ret < 0)
976 return ret;
977
978 ret = gpmc_cs_set_memconf(cs, base, size);
979
980 return ret;
981 }
982
gpmc_cs_request(int cs,unsigned long size,unsigned long * base)983 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
984 {
985 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
986 struct resource *res = &gpmc->mem;
987 int r = -1;
988
989 if (cs >= gpmc_cs_num) {
990 pr_err("%s: requested chip-select is disabled\n", __func__);
991 return -ENODEV;
992 }
993 size = gpmc_mem_align(size);
994 if (size > (1 << GPMC_SECTION_SHIFT))
995 return -ENOMEM;
996
997 spin_lock(&gpmc_mem_lock);
998 if (gpmc_cs_reserved(cs)) {
999 r = -EBUSY;
1000 goto out;
1001 }
1002 if (gpmc_cs_mem_enabled(cs))
1003 r = adjust_resource(res, res->start & ~(size - 1), size);
1004 if (r < 0)
1005 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
1006 size, NULL, NULL);
1007 if (r < 0)
1008 goto out;
1009
1010 /* Disable CS while changing base address and size mask */
1011 gpmc_cs_disable_mem(cs);
1012
1013 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1014 if (r < 0) {
1015 release_resource(res);
1016 goto out;
1017 }
1018
1019 /* Enable CS */
1020 gpmc_cs_enable_mem(cs);
1021 *base = res->start;
1022 gpmc_cs_set_reserved(cs, 1);
1023 out:
1024 spin_unlock(&gpmc_mem_lock);
1025 return r;
1026 }
1027 EXPORT_SYMBOL(gpmc_cs_request);
1028
gpmc_cs_free(int cs)1029 void gpmc_cs_free(int cs)
1030 {
1031 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1032 struct resource *res = &gpmc->mem;
1033
1034 spin_lock(&gpmc_mem_lock);
1035 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1036 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs);
1037 BUG();
1038 spin_unlock(&gpmc_mem_lock);
1039 return;
1040 }
1041 gpmc_cs_disable_mem(cs);
1042 if (res->flags)
1043 release_resource(res);
1044 gpmc_cs_set_reserved(cs, 0);
1045 spin_unlock(&gpmc_mem_lock);
1046 }
1047 EXPORT_SYMBOL(gpmc_cs_free);
1048
1049 /**
1050 * gpmc_configure - write request to configure gpmc
1051 * @cmd: command type
1052 * @wval: value to write
1053 * @return status of the operation
1054 */
gpmc_configure(int cmd,int wval)1055 int gpmc_configure(int cmd, int wval)
1056 {
1057 u32 regval;
1058
1059 switch (cmd) {
1060 case GPMC_CONFIG_WP:
1061 regval = gpmc_read_reg(GPMC_CONFIG);
1062 if (wval)
1063 regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1064 else
1065 regval |= GPMC_CONFIG_WRITEPROTECT; /* WP is OFF */
1066 gpmc_write_reg(GPMC_CONFIG, regval);
1067 break;
1068
1069 default:
1070 pr_err("%s: command not supported\n", __func__);
1071 return -EINVAL;
1072 }
1073
1074 return 0;
1075 }
1076 EXPORT_SYMBOL(gpmc_configure);
1077
gpmc_nand_writebuffer_empty(void)1078 static bool gpmc_nand_writebuffer_empty(void)
1079 {
1080 if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1081 return true;
1082
1083 return false;
1084 }
1085
1086 static struct gpmc_nand_ops nand_ops = {
1087 .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1088 };
1089
1090 /**
1091 * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1092 * @regs: the GPMC NAND register map exclusive for NAND use.
1093 * @cs: GPMC chip select number on which the NAND sits. The
1094 * register map returned will be specific to this chip select.
1095 *
1096 * Returns NULL on error e.g. invalid cs.
1097 */
gpmc_omap_get_nand_ops(struct gpmc_nand_regs * reg,int cs)1098 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1099 {
1100 int i;
1101
1102 if (cs >= gpmc_cs_num)
1103 return NULL;
1104
1105 reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1106 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1107 reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1108 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1109 reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1110 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1111 reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1112 reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1113 reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1114 reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1115 reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1116 reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1117 reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1118 reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1119
1120 for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1121 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1122 GPMC_BCH_SIZE * i;
1123 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1124 GPMC_BCH_SIZE * i;
1125 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1126 GPMC_BCH_SIZE * i;
1127 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1128 GPMC_BCH_SIZE * i;
1129 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1130 i * GPMC_BCH_SIZE;
1131 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1132 i * GPMC_BCH_SIZE;
1133 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1134 i * GPMC_BCH_SIZE;
1135 }
1136
1137 return &nand_ops;
1138 }
1139 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1140
gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings * t,struct gpmc_settings * s,int freq,int latency)1141 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1142 struct gpmc_settings *s,
1143 int freq, int latency)
1144 {
1145 struct gpmc_device_timings dev_t;
1146 const int t_cer = 15;
1147 const int t_avdp = 12;
1148 const int t_cez = 20; /* max of t_cez, t_oez */
1149 const int t_wpl = 40;
1150 const int t_wph = 30;
1151 int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1152
1153 switch (freq) {
1154 case 104:
1155 min_gpmc_clk_period = 9600; /* 104 MHz */
1156 t_ces = 3;
1157 t_avds = 4;
1158 t_avdh = 2;
1159 t_ach = 3;
1160 t_aavdh = 6;
1161 t_rdyo = 6;
1162 break;
1163 case 83:
1164 min_gpmc_clk_period = 12000; /* 83 MHz */
1165 t_ces = 5;
1166 t_avds = 4;
1167 t_avdh = 2;
1168 t_ach = 6;
1169 t_aavdh = 6;
1170 t_rdyo = 9;
1171 break;
1172 case 66:
1173 min_gpmc_clk_period = 15000; /* 66 MHz */
1174 t_ces = 6;
1175 t_avds = 5;
1176 t_avdh = 2;
1177 t_ach = 6;
1178 t_aavdh = 6;
1179 t_rdyo = 11;
1180 break;
1181 default:
1182 min_gpmc_clk_period = 18500; /* 54 MHz */
1183 t_ces = 7;
1184 t_avds = 7;
1185 t_avdh = 7;
1186 t_ach = 9;
1187 t_aavdh = 7;
1188 t_rdyo = 15;
1189 break;
1190 }
1191
1192 /* Set synchronous read timings */
1193 memset(&dev_t, 0, sizeof(dev_t));
1194
1195 if (!s->sync_write) {
1196 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1197 dev_t.t_wpl = t_wpl * 1000;
1198 dev_t.t_wph = t_wph * 1000;
1199 dev_t.t_aavdh = t_aavdh * 1000;
1200 }
1201 dev_t.ce_xdelay = true;
1202 dev_t.avd_xdelay = true;
1203 dev_t.oe_xdelay = true;
1204 dev_t.we_xdelay = true;
1205 dev_t.clk = min_gpmc_clk_period;
1206 dev_t.t_bacc = dev_t.clk;
1207 dev_t.t_ces = t_ces * 1000;
1208 dev_t.t_avds = t_avds * 1000;
1209 dev_t.t_avdh = t_avdh * 1000;
1210 dev_t.t_ach = t_ach * 1000;
1211 dev_t.cyc_iaa = (latency + 1);
1212 dev_t.t_cez_r = t_cez * 1000;
1213 dev_t.t_cez_w = dev_t.t_cez_r;
1214 dev_t.cyc_aavdh_oe = 1;
1215 dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1216
1217 gpmc_calc_timings(t, s, &dev_t);
1218 }
1219
gpmc_omap_onenand_set_timings(struct device * dev,int cs,int freq,int latency,struct gpmc_onenand_info * info)1220 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1221 int latency,
1222 struct gpmc_onenand_info *info)
1223 {
1224 int ret;
1225 struct gpmc_timings gpmc_t;
1226 struct gpmc_settings gpmc_s;
1227
1228 gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1229
1230 info->sync_read = gpmc_s.sync_read;
1231 info->sync_write = gpmc_s.sync_write;
1232 info->burst_len = gpmc_s.burst_len;
1233
1234 if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1235 return 0;
1236
1237 gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1238
1239 ret = gpmc_cs_program_settings(cs, &gpmc_s);
1240 if (ret < 0)
1241 return ret;
1242
1243 return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1244 }
1245 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1246
gpmc_get_client_irq(unsigned irq_config)1247 int gpmc_get_client_irq(unsigned irq_config)
1248 {
1249 if (!gpmc_irq_domain) {
1250 pr_warn("%s called before GPMC IRQ domain available\n",
1251 __func__);
1252 return 0;
1253 }
1254
1255 /* we restrict this to NAND IRQs only */
1256 if (irq_config >= GPMC_NR_NAND_IRQS)
1257 return 0;
1258
1259 return irq_create_mapping(gpmc_irq_domain, irq_config);
1260 }
1261
gpmc_irq_endis(unsigned long hwirq,bool endis)1262 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1263 {
1264 u32 regval;
1265
1266 /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1267 if (hwirq >= GPMC_NR_NAND_IRQS)
1268 hwirq += 8 - GPMC_NR_NAND_IRQS;
1269
1270 regval = gpmc_read_reg(GPMC_IRQENABLE);
1271 if (endis)
1272 regval |= BIT(hwirq);
1273 else
1274 regval &= ~BIT(hwirq);
1275 gpmc_write_reg(GPMC_IRQENABLE, regval);
1276
1277 return 0;
1278 }
1279
gpmc_irq_disable(struct irq_data * p)1280 static void gpmc_irq_disable(struct irq_data *p)
1281 {
1282 gpmc_irq_endis(p->hwirq, false);
1283 }
1284
gpmc_irq_enable(struct irq_data * p)1285 static void gpmc_irq_enable(struct irq_data *p)
1286 {
1287 gpmc_irq_endis(p->hwirq, true);
1288 }
1289
gpmc_irq_mask(struct irq_data * d)1290 static void gpmc_irq_mask(struct irq_data *d)
1291 {
1292 gpmc_irq_endis(d->hwirq, false);
1293 }
1294
gpmc_irq_unmask(struct irq_data * d)1295 static void gpmc_irq_unmask(struct irq_data *d)
1296 {
1297 gpmc_irq_endis(d->hwirq, true);
1298 }
1299
gpmc_irq_edge_config(unsigned long hwirq,bool rising_edge)1300 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1301 {
1302 u32 regval;
1303
1304 /* NAND IRQs polarity is not configurable */
1305 if (hwirq < GPMC_NR_NAND_IRQS)
1306 return;
1307
1308 /* WAITPIN starts at BIT 8 */
1309 hwirq += 8 - GPMC_NR_NAND_IRQS;
1310
1311 regval = gpmc_read_reg(GPMC_CONFIG);
1312 if (rising_edge)
1313 regval &= ~BIT(hwirq);
1314 else
1315 regval |= BIT(hwirq);
1316
1317 gpmc_write_reg(GPMC_CONFIG, regval);
1318 }
1319
gpmc_irq_ack(struct irq_data * d)1320 static void gpmc_irq_ack(struct irq_data *d)
1321 {
1322 unsigned int hwirq = d->hwirq;
1323
1324 /* skip reserved bits */
1325 if (hwirq >= GPMC_NR_NAND_IRQS)
1326 hwirq += 8 - GPMC_NR_NAND_IRQS;
1327
1328 /* Setting bit to 1 clears (or Acks) the interrupt */
1329 gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1330 }
1331
gpmc_irq_set_type(struct irq_data * d,unsigned int trigger)1332 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1333 {
1334 /* can't set type for NAND IRQs */
1335 if (d->hwirq < GPMC_NR_NAND_IRQS)
1336 return -EINVAL;
1337
1338 /* We can support either rising or falling edge at a time */
1339 if (trigger == IRQ_TYPE_EDGE_FALLING)
1340 gpmc_irq_edge_config(d->hwirq, false);
1341 else if (trigger == IRQ_TYPE_EDGE_RISING)
1342 gpmc_irq_edge_config(d->hwirq, true);
1343 else
1344 return -EINVAL;
1345
1346 return 0;
1347 }
1348
gpmc_irq_map(struct irq_domain * d,unsigned int virq,irq_hw_number_t hw)1349 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1350 irq_hw_number_t hw)
1351 {
1352 struct gpmc_device *gpmc = d->host_data;
1353
1354 irq_set_chip_data(virq, gpmc);
1355 if (hw < GPMC_NR_NAND_IRQS) {
1356 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1357 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1358 handle_simple_irq);
1359 } else {
1360 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1361 handle_edge_irq);
1362 }
1363
1364 return 0;
1365 }
1366
1367 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1368 .map = gpmc_irq_map,
1369 .xlate = irq_domain_xlate_twocell,
1370 };
1371
gpmc_handle_irq(int irq,void * data)1372 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1373 {
1374 int hwirq, virq;
1375 u32 regval, regvalx;
1376 struct gpmc_device *gpmc = data;
1377
1378 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1379 regvalx = regval;
1380
1381 if (!regval)
1382 return IRQ_NONE;
1383
1384 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1385 /* skip reserved status bits */
1386 if (hwirq == GPMC_NR_NAND_IRQS)
1387 regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1388
1389 if (regvalx & BIT(hwirq)) {
1390 virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1391 if (!virq) {
1392 dev_warn(gpmc->dev,
1393 "spurious irq detected hwirq %d, virq %d\n",
1394 hwirq, virq);
1395 }
1396
1397 generic_handle_irq(virq);
1398 }
1399 }
1400
1401 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1402
1403 return IRQ_HANDLED;
1404 }
1405
gpmc_setup_irq(struct gpmc_device * gpmc)1406 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1407 {
1408 u32 regval;
1409 int rc;
1410
1411 /* Disable interrupts */
1412 gpmc_write_reg(GPMC_IRQENABLE, 0);
1413
1414 /* clear interrupts */
1415 regval = gpmc_read_reg(GPMC_IRQSTATUS);
1416 gpmc_write_reg(GPMC_IRQSTATUS, regval);
1417
1418 gpmc->irq_chip.name = "gpmc";
1419 gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1420 gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1421 gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1422 gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1423 gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1424 gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1425
1426 gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1427 gpmc->nirqs,
1428 &gpmc_irq_domain_ops,
1429 gpmc);
1430 if (!gpmc_irq_domain) {
1431 dev_err(gpmc->dev, "IRQ domain add failed\n");
1432 return -ENODEV;
1433 }
1434
1435 rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1436 if (rc) {
1437 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1438 gpmc->irq, rc);
1439 irq_domain_remove(gpmc_irq_domain);
1440 gpmc_irq_domain = NULL;
1441 }
1442
1443 return rc;
1444 }
1445
gpmc_free_irq(struct gpmc_device * gpmc)1446 static int gpmc_free_irq(struct gpmc_device *gpmc)
1447 {
1448 int hwirq;
1449
1450 free_irq(gpmc->irq, gpmc);
1451
1452 for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1453 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1454
1455 irq_domain_remove(gpmc_irq_domain);
1456 gpmc_irq_domain = NULL;
1457
1458 return 0;
1459 }
1460
gpmc_mem_exit(void)1461 static void gpmc_mem_exit(void)
1462 {
1463 int cs;
1464
1465 for (cs = 0; cs < gpmc_cs_num; cs++) {
1466 if (!gpmc_cs_mem_enabled(cs))
1467 continue;
1468 gpmc_cs_delete_mem(cs);
1469 }
1470
1471 }
1472
gpmc_mem_init(void)1473 static void gpmc_mem_init(void)
1474 {
1475 int cs;
1476
1477 gpmc_mem_root.start = GPMC_MEM_START;
1478 gpmc_mem_root.end = GPMC_MEM_END;
1479
1480 /* Reserve all regions that has been set up by bootloader */
1481 for (cs = 0; cs < gpmc_cs_num; cs++) {
1482 u32 base, size;
1483
1484 if (!gpmc_cs_mem_enabled(cs))
1485 continue;
1486 gpmc_cs_get_memconf(cs, &base, &size);
1487 if (gpmc_cs_insert_mem(cs, base, size)) {
1488 pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1489 __func__, cs, base, base + size);
1490 gpmc_cs_disable_mem(cs);
1491 }
1492 }
1493 }
1494
gpmc_round_ps_to_sync_clk(u32 time_ps,u32 sync_clk)1495 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1496 {
1497 u32 temp;
1498 int div;
1499
1500 div = gpmc_calc_divider(sync_clk);
1501 temp = gpmc_ps_to_ticks(time_ps);
1502 temp = (temp + div - 1) / div;
1503 return gpmc_ticks_to_ps(temp * div);
1504 }
1505
1506 /* XXX: can the cycles be avoided ? */
gpmc_calc_sync_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1507 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1508 struct gpmc_device_timings *dev_t,
1509 bool mux)
1510 {
1511 u32 temp;
1512
1513 /* adv_rd_off */
1514 temp = dev_t->t_avdp_r;
1515 /* XXX: mux check required ? */
1516 if (mux) {
1517 /* XXX: t_avdp not to be required for sync, only added for tusb
1518 * this indirectly necessitates requirement of t_avdp_r and
1519 * t_avdp_w instead of having a single t_avdp
1520 */
1521 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1522 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1523 }
1524 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1525
1526 /* oe_on */
1527 temp = dev_t->t_oeasu; /* XXX: remove this ? */
1528 if (mux) {
1529 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1530 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1531 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1532 }
1533 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1534
1535 /* access */
1536 /* XXX: any scope for improvement ?, by combining oe_on
1537 * and clk_activation, need to check whether
1538 * access = clk_activation + round to sync clk ?
1539 */
1540 temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1541 temp += gpmc_t->clk_activation;
1542 if (dev_t->cyc_oe)
1543 temp = max_t(u32, temp, gpmc_t->oe_on +
1544 gpmc_ticks_to_ps(dev_t->cyc_oe));
1545 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1546
1547 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1548 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1549
1550 /* rd_cycle */
1551 temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1552 temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1553 gpmc_t->access;
1554 /* XXX: barter t_ce_rdyz with t_cez_r ? */
1555 if (dev_t->t_ce_rdyz)
1556 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1557 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1558
1559 return 0;
1560 }
1561
gpmc_calc_sync_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1562 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1563 struct gpmc_device_timings *dev_t,
1564 bool mux)
1565 {
1566 u32 temp;
1567
1568 /* adv_wr_off */
1569 temp = dev_t->t_avdp_w;
1570 if (mux) {
1571 temp = max_t(u32, temp,
1572 gpmc_t->clk_activation + dev_t->t_avdh);
1573 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1574 }
1575 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1576
1577 /* wr_data_mux_bus */
1578 temp = max_t(u32, dev_t->t_weasu,
1579 gpmc_t->clk_activation + dev_t->t_rdyo);
1580 /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1581 * and in that case remember to handle we_on properly
1582 */
1583 if (mux) {
1584 temp = max_t(u32, temp,
1585 gpmc_t->adv_wr_off + dev_t->t_aavdh);
1586 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1587 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1588 }
1589 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1590
1591 /* we_on */
1592 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1593 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1594 else
1595 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1596
1597 /* wr_access */
1598 /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1599 gpmc_t->wr_access = gpmc_t->access;
1600
1601 /* we_off */
1602 temp = gpmc_t->we_on + dev_t->t_wpl;
1603 temp = max_t(u32, temp,
1604 gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1605 temp = max_t(u32, temp,
1606 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1607 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1608
1609 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1610 dev_t->t_wph);
1611
1612 /* wr_cycle */
1613 temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1614 temp += gpmc_t->wr_access;
1615 /* XXX: barter t_ce_rdyz with t_cez_w ? */
1616 if (dev_t->t_ce_rdyz)
1617 temp = max_t(u32, temp,
1618 gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1619 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1620
1621 return 0;
1622 }
1623
gpmc_calc_async_read_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1624 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1625 struct gpmc_device_timings *dev_t,
1626 bool mux)
1627 {
1628 u32 temp;
1629
1630 /* adv_rd_off */
1631 temp = dev_t->t_avdp_r;
1632 if (mux)
1633 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1634 gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1635
1636 /* oe_on */
1637 temp = dev_t->t_oeasu;
1638 if (mux)
1639 temp = max_t(u32, temp,
1640 gpmc_t->adv_rd_off + dev_t->t_aavdh);
1641 gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1642
1643 /* access */
1644 temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1645 gpmc_t->oe_on + dev_t->t_oe);
1646 temp = max_t(u32, temp,
1647 gpmc_t->cs_on + dev_t->t_ce);
1648 temp = max_t(u32, temp,
1649 gpmc_t->adv_on + dev_t->t_aa);
1650 gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1651
1652 gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1653 gpmc_t->cs_rd_off = gpmc_t->oe_off;
1654
1655 /* rd_cycle */
1656 temp = max_t(u32, dev_t->t_rd_cycle,
1657 gpmc_t->cs_rd_off + dev_t->t_cez_r);
1658 temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1659 gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1660
1661 return 0;
1662 }
1663
gpmc_calc_async_write_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool mux)1664 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1665 struct gpmc_device_timings *dev_t,
1666 bool mux)
1667 {
1668 u32 temp;
1669
1670 /* adv_wr_off */
1671 temp = dev_t->t_avdp_w;
1672 if (mux)
1673 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1674 gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1675
1676 /* wr_data_mux_bus */
1677 temp = dev_t->t_weasu;
1678 if (mux) {
1679 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1680 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1681 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1682 }
1683 gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1684
1685 /* we_on */
1686 if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1687 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1688 else
1689 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1690
1691 /* we_off */
1692 temp = gpmc_t->we_on + dev_t->t_wpl;
1693 gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1694
1695 gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1696 dev_t->t_wph);
1697
1698 /* wr_cycle */
1699 temp = max_t(u32, dev_t->t_wr_cycle,
1700 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1701 gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1702
1703 return 0;
1704 }
1705
gpmc_calc_sync_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t)1706 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1707 struct gpmc_device_timings *dev_t)
1708 {
1709 u32 temp;
1710
1711 gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1712 gpmc_get_fclk_period();
1713
1714 gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1715 dev_t->t_bacc,
1716 gpmc_t->sync_clk);
1717
1718 temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1719 gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1720
1721 if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1722 return 0;
1723
1724 if (dev_t->ce_xdelay)
1725 gpmc_t->bool_timings.cs_extra_delay = true;
1726 if (dev_t->avd_xdelay)
1727 gpmc_t->bool_timings.adv_extra_delay = true;
1728 if (dev_t->oe_xdelay)
1729 gpmc_t->bool_timings.oe_extra_delay = true;
1730 if (dev_t->we_xdelay)
1731 gpmc_t->bool_timings.we_extra_delay = true;
1732
1733 return 0;
1734 }
1735
gpmc_calc_common_timings(struct gpmc_timings * gpmc_t,struct gpmc_device_timings * dev_t,bool sync)1736 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1737 struct gpmc_device_timings *dev_t,
1738 bool sync)
1739 {
1740 u32 temp;
1741
1742 /* cs_on */
1743 gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1744
1745 /* adv_on */
1746 temp = dev_t->t_avdasu;
1747 if (dev_t->t_ce_avd)
1748 temp = max_t(u32, temp,
1749 gpmc_t->cs_on + dev_t->t_ce_avd);
1750 gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1751
1752 if (sync)
1753 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1754
1755 return 0;
1756 }
1757
1758 /* TODO: remove this function once all peripherals are confirmed to
1759 * work with generic timing. Simultaneously gpmc_cs_set_timings()
1760 * has to be modified to handle timings in ps instead of ns
1761 */
gpmc_convert_ps_to_ns(struct gpmc_timings * t)1762 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1763 {
1764 t->cs_on /= 1000;
1765 t->cs_rd_off /= 1000;
1766 t->cs_wr_off /= 1000;
1767 t->adv_on /= 1000;
1768 t->adv_rd_off /= 1000;
1769 t->adv_wr_off /= 1000;
1770 t->we_on /= 1000;
1771 t->we_off /= 1000;
1772 t->oe_on /= 1000;
1773 t->oe_off /= 1000;
1774 t->page_burst_access /= 1000;
1775 t->access /= 1000;
1776 t->rd_cycle /= 1000;
1777 t->wr_cycle /= 1000;
1778 t->bus_turnaround /= 1000;
1779 t->cycle2cycle_delay /= 1000;
1780 t->wait_monitoring /= 1000;
1781 t->clk_activation /= 1000;
1782 t->wr_access /= 1000;
1783 t->wr_data_mux_bus /= 1000;
1784 }
1785
gpmc_calc_timings(struct gpmc_timings * gpmc_t,struct gpmc_settings * gpmc_s,struct gpmc_device_timings * dev_t)1786 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1787 struct gpmc_settings *gpmc_s,
1788 struct gpmc_device_timings *dev_t)
1789 {
1790 bool mux = false, sync = false;
1791
1792 if (gpmc_s) {
1793 mux = gpmc_s->mux_add_data ? true : false;
1794 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1795 }
1796
1797 memset(gpmc_t, 0, sizeof(*gpmc_t));
1798
1799 gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1800
1801 if (gpmc_s && gpmc_s->sync_read)
1802 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1803 else
1804 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1805
1806 if (gpmc_s && gpmc_s->sync_write)
1807 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1808 else
1809 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1810
1811 /* TODO: remove, see function definition */
1812 gpmc_convert_ps_to_ns(gpmc_t);
1813
1814 return 0;
1815 }
1816
1817 /**
1818 * gpmc_cs_program_settings - programs non-timing related settings
1819 * @cs: GPMC chip-select to program
1820 * @p: pointer to GPMC settings structure
1821 *
1822 * Programs non-timing related settings for a GPMC chip-select, such as
1823 * bus-width, burst configuration, etc. Function should be called once
1824 * for each chip-select that is being used and must be called before
1825 * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1826 * register will be initialised to zero by this function. Returns 0 on
1827 * success and appropriate negative error code on failure.
1828 */
gpmc_cs_program_settings(int cs,struct gpmc_settings * p)1829 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1830 {
1831 u32 config1;
1832
1833 if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1834 pr_err("%s: invalid width %d!", __func__, p->device_width);
1835 return -EINVAL;
1836 }
1837
1838 /* Address-data multiplexing not supported for NAND devices */
1839 if (p->device_nand && p->mux_add_data) {
1840 pr_err("%s: invalid configuration!\n", __func__);
1841 return -EINVAL;
1842 }
1843
1844 if ((p->mux_add_data > GPMC_MUX_AD) ||
1845 ((p->mux_add_data == GPMC_MUX_AAD) &&
1846 !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1847 pr_err("%s: invalid multiplex configuration!\n", __func__);
1848 return -EINVAL;
1849 }
1850
1851 /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1852 if (p->burst_read || p->burst_write) {
1853 switch (p->burst_len) {
1854 case GPMC_BURST_4:
1855 case GPMC_BURST_8:
1856 case GPMC_BURST_16:
1857 break;
1858 default:
1859 pr_err("%s: invalid page/burst-length (%d)\n",
1860 __func__, p->burst_len);
1861 return -EINVAL;
1862 }
1863 }
1864
1865 if (p->wait_pin > gpmc_nr_waitpins) {
1866 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1867 return -EINVAL;
1868 }
1869
1870 config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1871
1872 if (p->sync_read)
1873 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1874 if (p->sync_write)
1875 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1876 if (p->wait_on_read)
1877 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1878 if (p->wait_on_write)
1879 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1880 if (p->wait_on_read || p->wait_on_write)
1881 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1882 if (p->device_nand)
1883 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1884 if (p->mux_add_data)
1885 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1886 if (p->burst_read)
1887 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1888 if (p->burst_write)
1889 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1890 if (p->burst_read || p->burst_write) {
1891 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1892 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1893 }
1894
1895 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1896
1897 return 0;
1898 }
1899
1900 #ifdef CONFIG_OF
1901 static const struct of_device_id gpmc_dt_ids[] = {
1902 { .compatible = "ti,omap2420-gpmc" },
1903 { .compatible = "ti,omap2430-gpmc" },
1904 { .compatible = "ti,omap3430-gpmc" }, /* omap3430 & omap3630 */
1905 { .compatible = "ti,omap4430-gpmc" }, /* omap4430 & omap4460 & omap543x */
1906 { .compatible = "ti,am3352-gpmc" }, /* am335x devices */
1907 { }
1908 };
1909
1910 /**
1911 * gpmc_read_settings_dt - read gpmc settings from device-tree
1912 * @np: pointer to device-tree node for a gpmc child device
1913 * @p: pointer to gpmc settings structure
1914 *
1915 * Reads the GPMC settings for a GPMC child device from device-tree and
1916 * stores them in the GPMC settings structure passed. The GPMC settings
1917 * structure is initialised to zero by this function and so any
1918 * previously stored settings will be cleared.
1919 */
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)1920 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1921 {
1922 memset(p, 0, sizeof(struct gpmc_settings));
1923
1924 p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1925 p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1926 of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1927 of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1928
1929 if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1930 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1931 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1932 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1933 if (!p->burst_read && !p->burst_write)
1934 pr_warn("%s: page/burst-length set but not used!\n",
1935 __func__);
1936 }
1937
1938 if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1939 p->wait_on_read = of_property_read_bool(np,
1940 "gpmc,wait-on-read");
1941 p->wait_on_write = of_property_read_bool(np,
1942 "gpmc,wait-on-write");
1943 if (!p->wait_on_read && !p->wait_on_write)
1944 pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1945 __func__);
1946 }
1947 }
1948
gpmc_read_timings_dt(struct device_node * np,struct gpmc_timings * gpmc_t)1949 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1950 struct gpmc_timings *gpmc_t)
1951 {
1952 struct gpmc_bool_timings *p;
1953
1954 if (!np || !gpmc_t)
1955 return;
1956
1957 memset(gpmc_t, 0, sizeof(*gpmc_t));
1958
1959 /* minimum clock period for syncronous mode */
1960 of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
1961
1962 /* chip select timtings */
1963 of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
1964 of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
1965 of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
1966
1967 /* ADV signal timings */
1968 of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
1969 of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
1970 of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
1971 of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
1972 &gpmc_t->adv_aad_mux_on);
1973 of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
1974 &gpmc_t->adv_aad_mux_rd_off);
1975 of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
1976 &gpmc_t->adv_aad_mux_wr_off);
1977
1978 /* WE signal timings */
1979 of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
1980 of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
1981
1982 /* OE signal timings */
1983 of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
1984 of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
1985 of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
1986 &gpmc_t->oe_aad_mux_on);
1987 of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
1988 &gpmc_t->oe_aad_mux_off);
1989
1990 /* access and cycle timings */
1991 of_property_read_u32(np, "gpmc,page-burst-access-ns",
1992 &gpmc_t->page_burst_access);
1993 of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
1994 of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
1995 of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
1996 of_property_read_u32(np, "gpmc,bus-turnaround-ns",
1997 &gpmc_t->bus_turnaround);
1998 of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
1999 &gpmc_t->cycle2cycle_delay);
2000 of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2001 &gpmc_t->wait_monitoring);
2002 of_property_read_u32(np, "gpmc,clk-activation-ns",
2003 &gpmc_t->clk_activation);
2004
2005 /* only applicable to OMAP3+ */
2006 of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2007 of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2008 &gpmc_t->wr_data_mux_bus);
2009
2010 /* bool timing parameters */
2011 p = &gpmc_t->bool_timings;
2012
2013 p->cycle2cyclediffcsen =
2014 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2015 p->cycle2cyclesamecsen =
2016 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2017 p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2018 p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2019 p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2020 p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2021 p->time_para_granularity =
2022 of_property_read_bool(np, "gpmc,time-para-granularity");
2023 }
2024
2025 /**
2026 * gpmc_probe_generic_child - configures the gpmc for a child device
2027 * @pdev: pointer to gpmc platform device
2028 * @child: pointer to device-tree node for child device
2029 *
2030 * Allocates and configures a GPMC chip-select for a child device.
2031 * Returns 0 on success and appropriate negative error code on failure.
2032 */
gpmc_probe_generic_child(struct platform_device * pdev,struct device_node * child)2033 static int gpmc_probe_generic_child(struct platform_device *pdev,
2034 struct device_node *child)
2035 {
2036 struct gpmc_settings gpmc_s;
2037 struct gpmc_timings gpmc_t;
2038 struct resource res;
2039 unsigned long base;
2040 const char *name;
2041 int ret, cs;
2042 u32 val;
2043 struct gpio_desc *waitpin_desc = NULL;
2044 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2045
2046 if (of_property_read_u32(child, "reg", &cs) < 0) {
2047 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2048 child);
2049 return -ENODEV;
2050 }
2051
2052 if (of_address_to_resource(child, 0, &res) < 0) {
2053 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2054 child);
2055 return -ENODEV;
2056 }
2057
2058 /*
2059 * Check if we have multiple instances of the same device
2060 * on a single chip select. If so, use the already initialized
2061 * timings.
2062 */
2063 name = gpmc_cs_get_name(cs);
2064 if (name && of_node_cmp(child->name, name) == 0)
2065 goto no_timings;
2066
2067 ret = gpmc_cs_request(cs, resource_size(&res), &base);
2068 if (ret < 0) {
2069 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2070 return ret;
2071 }
2072 gpmc_cs_set_name(cs, child->name);
2073
2074 gpmc_read_settings_dt(child, &gpmc_s);
2075 gpmc_read_timings_dt(child, &gpmc_t);
2076
2077 /*
2078 * For some GPMC devices we still need to rely on the bootloader
2079 * timings because the devices can be connected via FPGA.
2080 * REVISIT: Add timing support from slls644g.pdf.
2081 */
2082 if (!gpmc_t.cs_rd_off) {
2083 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2084 cs);
2085 gpmc_cs_show_timings(cs,
2086 "please add GPMC bootloader timings to .dts");
2087 goto no_timings;
2088 }
2089
2090 /* CS must be disabled while making changes to gpmc configuration */
2091 gpmc_cs_disable_mem(cs);
2092
2093 /*
2094 * FIXME: gpmc_cs_request() will map the CS to an arbitary
2095 * location in the gpmc address space. When booting with
2096 * device-tree we want the NOR flash to be mapped to the
2097 * location specified in the device-tree blob. So remap the
2098 * CS to this location. Once DT migration is complete should
2099 * just make gpmc_cs_request() map a specific address.
2100 */
2101 ret = gpmc_cs_remap(cs, res.start);
2102 if (ret < 0) {
2103 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2104 cs, &res.start);
2105 if (res.start < GPMC_MEM_START) {
2106 dev_info(&pdev->dev,
2107 "GPMC CS %d start cannot be lesser than 0x%x\n",
2108 cs, GPMC_MEM_START);
2109 } else if (res.end > GPMC_MEM_END) {
2110 dev_info(&pdev->dev,
2111 "GPMC CS %d end cannot be greater than 0x%x\n",
2112 cs, GPMC_MEM_END);
2113 }
2114 goto err;
2115 }
2116
2117 if (of_node_cmp(child->name, "nand") == 0) {
2118 /* Warn about older DT blobs with no compatible property */
2119 if (!of_property_read_bool(child, "compatible")) {
2120 dev_warn(&pdev->dev,
2121 "Incompatible NAND node: missing compatible");
2122 ret = -EINVAL;
2123 goto err;
2124 }
2125 }
2126
2127 if (of_node_cmp(child->name, "onenand") == 0) {
2128 /* Warn about older DT blobs with no compatible property */
2129 if (!of_property_read_bool(child, "compatible")) {
2130 dev_warn(&pdev->dev,
2131 "Incompatible OneNAND node: missing compatible");
2132 ret = -EINVAL;
2133 goto err;
2134 }
2135 }
2136
2137 if (of_device_is_compatible(child, "ti,omap2-nand")) {
2138 /* NAND specific setup */
2139 val = 8;
2140 of_property_read_u32(child, "nand-bus-width", &val);
2141 switch (val) {
2142 case 8:
2143 gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2144 break;
2145 case 16:
2146 gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2147 break;
2148 default:
2149 dev_err(&pdev->dev, "%s: invalid 'nand-bus-width'\n",
2150 child->name);
2151 ret = -EINVAL;
2152 goto err;
2153 }
2154
2155 /* disable write protect */
2156 gpmc_configure(GPMC_CONFIG_WP, 0);
2157 gpmc_s.device_nand = true;
2158 } else {
2159 ret = of_property_read_u32(child, "bank-width",
2160 &gpmc_s.device_width);
2161 if (ret < 0 && !gpmc_s.device_width) {
2162 dev_err(&pdev->dev,
2163 "%pOF has no 'gpmc,device-width' property\n",
2164 child);
2165 goto err;
2166 }
2167 }
2168
2169 /* Reserve wait pin if it is required and valid */
2170 if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2171 unsigned int wait_pin = gpmc_s.wait_pin;
2172
2173 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2174 wait_pin, "WAITPIN");
2175 if (IS_ERR(waitpin_desc)) {
2176 dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2177 ret = PTR_ERR(waitpin_desc);
2178 goto err;
2179 }
2180 }
2181
2182 gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2183
2184 ret = gpmc_cs_program_settings(cs, &gpmc_s);
2185 if (ret < 0)
2186 goto err_cs;
2187
2188 ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2189 if (ret) {
2190 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
2191 child->name);
2192 goto err_cs;
2193 }
2194
2195 /* Clear limited address i.e. enable A26-A11 */
2196 val = gpmc_read_reg(GPMC_CONFIG);
2197 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2198 gpmc_write_reg(GPMC_CONFIG, val);
2199
2200 /* Enable CS region */
2201 gpmc_cs_enable_mem(cs);
2202
2203 no_timings:
2204
2205 /* create platform device, NULL on error or when disabled */
2206 if (!of_platform_device_create(child, NULL, &pdev->dev))
2207 goto err_child_fail;
2208
2209 /* is child a common bus? */
2210 if (of_match_node(of_default_bus_match_table, child))
2211 /* create children and other common bus children */
2212 if (of_platform_default_populate(child, NULL, &pdev->dev))
2213 goto err_child_fail;
2214
2215 return 0;
2216
2217 err_child_fail:
2218
2219 dev_err(&pdev->dev, "failed to create gpmc child %s\n", child->name);
2220 ret = -ENODEV;
2221
2222 err_cs:
2223 gpiochip_free_own_desc(waitpin_desc);
2224 err:
2225 gpmc_cs_free(cs);
2226
2227 return ret;
2228 }
2229
gpmc_probe_dt(struct platform_device * pdev)2230 static int gpmc_probe_dt(struct platform_device *pdev)
2231 {
2232 int ret;
2233 const struct of_device_id *of_id =
2234 of_match_device(gpmc_dt_ids, &pdev->dev);
2235
2236 if (!of_id)
2237 return 0;
2238
2239 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2240 &gpmc_cs_num);
2241 if (ret < 0) {
2242 pr_err("%s: number of chip-selects not defined\n", __func__);
2243 return ret;
2244 } else if (gpmc_cs_num < 1) {
2245 pr_err("%s: all chip-selects are disabled\n", __func__);
2246 return -EINVAL;
2247 } else if (gpmc_cs_num > GPMC_CS_NUM) {
2248 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2249 __func__, GPMC_CS_NUM);
2250 return -EINVAL;
2251 }
2252
2253 ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2254 &gpmc_nr_waitpins);
2255 if (ret < 0) {
2256 pr_err("%s: number of wait pins not found!\n", __func__);
2257 return ret;
2258 }
2259
2260 return 0;
2261 }
2262
gpmc_probe_dt_children(struct platform_device * pdev)2263 static void gpmc_probe_dt_children(struct platform_device *pdev)
2264 {
2265 int ret;
2266 struct device_node *child;
2267
2268 for_each_available_child_of_node(pdev->dev.of_node, child) {
2269
2270 if (!child->name)
2271 continue;
2272
2273 ret = gpmc_probe_generic_child(pdev, child);
2274 if (ret) {
2275 dev_err(&pdev->dev, "failed to probe DT child '%s': %d\n",
2276 child->name, ret);
2277 }
2278 }
2279 }
2280 #else
gpmc_read_settings_dt(struct device_node * np,struct gpmc_settings * p)2281 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2282 {
2283 memset(p, 0, sizeof(*p));
2284 }
gpmc_probe_dt(struct platform_device * pdev)2285 static int gpmc_probe_dt(struct platform_device *pdev)
2286 {
2287 return 0;
2288 }
2289
gpmc_probe_dt_children(struct platform_device * pdev)2290 static void gpmc_probe_dt_children(struct platform_device *pdev)
2291 {
2292 }
2293 #endif /* CONFIG_OF */
2294
gpmc_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)2295 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2296 {
2297 return 1; /* we're input only */
2298 }
2299
gpmc_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)2300 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2301 unsigned int offset)
2302 {
2303 return 0; /* we're input only */
2304 }
2305
gpmc_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)2306 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2307 unsigned int offset, int value)
2308 {
2309 return -EINVAL; /* we're input only */
2310 }
2311
gpmc_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)2312 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2313 int value)
2314 {
2315 }
2316
gpmc_gpio_get(struct gpio_chip * chip,unsigned int offset)2317 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2318 {
2319 u32 reg;
2320
2321 offset += 8;
2322
2323 reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2324
2325 return !!reg;
2326 }
2327
gpmc_gpio_init(struct gpmc_device * gpmc)2328 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2329 {
2330 int ret;
2331
2332 gpmc->gpio_chip.parent = gpmc->dev;
2333 gpmc->gpio_chip.owner = THIS_MODULE;
2334 gpmc->gpio_chip.label = DEVICE_NAME;
2335 gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2336 gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2337 gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2338 gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2339 gpmc->gpio_chip.set = gpmc_gpio_set;
2340 gpmc->gpio_chip.get = gpmc_gpio_get;
2341 gpmc->gpio_chip.base = -1;
2342
2343 ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2344 if (ret < 0) {
2345 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2346 return ret;
2347 }
2348
2349 return 0;
2350 }
2351
gpmc_probe(struct platform_device * pdev)2352 static int gpmc_probe(struct platform_device *pdev)
2353 {
2354 int rc;
2355 u32 l;
2356 struct resource *res;
2357 struct gpmc_device *gpmc;
2358
2359 gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2360 if (!gpmc)
2361 return -ENOMEM;
2362
2363 gpmc->dev = &pdev->dev;
2364 platform_set_drvdata(pdev, gpmc);
2365
2366 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2367 if (res == NULL)
2368 return -ENOENT;
2369
2370 phys_base = res->start;
2371 mem_size = resource_size(res);
2372
2373 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2374 if (IS_ERR(gpmc_base))
2375 return PTR_ERR(gpmc_base);
2376
2377 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
2378 if (!res) {
2379 dev_err(&pdev->dev, "Failed to get resource: irq\n");
2380 return -ENOENT;
2381 }
2382
2383 gpmc->irq = res->start;
2384
2385 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2386 if (IS_ERR(gpmc_l3_clk)) {
2387 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2388 return PTR_ERR(gpmc_l3_clk);
2389 }
2390
2391 if (!clk_get_rate(gpmc_l3_clk)) {
2392 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2393 return -EINVAL;
2394 }
2395
2396 if (pdev->dev.of_node) {
2397 rc = gpmc_probe_dt(pdev);
2398 if (rc)
2399 return rc;
2400 } else {
2401 gpmc_cs_num = GPMC_CS_NUM;
2402 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2403 }
2404
2405 pm_runtime_enable(&pdev->dev);
2406 pm_runtime_get_sync(&pdev->dev);
2407
2408 l = gpmc_read_reg(GPMC_REVISION);
2409
2410 /*
2411 * FIXME: Once device-tree migration is complete the below flags
2412 * should be populated based upon the device-tree compatible
2413 * string. For now just use the IP revision. OMAP3+ devices have
2414 * the wr_access and wr_data_mux_bus register fields. OMAP4+
2415 * devices support the addr-addr-data multiplex protocol.
2416 *
2417 * GPMC IP revisions:
2418 * - OMAP24xx = 2.0
2419 * - OMAP3xxx = 5.0
2420 * - OMAP44xx/54xx/AM335x = 6.0
2421 */
2422 if (GPMC_REVISION_MAJOR(l) > 0x4)
2423 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2424 if (GPMC_REVISION_MAJOR(l) > 0x5)
2425 gpmc_capability |= GPMC_HAS_MUX_AAD;
2426 dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2427 GPMC_REVISION_MINOR(l));
2428
2429 gpmc_mem_init();
2430 rc = gpmc_gpio_init(gpmc);
2431 if (rc)
2432 goto gpio_init_failed;
2433
2434 gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2435 rc = gpmc_setup_irq(gpmc);
2436 if (rc) {
2437 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2438 goto gpio_init_failed;
2439 }
2440
2441 gpmc_probe_dt_children(pdev);
2442
2443 return 0;
2444
2445 gpio_init_failed:
2446 gpmc_mem_exit();
2447 pm_runtime_put_sync(&pdev->dev);
2448 pm_runtime_disable(&pdev->dev);
2449
2450 return rc;
2451 }
2452
gpmc_remove(struct platform_device * pdev)2453 static int gpmc_remove(struct platform_device *pdev)
2454 {
2455 struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2456
2457 gpmc_free_irq(gpmc);
2458 gpmc_mem_exit();
2459 pm_runtime_put_sync(&pdev->dev);
2460 pm_runtime_disable(&pdev->dev);
2461
2462 return 0;
2463 }
2464
2465 #ifdef CONFIG_PM_SLEEP
gpmc_suspend(struct device * dev)2466 static int gpmc_suspend(struct device *dev)
2467 {
2468 omap3_gpmc_save_context();
2469 pm_runtime_put_sync(dev);
2470 return 0;
2471 }
2472
gpmc_resume(struct device * dev)2473 static int gpmc_resume(struct device *dev)
2474 {
2475 pm_runtime_get_sync(dev);
2476 omap3_gpmc_restore_context();
2477 return 0;
2478 }
2479 #endif
2480
2481 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2482
2483 static struct platform_driver gpmc_driver = {
2484 .probe = gpmc_probe,
2485 .remove = gpmc_remove,
2486 .driver = {
2487 .name = DEVICE_NAME,
2488 .of_match_table = of_match_ptr(gpmc_dt_ids),
2489 .pm = &gpmc_pm_ops,
2490 },
2491 };
2492
gpmc_init(void)2493 static __init int gpmc_init(void)
2494 {
2495 return platform_driver_register(&gpmc_driver);
2496 }
2497 postcore_initcall(gpmc_init);
2498
2499 static struct omap3_gpmc_regs gpmc_context;
2500
omap3_gpmc_save_context(void)2501 void omap3_gpmc_save_context(void)
2502 {
2503 int i;
2504
2505 if (!gpmc_base)
2506 return;
2507
2508 gpmc_context.sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2509 gpmc_context.irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2510 gpmc_context.timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2511 gpmc_context.config = gpmc_read_reg(GPMC_CONFIG);
2512 gpmc_context.prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2513 gpmc_context.prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2514 gpmc_context.prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2515 for (i = 0; i < gpmc_cs_num; i++) {
2516 gpmc_context.cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2517 if (gpmc_context.cs_context[i].is_valid) {
2518 gpmc_context.cs_context[i].config1 =
2519 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2520 gpmc_context.cs_context[i].config2 =
2521 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2522 gpmc_context.cs_context[i].config3 =
2523 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2524 gpmc_context.cs_context[i].config4 =
2525 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2526 gpmc_context.cs_context[i].config5 =
2527 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2528 gpmc_context.cs_context[i].config6 =
2529 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2530 gpmc_context.cs_context[i].config7 =
2531 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2532 }
2533 }
2534 }
2535
omap3_gpmc_restore_context(void)2536 void omap3_gpmc_restore_context(void)
2537 {
2538 int i;
2539
2540 if (!gpmc_base)
2541 return;
2542
2543 gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context.sysconfig);
2544 gpmc_write_reg(GPMC_IRQENABLE, gpmc_context.irqenable);
2545 gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context.timeout_ctrl);
2546 gpmc_write_reg(GPMC_CONFIG, gpmc_context.config);
2547 gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context.prefetch_config1);
2548 gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context.prefetch_config2);
2549 gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context.prefetch_control);
2550 for (i = 0; i < gpmc_cs_num; i++) {
2551 if (gpmc_context.cs_context[i].is_valid) {
2552 gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2553 gpmc_context.cs_context[i].config1);
2554 gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2555 gpmc_context.cs_context[i].config2);
2556 gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2557 gpmc_context.cs_context[i].config3);
2558 gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2559 gpmc_context.cs_context[i].config4);
2560 gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2561 gpmc_context.cs_context[i].config5);
2562 gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2563 gpmc_context.cs_context[i].config6);
2564 gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2565 gpmc_context.cs_context[i].config7);
2566 }
2567 }
2568 }
2569