1 /*
2 * Common Flash Interface support:
3 * AMD & Fujitsu Standard Vendor Command Set (ID 0x0002)
4 *
5 * Copyright (C) 2000 Crossnet Co. <info@crossnet.co.jp>
6 * Copyright (C) 2004 Arcom Control Systems Ltd <linux@arcom.com>
7 * Copyright (C) 2005 MontaVista Software Inc. <source@mvista.com>
8 *
9 * 2_by_8 routines added by Simon Munton
10 *
11 * 4_by_16 work by Carolyn J. Smith
12 *
13 * XIP support hooks by Vitaly Wool (based on code for Intel flash
14 * by Nicolas Pitre)
15 *
16 * 25/09/2008 Christopher Moore: TopBottom fixup for many Macronix with CFI V1.0
17 *
18 * Occasionally maintained by Thayne Harbaugh tharbaugh at lnxi dot com
19 *
20 * This code is GPL
21 */
22
23 #include <linux/module.h>
24 #include <linux/types.h>
25 #include <linux/kernel.h>
26 #include <linux/sched.h>
27 #include <asm/io.h>
28 #include <asm/byteorder.h>
29
30 #include <linux/errno.h>
31 #include <linux/slab.h>
32 #include <linux/delay.h>
33 #include <linux/interrupt.h>
34 #include <linux/reboot.h>
35 #include <linux/of.h>
36 #include <linux/of_platform.h>
37 #include <linux/mtd/map.h>
38 #include <linux/mtd/mtd.h>
39 #include <linux/mtd/cfi.h>
40 #include <linux/mtd/xip.h>
41
42 #define AMD_BOOTLOC_BUG
43 #define FORCE_WORD_WRITE 0
44
45 #define MAX_RETRIES 3
46
47 #define SST49LF004B 0x0060
48 #define SST49LF040B 0x0050
49 #define SST49LF008A 0x005a
50 #define AT49BV6416 0x00d6
51
52 static int cfi_amdstd_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
53 static int cfi_amdstd_write_words(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
54 static int cfi_amdstd_write_buffers(struct mtd_info *, loff_t, size_t, size_t *, const u_char *);
55 static int cfi_amdstd_erase_chip(struct mtd_info *, struct erase_info *);
56 static int cfi_amdstd_erase_varsize(struct mtd_info *, struct erase_info *);
57 static void cfi_amdstd_sync (struct mtd_info *);
58 static int cfi_amdstd_suspend (struct mtd_info *);
59 static void cfi_amdstd_resume (struct mtd_info *);
60 static int cfi_amdstd_reboot(struct notifier_block *, unsigned long, void *);
61 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *, size_t,
62 size_t *, struct otp_info *);
63 static int cfi_amdstd_get_user_prot_info(struct mtd_info *, size_t,
64 size_t *, struct otp_info *);
65 static int cfi_amdstd_secsi_read (struct mtd_info *, loff_t, size_t, size_t *, u_char *);
66 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *, loff_t, size_t,
67 size_t *, u_char *);
68 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *, loff_t, size_t,
69 size_t *, u_char *);
70 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *, loff_t, size_t,
71 size_t *, u_char *);
72 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *, loff_t, size_t);
73
74 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
75 size_t *retlen, const u_char *buf);
76
77 static void cfi_amdstd_destroy(struct mtd_info *);
78
79 struct mtd_info *cfi_cmdset_0002(struct map_info *, int);
80 static struct mtd_info *cfi_amdstd_setup (struct mtd_info *);
81
82 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode);
83 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr);
84 #include "fwh_lock.h"
85
86 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
87 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
88
89 static int cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
90 static int cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len);
91 static int cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs, uint64_t len);
92
93 static struct mtd_chip_driver cfi_amdstd_chipdrv = {
94 .probe = NULL, /* Not usable directly */
95 .destroy = cfi_amdstd_destroy,
96 .name = "cfi_cmdset_0002",
97 .module = THIS_MODULE
98 };
99
100
101 /* #define DEBUG_CFI_FEATURES */
102
103
104 #ifdef DEBUG_CFI_FEATURES
cfi_tell_features(struct cfi_pri_amdstd * extp)105 static void cfi_tell_features(struct cfi_pri_amdstd *extp)
106 {
107 const char* erase_suspend[3] = {
108 "Not supported", "Read only", "Read/write"
109 };
110 const char* top_bottom[6] = {
111 "No WP", "8x8KiB sectors at top & bottom, no WP",
112 "Bottom boot", "Top boot",
113 "Uniform, Bottom WP", "Uniform, Top WP"
114 };
115
116 printk(" Silicon revision: %d\n", extp->SiliconRevision >> 1);
117 printk(" Address sensitive unlock: %s\n",
118 (extp->SiliconRevision & 1) ? "Not required" : "Required");
119
120 if (extp->EraseSuspend < ARRAY_SIZE(erase_suspend))
121 printk(" Erase Suspend: %s\n", erase_suspend[extp->EraseSuspend]);
122 else
123 printk(" Erase Suspend: Unknown value %d\n", extp->EraseSuspend);
124
125 if (extp->BlkProt == 0)
126 printk(" Block protection: Not supported\n");
127 else
128 printk(" Block protection: %d sectors per group\n", extp->BlkProt);
129
130
131 printk(" Temporary block unprotect: %s\n",
132 extp->TmpBlkUnprotect ? "Supported" : "Not supported");
133 printk(" Block protect/unprotect scheme: %d\n", extp->BlkProtUnprot);
134 printk(" Number of simultaneous operations: %d\n", extp->SimultaneousOps);
135 printk(" Burst mode: %s\n",
136 extp->BurstMode ? "Supported" : "Not supported");
137 if (extp->PageMode == 0)
138 printk(" Page mode: Not supported\n");
139 else
140 printk(" Page mode: %d word page\n", extp->PageMode << 2);
141
142 printk(" Vpp Supply Minimum Program/Erase Voltage: %d.%d V\n",
143 extp->VppMin >> 4, extp->VppMin & 0xf);
144 printk(" Vpp Supply Maximum Program/Erase Voltage: %d.%d V\n",
145 extp->VppMax >> 4, extp->VppMax & 0xf);
146
147 if (extp->TopBottom < ARRAY_SIZE(top_bottom))
148 printk(" Top/Bottom Boot Block: %s\n", top_bottom[extp->TopBottom]);
149 else
150 printk(" Top/Bottom Boot Block: Unknown value %d\n", extp->TopBottom);
151 }
152 #endif
153
154 #ifdef AMD_BOOTLOC_BUG
155 /* Wheee. Bring me the head of someone at AMD. */
fixup_amd_bootblock(struct mtd_info * mtd)156 static void fixup_amd_bootblock(struct mtd_info *mtd)
157 {
158 struct map_info *map = mtd->priv;
159 struct cfi_private *cfi = map->fldrv_priv;
160 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
161 __u8 major = extp->MajorVersion;
162 __u8 minor = extp->MinorVersion;
163
164 if (((major << 8) | minor) < 0x3131) {
165 /* CFI version 1.0 => don't trust bootloc */
166
167 pr_debug("%s: JEDEC Vendor ID is 0x%02X Device ID is 0x%02X\n",
168 map->name, cfi->mfr, cfi->id);
169
170 /* AFAICS all 29LV400 with a bottom boot block have a device ID
171 * of 0x22BA in 16-bit mode and 0xBA in 8-bit mode.
172 * These were badly detected as they have the 0x80 bit set
173 * so treat them as a special case.
174 */
175 if (((cfi->id == 0xBA) || (cfi->id == 0x22BA)) &&
176
177 /* Macronix added CFI to their 2nd generation
178 * MX29LV400C B/T but AFAICS no other 29LV400 (AMD,
179 * Fujitsu, Spansion, EON, ESI and older Macronix)
180 * has CFI.
181 *
182 * Therefore also check the manufacturer.
183 * This reduces the risk of false detection due to
184 * the 8-bit device ID.
185 */
186 (cfi->mfr == CFI_MFR_MACRONIX)) {
187 pr_debug("%s: Macronix MX29LV400C with bottom boot block"
188 " detected\n", map->name);
189 extp->TopBottom = 2; /* bottom boot */
190 } else
191 if (cfi->id & 0x80) {
192 printk(KERN_WARNING "%s: JEDEC Device ID is 0x%02X. Assuming broken CFI table.\n", map->name, cfi->id);
193 extp->TopBottom = 3; /* top boot */
194 } else {
195 extp->TopBottom = 2; /* bottom boot */
196 }
197
198 pr_debug("%s: AMD CFI PRI V%c.%c has no boot block field;"
199 " deduced %s from Device ID\n", map->name, major, minor,
200 extp->TopBottom == 2 ? "bottom" : "top");
201 }
202 }
203 #endif
204
fixup_use_write_buffers(struct mtd_info * mtd)205 static void fixup_use_write_buffers(struct mtd_info *mtd)
206 {
207 struct map_info *map = mtd->priv;
208 struct cfi_private *cfi = map->fldrv_priv;
209 if (cfi->cfiq->BufWriteTimeoutTyp) {
210 pr_debug("Using buffer write method\n");
211 mtd->_write = cfi_amdstd_write_buffers;
212 }
213 }
214
215 /* Atmel chips don't use the same PRI format as AMD chips */
fixup_convert_atmel_pri(struct mtd_info * mtd)216 static void fixup_convert_atmel_pri(struct mtd_info *mtd)
217 {
218 struct map_info *map = mtd->priv;
219 struct cfi_private *cfi = map->fldrv_priv;
220 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
221 struct cfi_pri_atmel atmel_pri;
222
223 memcpy(&atmel_pri, extp, sizeof(atmel_pri));
224 memset((char *)extp + 5, 0, sizeof(*extp) - 5);
225
226 if (atmel_pri.Features & 0x02)
227 extp->EraseSuspend = 2;
228
229 /* Some chips got it backwards... */
230 if (cfi->id == AT49BV6416) {
231 if (atmel_pri.BottomBoot)
232 extp->TopBottom = 3;
233 else
234 extp->TopBottom = 2;
235 } else {
236 if (atmel_pri.BottomBoot)
237 extp->TopBottom = 2;
238 else
239 extp->TopBottom = 3;
240 }
241
242 /* burst write mode not supported */
243 cfi->cfiq->BufWriteTimeoutTyp = 0;
244 cfi->cfiq->BufWriteTimeoutMax = 0;
245 }
246
fixup_use_secsi(struct mtd_info * mtd)247 static void fixup_use_secsi(struct mtd_info *mtd)
248 {
249 /* Setup for chips with a secsi area */
250 mtd->_read_user_prot_reg = cfi_amdstd_secsi_read;
251 mtd->_read_fact_prot_reg = cfi_amdstd_secsi_read;
252 }
253
fixup_use_erase_chip(struct mtd_info * mtd)254 static void fixup_use_erase_chip(struct mtd_info *mtd)
255 {
256 struct map_info *map = mtd->priv;
257 struct cfi_private *cfi = map->fldrv_priv;
258 if ((cfi->cfiq->NumEraseRegions == 1) &&
259 ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0)) {
260 mtd->_erase = cfi_amdstd_erase_chip;
261 }
262
263 }
264
265 /*
266 * Some Atmel chips (e.g. the AT49BV6416) power-up with all sectors
267 * locked by default.
268 */
fixup_use_atmel_lock(struct mtd_info * mtd)269 static void fixup_use_atmel_lock(struct mtd_info *mtd)
270 {
271 mtd->_lock = cfi_atmel_lock;
272 mtd->_unlock = cfi_atmel_unlock;
273 mtd->flags |= MTD_POWERUP_LOCK;
274 }
275
fixup_old_sst_eraseregion(struct mtd_info * mtd)276 static void fixup_old_sst_eraseregion(struct mtd_info *mtd)
277 {
278 struct map_info *map = mtd->priv;
279 struct cfi_private *cfi = map->fldrv_priv;
280
281 /*
282 * These flashes report two separate eraseblock regions based on the
283 * sector_erase-size and block_erase-size, although they both operate on the
284 * same memory. This is not allowed according to CFI, so we just pick the
285 * sector_erase-size.
286 */
287 cfi->cfiq->NumEraseRegions = 1;
288 }
289
fixup_sst39vf(struct mtd_info * mtd)290 static void fixup_sst39vf(struct mtd_info *mtd)
291 {
292 struct map_info *map = mtd->priv;
293 struct cfi_private *cfi = map->fldrv_priv;
294
295 fixup_old_sst_eraseregion(mtd);
296
297 cfi->addr_unlock1 = 0x5555;
298 cfi->addr_unlock2 = 0x2AAA;
299 }
300
fixup_sst39vf_rev_b(struct mtd_info * mtd)301 static void fixup_sst39vf_rev_b(struct mtd_info *mtd)
302 {
303 struct map_info *map = mtd->priv;
304 struct cfi_private *cfi = map->fldrv_priv;
305
306 fixup_old_sst_eraseregion(mtd);
307
308 cfi->addr_unlock1 = 0x555;
309 cfi->addr_unlock2 = 0x2AA;
310
311 cfi->sector_erase_cmd = CMD(0x50);
312 }
313
fixup_sst38vf640x_sectorsize(struct mtd_info * mtd)314 static void fixup_sst38vf640x_sectorsize(struct mtd_info *mtd)
315 {
316 struct map_info *map = mtd->priv;
317 struct cfi_private *cfi = map->fldrv_priv;
318
319 fixup_sst39vf_rev_b(mtd);
320
321 /*
322 * CFI reports 1024 sectors (0x03ff+1) of 64KBytes (0x0100*256) where
323 * it should report a size of 8KBytes (0x0020*256).
324 */
325 cfi->cfiq->EraseRegionInfo[0] = 0x002003ff;
326 pr_warn("%s: Bad 38VF640x CFI data; adjusting sector size from 64 to 8KiB\n",
327 mtd->name);
328 }
329
fixup_s29gl064n_sectors(struct mtd_info * mtd)330 static void fixup_s29gl064n_sectors(struct mtd_info *mtd)
331 {
332 struct map_info *map = mtd->priv;
333 struct cfi_private *cfi = map->fldrv_priv;
334
335 if ((cfi->cfiq->EraseRegionInfo[0] & 0xffff) == 0x003f) {
336 cfi->cfiq->EraseRegionInfo[0] |= 0x0040;
337 pr_warn("%s: Bad S29GL064N CFI data; adjust from 64 to 128 sectors\n",
338 mtd->name);
339 }
340 }
341
fixup_s29gl032n_sectors(struct mtd_info * mtd)342 static void fixup_s29gl032n_sectors(struct mtd_info *mtd)
343 {
344 struct map_info *map = mtd->priv;
345 struct cfi_private *cfi = map->fldrv_priv;
346
347 if ((cfi->cfiq->EraseRegionInfo[1] & 0xffff) == 0x007e) {
348 cfi->cfiq->EraseRegionInfo[1] &= ~0x0040;
349 pr_warn("%s: Bad S29GL032N CFI data; adjust from 127 to 63 sectors\n",
350 mtd->name);
351 }
352 }
353
fixup_s29ns512p_sectors(struct mtd_info * mtd)354 static void fixup_s29ns512p_sectors(struct mtd_info *mtd)
355 {
356 struct map_info *map = mtd->priv;
357 struct cfi_private *cfi = map->fldrv_priv;
358
359 /*
360 * S29NS512P flash uses more than 8bits to report number of sectors,
361 * which is not permitted by CFI.
362 */
363 cfi->cfiq->EraseRegionInfo[0] = 0x020001ff;
364 pr_warn("%s: Bad S29NS512P CFI data; adjust to 512 sectors\n",
365 mtd->name);
366 }
367
368 /* Used to fix CFI-Tables of chips without Extended Query Tables */
369 static struct cfi_fixup cfi_nopri_fixup_table[] = {
370 { CFI_MFR_SST, 0x234a, fixup_sst39vf }, /* SST39VF1602 */
371 { CFI_MFR_SST, 0x234b, fixup_sst39vf }, /* SST39VF1601 */
372 { CFI_MFR_SST, 0x235a, fixup_sst39vf }, /* SST39VF3202 */
373 { CFI_MFR_SST, 0x235b, fixup_sst39vf }, /* SST39VF3201 */
374 { CFI_MFR_SST, 0x235c, fixup_sst39vf_rev_b }, /* SST39VF3202B */
375 { CFI_MFR_SST, 0x235d, fixup_sst39vf_rev_b }, /* SST39VF3201B */
376 { CFI_MFR_SST, 0x236c, fixup_sst39vf_rev_b }, /* SST39VF6402B */
377 { CFI_MFR_SST, 0x236d, fixup_sst39vf_rev_b }, /* SST39VF6401B */
378 { 0, 0, NULL }
379 };
380
381 static struct cfi_fixup cfi_fixup_table[] = {
382 { CFI_MFR_ATMEL, CFI_ID_ANY, fixup_convert_atmel_pri },
383 #ifdef AMD_BOOTLOC_BUG
384 { CFI_MFR_AMD, CFI_ID_ANY, fixup_amd_bootblock },
385 { CFI_MFR_AMIC, CFI_ID_ANY, fixup_amd_bootblock },
386 { CFI_MFR_MACRONIX, CFI_ID_ANY, fixup_amd_bootblock },
387 #endif
388 { CFI_MFR_AMD, 0x0050, fixup_use_secsi },
389 { CFI_MFR_AMD, 0x0053, fixup_use_secsi },
390 { CFI_MFR_AMD, 0x0055, fixup_use_secsi },
391 { CFI_MFR_AMD, 0x0056, fixup_use_secsi },
392 { CFI_MFR_AMD, 0x005C, fixup_use_secsi },
393 { CFI_MFR_AMD, 0x005F, fixup_use_secsi },
394 { CFI_MFR_AMD, 0x0c01, fixup_s29gl064n_sectors },
395 { CFI_MFR_AMD, 0x1301, fixup_s29gl064n_sectors },
396 { CFI_MFR_AMD, 0x1a00, fixup_s29gl032n_sectors },
397 { CFI_MFR_AMD, 0x1a01, fixup_s29gl032n_sectors },
398 { CFI_MFR_AMD, 0x3f00, fixup_s29ns512p_sectors },
399 { CFI_MFR_SST, 0x536a, fixup_sst38vf640x_sectorsize }, /* SST38VF6402 */
400 { CFI_MFR_SST, 0x536b, fixup_sst38vf640x_sectorsize }, /* SST38VF6401 */
401 { CFI_MFR_SST, 0x536c, fixup_sst38vf640x_sectorsize }, /* SST38VF6404 */
402 { CFI_MFR_SST, 0x536d, fixup_sst38vf640x_sectorsize }, /* SST38VF6403 */
403 #if !FORCE_WORD_WRITE
404 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_write_buffers },
405 #endif
406 { 0, 0, NULL }
407 };
408 static struct cfi_fixup jedec_fixup_table[] = {
409 { CFI_MFR_SST, SST49LF004B, fixup_use_fwh_lock },
410 { CFI_MFR_SST, SST49LF040B, fixup_use_fwh_lock },
411 { CFI_MFR_SST, SST49LF008A, fixup_use_fwh_lock },
412 { 0, 0, NULL }
413 };
414
415 static struct cfi_fixup fixup_table[] = {
416 /* The CFI vendor ids and the JEDEC vendor IDs appear
417 * to be common. It is like the devices id's are as
418 * well. This table is to pick all cases where
419 * we know that is the case.
420 */
421 { CFI_MFR_ANY, CFI_ID_ANY, fixup_use_erase_chip },
422 { CFI_MFR_ATMEL, AT49BV6416, fixup_use_atmel_lock },
423 { 0, 0, NULL }
424 };
425
426
cfi_fixup_major_minor(struct cfi_private * cfi,struct cfi_pri_amdstd * extp)427 static void cfi_fixup_major_minor(struct cfi_private *cfi,
428 struct cfi_pri_amdstd *extp)
429 {
430 if (cfi->mfr == CFI_MFR_SAMSUNG) {
431 if ((extp->MajorVersion == '0' && extp->MinorVersion == '0') ||
432 (extp->MajorVersion == '3' && extp->MinorVersion == '3')) {
433 /*
434 * Samsung K8P2815UQB and K8D6x16UxM chips
435 * report major=0 / minor=0.
436 * K8D3x16UxC chips report major=3 / minor=3.
437 */
438 printk(KERN_NOTICE " Fixing Samsung's Amd/Fujitsu"
439 " Extended Query version to 1.%c\n",
440 extp->MinorVersion);
441 extp->MajorVersion = '1';
442 }
443 }
444
445 /*
446 * SST 38VF640x chips report major=0xFF / minor=0xFF.
447 */
448 if (cfi->mfr == CFI_MFR_SST && (cfi->id >> 4) == 0x0536) {
449 extp->MajorVersion = '1';
450 extp->MinorVersion = '0';
451 }
452 }
453
is_m29ew(struct cfi_private * cfi)454 static int is_m29ew(struct cfi_private *cfi)
455 {
456 if (cfi->mfr == CFI_MFR_INTEL &&
457 ((cfi->device_type == CFI_DEVICETYPE_X8 && (cfi->id & 0xff) == 0x7e) ||
458 (cfi->device_type == CFI_DEVICETYPE_X16 && cfi->id == 0x227e)))
459 return 1;
460 return 0;
461 }
462
463 /*
464 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 20:
465 * Some revisions of the M29EW suffer from erase suspend hang ups. In
466 * particular, it can occur when the sequence
467 * Erase Confirm -> Suspend -> Program -> Resume
468 * causes a lockup due to internal timing issues. The consequence is that the
469 * erase cannot be resumed without inserting a dummy command after programming
470 * and prior to resuming. [...] The work-around is to issue a dummy write cycle
471 * that writes an F0 command code before the RESUME command.
472 */
cfi_fixup_m29ew_erase_suspend(struct map_info * map,unsigned long adr)473 static void cfi_fixup_m29ew_erase_suspend(struct map_info *map,
474 unsigned long adr)
475 {
476 struct cfi_private *cfi = map->fldrv_priv;
477 /* before resume, insert a dummy 0xF0 cycle for Micron M29EW devices */
478 if (is_m29ew(cfi))
479 map_write(map, CMD(0xF0), adr);
480 }
481
482 /*
483 * From TN-13-07: Patching the Linux Kernel and U-Boot for M29 Flash, page 22:
484 *
485 * Some revisions of the M29EW (for example, A1 and A2 step revisions)
486 * are affected by a problem that could cause a hang up when an ERASE SUSPEND
487 * command is issued after an ERASE RESUME operation without waiting for a
488 * minimum delay. The result is that once the ERASE seems to be completed
489 * (no bits are toggling), the contents of the Flash memory block on which
490 * the erase was ongoing could be inconsistent with the expected values
491 * (typically, the array value is stuck to the 0xC0, 0xC4, 0x80, or 0x84
492 * values), causing a consequent failure of the ERASE operation.
493 * The occurrence of this issue could be high, especially when file system
494 * operations on the Flash are intensive. As a result, it is recommended
495 * that a patch be applied. Intensive file system operations can cause many
496 * calls to the garbage routine to free Flash space (also by erasing physical
497 * Flash blocks) and as a result, many consecutive SUSPEND and RESUME
498 * commands can occur. The problem disappears when a delay is inserted after
499 * the RESUME command by using the udelay() function available in Linux.
500 * The DELAY value must be tuned based on the customer's platform.
501 * The maximum value that fixes the problem in all cases is 500us.
502 * But, in our experience, a delay of 30 µs to 50 µs is sufficient
503 * in most cases.
504 * We have chosen 500µs because this latency is acceptable.
505 */
cfi_fixup_m29ew_delay_after_resume(struct cfi_private * cfi)506 static void cfi_fixup_m29ew_delay_after_resume(struct cfi_private *cfi)
507 {
508 /*
509 * Resolving the Delay After Resume Issue see Micron TN-13-07
510 * Worst case delay must be 500µs but 30-50µs should be ok as well
511 */
512 if (is_m29ew(cfi))
513 cfi_udelay(500);
514 }
515
cfi_cmdset_0002(struct map_info * map,int primary)516 struct mtd_info *cfi_cmdset_0002(struct map_info *map, int primary)
517 {
518 struct cfi_private *cfi = map->fldrv_priv;
519 struct device_node __maybe_unused *np = map->device_node;
520 struct mtd_info *mtd;
521 int i;
522
523 mtd = kzalloc(sizeof(*mtd), GFP_KERNEL);
524 if (!mtd)
525 return NULL;
526 mtd->priv = map;
527 mtd->type = MTD_NORFLASH;
528
529 /* Fill in the default mtd operations */
530 mtd->_erase = cfi_amdstd_erase_varsize;
531 mtd->_write = cfi_amdstd_write_words;
532 mtd->_read = cfi_amdstd_read;
533 mtd->_sync = cfi_amdstd_sync;
534 mtd->_suspend = cfi_amdstd_suspend;
535 mtd->_resume = cfi_amdstd_resume;
536 mtd->_read_user_prot_reg = cfi_amdstd_read_user_prot_reg;
537 mtd->_read_fact_prot_reg = cfi_amdstd_read_fact_prot_reg;
538 mtd->_get_fact_prot_info = cfi_amdstd_get_fact_prot_info;
539 mtd->_get_user_prot_info = cfi_amdstd_get_user_prot_info;
540 mtd->_write_user_prot_reg = cfi_amdstd_write_user_prot_reg;
541 mtd->_lock_user_prot_reg = cfi_amdstd_lock_user_prot_reg;
542 mtd->flags = MTD_CAP_NORFLASH;
543 mtd->name = map->name;
544 mtd->writesize = 1;
545 mtd->writebufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
546
547 pr_debug("MTD %s(): write buffer size %d\n", __func__,
548 mtd->writebufsize);
549
550 mtd->_panic_write = cfi_amdstd_panic_write;
551 mtd->reboot_notifier.notifier_call = cfi_amdstd_reboot;
552
553 if (cfi->cfi_mode==CFI_MODE_CFI){
554 unsigned char bootloc;
555 __u16 adr = primary?cfi->cfiq->P_ADR:cfi->cfiq->A_ADR;
556 struct cfi_pri_amdstd *extp;
557
558 extp = (struct cfi_pri_amdstd*)cfi_read_pri(map, adr, sizeof(*extp), "Amd/Fujitsu");
559 if (extp) {
560 /*
561 * It's a real CFI chip, not one for which the probe
562 * routine faked a CFI structure.
563 */
564 cfi_fixup_major_minor(cfi, extp);
565
566 /*
567 * Valid primary extension versions are: 1.0, 1.1, 1.2, 1.3, 1.4, 1.5
568 * see: http://cs.ozerki.net/zap/pub/axim-x5/docs/cfi_r20.pdf, page 19
569 * http://www.spansion.com/Support/AppNotes/cfi_100_20011201.pdf
570 * http://www.spansion.com/Support/Datasheets/s29ws-p_00_a12_e.pdf
571 * http://www.spansion.com/Support/Datasheets/S29GL_128S_01GS_00_02_e.pdf
572 */
573 if (extp->MajorVersion != '1' ||
574 (extp->MajorVersion == '1' && (extp->MinorVersion < '0' || extp->MinorVersion > '5'))) {
575 printk(KERN_ERR " Unknown Amd/Fujitsu Extended Query "
576 "version %c.%c (%#02x/%#02x).\n",
577 extp->MajorVersion, extp->MinorVersion,
578 extp->MajorVersion, extp->MinorVersion);
579 kfree(extp);
580 kfree(mtd);
581 return NULL;
582 }
583
584 printk(KERN_INFO " Amd/Fujitsu Extended Query version %c.%c.\n",
585 extp->MajorVersion, extp->MinorVersion);
586
587 /* Install our own private info structure */
588 cfi->cmdset_priv = extp;
589
590 /* Apply cfi device specific fixups */
591 cfi_fixup(mtd, cfi_fixup_table);
592
593 #ifdef DEBUG_CFI_FEATURES
594 /* Tell the user about it in lots of lovely detail */
595 cfi_tell_features(extp);
596 #endif
597
598 #ifdef CONFIG_OF
599 if (np && of_property_read_bool(
600 np, "use-advanced-sector-protection")
601 && extp->BlkProtUnprot == 8) {
602 printk(KERN_INFO " Advanced Sector Protection (PPB Locking) supported\n");
603 mtd->_lock = cfi_ppb_lock;
604 mtd->_unlock = cfi_ppb_unlock;
605 mtd->_is_locked = cfi_ppb_is_locked;
606 }
607 #endif
608
609 bootloc = extp->TopBottom;
610 if ((bootloc < 2) || (bootloc > 5)) {
611 printk(KERN_WARNING "%s: CFI contains unrecognised boot "
612 "bank location (%d). Assuming bottom.\n",
613 map->name, bootloc);
614 bootloc = 2;
615 }
616
617 if (bootloc == 3 && cfi->cfiq->NumEraseRegions > 1) {
618 printk(KERN_WARNING "%s: Swapping erase regions for top-boot CFI table.\n", map->name);
619
620 for (i=0; i<cfi->cfiq->NumEraseRegions / 2; i++) {
621 int j = (cfi->cfiq->NumEraseRegions-1)-i;
622
623 swap(cfi->cfiq->EraseRegionInfo[i],
624 cfi->cfiq->EraseRegionInfo[j]);
625 }
626 }
627 /* Set the default CFI lock/unlock addresses */
628 cfi->addr_unlock1 = 0x555;
629 cfi->addr_unlock2 = 0x2aa;
630 }
631 cfi_fixup(mtd, cfi_nopri_fixup_table);
632
633 if (!cfi->addr_unlock1 || !cfi->addr_unlock2) {
634 kfree(mtd);
635 return NULL;
636 }
637
638 } /* CFI mode */
639 else if (cfi->cfi_mode == CFI_MODE_JEDEC) {
640 /* Apply jedec specific fixups */
641 cfi_fixup(mtd, jedec_fixup_table);
642 }
643 /* Apply generic fixups */
644 cfi_fixup(mtd, fixup_table);
645
646 for (i=0; i< cfi->numchips; i++) {
647 cfi->chips[i].word_write_time = 1<<cfi->cfiq->WordWriteTimeoutTyp;
648 cfi->chips[i].buffer_write_time = 1<<cfi->cfiq->BufWriteTimeoutTyp;
649 cfi->chips[i].erase_time = 1<<cfi->cfiq->BlockEraseTimeoutTyp;
650 /*
651 * First calculate the timeout max according to timeout field
652 * of struct cfi_ident that probed from chip's CFI aera, if
653 * available. Specify a minimum of 2000us, in case the CFI data
654 * is wrong.
655 */
656 if (cfi->cfiq->BufWriteTimeoutTyp &&
657 cfi->cfiq->BufWriteTimeoutMax)
658 cfi->chips[i].buffer_write_time_max =
659 1 << (cfi->cfiq->BufWriteTimeoutTyp +
660 cfi->cfiq->BufWriteTimeoutMax);
661 else
662 cfi->chips[i].buffer_write_time_max = 0;
663
664 cfi->chips[i].buffer_write_time_max =
665 max(cfi->chips[i].buffer_write_time_max, 2000);
666
667 cfi->chips[i].ref_point_counter = 0;
668 init_waitqueue_head(&(cfi->chips[i].wq));
669 }
670
671 map->fldrv = &cfi_amdstd_chipdrv;
672
673 return cfi_amdstd_setup(mtd);
674 }
675 struct mtd_info *cfi_cmdset_0006(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
676 struct mtd_info *cfi_cmdset_0701(struct map_info *map, int primary) __attribute__((alias("cfi_cmdset_0002")));
677 EXPORT_SYMBOL_GPL(cfi_cmdset_0002);
678 EXPORT_SYMBOL_GPL(cfi_cmdset_0006);
679 EXPORT_SYMBOL_GPL(cfi_cmdset_0701);
680
cfi_amdstd_setup(struct mtd_info * mtd)681 static struct mtd_info *cfi_amdstd_setup(struct mtd_info *mtd)
682 {
683 struct map_info *map = mtd->priv;
684 struct cfi_private *cfi = map->fldrv_priv;
685 unsigned long devsize = (1<<cfi->cfiq->DevSize) * cfi->interleave;
686 unsigned long offset = 0;
687 int i,j;
688
689 printk(KERN_NOTICE "number of %s chips: %d\n",
690 (cfi->cfi_mode == CFI_MODE_CFI)?"CFI":"JEDEC",cfi->numchips);
691 /* Select the correct geometry setup */
692 mtd->size = devsize * cfi->numchips;
693
694 mtd->numeraseregions = cfi->cfiq->NumEraseRegions * cfi->numchips;
695 mtd->eraseregions = kmalloc_array(mtd->numeraseregions,
696 sizeof(struct mtd_erase_region_info),
697 GFP_KERNEL);
698 if (!mtd->eraseregions)
699 goto setup_err;
700
701 for (i=0; i<cfi->cfiq->NumEraseRegions; i++) {
702 unsigned long ernum, ersize;
703 ersize = ((cfi->cfiq->EraseRegionInfo[i] >> 8) & ~0xff) * cfi->interleave;
704 ernum = (cfi->cfiq->EraseRegionInfo[i] & 0xffff) + 1;
705
706 if (mtd->erasesize < ersize) {
707 mtd->erasesize = ersize;
708 }
709 for (j=0; j<cfi->numchips; j++) {
710 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].offset = (j*devsize)+offset;
711 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].erasesize = ersize;
712 mtd->eraseregions[(j*cfi->cfiq->NumEraseRegions)+i].numblocks = ernum;
713 }
714 offset += (ersize * ernum);
715 }
716 if (offset != devsize) {
717 /* Argh */
718 printk(KERN_WARNING "Sum of regions (%lx) != total size of set of interleaved chips (%lx)\n", offset, devsize);
719 goto setup_err;
720 }
721
722 __module_get(THIS_MODULE);
723 register_reboot_notifier(&mtd->reboot_notifier);
724 return mtd;
725
726 setup_err:
727 kfree(mtd->eraseregions);
728 kfree(mtd);
729 kfree(cfi->cmdset_priv);
730 return NULL;
731 }
732
733 /*
734 * Return true if the chip is ready.
735 *
736 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
737 * non-suspended sector) and is indicated by no toggle bits toggling.
738 *
739 * Note that anything more complicated than checking if no bits are toggling
740 * (including checking DQ5 for an error status) is tricky to get working
741 * correctly and is therefore not done (particularly with interleaved chips
742 * as each chip must be checked independently of the others).
743 */
chip_ready(struct map_info * map,unsigned long addr)744 static int __xipram chip_ready(struct map_info *map, unsigned long addr)
745 {
746 map_word d, t;
747
748 d = map_read(map, addr);
749 t = map_read(map, addr);
750
751 return map_word_equal(map, d, t);
752 }
753
754 /*
755 * Return true if the chip is ready and has the correct value.
756 *
757 * Ready is one of: read mode, query mode, erase-suspend-read mode (in any
758 * non-suspended sector) and it is indicated by no bits toggling.
759 *
760 * Error are indicated by toggling bits or bits held with the wrong value,
761 * or with bits toggling.
762 *
763 * Note that anything more complicated than checking if no bits are toggling
764 * (including checking DQ5 for an error status) is tricky to get working
765 * correctly and is therefore not done (particularly with interleaved chips
766 * as each chip must be checked independently of the others).
767 *
768 */
chip_good(struct map_info * map,unsigned long addr,map_word expected)769 static int __xipram chip_good(struct map_info *map, unsigned long addr, map_word expected)
770 {
771 map_word oldd, curd;
772
773 oldd = map_read(map, addr);
774 curd = map_read(map, addr);
775
776 return map_word_equal(map, oldd, curd) &&
777 map_word_equal(map, curd, expected);
778 }
779
get_chip(struct map_info * map,struct flchip * chip,unsigned long adr,int mode)780 static int get_chip(struct map_info *map, struct flchip *chip, unsigned long adr, int mode)
781 {
782 DECLARE_WAITQUEUE(wait, current);
783 struct cfi_private *cfi = map->fldrv_priv;
784 unsigned long timeo;
785 struct cfi_pri_amdstd *cfip = (struct cfi_pri_amdstd *)cfi->cmdset_priv;
786
787 resettime:
788 timeo = jiffies + HZ;
789 retry:
790 switch (chip->state) {
791
792 case FL_STATUS:
793 for (;;) {
794 if (chip_ready(map, adr))
795 break;
796
797 if (time_after(jiffies, timeo)) {
798 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
799 return -EIO;
800 }
801 mutex_unlock(&chip->mutex);
802 cfi_udelay(1);
803 mutex_lock(&chip->mutex);
804 /* Someone else might have been playing with it. */
805 goto retry;
806 }
807
808 case FL_READY:
809 case FL_CFI_QUERY:
810 case FL_JEDEC_QUERY:
811 return 0;
812
813 case FL_ERASING:
814 if (!cfip || !(cfip->EraseSuspend & (0x1|0x2)) ||
815 !(mode == FL_READY || mode == FL_POINT ||
816 (mode == FL_WRITING && (cfip->EraseSuspend & 0x2))))
817 goto sleep;
818
819 /* Do not allow suspend iff read/write to EB address */
820 if ((adr & chip->in_progress_block_mask) ==
821 chip->in_progress_block_addr)
822 goto sleep;
823
824 /* Erase suspend */
825 /* It's harmless to issue the Erase-Suspend and Erase-Resume
826 * commands when the erase algorithm isn't in progress. */
827 map_write(map, CMD(0xB0), chip->in_progress_block_addr);
828 chip->oldstate = FL_ERASING;
829 chip->state = FL_ERASE_SUSPENDING;
830 chip->erase_suspended = 1;
831 for (;;) {
832 if (chip_ready(map, adr))
833 break;
834
835 if (time_after(jiffies, timeo)) {
836 /* Should have suspended the erase by now.
837 * Send an Erase-Resume command as either
838 * there was an error (so leave the erase
839 * routine to recover from it) or we trying to
840 * use the erase-in-progress sector. */
841 put_chip(map, chip, adr);
842 printk(KERN_ERR "MTD %s(): chip not ready after erase suspend\n", __func__);
843 return -EIO;
844 }
845
846 mutex_unlock(&chip->mutex);
847 cfi_udelay(1);
848 mutex_lock(&chip->mutex);
849 /* Nobody will touch it while it's in state FL_ERASE_SUSPENDING.
850 So we can just loop here. */
851 }
852 chip->state = FL_READY;
853 return 0;
854
855 case FL_XIP_WHILE_ERASING:
856 if (mode != FL_READY && mode != FL_POINT &&
857 (!cfip || !(cfip->EraseSuspend&2)))
858 goto sleep;
859 chip->oldstate = chip->state;
860 chip->state = FL_READY;
861 return 0;
862
863 case FL_SHUTDOWN:
864 /* The machine is rebooting */
865 return -EIO;
866
867 case FL_POINT:
868 /* Only if there's no operation suspended... */
869 if (mode == FL_READY && chip->oldstate == FL_READY)
870 return 0;
871
872 default:
873 sleep:
874 set_current_state(TASK_UNINTERRUPTIBLE);
875 add_wait_queue(&chip->wq, &wait);
876 mutex_unlock(&chip->mutex);
877 schedule();
878 remove_wait_queue(&chip->wq, &wait);
879 mutex_lock(&chip->mutex);
880 goto resettime;
881 }
882 }
883
884
put_chip(struct map_info * map,struct flchip * chip,unsigned long adr)885 static void put_chip(struct map_info *map, struct flchip *chip, unsigned long adr)
886 {
887 struct cfi_private *cfi = map->fldrv_priv;
888
889 switch(chip->oldstate) {
890 case FL_ERASING:
891 cfi_fixup_m29ew_erase_suspend(map,
892 chip->in_progress_block_addr);
893 map_write(map, cfi->sector_erase_cmd, chip->in_progress_block_addr);
894 cfi_fixup_m29ew_delay_after_resume(cfi);
895 chip->oldstate = FL_READY;
896 chip->state = FL_ERASING;
897 break;
898
899 case FL_XIP_WHILE_ERASING:
900 chip->state = chip->oldstate;
901 chip->oldstate = FL_READY;
902 break;
903
904 case FL_READY:
905 case FL_STATUS:
906 break;
907 default:
908 printk(KERN_ERR "MTD: put_chip() called with oldstate %d!!\n", chip->oldstate);
909 }
910 wake_up(&chip->wq);
911 }
912
913 #ifdef CONFIG_MTD_XIP
914
915 /*
916 * No interrupt what so ever can be serviced while the flash isn't in array
917 * mode. This is ensured by the xip_disable() and xip_enable() functions
918 * enclosing any code path where the flash is known not to be in array mode.
919 * And within a XIP disabled code path, only functions marked with __xipram
920 * may be called and nothing else (it's a good thing to inspect generated
921 * assembly to make sure inline functions were actually inlined and that gcc
922 * didn't emit calls to its own support functions). Also configuring MTD CFI
923 * support to a single buswidth and a single interleave is also recommended.
924 */
925
xip_disable(struct map_info * map,struct flchip * chip,unsigned long adr)926 static void xip_disable(struct map_info *map, struct flchip *chip,
927 unsigned long adr)
928 {
929 /* TODO: chips with no XIP use should ignore and return */
930 (void) map_read(map, adr); /* ensure mmu mapping is up to date */
931 local_irq_disable();
932 }
933
xip_enable(struct map_info * map,struct flchip * chip,unsigned long adr)934 static void __xipram xip_enable(struct map_info *map, struct flchip *chip,
935 unsigned long adr)
936 {
937 struct cfi_private *cfi = map->fldrv_priv;
938
939 if (chip->state != FL_POINT && chip->state != FL_READY) {
940 map_write(map, CMD(0xf0), adr);
941 chip->state = FL_READY;
942 }
943 (void) map_read(map, adr);
944 xip_iprefetch();
945 local_irq_enable();
946 }
947
948 /*
949 * When a delay is required for the flash operation to complete, the
950 * xip_udelay() function is polling for both the given timeout and pending
951 * (but still masked) hardware interrupts. Whenever there is an interrupt
952 * pending then the flash erase operation is suspended, array mode restored
953 * and interrupts unmasked. Task scheduling might also happen at that
954 * point. The CPU eventually returns from the interrupt or the call to
955 * schedule() and the suspended flash operation is resumed for the remaining
956 * of the delay period.
957 *
958 * Warning: this function _will_ fool interrupt latency tracing tools.
959 */
960
xip_udelay(struct map_info * map,struct flchip * chip,unsigned long adr,int usec)961 static void __xipram xip_udelay(struct map_info *map, struct flchip *chip,
962 unsigned long adr, int usec)
963 {
964 struct cfi_private *cfi = map->fldrv_priv;
965 struct cfi_pri_amdstd *extp = cfi->cmdset_priv;
966 map_word status, OK = CMD(0x80);
967 unsigned long suspended, start = xip_currtime();
968 flstate_t oldstate;
969
970 do {
971 cpu_relax();
972 if (xip_irqpending() && extp &&
973 ((chip->state == FL_ERASING && (extp->EraseSuspend & 2))) &&
974 (cfi_interleave_is_1(cfi) || chip->oldstate == FL_READY)) {
975 /*
976 * Let's suspend the erase operation when supported.
977 * Note that we currently don't try to suspend
978 * interleaved chips if there is already another
979 * operation suspended (imagine what happens
980 * when one chip was already done with the current
981 * operation while another chip suspended it, then
982 * we resume the whole thing at once). Yes, it
983 * can happen!
984 */
985 map_write(map, CMD(0xb0), adr);
986 usec -= xip_elapsed_since(start);
987 suspended = xip_currtime();
988 do {
989 if (xip_elapsed_since(suspended) > 100000) {
990 /*
991 * The chip doesn't want to suspend
992 * after waiting for 100 msecs.
993 * This is a critical error but there
994 * is not much we can do here.
995 */
996 return;
997 }
998 status = map_read(map, adr);
999 } while (!map_word_andequal(map, status, OK, OK));
1000
1001 /* Suspend succeeded */
1002 oldstate = chip->state;
1003 if (!map_word_bitsset(map, status, CMD(0x40)))
1004 break;
1005 chip->state = FL_XIP_WHILE_ERASING;
1006 chip->erase_suspended = 1;
1007 map_write(map, CMD(0xf0), adr);
1008 (void) map_read(map, adr);
1009 xip_iprefetch();
1010 local_irq_enable();
1011 mutex_unlock(&chip->mutex);
1012 xip_iprefetch();
1013 cond_resched();
1014
1015 /*
1016 * We're back. However someone else might have
1017 * decided to go write to the chip if we are in
1018 * a suspended erase state. If so let's wait
1019 * until it's done.
1020 */
1021 mutex_lock(&chip->mutex);
1022 while (chip->state != FL_XIP_WHILE_ERASING) {
1023 DECLARE_WAITQUEUE(wait, current);
1024 set_current_state(TASK_UNINTERRUPTIBLE);
1025 add_wait_queue(&chip->wq, &wait);
1026 mutex_unlock(&chip->mutex);
1027 schedule();
1028 remove_wait_queue(&chip->wq, &wait);
1029 mutex_lock(&chip->mutex);
1030 }
1031 /* Disallow XIP again */
1032 local_irq_disable();
1033
1034 /* Correct Erase Suspend Hangups for M29EW */
1035 cfi_fixup_m29ew_erase_suspend(map, adr);
1036 /* Resume the write or erase operation */
1037 map_write(map, cfi->sector_erase_cmd, adr);
1038 chip->state = oldstate;
1039 start = xip_currtime();
1040 } else if (usec >= 1000000/HZ) {
1041 /*
1042 * Try to save on CPU power when waiting delay
1043 * is at least a system timer tick period.
1044 * No need to be extremely accurate here.
1045 */
1046 xip_cpu_idle();
1047 }
1048 status = map_read(map, adr);
1049 } while (!map_word_andequal(map, status, OK, OK)
1050 && xip_elapsed_since(start) < usec);
1051 }
1052
1053 #define UDELAY(map, chip, adr, usec) xip_udelay(map, chip, adr, usec)
1054
1055 /*
1056 * The INVALIDATE_CACHED_RANGE() macro is normally used in parallel while
1057 * the flash is actively programming or erasing since we have to poll for
1058 * the operation to complete anyway. We can't do that in a generic way with
1059 * a XIP setup so do it before the actual flash operation in this case
1060 * and stub it out from INVALIDATE_CACHE_UDELAY.
1061 */
1062 #define XIP_INVAL_CACHED_RANGE(map, from, size) \
1063 INVALIDATE_CACHED_RANGE(map, from, size)
1064
1065 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1066 UDELAY(map, chip, adr, usec)
1067
1068 /*
1069 * Extra notes:
1070 *
1071 * Activating this XIP support changes the way the code works a bit. For
1072 * example the code to suspend the current process when concurrent access
1073 * happens is never executed because xip_udelay() will always return with the
1074 * same chip state as it was entered with. This is why there is no care for
1075 * the presence of add_wait_queue() or schedule() calls from within a couple
1076 * xip_disable()'d areas of code, like in do_erase_oneblock for example.
1077 * The queueing and scheduling are always happening within xip_udelay().
1078 *
1079 * Similarly, get_chip() and put_chip() just happen to always be executed
1080 * with chip->state set to FL_READY (or FL_XIP_WHILE_*) where flash state
1081 * is in array mode, therefore never executing many cases therein and not
1082 * causing any problem with XIP.
1083 */
1084
1085 #else
1086
1087 #define xip_disable(map, chip, adr)
1088 #define xip_enable(map, chip, adr)
1089 #define XIP_INVAL_CACHED_RANGE(x...)
1090
1091 #define UDELAY(map, chip, adr, usec) \
1092 do { \
1093 mutex_unlock(&chip->mutex); \
1094 cfi_udelay(usec); \
1095 mutex_lock(&chip->mutex); \
1096 } while (0)
1097
1098 #define INVALIDATE_CACHE_UDELAY(map, chip, adr, len, usec) \
1099 do { \
1100 mutex_unlock(&chip->mutex); \
1101 INVALIDATE_CACHED_RANGE(map, adr, len); \
1102 cfi_udelay(usec); \
1103 mutex_lock(&chip->mutex); \
1104 } while (0)
1105
1106 #endif
1107
do_read_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf)1108 static inline int do_read_onechip(struct map_info *map, struct flchip *chip, loff_t adr, size_t len, u_char *buf)
1109 {
1110 unsigned long cmd_addr;
1111 struct cfi_private *cfi = map->fldrv_priv;
1112 int ret;
1113
1114 adr += chip->start;
1115
1116 /* Ensure cmd read/writes are aligned. */
1117 cmd_addr = adr & ~(map_bankwidth(map)-1);
1118
1119 mutex_lock(&chip->mutex);
1120 ret = get_chip(map, chip, cmd_addr, FL_READY);
1121 if (ret) {
1122 mutex_unlock(&chip->mutex);
1123 return ret;
1124 }
1125
1126 if (chip->state != FL_POINT && chip->state != FL_READY) {
1127 map_write(map, CMD(0xf0), cmd_addr);
1128 chip->state = FL_READY;
1129 }
1130
1131 map_copy_from(map, buf, adr, len);
1132
1133 put_chip(map, chip, cmd_addr);
1134
1135 mutex_unlock(&chip->mutex);
1136 return 0;
1137 }
1138
1139
cfi_amdstd_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1140 static int cfi_amdstd_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1141 {
1142 struct map_info *map = mtd->priv;
1143 struct cfi_private *cfi = map->fldrv_priv;
1144 unsigned long ofs;
1145 int chipnum;
1146 int ret = 0;
1147
1148 /* ofs: offset within the first chip that the first read should start */
1149 chipnum = (from >> cfi->chipshift);
1150 ofs = from - (chipnum << cfi->chipshift);
1151
1152 while (len) {
1153 unsigned long thislen;
1154
1155 if (chipnum >= cfi->numchips)
1156 break;
1157
1158 if ((len + ofs -1) >> cfi->chipshift)
1159 thislen = (1<<cfi->chipshift) - ofs;
1160 else
1161 thislen = len;
1162
1163 ret = do_read_onechip(map, &cfi->chips[chipnum], ofs, thislen, buf);
1164 if (ret)
1165 break;
1166
1167 *retlen += thislen;
1168 len -= thislen;
1169 buf += thislen;
1170
1171 ofs = 0;
1172 chipnum++;
1173 }
1174 return ret;
1175 }
1176
1177 typedef int (*otp_op_t)(struct map_info *map, struct flchip *chip,
1178 loff_t adr, size_t len, u_char *buf, size_t grouplen);
1179
otp_enter(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1180 static inline void otp_enter(struct map_info *map, struct flchip *chip,
1181 loff_t adr, size_t len)
1182 {
1183 struct cfi_private *cfi = map->fldrv_priv;
1184
1185 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1186 cfi->device_type, NULL);
1187 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1188 cfi->device_type, NULL);
1189 cfi_send_gen_cmd(0x88, cfi->addr_unlock1, chip->start, map, cfi,
1190 cfi->device_type, NULL);
1191
1192 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1193 }
1194
otp_exit(struct map_info * map,struct flchip * chip,loff_t adr,size_t len)1195 static inline void otp_exit(struct map_info *map, struct flchip *chip,
1196 loff_t adr, size_t len)
1197 {
1198 struct cfi_private *cfi = map->fldrv_priv;
1199
1200 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1201 cfi->device_type, NULL);
1202 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1203 cfi->device_type, NULL);
1204 cfi_send_gen_cmd(0x90, cfi->addr_unlock1, chip->start, map, cfi,
1205 cfi->device_type, NULL);
1206 cfi_send_gen_cmd(0x00, cfi->addr_unlock1, chip->start, map, cfi,
1207 cfi->device_type, NULL);
1208
1209 INVALIDATE_CACHED_RANGE(map, chip->start + adr, len);
1210 }
1211
do_read_secsi_onechip(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1212 static inline int do_read_secsi_onechip(struct map_info *map,
1213 struct flchip *chip, loff_t adr,
1214 size_t len, u_char *buf,
1215 size_t grouplen)
1216 {
1217 DECLARE_WAITQUEUE(wait, current);
1218
1219 retry:
1220 mutex_lock(&chip->mutex);
1221
1222 if (chip->state != FL_READY){
1223 set_current_state(TASK_UNINTERRUPTIBLE);
1224 add_wait_queue(&chip->wq, &wait);
1225
1226 mutex_unlock(&chip->mutex);
1227
1228 schedule();
1229 remove_wait_queue(&chip->wq, &wait);
1230
1231 goto retry;
1232 }
1233
1234 adr += chip->start;
1235
1236 chip->state = FL_READY;
1237
1238 otp_enter(map, chip, adr, len);
1239 map_copy_from(map, buf, adr, len);
1240 otp_exit(map, chip, adr, len);
1241
1242 wake_up(&chip->wq);
1243 mutex_unlock(&chip->mutex);
1244
1245 return 0;
1246 }
1247
cfi_amdstd_secsi_read(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1248 static int cfi_amdstd_secsi_read (struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen, u_char *buf)
1249 {
1250 struct map_info *map = mtd->priv;
1251 struct cfi_private *cfi = map->fldrv_priv;
1252 unsigned long ofs;
1253 int chipnum;
1254 int ret = 0;
1255
1256 /* ofs: offset within the first chip that the first read should start */
1257 /* 8 secsi bytes per chip */
1258 chipnum=from>>3;
1259 ofs=from & 7;
1260
1261 while (len) {
1262 unsigned long thislen;
1263
1264 if (chipnum >= cfi->numchips)
1265 break;
1266
1267 if ((len + ofs -1) >> 3)
1268 thislen = (1<<3) - ofs;
1269 else
1270 thislen = len;
1271
1272 ret = do_read_secsi_onechip(map, &cfi->chips[chipnum], ofs,
1273 thislen, buf, 0);
1274 if (ret)
1275 break;
1276
1277 *retlen += thislen;
1278 len -= thislen;
1279 buf += thislen;
1280
1281 ofs = 0;
1282 chipnum++;
1283 }
1284 return ret;
1285 }
1286
1287 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1288 unsigned long adr, map_word datum,
1289 int mode);
1290
do_otp_write(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1291 static int do_otp_write(struct map_info *map, struct flchip *chip, loff_t adr,
1292 size_t len, u_char *buf, size_t grouplen)
1293 {
1294 int ret;
1295 while (len) {
1296 unsigned long bus_ofs = adr & ~(map_bankwidth(map)-1);
1297 int gap = adr - bus_ofs;
1298 int n = min_t(int, len, map_bankwidth(map) - gap);
1299 map_word datum = map_word_ff(map);
1300
1301 if (n != map_bankwidth(map)) {
1302 /* partial write of a word, load old contents */
1303 otp_enter(map, chip, bus_ofs, map_bankwidth(map));
1304 datum = map_read(map, bus_ofs);
1305 otp_exit(map, chip, bus_ofs, map_bankwidth(map));
1306 }
1307
1308 datum = map_word_load_partial(map, datum, buf, gap, n);
1309 ret = do_write_oneword(map, chip, bus_ofs, datum, FL_OTP_WRITE);
1310 if (ret)
1311 return ret;
1312
1313 adr += n;
1314 buf += n;
1315 len -= n;
1316 }
1317
1318 return 0;
1319 }
1320
do_otp_lock(struct map_info * map,struct flchip * chip,loff_t adr,size_t len,u_char * buf,size_t grouplen)1321 static int do_otp_lock(struct map_info *map, struct flchip *chip, loff_t adr,
1322 size_t len, u_char *buf, size_t grouplen)
1323 {
1324 struct cfi_private *cfi = map->fldrv_priv;
1325 uint8_t lockreg;
1326 unsigned long timeo;
1327 int ret;
1328
1329 /* make sure area matches group boundaries */
1330 if ((adr != 0) || (len != grouplen))
1331 return -EINVAL;
1332
1333 mutex_lock(&chip->mutex);
1334 ret = get_chip(map, chip, chip->start, FL_LOCKING);
1335 if (ret) {
1336 mutex_unlock(&chip->mutex);
1337 return ret;
1338 }
1339 chip->state = FL_LOCKING;
1340
1341 /* Enter lock register command */
1342 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1343 cfi->device_type, NULL);
1344 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1345 cfi->device_type, NULL);
1346 cfi_send_gen_cmd(0x40, cfi->addr_unlock1, chip->start, map, cfi,
1347 cfi->device_type, NULL);
1348
1349 /* read lock register */
1350 lockreg = cfi_read_query(map, 0);
1351
1352 /* set bit 0 to protect extended memory block */
1353 lockreg &= ~0x01;
1354
1355 /* set bit 0 to protect extended memory block */
1356 /* write lock register */
1357 map_write(map, CMD(0xA0), chip->start);
1358 map_write(map, CMD(lockreg), chip->start);
1359
1360 /* wait for chip to become ready */
1361 timeo = jiffies + msecs_to_jiffies(2);
1362 for (;;) {
1363 if (chip_ready(map, adr))
1364 break;
1365
1366 if (time_after(jiffies, timeo)) {
1367 pr_err("Waiting for chip to be ready timed out.\n");
1368 ret = -EIO;
1369 break;
1370 }
1371 UDELAY(map, chip, 0, 1);
1372 }
1373
1374 /* exit protection commands */
1375 map_write(map, CMD(0x90), chip->start);
1376 map_write(map, CMD(0x00), chip->start);
1377
1378 chip->state = FL_READY;
1379 put_chip(map, chip, chip->start);
1380 mutex_unlock(&chip->mutex);
1381
1382 return ret;
1383 }
1384
cfi_amdstd_otp_walk(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf,otp_op_t action,int user_regs)1385 static int cfi_amdstd_otp_walk(struct mtd_info *mtd, loff_t from, size_t len,
1386 size_t *retlen, u_char *buf,
1387 otp_op_t action, int user_regs)
1388 {
1389 struct map_info *map = mtd->priv;
1390 struct cfi_private *cfi = map->fldrv_priv;
1391 int ofs_factor = cfi->interleave * cfi->device_type;
1392 unsigned long base;
1393 int chipnum;
1394 struct flchip *chip;
1395 uint8_t otp, lockreg;
1396 int ret;
1397
1398 size_t user_size, factory_size, otpsize;
1399 loff_t user_offset, factory_offset, otpoffset;
1400 int user_locked = 0, otplocked;
1401
1402 *retlen = 0;
1403
1404 for (chipnum = 0; chipnum < cfi->numchips; chipnum++) {
1405 chip = &cfi->chips[chipnum];
1406 factory_size = 0;
1407 user_size = 0;
1408
1409 /* Micron M29EW family */
1410 if (is_m29ew(cfi)) {
1411 base = chip->start;
1412
1413 /* check whether secsi area is factory locked
1414 or user lockable */
1415 mutex_lock(&chip->mutex);
1416 ret = get_chip(map, chip, base, FL_CFI_QUERY);
1417 if (ret) {
1418 mutex_unlock(&chip->mutex);
1419 return ret;
1420 }
1421 cfi_qry_mode_on(base, map, cfi);
1422 otp = cfi_read_query(map, base + 0x3 * ofs_factor);
1423 cfi_qry_mode_off(base, map, cfi);
1424 put_chip(map, chip, base);
1425 mutex_unlock(&chip->mutex);
1426
1427 if (otp & 0x80) {
1428 /* factory locked */
1429 factory_offset = 0;
1430 factory_size = 0x100;
1431 } else {
1432 /* customer lockable */
1433 user_offset = 0;
1434 user_size = 0x100;
1435
1436 mutex_lock(&chip->mutex);
1437 ret = get_chip(map, chip, base, FL_LOCKING);
1438 if (ret) {
1439 mutex_unlock(&chip->mutex);
1440 return ret;
1441 }
1442
1443 /* Enter lock register command */
1444 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1,
1445 chip->start, map, cfi,
1446 cfi->device_type, NULL);
1447 cfi_send_gen_cmd(0x55, cfi->addr_unlock2,
1448 chip->start, map, cfi,
1449 cfi->device_type, NULL);
1450 cfi_send_gen_cmd(0x40, cfi->addr_unlock1,
1451 chip->start, map, cfi,
1452 cfi->device_type, NULL);
1453 /* read lock register */
1454 lockreg = cfi_read_query(map, 0);
1455 /* exit protection commands */
1456 map_write(map, CMD(0x90), chip->start);
1457 map_write(map, CMD(0x00), chip->start);
1458 put_chip(map, chip, chip->start);
1459 mutex_unlock(&chip->mutex);
1460
1461 user_locked = ((lockreg & 0x01) == 0x00);
1462 }
1463 }
1464
1465 otpsize = user_regs ? user_size : factory_size;
1466 if (!otpsize)
1467 continue;
1468 otpoffset = user_regs ? user_offset : factory_offset;
1469 otplocked = user_regs ? user_locked : 1;
1470
1471 if (!action) {
1472 /* return otpinfo */
1473 struct otp_info *otpinfo;
1474 len -= sizeof(*otpinfo);
1475 if (len <= 0)
1476 return -ENOSPC;
1477 otpinfo = (struct otp_info *)buf;
1478 otpinfo->start = from;
1479 otpinfo->length = otpsize;
1480 otpinfo->locked = otplocked;
1481 buf += sizeof(*otpinfo);
1482 *retlen += sizeof(*otpinfo);
1483 from += otpsize;
1484 } else if ((from < otpsize) && (len > 0)) {
1485 size_t size;
1486 size = (len < otpsize - from) ? len : otpsize - from;
1487 ret = action(map, chip, otpoffset + from, size, buf,
1488 otpsize);
1489 if (ret < 0)
1490 return ret;
1491
1492 buf += size;
1493 len -= size;
1494 *retlen += size;
1495 from = 0;
1496 } else {
1497 from -= otpsize;
1498 }
1499 }
1500 return 0;
1501 }
1502
cfi_amdstd_get_fact_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1503 static int cfi_amdstd_get_fact_prot_info(struct mtd_info *mtd, size_t len,
1504 size_t *retlen, struct otp_info *buf)
1505 {
1506 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1507 NULL, 0);
1508 }
1509
cfi_amdstd_get_user_prot_info(struct mtd_info * mtd,size_t len,size_t * retlen,struct otp_info * buf)1510 static int cfi_amdstd_get_user_prot_info(struct mtd_info *mtd, size_t len,
1511 size_t *retlen, struct otp_info *buf)
1512 {
1513 return cfi_amdstd_otp_walk(mtd, 0, len, retlen, (u_char *)buf,
1514 NULL, 1);
1515 }
1516
cfi_amdstd_read_fact_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1517 static int cfi_amdstd_read_fact_prot_reg(struct mtd_info *mtd, loff_t from,
1518 size_t len, size_t *retlen,
1519 u_char *buf)
1520 {
1521 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1522 buf, do_read_secsi_onechip, 0);
1523 }
1524
cfi_amdstd_read_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1525 static int cfi_amdstd_read_user_prot_reg(struct mtd_info *mtd, loff_t from,
1526 size_t len, size_t *retlen,
1527 u_char *buf)
1528 {
1529 return cfi_amdstd_otp_walk(mtd, from, len, retlen,
1530 buf, do_read_secsi_onechip, 1);
1531 }
1532
cfi_amdstd_write_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len,size_t * retlen,u_char * buf)1533 static int cfi_amdstd_write_user_prot_reg(struct mtd_info *mtd, loff_t from,
1534 size_t len, size_t *retlen,
1535 u_char *buf)
1536 {
1537 return cfi_amdstd_otp_walk(mtd, from, len, retlen, buf,
1538 do_otp_write, 1);
1539 }
1540
cfi_amdstd_lock_user_prot_reg(struct mtd_info * mtd,loff_t from,size_t len)1541 static int cfi_amdstd_lock_user_prot_reg(struct mtd_info *mtd, loff_t from,
1542 size_t len)
1543 {
1544 size_t retlen;
1545 return cfi_amdstd_otp_walk(mtd, from, len, &retlen, NULL,
1546 do_otp_lock, 1);
1547 }
1548
do_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum,int mode)1549 static int __xipram do_write_oneword(struct map_info *map, struct flchip *chip,
1550 unsigned long adr, map_word datum,
1551 int mode)
1552 {
1553 struct cfi_private *cfi = map->fldrv_priv;
1554 unsigned long timeo = jiffies + HZ;
1555 /*
1556 * We use a 1ms + 1 jiffies generic timeout for writes (most devices
1557 * have a max write time of a few hundreds usec). However, we should
1558 * use the maximum timeout value given by the chip at probe time
1559 * instead. Unfortunately, struct flchip does have a field for
1560 * maximum timeout, only for typical which can be far too short
1561 * depending of the conditions. The ' + 1' is to avoid having a
1562 * timeout of 0 jiffies if HZ is smaller than 1000.
1563 */
1564 unsigned long uWriteTimeout = (HZ / 1000) + 1;
1565 int ret = 0;
1566 map_word oldd;
1567 int retry_cnt = 0;
1568
1569 adr += chip->start;
1570
1571 mutex_lock(&chip->mutex);
1572 ret = get_chip(map, chip, adr, mode);
1573 if (ret) {
1574 mutex_unlock(&chip->mutex);
1575 return ret;
1576 }
1577
1578 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1579 __func__, adr, datum.x[0]);
1580
1581 if (mode == FL_OTP_WRITE)
1582 otp_enter(map, chip, adr, map_bankwidth(map));
1583
1584 /*
1585 * Check for a NOP for the case when the datum to write is already
1586 * present - it saves time and works around buggy chips that corrupt
1587 * data at other locations when 0xff is written to a location that
1588 * already contains 0xff.
1589 */
1590 oldd = map_read(map, adr);
1591 if (map_word_equal(map, oldd, datum)) {
1592 pr_debug("MTD %s(): NOP\n",
1593 __func__);
1594 goto op_done;
1595 }
1596
1597 XIP_INVAL_CACHED_RANGE(map, adr, map_bankwidth(map));
1598 ENABLE_VPP(map);
1599 xip_disable(map, chip, adr);
1600
1601 retry:
1602 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1603 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1604 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1605 map_write(map, datum, adr);
1606 chip->state = mode;
1607
1608 INVALIDATE_CACHE_UDELAY(map, chip,
1609 adr, map_bankwidth(map),
1610 chip->word_write_time);
1611
1612 /* See comment above for timeout value. */
1613 timeo = jiffies + uWriteTimeout;
1614 for (;;) {
1615 if (chip->state != mode) {
1616 /* Someone's suspended the write. Sleep */
1617 DECLARE_WAITQUEUE(wait, current);
1618
1619 set_current_state(TASK_UNINTERRUPTIBLE);
1620 add_wait_queue(&chip->wq, &wait);
1621 mutex_unlock(&chip->mutex);
1622 schedule();
1623 remove_wait_queue(&chip->wq, &wait);
1624 timeo = jiffies + (HZ / 2); /* FIXME */
1625 mutex_lock(&chip->mutex);
1626 continue;
1627 }
1628
1629 /*
1630 * We check "time_after" and "!chip_good" before checking
1631 * "chip_good" to avoid the failure due to scheduling.
1632 */
1633 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum)) {
1634 xip_enable(map, chip, adr);
1635 printk(KERN_WARNING "MTD %s(): software timeout\n", __func__);
1636 xip_disable(map, chip, adr);
1637 ret = -EIO;
1638 break;
1639 }
1640
1641 if (chip_good(map, adr, datum))
1642 break;
1643
1644 /* Latency issues. Drop the lock, wait a while and retry */
1645 UDELAY(map, chip, adr, 1);
1646 }
1647
1648 /* Did we succeed? */
1649 if (ret) {
1650 /* reset on all failures. */
1651 map_write(map, CMD(0xF0), chip->start);
1652 /* FIXME - should have reset delay before continuing */
1653
1654 if (++retry_cnt <= MAX_RETRIES) {
1655 ret = 0;
1656 goto retry;
1657 }
1658 }
1659 xip_enable(map, chip, adr);
1660 op_done:
1661 if (mode == FL_OTP_WRITE)
1662 otp_exit(map, chip, adr, map_bankwidth(map));
1663 chip->state = FL_READY;
1664 DISABLE_VPP(map);
1665 put_chip(map, chip, adr);
1666 mutex_unlock(&chip->mutex);
1667
1668 return ret;
1669 }
1670
1671
cfi_amdstd_write_words(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1672 static int cfi_amdstd_write_words(struct mtd_info *mtd, loff_t to, size_t len,
1673 size_t *retlen, const u_char *buf)
1674 {
1675 struct map_info *map = mtd->priv;
1676 struct cfi_private *cfi = map->fldrv_priv;
1677 int ret = 0;
1678 int chipnum;
1679 unsigned long ofs, chipstart;
1680 DECLARE_WAITQUEUE(wait, current);
1681
1682 chipnum = to >> cfi->chipshift;
1683 ofs = to - (chipnum << cfi->chipshift);
1684 chipstart = cfi->chips[chipnum].start;
1685
1686 /* If it's not bus-aligned, do the first byte write */
1687 if (ofs & (map_bankwidth(map)-1)) {
1688 unsigned long bus_ofs = ofs & ~(map_bankwidth(map)-1);
1689 int i = ofs - bus_ofs;
1690 int n = 0;
1691 map_word tmp_buf;
1692
1693 retry:
1694 mutex_lock(&cfi->chips[chipnum].mutex);
1695
1696 if (cfi->chips[chipnum].state != FL_READY) {
1697 set_current_state(TASK_UNINTERRUPTIBLE);
1698 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1699
1700 mutex_unlock(&cfi->chips[chipnum].mutex);
1701
1702 schedule();
1703 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1704 goto retry;
1705 }
1706
1707 /* Load 'tmp_buf' with old contents of flash */
1708 tmp_buf = map_read(map, bus_ofs+chipstart);
1709
1710 mutex_unlock(&cfi->chips[chipnum].mutex);
1711
1712 /* Number of bytes to copy from buffer */
1713 n = min_t(int, len, map_bankwidth(map)-i);
1714
1715 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
1716
1717 ret = do_write_oneword(map, &cfi->chips[chipnum],
1718 bus_ofs, tmp_buf, FL_WRITING);
1719 if (ret)
1720 return ret;
1721
1722 ofs += n;
1723 buf += n;
1724 (*retlen) += n;
1725 len -= n;
1726
1727 if (ofs >> cfi->chipshift) {
1728 chipnum ++;
1729 ofs = 0;
1730 if (chipnum == cfi->numchips)
1731 return 0;
1732 }
1733 }
1734
1735 /* We are now aligned, write as much as possible */
1736 while(len >= map_bankwidth(map)) {
1737 map_word datum;
1738
1739 datum = map_word_load(map, buf);
1740
1741 ret = do_write_oneword(map, &cfi->chips[chipnum],
1742 ofs, datum, FL_WRITING);
1743 if (ret)
1744 return ret;
1745
1746 ofs += map_bankwidth(map);
1747 buf += map_bankwidth(map);
1748 (*retlen) += map_bankwidth(map);
1749 len -= map_bankwidth(map);
1750
1751 if (ofs >> cfi->chipshift) {
1752 chipnum ++;
1753 ofs = 0;
1754 if (chipnum == cfi->numchips)
1755 return 0;
1756 chipstart = cfi->chips[chipnum].start;
1757 }
1758 }
1759
1760 /* Write the trailing bytes if any */
1761 if (len & (map_bankwidth(map)-1)) {
1762 map_word tmp_buf;
1763
1764 retry1:
1765 mutex_lock(&cfi->chips[chipnum].mutex);
1766
1767 if (cfi->chips[chipnum].state != FL_READY) {
1768 set_current_state(TASK_UNINTERRUPTIBLE);
1769 add_wait_queue(&cfi->chips[chipnum].wq, &wait);
1770
1771 mutex_unlock(&cfi->chips[chipnum].mutex);
1772
1773 schedule();
1774 remove_wait_queue(&cfi->chips[chipnum].wq, &wait);
1775 goto retry1;
1776 }
1777
1778 tmp_buf = map_read(map, ofs + chipstart);
1779
1780 mutex_unlock(&cfi->chips[chipnum].mutex);
1781
1782 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
1783
1784 ret = do_write_oneword(map, &cfi->chips[chipnum],
1785 ofs, tmp_buf, FL_WRITING);
1786 if (ret)
1787 return ret;
1788
1789 (*retlen) += len;
1790 }
1791
1792 return 0;
1793 }
1794
1795
1796 /*
1797 * FIXME: interleaved mode not tested, and probably not supported!
1798 */
do_write_buffer(struct map_info * map,struct flchip * chip,unsigned long adr,const u_char * buf,int len)1799 static int __xipram do_write_buffer(struct map_info *map, struct flchip *chip,
1800 unsigned long adr, const u_char *buf,
1801 int len)
1802 {
1803 struct cfi_private *cfi = map->fldrv_priv;
1804 unsigned long timeo = jiffies + HZ;
1805 /*
1806 * Timeout is calculated according to CFI data, if available.
1807 * See more comments in cfi_cmdset_0002().
1808 */
1809 unsigned long uWriteTimeout =
1810 usecs_to_jiffies(chip->buffer_write_time_max);
1811 int ret = -EIO;
1812 unsigned long cmd_adr;
1813 int z, words;
1814 map_word datum;
1815
1816 adr += chip->start;
1817 cmd_adr = adr;
1818
1819 mutex_lock(&chip->mutex);
1820 ret = get_chip(map, chip, adr, FL_WRITING);
1821 if (ret) {
1822 mutex_unlock(&chip->mutex);
1823 return ret;
1824 }
1825
1826 datum = map_word_load(map, buf);
1827
1828 pr_debug("MTD %s(): WRITE 0x%.8lx(0x%.8lx)\n",
1829 __func__, adr, datum.x[0]);
1830
1831 XIP_INVAL_CACHED_RANGE(map, adr, len);
1832 ENABLE_VPP(map);
1833 xip_disable(map, chip, cmd_adr);
1834
1835 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
1836 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
1837
1838 /* Write Buffer Load */
1839 map_write(map, CMD(0x25), cmd_adr);
1840
1841 chip->state = FL_WRITING_TO_BUFFER;
1842
1843 /* Write length of data to come */
1844 words = len / map_bankwidth(map);
1845 map_write(map, CMD(words - 1), cmd_adr);
1846 /* Write data */
1847 z = 0;
1848 while(z < words * map_bankwidth(map)) {
1849 datum = map_word_load(map, buf);
1850 map_write(map, datum, adr + z);
1851
1852 z += map_bankwidth(map);
1853 buf += map_bankwidth(map);
1854 }
1855 z -= map_bankwidth(map);
1856
1857 adr += z;
1858
1859 /* Write Buffer Program Confirm: GO GO GO */
1860 map_write(map, CMD(0x29), cmd_adr);
1861 chip->state = FL_WRITING;
1862
1863 INVALIDATE_CACHE_UDELAY(map, chip,
1864 adr, map_bankwidth(map),
1865 chip->word_write_time);
1866
1867 timeo = jiffies + uWriteTimeout;
1868
1869 for (;;) {
1870 if (chip->state != FL_WRITING) {
1871 /* Someone's suspended the write. Sleep */
1872 DECLARE_WAITQUEUE(wait, current);
1873
1874 set_current_state(TASK_UNINTERRUPTIBLE);
1875 add_wait_queue(&chip->wq, &wait);
1876 mutex_unlock(&chip->mutex);
1877 schedule();
1878 remove_wait_queue(&chip->wq, &wait);
1879 timeo = jiffies + (HZ / 2); /* FIXME */
1880 mutex_lock(&chip->mutex);
1881 continue;
1882 }
1883
1884 /*
1885 * We check "time_after" and "!chip_good" before checking "chip_good" to avoid
1886 * the failure due to scheduling.
1887 */
1888 if (time_after(jiffies, timeo) && !chip_good(map, adr, datum))
1889 break;
1890
1891 if (chip_good(map, adr, datum)) {
1892 xip_enable(map, chip, adr);
1893 goto op_done;
1894 }
1895
1896 /* Latency issues. Drop the lock, wait a while and retry */
1897 UDELAY(map, chip, adr, 1);
1898 }
1899
1900 /*
1901 * Recovery from write-buffer programming failures requires
1902 * the write-to-buffer-reset sequence. Since the last part
1903 * of the sequence also works as a normal reset, we can run
1904 * the same commands regardless of why we are here.
1905 * See e.g.
1906 * http://www.spansion.com/Support/Application%20Notes/MirrorBit_Write_Buffer_Prog_Page_Buffer_Read_AN.pdf
1907 */
1908 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
1909 cfi->device_type, NULL);
1910 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
1911 cfi->device_type, NULL);
1912 cfi_send_gen_cmd(0xF0, cfi->addr_unlock1, chip->start, map, cfi,
1913 cfi->device_type, NULL);
1914 xip_enable(map, chip, adr);
1915 /* FIXME - should have reset delay before continuing */
1916
1917 printk(KERN_WARNING "MTD %s(): software timeout, address:0x%.8lx.\n",
1918 __func__, adr);
1919
1920 ret = -EIO;
1921 op_done:
1922 chip->state = FL_READY;
1923 DISABLE_VPP(map);
1924 put_chip(map, chip, adr);
1925 mutex_unlock(&chip->mutex);
1926
1927 return ret;
1928 }
1929
1930
cfi_amdstd_write_buffers(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)1931 static int cfi_amdstd_write_buffers(struct mtd_info *mtd, loff_t to, size_t len,
1932 size_t *retlen, const u_char *buf)
1933 {
1934 struct map_info *map = mtd->priv;
1935 struct cfi_private *cfi = map->fldrv_priv;
1936 int wbufsize = cfi_interleave(cfi) << cfi->cfiq->MaxBufWriteSize;
1937 int ret = 0;
1938 int chipnum;
1939 unsigned long ofs;
1940
1941 chipnum = to >> cfi->chipshift;
1942 ofs = to - (chipnum << cfi->chipshift);
1943
1944 /* If it's not bus-aligned, do the first word write */
1945 if (ofs & (map_bankwidth(map)-1)) {
1946 size_t local_len = (-ofs)&(map_bankwidth(map)-1);
1947 if (local_len > len)
1948 local_len = len;
1949 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1950 local_len, retlen, buf);
1951 if (ret)
1952 return ret;
1953 ofs += local_len;
1954 buf += local_len;
1955 len -= local_len;
1956
1957 if (ofs >> cfi->chipshift) {
1958 chipnum ++;
1959 ofs = 0;
1960 if (chipnum == cfi->numchips)
1961 return 0;
1962 }
1963 }
1964
1965 /* Write buffer is worth it only if more than one word to write... */
1966 while (len >= map_bankwidth(map) * 2) {
1967 /* We must not cross write block boundaries */
1968 int size = wbufsize - (ofs & (wbufsize-1));
1969
1970 if (size > len)
1971 size = len;
1972 if (size % map_bankwidth(map))
1973 size -= size % map_bankwidth(map);
1974
1975 ret = do_write_buffer(map, &cfi->chips[chipnum],
1976 ofs, buf, size);
1977 if (ret)
1978 return ret;
1979
1980 ofs += size;
1981 buf += size;
1982 (*retlen) += size;
1983 len -= size;
1984
1985 if (ofs >> cfi->chipshift) {
1986 chipnum ++;
1987 ofs = 0;
1988 if (chipnum == cfi->numchips)
1989 return 0;
1990 }
1991 }
1992
1993 if (len) {
1994 size_t retlen_dregs = 0;
1995
1996 ret = cfi_amdstd_write_words(mtd, ofs + (chipnum<<cfi->chipshift),
1997 len, &retlen_dregs, buf);
1998
1999 *retlen += retlen_dregs;
2000 return ret;
2001 }
2002
2003 return 0;
2004 }
2005
2006 /*
2007 * Wait for the flash chip to become ready to write data
2008 *
2009 * This is only called during the panic_write() path. When panic_write()
2010 * is called, the kernel is in the process of a panic, and will soon be
2011 * dead. Therefore we don't take any locks, and attempt to get access
2012 * to the chip as soon as possible.
2013 */
cfi_amdstd_panic_wait(struct map_info * map,struct flchip * chip,unsigned long adr)2014 static int cfi_amdstd_panic_wait(struct map_info *map, struct flchip *chip,
2015 unsigned long adr)
2016 {
2017 struct cfi_private *cfi = map->fldrv_priv;
2018 int retries = 10;
2019 int i;
2020
2021 /*
2022 * If the driver thinks the chip is idle, and no toggle bits
2023 * are changing, then the chip is actually idle for sure.
2024 */
2025 if (chip->state == FL_READY && chip_ready(map, adr))
2026 return 0;
2027
2028 /*
2029 * Try several times to reset the chip and then wait for it
2030 * to become idle. The upper limit of a few milliseconds of
2031 * delay isn't a big problem: the kernel is dying anyway. It
2032 * is more important to save the messages.
2033 */
2034 while (retries > 0) {
2035 const unsigned long timeo = (HZ / 1000) + 1;
2036
2037 /* send the reset command */
2038 map_write(map, CMD(0xF0), chip->start);
2039
2040 /* wait for the chip to become ready */
2041 for (i = 0; i < jiffies_to_usecs(timeo); i++) {
2042 if (chip_ready(map, adr))
2043 return 0;
2044
2045 udelay(1);
2046 }
2047
2048 retries--;
2049 }
2050
2051 /* the chip never became ready */
2052 return -EBUSY;
2053 }
2054
2055 /*
2056 * Write out one word of data to a single flash chip during a kernel panic
2057 *
2058 * This is only called during the panic_write() path. When panic_write()
2059 * is called, the kernel is in the process of a panic, and will soon be
2060 * dead. Therefore we don't take any locks, and attempt to get access
2061 * to the chip as soon as possible.
2062 *
2063 * The implementation of this routine is intentionally similar to
2064 * do_write_oneword(), in order to ease code maintenance.
2065 */
do_panic_write_oneword(struct map_info * map,struct flchip * chip,unsigned long adr,map_word datum)2066 static int do_panic_write_oneword(struct map_info *map, struct flchip *chip,
2067 unsigned long adr, map_word datum)
2068 {
2069 const unsigned long uWriteTimeout = (HZ / 1000) + 1;
2070 struct cfi_private *cfi = map->fldrv_priv;
2071 int retry_cnt = 0;
2072 map_word oldd;
2073 int ret = 0;
2074 int i;
2075
2076 adr += chip->start;
2077
2078 ret = cfi_amdstd_panic_wait(map, chip, adr);
2079 if (ret)
2080 return ret;
2081
2082 pr_debug("MTD %s(): PANIC WRITE 0x%.8lx(0x%.8lx)\n",
2083 __func__, adr, datum.x[0]);
2084
2085 /*
2086 * Check for a NOP for the case when the datum to write is already
2087 * present - it saves time and works around buggy chips that corrupt
2088 * data at other locations when 0xff is written to a location that
2089 * already contains 0xff.
2090 */
2091 oldd = map_read(map, adr);
2092 if (map_word_equal(map, oldd, datum)) {
2093 pr_debug("MTD %s(): NOP\n", __func__);
2094 goto op_done;
2095 }
2096
2097 ENABLE_VPP(map);
2098
2099 retry:
2100 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2101 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2102 cfi_send_gen_cmd(0xA0, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2103 map_write(map, datum, adr);
2104
2105 for (i = 0; i < jiffies_to_usecs(uWriteTimeout); i++) {
2106 if (chip_ready(map, adr))
2107 break;
2108
2109 udelay(1);
2110 }
2111
2112 if (!chip_good(map, adr, datum)) {
2113 /* reset on all failures. */
2114 map_write(map, CMD(0xF0), chip->start);
2115 /* FIXME - should have reset delay before continuing */
2116
2117 if (++retry_cnt <= MAX_RETRIES)
2118 goto retry;
2119
2120 ret = -EIO;
2121 }
2122
2123 op_done:
2124 DISABLE_VPP(map);
2125 return ret;
2126 }
2127
2128 /*
2129 * Write out some data during a kernel panic
2130 *
2131 * This is used by the mtdoops driver to save the dying messages from a
2132 * kernel which has panic'd.
2133 *
2134 * This routine ignores all of the locking used throughout the rest of the
2135 * driver, in order to ensure that the data gets written out no matter what
2136 * state this driver (and the flash chip itself) was in when the kernel crashed.
2137 *
2138 * The implementation of this routine is intentionally similar to
2139 * cfi_amdstd_write_words(), in order to ease code maintenance.
2140 */
cfi_amdstd_panic_write(struct mtd_info * mtd,loff_t to,size_t len,size_t * retlen,const u_char * buf)2141 static int cfi_amdstd_panic_write(struct mtd_info *mtd, loff_t to, size_t len,
2142 size_t *retlen, const u_char *buf)
2143 {
2144 struct map_info *map = mtd->priv;
2145 struct cfi_private *cfi = map->fldrv_priv;
2146 unsigned long ofs, chipstart;
2147 int ret = 0;
2148 int chipnum;
2149
2150 chipnum = to >> cfi->chipshift;
2151 ofs = to - (chipnum << cfi->chipshift);
2152 chipstart = cfi->chips[chipnum].start;
2153
2154 /* If it's not bus aligned, do the first byte write */
2155 if (ofs & (map_bankwidth(map) - 1)) {
2156 unsigned long bus_ofs = ofs & ~(map_bankwidth(map) - 1);
2157 int i = ofs - bus_ofs;
2158 int n = 0;
2159 map_word tmp_buf;
2160
2161 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], bus_ofs);
2162 if (ret)
2163 return ret;
2164
2165 /* Load 'tmp_buf' with old contents of flash */
2166 tmp_buf = map_read(map, bus_ofs + chipstart);
2167
2168 /* Number of bytes to copy from buffer */
2169 n = min_t(int, len, map_bankwidth(map) - i);
2170
2171 tmp_buf = map_word_load_partial(map, tmp_buf, buf, i, n);
2172
2173 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2174 bus_ofs, tmp_buf);
2175 if (ret)
2176 return ret;
2177
2178 ofs += n;
2179 buf += n;
2180 (*retlen) += n;
2181 len -= n;
2182
2183 if (ofs >> cfi->chipshift) {
2184 chipnum++;
2185 ofs = 0;
2186 if (chipnum == cfi->numchips)
2187 return 0;
2188 }
2189 }
2190
2191 /* We are now aligned, write as much as possible */
2192 while (len >= map_bankwidth(map)) {
2193 map_word datum;
2194
2195 datum = map_word_load(map, buf);
2196
2197 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2198 ofs, datum);
2199 if (ret)
2200 return ret;
2201
2202 ofs += map_bankwidth(map);
2203 buf += map_bankwidth(map);
2204 (*retlen) += map_bankwidth(map);
2205 len -= map_bankwidth(map);
2206
2207 if (ofs >> cfi->chipshift) {
2208 chipnum++;
2209 ofs = 0;
2210 if (chipnum == cfi->numchips)
2211 return 0;
2212
2213 chipstart = cfi->chips[chipnum].start;
2214 }
2215 }
2216
2217 /* Write the trailing bytes if any */
2218 if (len & (map_bankwidth(map) - 1)) {
2219 map_word tmp_buf;
2220
2221 ret = cfi_amdstd_panic_wait(map, &cfi->chips[chipnum], ofs);
2222 if (ret)
2223 return ret;
2224
2225 tmp_buf = map_read(map, ofs + chipstart);
2226
2227 tmp_buf = map_word_load_partial(map, tmp_buf, buf, 0, len);
2228
2229 ret = do_panic_write_oneword(map, &cfi->chips[chipnum],
2230 ofs, tmp_buf);
2231 if (ret)
2232 return ret;
2233
2234 (*retlen) += len;
2235 }
2236
2237 return 0;
2238 }
2239
2240
2241 /*
2242 * Handle devices with one erase region, that only implement
2243 * the chip erase command.
2244 */
do_erase_chip(struct map_info * map,struct flchip * chip)2245 static int __xipram do_erase_chip(struct map_info *map, struct flchip *chip)
2246 {
2247 struct cfi_private *cfi = map->fldrv_priv;
2248 unsigned long timeo = jiffies + HZ;
2249 unsigned long int adr;
2250 DECLARE_WAITQUEUE(wait, current);
2251 int ret = 0;
2252 int retry_cnt = 0;
2253
2254 adr = cfi->addr_unlock1;
2255
2256 mutex_lock(&chip->mutex);
2257 ret = get_chip(map, chip, adr, FL_WRITING);
2258 if (ret) {
2259 mutex_unlock(&chip->mutex);
2260 return ret;
2261 }
2262
2263 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2264 __func__, chip->start);
2265
2266 XIP_INVAL_CACHED_RANGE(map, adr, map->size);
2267 ENABLE_VPP(map);
2268 xip_disable(map, chip, adr);
2269
2270 retry:
2271 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2272 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2273 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2274 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2275 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2276 cfi_send_gen_cmd(0x10, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2277
2278 chip->state = FL_ERASING;
2279 chip->erase_suspended = 0;
2280 chip->in_progress_block_addr = adr;
2281 chip->in_progress_block_mask = ~(map->size - 1);
2282
2283 INVALIDATE_CACHE_UDELAY(map, chip,
2284 adr, map->size,
2285 chip->erase_time*500);
2286
2287 timeo = jiffies + (HZ*20);
2288
2289 for (;;) {
2290 if (chip->state != FL_ERASING) {
2291 /* Someone's suspended the erase. Sleep */
2292 set_current_state(TASK_UNINTERRUPTIBLE);
2293 add_wait_queue(&chip->wq, &wait);
2294 mutex_unlock(&chip->mutex);
2295 schedule();
2296 remove_wait_queue(&chip->wq, &wait);
2297 mutex_lock(&chip->mutex);
2298 continue;
2299 }
2300 if (chip->erase_suspended) {
2301 /* This erase was suspended and resumed.
2302 Adjust the timeout */
2303 timeo = jiffies + (HZ*20); /* FIXME */
2304 chip->erase_suspended = 0;
2305 }
2306
2307 if (chip_good(map, adr, map_word_ff(map)))
2308 break;
2309
2310 if (time_after(jiffies, timeo)) {
2311 printk(KERN_WARNING "MTD %s(): software timeout\n",
2312 __func__);
2313 ret = -EIO;
2314 break;
2315 }
2316
2317 /* Latency issues. Drop the lock, wait a while and retry */
2318 UDELAY(map, chip, adr, 1000000/HZ);
2319 }
2320 /* Did we succeed? */
2321 if (ret) {
2322 /* reset on all failures. */
2323 map_write(map, CMD(0xF0), chip->start);
2324 /* FIXME - should have reset delay before continuing */
2325
2326 if (++retry_cnt <= MAX_RETRIES) {
2327 ret = 0;
2328 goto retry;
2329 }
2330 }
2331
2332 chip->state = FL_READY;
2333 xip_enable(map, chip, adr);
2334 DISABLE_VPP(map);
2335 put_chip(map, chip, adr);
2336 mutex_unlock(&chip->mutex);
2337
2338 return ret;
2339 }
2340
2341
do_erase_oneblock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2342 static int __xipram do_erase_oneblock(struct map_info *map, struct flchip *chip, unsigned long adr, int len, void *thunk)
2343 {
2344 struct cfi_private *cfi = map->fldrv_priv;
2345 unsigned long timeo = jiffies + HZ;
2346 DECLARE_WAITQUEUE(wait, current);
2347 int ret = 0;
2348 int retry_cnt = 0;
2349
2350 adr += chip->start;
2351
2352 mutex_lock(&chip->mutex);
2353 ret = get_chip(map, chip, adr, FL_ERASING);
2354 if (ret) {
2355 mutex_unlock(&chip->mutex);
2356 return ret;
2357 }
2358
2359 pr_debug("MTD %s(): ERASE 0x%.8lx\n",
2360 __func__, adr);
2361
2362 XIP_INVAL_CACHED_RANGE(map, adr, len);
2363 ENABLE_VPP(map);
2364 xip_disable(map, chip, adr);
2365
2366 retry:
2367 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2368 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2369 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2370 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL);
2371 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL);
2372 map_write(map, cfi->sector_erase_cmd, adr);
2373
2374 chip->state = FL_ERASING;
2375 chip->erase_suspended = 0;
2376 chip->in_progress_block_addr = adr;
2377 chip->in_progress_block_mask = ~(len - 1);
2378
2379 INVALIDATE_CACHE_UDELAY(map, chip,
2380 adr, len,
2381 chip->erase_time*500);
2382
2383 timeo = jiffies + (HZ*20);
2384
2385 for (;;) {
2386 if (chip->state != FL_ERASING) {
2387 /* Someone's suspended the erase. Sleep */
2388 set_current_state(TASK_UNINTERRUPTIBLE);
2389 add_wait_queue(&chip->wq, &wait);
2390 mutex_unlock(&chip->mutex);
2391 schedule();
2392 remove_wait_queue(&chip->wq, &wait);
2393 mutex_lock(&chip->mutex);
2394 continue;
2395 }
2396 if (chip->erase_suspended) {
2397 /* This erase was suspended and resumed.
2398 Adjust the timeout */
2399 timeo = jiffies + (HZ*20); /* FIXME */
2400 chip->erase_suspended = 0;
2401 }
2402
2403 if (chip_good(map, adr, map_word_ff(map)))
2404 break;
2405
2406 if (time_after(jiffies, timeo)) {
2407 printk(KERN_WARNING "MTD %s(): software timeout\n",
2408 __func__);
2409 ret = -EIO;
2410 break;
2411 }
2412
2413 /* Latency issues. Drop the lock, wait a while and retry */
2414 UDELAY(map, chip, adr, 1000000/HZ);
2415 }
2416 /* Did we succeed? */
2417 if (ret) {
2418 /* reset on all failures. */
2419 map_write(map, CMD(0xF0), chip->start);
2420 /* FIXME - should have reset delay before continuing */
2421
2422 if (++retry_cnt <= MAX_RETRIES) {
2423 ret = 0;
2424 goto retry;
2425 }
2426 }
2427
2428 chip->state = FL_READY;
2429 xip_enable(map, chip, adr);
2430 DISABLE_VPP(map);
2431 put_chip(map, chip, adr);
2432 mutex_unlock(&chip->mutex);
2433 return ret;
2434 }
2435
2436
cfi_amdstd_erase_varsize(struct mtd_info * mtd,struct erase_info * instr)2437 static int cfi_amdstd_erase_varsize(struct mtd_info *mtd, struct erase_info *instr)
2438 {
2439 return cfi_varsize_frob(mtd, do_erase_oneblock, instr->addr,
2440 instr->len, NULL);
2441 }
2442
2443
cfi_amdstd_erase_chip(struct mtd_info * mtd,struct erase_info * instr)2444 static int cfi_amdstd_erase_chip(struct mtd_info *mtd, struct erase_info *instr)
2445 {
2446 struct map_info *map = mtd->priv;
2447 struct cfi_private *cfi = map->fldrv_priv;
2448
2449 if (instr->addr != 0)
2450 return -EINVAL;
2451
2452 if (instr->len != mtd->size)
2453 return -EINVAL;
2454
2455 return do_erase_chip(map, &cfi->chips[0]);
2456 }
2457
do_atmel_lock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2458 static int do_atmel_lock(struct map_info *map, struct flchip *chip,
2459 unsigned long adr, int len, void *thunk)
2460 {
2461 struct cfi_private *cfi = map->fldrv_priv;
2462 int ret;
2463
2464 mutex_lock(&chip->mutex);
2465 ret = get_chip(map, chip, adr + chip->start, FL_LOCKING);
2466 if (ret)
2467 goto out_unlock;
2468 chip->state = FL_LOCKING;
2469
2470 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2471
2472 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2473 cfi->device_type, NULL);
2474 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2475 cfi->device_type, NULL);
2476 cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi,
2477 cfi->device_type, NULL);
2478 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2479 cfi->device_type, NULL);
2480 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2481 cfi->device_type, NULL);
2482 map_write(map, CMD(0x40), chip->start + adr);
2483
2484 chip->state = FL_READY;
2485 put_chip(map, chip, adr + chip->start);
2486 ret = 0;
2487
2488 out_unlock:
2489 mutex_unlock(&chip->mutex);
2490 return ret;
2491 }
2492
do_atmel_unlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2493 static int do_atmel_unlock(struct map_info *map, struct flchip *chip,
2494 unsigned long adr, int len, void *thunk)
2495 {
2496 struct cfi_private *cfi = map->fldrv_priv;
2497 int ret;
2498
2499 mutex_lock(&chip->mutex);
2500 ret = get_chip(map, chip, adr + chip->start, FL_UNLOCKING);
2501 if (ret)
2502 goto out_unlock;
2503 chip->state = FL_UNLOCKING;
2504
2505 pr_debug("MTD %s(): LOCK 0x%08lx len %d\n", __func__, adr, len);
2506
2507 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2508 cfi->device_type, NULL);
2509 map_write(map, CMD(0x70), adr);
2510
2511 chip->state = FL_READY;
2512 put_chip(map, chip, adr + chip->start);
2513 ret = 0;
2514
2515 out_unlock:
2516 mutex_unlock(&chip->mutex);
2517 return ret;
2518 }
2519
cfi_atmel_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2520 static int cfi_atmel_lock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2521 {
2522 return cfi_varsize_frob(mtd, do_atmel_lock, ofs, len, NULL);
2523 }
2524
cfi_atmel_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2525 static int cfi_atmel_unlock(struct mtd_info *mtd, loff_t ofs, uint64_t len)
2526 {
2527 return cfi_varsize_frob(mtd, do_atmel_unlock, ofs, len, NULL);
2528 }
2529
2530 /*
2531 * Advanced Sector Protection - PPB (Persistent Protection Bit) locking
2532 */
2533
2534 struct ppb_lock {
2535 struct flchip *chip;
2536 unsigned long adr;
2537 int locked;
2538 };
2539
2540 #define MAX_SECTORS 512
2541
2542 #define DO_XXLOCK_ONEBLOCK_LOCK ((void *)1)
2543 #define DO_XXLOCK_ONEBLOCK_UNLOCK ((void *)2)
2544 #define DO_XXLOCK_ONEBLOCK_GETLOCK ((void *)3)
2545
do_ppb_xxlock(struct map_info * map,struct flchip * chip,unsigned long adr,int len,void * thunk)2546 static int __maybe_unused do_ppb_xxlock(struct map_info *map,
2547 struct flchip *chip,
2548 unsigned long adr, int len, void *thunk)
2549 {
2550 struct cfi_private *cfi = map->fldrv_priv;
2551 unsigned long timeo;
2552 int ret;
2553
2554 adr += chip->start;
2555 mutex_lock(&chip->mutex);
2556 ret = get_chip(map, chip, adr, FL_LOCKING);
2557 if (ret) {
2558 mutex_unlock(&chip->mutex);
2559 return ret;
2560 }
2561
2562 pr_debug("MTD %s(): XXLOCK 0x%08lx len %d\n", __func__, adr, len);
2563
2564 cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi,
2565 cfi->device_type, NULL);
2566 cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi,
2567 cfi->device_type, NULL);
2568 /* PPB entry command */
2569 cfi_send_gen_cmd(0xC0, cfi->addr_unlock1, chip->start, map, cfi,
2570 cfi->device_type, NULL);
2571
2572 if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) {
2573 chip->state = FL_LOCKING;
2574 map_write(map, CMD(0xA0), adr);
2575 map_write(map, CMD(0x00), adr);
2576 } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) {
2577 /*
2578 * Unlocking of one specific sector is not supported, so we
2579 * have to unlock all sectors of this device instead
2580 */
2581 chip->state = FL_UNLOCKING;
2582 map_write(map, CMD(0x80), chip->start);
2583 map_write(map, CMD(0x30), chip->start);
2584 } else if (thunk == DO_XXLOCK_ONEBLOCK_GETLOCK) {
2585 chip->state = FL_JEDEC_QUERY;
2586 /* Return locked status: 0->locked, 1->unlocked */
2587 ret = !cfi_read_query(map, adr);
2588 } else
2589 BUG();
2590
2591 /*
2592 * Wait for some time as unlocking of all sectors takes quite long
2593 */
2594 timeo = jiffies + msecs_to_jiffies(2000); /* 2s max (un)locking */
2595 for (;;) {
2596 if (chip_ready(map, adr))
2597 break;
2598
2599 if (time_after(jiffies, timeo)) {
2600 printk(KERN_ERR "Waiting for chip to be ready timed out.\n");
2601 ret = -EIO;
2602 break;
2603 }
2604
2605 UDELAY(map, chip, adr, 1);
2606 }
2607
2608 /* Exit BC commands */
2609 map_write(map, CMD(0x90), chip->start);
2610 map_write(map, CMD(0x00), chip->start);
2611
2612 chip->state = FL_READY;
2613 put_chip(map, chip, adr);
2614 mutex_unlock(&chip->mutex);
2615
2616 return ret;
2617 }
2618
cfi_ppb_lock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2619 static int __maybe_unused cfi_ppb_lock(struct mtd_info *mtd, loff_t ofs,
2620 uint64_t len)
2621 {
2622 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2623 DO_XXLOCK_ONEBLOCK_LOCK);
2624 }
2625
cfi_ppb_unlock(struct mtd_info * mtd,loff_t ofs,uint64_t len)2626 static int __maybe_unused cfi_ppb_unlock(struct mtd_info *mtd, loff_t ofs,
2627 uint64_t len)
2628 {
2629 struct mtd_erase_region_info *regions = mtd->eraseregions;
2630 struct map_info *map = mtd->priv;
2631 struct cfi_private *cfi = map->fldrv_priv;
2632 struct ppb_lock *sect;
2633 unsigned long adr;
2634 loff_t offset;
2635 uint64_t length;
2636 int chipnum;
2637 int i;
2638 int sectors;
2639 int ret;
2640
2641 /*
2642 * PPB unlocking always unlocks all sectors of the flash chip.
2643 * We need to re-lock all previously locked sectors. So lets
2644 * first check the locking status of all sectors and save
2645 * it for future use.
2646 */
2647 sect = kcalloc(MAX_SECTORS, sizeof(struct ppb_lock), GFP_KERNEL);
2648 if (!sect)
2649 return -ENOMEM;
2650
2651 /*
2652 * This code to walk all sectors is a slightly modified version
2653 * of the cfi_varsize_frob() code.
2654 */
2655 i = 0;
2656 chipnum = 0;
2657 adr = 0;
2658 sectors = 0;
2659 offset = 0;
2660 length = mtd->size;
2661
2662 while (length) {
2663 int size = regions[i].erasesize;
2664
2665 /*
2666 * Only test sectors that shall not be unlocked. The other
2667 * sectors shall be unlocked, so lets keep their locking
2668 * status at "unlocked" (locked=0) for the final re-locking.
2669 */
2670 if ((offset < ofs) || (offset >= (ofs + len))) {
2671 sect[sectors].chip = &cfi->chips[chipnum];
2672 sect[sectors].adr = adr;
2673 sect[sectors].locked = do_ppb_xxlock(
2674 map, &cfi->chips[chipnum], adr, 0,
2675 DO_XXLOCK_ONEBLOCK_GETLOCK);
2676 }
2677
2678 adr += size;
2679 offset += size;
2680 length -= size;
2681
2682 if (offset == regions[i].offset + size * regions[i].numblocks)
2683 i++;
2684
2685 if (adr >> cfi->chipshift) {
2686 if (offset >= (ofs + len))
2687 break;
2688 adr = 0;
2689 chipnum++;
2690
2691 if (chipnum >= cfi->numchips)
2692 break;
2693 }
2694
2695 sectors++;
2696 if (sectors >= MAX_SECTORS) {
2697 printk(KERN_ERR "Only %d sectors for PPB locking supported!\n",
2698 MAX_SECTORS);
2699 kfree(sect);
2700 return -EINVAL;
2701 }
2702 }
2703
2704 /* Now unlock the whole chip */
2705 ret = cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2706 DO_XXLOCK_ONEBLOCK_UNLOCK);
2707 if (ret) {
2708 kfree(sect);
2709 return ret;
2710 }
2711
2712 /*
2713 * PPB unlocking always unlocks all sectors of the flash chip.
2714 * We need to re-lock all previously locked sectors.
2715 */
2716 for (i = 0; i < sectors; i++) {
2717 if (sect[i].locked)
2718 do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0,
2719 DO_XXLOCK_ONEBLOCK_LOCK);
2720 }
2721
2722 kfree(sect);
2723 return ret;
2724 }
2725
cfi_ppb_is_locked(struct mtd_info * mtd,loff_t ofs,uint64_t len)2726 static int __maybe_unused cfi_ppb_is_locked(struct mtd_info *mtd, loff_t ofs,
2727 uint64_t len)
2728 {
2729 return cfi_varsize_frob(mtd, do_ppb_xxlock, ofs, len,
2730 DO_XXLOCK_ONEBLOCK_GETLOCK) ? 1 : 0;
2731 }
2732
cfi_amdstd_sync(struct mtd_info * mtd)2733 static void cfi_amdstd_sync (struct mtd_info *mtd)
2734 {
2735 struct map_info *map = mtd->priv;
2736 struct cfi_private *cfi = map->fldrv_priv;
2737 int i;
2738 struct flchip *chip;
2739 int ret = 0;
2740 DECLARE_WAITQUEUE(wait, current);
2741
2742 for (i=0; !ret && i<cfi->numchips; i++) {
2743 chip = &cfi->chips[i];
2744
2745 retry:
2746 mutex_lock(&chip->mutex);
2747
2748 switch(chip->state) {
2749 case FL_READY:
2750 case FL_STATUS:
2751 case FL_CFI_QUERY:
2752 case FL_JEDEC_QUERY:
2753 chip->oldstate = chip->state;
2754 chip->state = FL_SYNCING;
2755 /* No need to wake_up() on this state change -
2756 * as the whole point is that nobody can do anything
2757 * with the chip now anyway.
2758 */
2759 case FL_SYNCING:
2760 mutex_unlock(&chip->mutex);
2761 break;
2762
2763 default:
2764 /* Not an idle state */
2765 set_current_state(TASK_UNINTERRUPTIBLE);
2766 add_wait_queue(&chip->wq, &wait);
2767
2768 mutex_unlock(&chip->mutex);
2769
2770 schedule();
2771
2772 remove_wait_queue(&chip->wq, &wait);
2773
2774 goto retry;
2775 }
2776 }
2777
2778 /* Unlock the chips again */
2779
2780 for (i--; i >=0; i--) {
2781 chip = &cfi->chips[i];
2782
2783 mutex_lock(&chip->mutex);
2784
2785 if (chip->state == FL_SYNCING) {
2786 chip->state = chip->oldstate;
2787 wake_up(&chip->wq);
2788 }
2789 mutex_unlock(&chip->mutex);
2790 }
2791 }
2792
2793
cfi_amdstd_suspend(struct mtd_info * mtd)2794 static int cfi_amdstd_suspend(struct mtd_info *mtd)
2795 {
2796 struct map_info *map = mtd->priv;
2797 struct cfi_private *cfi = map->fldrv_priv;
2798 int i;
2799 struct flchip *chip;
2800 int ret = 0;
2801
2802 for (i=0; !ret && i<cfi->numchips; i++) {
2803 chip = &cfi->chips[i];
2804
2805 mutex_lock(&chip->mutex);
2806
2807 switch(chip->state) {
2808 case FL_READY:
2809 case FL_STATUS:
2810 case FL_CFI_QUERY:
2811 case FL_JEDEC_QUERY:
2812 chip->oldstate = chip->state;
2813 chip->state = FL_PM_SUSPENDED;
2814 /* No need to wake_up() on this state change -
2815 * as the whole point is that nobody can do anything
2816 * with the chip now anyway.
2817 */
2818 case FL_PM_SUSPENDED:
2819 break;
2820
2821 default:
2822 ret = -EAGAIN;
2823 break;
2824 }
2825 mutex_unlock(&chip->mutex);
2826 }
2827
2828 /* Unlock the chips again */
2829
2830 if (ret) {
2831 for (i--; i >=0; i--) {
2832 chip = &cfi->chips[i];
2833
2834 mutex_lock(&chip->mutex);
2835
2836 if (chip->state == FL_PM_SUSPENDED) {
2837 chip->state = chip->oldstate;
2838 wake_up(&chip->wq);
2839 }
2840 mutex_unlock(&chip->mutex);
2841 }
2842 }
2843
2844 return ret;
2845 }
2846
2847
cfi_amdstd_resume(struct mtd_info * mtd)2848 static void cfi_amdstd_resume(struct mtd_info *mtd)
2849 {
2850 struct map_info *map = mtd->priv;
2851 struct cfi_private *cfi = map->fldrv_priv;
2852 int i;
2853 struct flchip *chip;
2854
2855 for (i=0; i<cfi->numchips; i++) {
2856
2857 chip = &cfi->chips[i];
2858
2859 mutex_lock(&chip->mutex);
2860
2861 if (chip->state == FL_PM_SUSPENDED) {
2862 chip->state = FL_READY;
2863 map_write(map, CMD(0xF0), chip->start);
2864 wake_up(&chip->wq);
2865 }
2866 else
2867 printk(KERN_ERR "Argh. Chip not in PM_SUSPENDED state upon resume()\n");
2868
2869 mutex_unlock(&chip->mutex);
2870 }
2871 }
2872
2873
2874 /*
2875 * Ensure that the flash device is put back into read array mode before
2876 * unloading the driver or rebooting. On some systems, rebooting while
2877 * the flash is in query/program/erase mode will prevent the CPU from
2878 * fetching the bootloader code, requiring a hard reset or power cycle.
2879 */
cfi_amdstd_reset(struct mtd_info * mtd)2880 static int cfi_amdstd_reset(struct mtd_info *mtd)
2881 {
2882 struct map_info *map = mtd->priv;
2883 struct cfi_private *cfi = map->fldrv_priv;
2884 int i, ret;
2885 struct flchip *chip;
2886
2887 for (i = 0; i < cfi->numchips; i++) {
2888
2889 chip = &cfi->chips[i];
2890
2891 mutex_lock(&chip->mutex);
2892
2893 ret = get_chip(map, chip, chip->start, FL_SHUTDOWN);
2894 if (!ret) {
2895 map_write(map, CMD(0xF0), chip->start);
2896 chip->state = FL_SHUTDOWN;
2897 put_chip(map, chip, chip->start);
2898 }
2899
2900 mutex_unlock(&chip->mutex);
2901 }
2902
2903 return 0;
2904 }
2905
2906
cfi_amdstd_reboot(struct notifier_block * nb,unsigned long val,void * v)2907 static int cfi_amdstd_reboot(struct notifier_block *nb, unsigned long val,
2908 void *v)
2909 {
2910 struct mtd_info *mtd;
2911
2912 mtd = container_of(nb, struct mtd_info, reboot_notifier);
2913 cfi_amdstd_reset(mtd);
2914 return NOTIFY_DONE;
2915 }
2916
2917
cfi_amdstd_destroy(struct mtd_info * mtd)2918 static void cfi_amdstd_destroy(struct mtd_info *mtd)
2919 {
2920 struct map_info *map = mtd->priv;
2921 struct cfi_private *cfi = map->fldrv_priv;
2922
2923 cfi_amdstd_reset(mtd);
2924 unregister_reboot_notifier(&mtd->reboot_notifier);
2925 kfree(cfi->cmdset_priv);
2926 kfree(cfi->cfiq);
2927 kfree(cfi);
2928 kfree(mtd->eraseregions);
2929 }
2930
2931 MODULE_LICENSE("GPL");
2932 MODULE_AUTHOR("Crossnet Co. <info@crossnet.co.jp> et al.");
2933 MODULE_DESCRIPTION("MTD chip driver for AMD/Fujitsu flash chips");
2934 MODULE_ALIAS("cfi_cmdset_0006");
2935 MODULE_ALIAS("cfi_cmdset_0701");
2936