1 /*
2 * Oxford Semiconductor OXNAS NAND driver
3
4 * Copyright (C) 2016 Neil Armstrong <narmstrong@baylibre.com>
5 * Heavily based on plat_nand.c :
6 * Author: Vitaly Wool <vitalywool@gmail.com>
7 * Copyright (C) 2013 Ma Haijun <mahaijuns@gmail.com>
8 * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 *
14 */
15
16 #include <linux/err.h>
17 #include <linux/io.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
21 #include <linux/clk.h>
22 #include <linux/reset.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/mtd/rawnand.h>
25 #include <linux/mtd/partitions.h>
26 #include <linux/of.h>
27
28 /* Nand commands */
29 #define OXNAS_NAND_CMD_ALE BIT(18)
30 #define OXNAS_NAND_CMD_CLE BIT(19)
31
32 #define OXNAS_NAND_MAX_CHIPS 1
33
34 struct oxnas_nand_ctrl {
35 struct nand_controller base;
36 void __iomem *io_base;
37 struct clk *clk;
38 struct nand_chip *chips[OXNAS_NAND_MAX_CHIPS];
39 unsigned int nchips;
40 };
41
oxnas_nand_read_byte(struct mtd_info * mtd)42 static uint8_t oxnas_nand_read_byte(struct mtd_info *mtd)
43 {
44 struct nand_chip *chip = mtd_to_nand(mtd);
45 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
46
47 return readb(oxnas->io_base);
48 }
49
oxnas_nand_read_buf(struct mtd_info * mtd,u8 * buf,int len)50 static void oxnas_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
51 {
52 struct nand_chip *chip = mtd_to_nand(mtd);
53 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
54
55 ioread8_rep(oxnas->io_base, buf, len);
56 }
57
oxnas_nand_write_buf(struct mtd_info * mtd,const u8 * buf,int len)58 static void oxnas_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
59 {
60 struct nand_chip *chip = mtd_to_nand(mtd);
61 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
62
63 iowrite8_rep(oxnas->io_base, buf, len);
64 }
65
66 /* Single CS command control */
oxnas_nand_cmd_ctrl(struct mtd_info * mtd,int cmd,unsigned int ctrl)67 static void oxnas_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
68 unsigned int ctrl)
69 {
70 struct nand_chip *chip = mtd_to_nand(mtd);
71 struct oxnas_nand_ctrl *oxnas = nand_get_controller_data(chip);
72
73 if (ctrl & NAND_CLE)
74 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_CLE);
75 else if (ctrl & NAND_ALE)
76 writeb(cmd, oxnas->io_base + OXNAS_NAND_CMD_ALE);
77 }
78
79 /*
80 * Probe for the NAND device.
81 */
oxnas_nand_probe(struct platform_device * pdev)82 static int oxnas_nand_probe(struct platform_device *pdev)
83 {
84 struct device_node *np = pdev->dev.of_node;
85 struct device_node *nand_np;
86 struct oxnas_nand_ctrl *oxnas;
87 struct nand_chip *chip;
88 struct mtd_info *mtd;
89 struct resource *res;
90 int count = 0;
91 int err = 0;
92 int i;
93
94 /* Allocate memory for the device structure (and zero it) */
95 oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas),
96 GFP_KERNEL);
97 if (!oxnas)
98 return -ENOMEM;
99
100 nand_controller_init(&oxnas->base);
101
102 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
103 oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
104 if (IS_ERR(oxnas->io_base))
105 return PTR_ERR(oxnas->io_base);
106
107 oxnas->clk = devm_clk_get(&pdev->dev, NULL);
108 if (IS_ERR(oxnas->clk))
109 oxnas->clk = NULL;
110
111 /* Only a single chip node is supported */
112 count = of_get_child_count(np);
113 if (count > 1)
114 return -EINVAL;
115
116 err = clk_prepare_enable(oxnas->clk);
117 if (err)
118 return err;
119
120 device_reset_optional(&pdev->dev);
121
122 for_each_child_of_node(np, nand_np) {
123 chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip),
124 GFP_KERNEL);
125 if (!chip) {
126 err = -ENOMEM;
127 goto err_release_child;
128 }
129
130 chip->controller = &oxnas->base;
131
132 nand_set_flash_node(chip, nand_np);
133 nand_set_controller_data(chip, oxnas);
134
135 mtd = nand_to_mtd(chip);
136 mtd->dev.parent = &pdev->dev;
137 mtd->priv = chip;
138
139 chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
140 chip->read_buf = oxnas_nand_read_buf;
141 chip->read_byte = oxnas_nand_read_byte;
142 chip->write_buf = oxnas_nand_write_buf;
143 chip->chip_delay = 30;
144
145 /* Scan to find existence of the device */
146 err = nand_scan(chip, 1);
147 if (err)
148 goto err_release_child;
149
150 err = mtd_device_register(mtd, NULL, 0);
151 if (err)
152 goto err_cleanup_nand;
153
154 oxnas->chips[oxnas->nchips] = chip;
155 ++oxnas->nchips;
156 }
157
158 /* Exit if no chips found */
159 if (!oxnas->nchips) {
160 err = -ENODEV;
161 goto err_clk_unprepare;
162 }
163
164 platform_set_drvdata(pdev, oxnas);
165
166 return 0;
167
168 err_cleanup_nand:
169 nand_cleanup(chip);
170 err_release_child:
171 of_node_put(nand_np);
172
173 for (i = 0; i < oxnas->nchips; i++) {
174 chip = oxnas->chips[i];
175 WARN_ON(mtd_device_unregister(nand_to_mtd(chip)));
176 nand_cleanup(chip);
177 }
178
179 err_clk_unprepare:
180 clk_disable_unprepare(oxnas->clk);
181 return err;
182 }
183
oxnas_nand_remove(struct platform_device * pdev)184 static int oxnas_nand_remove(struct platform_device *pdev)
185 {
186 struct oxnas_nand_ctrl *oxnas = platform_get_drvdata(pdev);
187 struct nand_chip *chip;
188 int i;
189
190 for (i = 0; i < oxnas->nchips; i++) {
191 chip = oxnas->chips[i];
192 nand_release(chip);
193 }
194
195 clk_disable_unprepare(oxnas->clk);
196
197 return 0;
198 }
199
200 static const struct of_device_id oxnas_nand_match[] = {
201 { .compatible = "oxsemi,ox820-nand" },
202 {},
203 };
204 MODULE_DEVICE_TABLE(of, oxnas_nand_match);
205
206 static struct platform_driver oxnas_nand_driver = {
207 .probe = oxnas_nand_probe,
208 .remove = oxnas_nand_remove,
209 .driver = {
210 .name = "oxnas_nand",
211 .of_match_table = oxnas_nand_match,
212 },
213 };
214
215 module_platform_driver(oxnas_nand_driver);
216
217 MODULE_LICENSE("GPL");
218 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>");
219 MODULE_DESCRIPTION("Oxnas NAND driver");
220 MODULE_ALIAS("platform:oxnas_nand");
221