1 /*
2 * Toshiba TMIO NAND flash controller driver
3 *
4 * Slightly murky pre-git history of the driver:
5 *
6 * Copyright (c) Ian Molton 2004, 2005, 2008
7 * Original work, independent of sharps code. Included hardware ECC support.
8 * Hard ECC did not work for writes in the early revisions.
9 * Copyright (c) Dirk Opfer 2005.
10 * Modifications developed from sharps code but
11 * NOT containing any, ported onto Ians base.
12 * Copyright (c) Chris Humbert 2005
13 * Copyright (c) Dmitry Baryshkov 2008
14 * Minor fixes
15 *
16 * Parts copyright Sebastian Carlier
17 *
18 * This file is licensed under
19 * the terms of the GNU General Public License version 2. This program
20 * is licensed "as is" without any warranty of any kind, whether express
21 * or implied.
22 *
23 */
24
25
26 #include <linux/kernel.h>
27 #include <linux/module.h>
28 #include <linux/platform_device.h>
29 #include <linux/mfd/core.h>
30 #include <linux/mfd/tmio.h>
31 #include <linux/delay.h>
32 #include <linux/io.h>
33 #include <linux/irq.h>
34 #include <linux/interrupt.h>
35 #include <linux/ioport.h>
36 #include <linux/mtd/mtd.h>
37 #include <linux/mtd/rawnand.h>
38 #include <linux/mtd/nand_ecc.h>
39 #include <linux/mtd/partitions.h>
40 #include <linux/slab.h>
41
42 /*--------------------------------------------------------------------------*/
43
44 /*
45 * NAND Flash Host Controller Configuration Register
46 */
47 #define CCR_COMMAND 0x04 /* w Command */
48 #define CCR_BASE 0x10 /* l NAND Flash Control Reg Base Addr */
49 #define CCR_INTP 0x3d /* b Interrupt Pin */
50 #define CCR_INTE 0x48 /* b Interrupt Enable */
51 #define CCR_EC 0x4a /* b Event Control */
52 #define CCR_ICC 0x4c /* b Internal Clock Control */
53 #define CCR_ECCC 0x5b /* b ECC Control */
54 #define CCR_NFTC 0x60 /* b NAND Flash Transaction Control */
55 #define CCR_NFM 0x61 /* b NAND Flash Monitor */
56 #define CCR_NFPSC 0x62 /* b NAND Flash Power Supply Control */
57 #define CCR_NFDC 0x63 /* b NAND Flash Detect Control */
58
59 /*
60 * NAND Flash Control Register
61 */
62 #define FCR_DATA 0x00 /* bwl Data Register */
63 #define FCR_MODE 0x04 /* b Mode Register */
64 #define FCR_STATUS 0x05 /* b Status Register */
65 #define FCR_ISR 0x06 /* b Interrupt Status Register */
66 #define FCR_IMR 0x07 /* b Interrupt Mask Register */
67
68 /* FCR_MODE Register Command List */
69 #define FCR_MODE_DATA 0x94 /* Data Data_Mode */
70 #define FCR_MODE_COMMAND 0x95 /* Data Command_Mode */
71 #define FCR_MODE_ADDRESS 0x96 /* Data Address_Mode */
72
73 #define FCR_MODE_HWECC_CALC 0xB4 /* HW-ECC Data */
74 #define FCR_MODE_HWECC_RESULT 0xD4 /* HW-ECC Calc result Read_Mode */
75 #define FCR_MODE_HWECC_RESET 0xF4 /* HW-ECC Reset */
76
77 #define FCR_MODE_POWER_ON 0x0C /* Power Supply ON to SSFDC card */
78 #define FCR_MODE_POWER_OFF 0x08 /* Power Supply OFF to SSFDC card */
79
80 #define FCR_MODE_LED_OFF 0x00 /* LED OFF */
81 #define FCR_MODE_LED_ON 0x04 /* LED ON */
82
83 #define FCR_MODE_EJECT_ON 0x68 /* Ejection events active */
84 #define FCR_MODE_EJECT_OFF 0x08 /* Ejection events ignored */
85
86 #define FCR_MODE_LOCK 0x6C /* Lock_Mode. Eject Switch Invalid */
87 #define FCR_MODE_UNLOCK 0x0C /* UnLock_Mode. Eject Switch is valid */
88
89 #define FCR_MODE_CONTROLLER_ID 0x40 /* Controller ID Read */
90 #define FCR_MODE_STANDBY 0x00 /* SSFDC card Changes Standby State */
91
92 #define FCR_MODE_WE 0x80
93 #define FCR_MODE_ECC1 0x40
94 #define FCR_MODE_ECC0 0x20
95 #define FCR_MODE_CE 0x10
96 #define FCR_MODE_PCNT1 0x08
97 #define FCR_MODE_PCNT0 0x04
98 #define FCR_MODE_ALE 0x02
99 #define FCR_MODE_CLE 0x01
100
101 #define FCR_STATUS_BUSY 0x80
102
103 /*--------------------------------------------------------------------------*/
104
105 struct tmio_nand {
106 struct nand_chip chip;
107
108 struct platform_device *dev;
109
110 void __iomem *ccr;
111 void __iomem *fcr;
112 unsigned long fcr_base;
113
114 unsigned int irq;
115
116 /* for tmio_nand_read_byte */
117 u8 read;
118 unsigned read_good:1;
119 };
120
mtd_to_tmio(struct mtd_info * mtd)121 static inline struct tmio_nand *mtd_to_tmio(struct mtd_info *mtd)
122 {
123 return container_of(mtd_to_nand(mtd), struct tmio_nand, chip);
124 }
125
126
127 /*--------------------------------------------------------------------------*/
128
tmio_nand_hwcontrol(struct mtd_info * mtd,int cmd,unsigned int ctrl)129 static void tmio_nand_hwcontrol(struct mtd_info *mtd, int cmd,
130 unsigned int ctrl)
131 {
132 struct tmio_nand *tmio = mtd_to_tmio(mtd);
133 struct nand_chip *chip = mtd_to_nand(mtd);
134
135 if (ctrl & NAND_CTRL_CHANGE) {
136 u8 mode;
137
138 if (ctrl & NAND_NCE) {
139 mode = FCR_MODE_DATA;
140
141 if (ctrl & NAND_CLE)
142 mode |= FCR_MODE_CLE;
143 else
144 mode &= ~FCR_MODE_CLE;
145
146 if (ctrl & NAND_ALE)
147 mode |= FCR_MODE_ALE;
148 else
149 mode &= ~FCR_MODE_ALE;
150 } else {
151 mode = FCR_MODE_STANDBY;
152 }
153
154 tmio_iowrite8(mode, tmio->fcr + FCR_MODE);
155 tmio->read_good = 0;
156 }
157
158 if (cmd != NAND_CMD_NONE)
159 tmio_iowrite8(cmd, chip->IO_ADDR_W);
160 }
161
tmio_nand_dev_ready(struct mtd_info * mtd)162 static int tmio_nand_dev_ready(struct mtd_info *mtd)
163 {
164 struct tmio_nand *tmio = mtd_to_tmio(mtd);
165
166 return !(tmio_ioread8(tmio->fcr + FCR_STATUS) & FCR_STATUS_BUSY);
167 }
168
tmio_irq(int irq,void * __tmio)169 static irqreturn_t tmio_irq(int irq, void *__tmio)
170 {
171 struct tmio_nand *tmio = __tmio;
172 struct nand_chip *nand_chip = &tmio->chip;
173
174 /* disable RDYREQ interrupt */
175 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
176
177 if (unlikely(!waitqueue_active(&nand_chip->controller->wq)))
178 dev_warn(&tmio->dev->dev, "spurious interrupt\n");
179
180 wake_up(&nand_chip->controller->wq);
181 return IRQ_HANDLED;
182 }
183
184 /*
185 *The TMIO core has a RDYREQ interrupt on the posedge of #SMRB.
186 *This interrupt is normally disabled, but for long operations like
187 *erase and write, we enable it to wake us up. The irq handler
188 *disables the interrupt.
189 */
190 static int
tmio_nand_wait(struct mtd_info * mtd,struct nand_chip * nand_chip)191 tmio_nand_wait(struct mtd_info *mtd, struct nand_chip *nand_chip)
192 {
193 struct tmio_nand *tmio = mtd_to_tmio(mtd);
194 long timeout;
195 u8 status;
196
197 /* enable RDYREQ interrupt */
198 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
199 tmio_iowrite8(0x81, tmio->fcr + FCR_IMR);
200
201 timeout = wait_event_timeout(nand_chip->controller->wq,
202 tmio_nand_dev_ready(mtd),
203 msecs_to_jiffies(nand_chip->state == FL_ERASING ? 400 : 20));
204
205 if (unlikely(!tmio_nand_dev_ready(mtd))) {
206 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
207 dev_warn(&tmio->dev->dev, "still busy with %s after %d ms\n",
208 nand_chip->state == FL_ERASING ? "erase" : "program",
209 nand_chip->state == FL_ERASING ? 400 : 20);
210
211 } else if (unlikely(!timeout)) {
212 tmio_iowrite8(0x00, tmio->fcr + FCR_IMR);
213 dev_warn(&tmio->dev->dev, "timeout waiting for interrupt\n");
214 }
215
216 nand_status_op(nand_chip, &status);
217 return status;
218 }
219
220 /*
221 *The TMIO controller combines two 8-bit data bytes into one 16-bit
222 *word. This function separates them so nand_base.c works as expected,
223 *especially its NAND_CMD_READID routines.
224 *
225 *To prevent stale data from being read, tmio_nand_hwcontrol() clears
226 *tmio->read_good.
227 */
tmio_nand_read_byte(struct mtd_info * mtd)228 static u_char tmio_nand_read_byte(struct mtd_info *mtd)
229 {
230 struct tmio_nand *tmio = mtd_to_tmio(mtd);
231 unsigned int data;
232
233 if (tmio->read_good--)
234 return tmio->read;
235
236 data = tmio_ioread16(tmio->fcr + FCR_DATA);
237 tmio->read = data >> 8;
238 return data;
239 }
240
241 /*
242 *The TMIO controller converts an 8-bit NAND interface to a 16-bit
243 *bus interface, so all data reads and writes must be 16-bit wide.
244 *Thus, we implement 16-bit versions of the read, write, and verify
245 *buffer functions.
246 */
247 static void
tmio_nand_write_buf(struct mtd_info * mtd,const u_char * buf,int len)248 tmio_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len)
249 {
250 struct tmio_nand *tmio = mtd_to_tmio(mtd);
251
252 tmio_iowrite16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
253 }
254
tmio_nand_read_buf(struct mtd_info * mtd,u_char * buf,int len)255 static void tmio_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
256 {
257 struct tmio_nand *tmio = mtd_to_tmio(mtd);
258
259 tmio_ioread16_rep(tmio->fcr + FCR_DATA, buf, len >> 1);
260 }
261
tmio_nand_enable_hwecc(struct mtd_info * mtd,int mode)262 static void tmio_nand_enable_hwecc(struct mtd_info *mtd, int mode)
263 {
264 struct tmio_nand *tmio = mtd_to_tmio(mtd);
265
266 tmio_iowrite8(FCR_MODE_HWECC_RESET, tmio->fcr + FCR_MODE);
267 tmio_ioread8(tmio->fcr + FCR_DATA); /* dummy read */
268 tmio_iowrite8(FCR_MODE_HWECC_CALC, tmio->fcr + FCR_MODE);
269 }
270
tmio_nand_calculate_ecc(struct mtd_info * mtd,const u_char * dat,u_char * ecc_code)271 static int tmio_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat,
272 u_char *ecc_code)
273 {
274 struct tmio_nand *tmio = mtd_to_tmio(mtd);
275 unsigned int ecc;
276
277 tmio_iowrite8(FCR_MODE_HWECC_RESULT, tmio->fcr + FCR_MODE);
278
279 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
280 ecc_code[1] = ecc; /* 000-255 LP7-0 */
281 ecc_code[0] = ecc >> 8; /* 000-255 LP15-8 */
282 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
283 ecc_code[2] = ecc; /* 000-255 CP5-0,11b */
284 ecc_code[4] = ecc >> 8; /* 256-511 LP7-0 */
285 ecc = tmio_ioread16(tmio->fcr + FCR_DATA);
286 ecc_code[3] = ecc; /* 256-511 LP15-8 */
287 ecc_code[5] = ecc >> 8; /* 256-511 CP5-0,11b */
288
289 tmio_iowrite8(FCR_MODE_DATA, tmio->fcr + FCR_MODE);
290 return 0;
291 }
292
tmio_nand_correct_data(struct mtd_info * mtd,unsigned char * buf,unsigned char * read_ecc,unsigned char * calc_ecc)293 static int tmio_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
294 unsigned char *read_ecc, unsigned char *calc_ecc)
295 {
296 int r0, r1;
297
298 /* assume ecc.size = 512 and ecc.bytes = 6 */
299 r0 = __nand_correct_data(buf, read_ecc, calc_ecc, 256);
300 if (r0 < 0)
301 return r0;
302 r1 = __nand_correct_data(buf + 256, read_ecc + 3, calc_ecc + 3, 256);
303 if (r1 < 0)
304 return r1;
305 return r0 + r1;
306 }
307
tmio_hw_init(struct platform_device * dev,struct tmio_nand * tmio)308 static int tmio_hw_init(struct platform_device *dev, struct tmio_nand *tmio)
309 {
310 const struct mfd_cell *cell = mfd_get_cell(dev);
311 int ret;
312
313 if (cell->enable) {
314 ret = cell->enable(dev);
315 if (ret)
316 return ret;
317 }
318
319 /* (4Ch) CLKRUN Enable 1st spcrunc */
320 tmio_iowrite8(0x81, tmio->ccr + CCR_ICC);
321
322 /* (10h)BaseAddress 0x1000 spba.spba2 */
323 tmio_iowrite16(tmio->fcr_base, tmio->ccr + CCR_BASE);
324 tmio_iowrite16(tmio->fcr_base >> 16, tmio->ccr + CCR_BASE + 2);
325
326 /* (04h)Command Register I/O spcmd */
327 tmio_iowrite8(0x02, tmio->ccr + CCR_COMMAND);
328
329 /* (62h) Power Supply Control ssmpwc */
330 /* HardPowerOFF - SuspendOFF - PowerSupplyWait_4MS */
331 tmio_iowrite8(0x02, tmio->ccr + CCR_NFPSC);
332
333 /* (63h) Detect Control ssmdtc */
334 tmio_iowrite8(0x02, tmio->ccr + CCR_NFDC);
335
336 /* Interrupt status register clear sintst */
337 tmio_iowrite8(0x0f, tmio->fcr + FCR_ISR);
338
339 /* After power supply, Media are reset smode */
340 tmio_iowrite8(FCR_MODE_POWER_ON, tmio->fcr + FCR_MODE);
341 tmio_iowrite8(FCR_MODE_COMMAND, tmio->fcr + FCR_MODE);
342 tmio_iowrite8(NAND_CMD_RESET, tmio->fcr + FCR_DATA);
343
344 /* Standby Mode smode */
345 tmio_iowrite8(FCR_MODE_STANDBY, tmio->fcr + FCR_MODE);
346
347 mdelay(5);
348
349 return 0;
350 }
351
tmio_hw_stop(struct platform_device * dev,struct tmio_nand * tmio)352 static void tmio_hw_stop(struct platform_device *dev, struct tmio_nand *tmio)
353 {
354 const struct mfd_cell *cell = mfd_get_cell(dev);
355
356 tmio_iowrite8(FCR_MODE_POWER_OFF, tmio->fcr + FCR_MODE);
357 if (cell->disable)
358 cell->disable(dev);
359 }
360
tmio_probe(struct platform_device * dev)361 static int tmio_probe(struct platform_device *dev)
362 {
363 struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
364 struct resource *fcr = platform_get_resource(dev,
365 IORESOURCE_MEM, 0);
366 struct resource *ccr = platform_get_resource(dev,
367 IORESOURCE_MEM, 1);
368 int irq = platform_get_irq(dev, 0);
369 struct tmio_nand *tmio;
370 struct mtd_info *mtd;
371 struct nand_chip *nand_chip;
372 int retval;
373
374 if (data == NULL)
375 dev_warn(&dev->dev, "NULL platform data!\n");
376
377 tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
378 if (!tmio)
379 return -ENOMEM;
380
381 tmio->dev = dev;
382
383 platform_set_drvdata(dev, tmio);
384 nand_chip = &tmio->chip;
385 mtd = nand_to_mtd(nand_chip);
386 mtd->name = "tmio-nand";
387 mtd->dev.parent = &dev->dev;
388
389 tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
390 if (!tmio->ccr)
391 return -EIO;
392
393 tmio->fcr_base = fcr->start & 0xfffff;
394 tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
395 if (!tmio->fcr)
396 return -EIO;
397
398 retval = tmio_hw_init(dev, tmio);
399 if (retval)
400 return retval;
401
402 /* Set address of NAND IO lines */
403 nand_chip->IO_ADDR_R = tmio->fcr;
404 nand_chip->IO_ADDR_W = tmio->fcr;
405
406 /* Set address of hardware control function */
407 nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
408 nand_chip->dev_ready = tmio_nand_dev_ready;
409 nand_chip->read_byte = tmio_nand_read_byte;
410 nand_chip->write_buf = tmio_nand_write_buf;
411 nand_chip->read_buf = tmio_nand_read_buf;
412
413 /* set eccmode using hardware ECC */
414 nand_chip->ecc.mode = NAND_ECC_HW;
415 nand_chip->ecc.size = 512;
416 nand_chip->ecc.bytes = 6;
417 nand_chip->ecc.strength = 2;
418 nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
419 nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
420 nand_chip->ecc.correct = tmio_nand_correct_data;
421
422 if (data)
423 nand_chip->badblock_pattern = data->badblock_pattern;
424
425 /* 15 us command delay time */
426 nand_chip->chip_delay = 15;
427
428 retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0,
429 dev_name(&dev->dev), tmio);
430 if (retval) {
431 dev_err(&dev->dev, "request_irq error %d\n", retval);
432 goto err_irq;
433 }
434
435 tmio->irq = irq;
436 nand_chip->waitfunc = tmio_nand_wait;
437
438 /* Scan to find existence of the device */
439 retval = nand_scan(nand_chip, 1);
440 if (retval)
441 goto err_irq;
442
443 /* Register the partitions */
444 retval = mtd_device_parse_register(mtd,
445 data ? data->part_parsers : NULL,
446 NULL,
447 data ? data->partition : NULL,
448 data ? data->num_partitions : 0);
449 if (!retval)
450 return retval;
451
452 nand_cleanup(nand_chip);
453
454 err_irq:
455 tmio_hw_stop(dev, tmio);
456 return retval;
457 }
458
tmio_remove(struct platform_device * dev)459 static int tmio_remove(struct platform_device *dev)
460 {
461 struct tmio_nand *tmio = platform_get_drvdata(dev);
462
463 nand_release(&tmio->chip);
464 tmio_hw_stop(dev, tmio);
465 return 0;
466 }
467
468 #ifdef CONFIG_PM
tmio_suspend(struct platform_device * dev,pm_message_t state)469 static int tmio_suspend(struct platform_device *dev, pm_message_t state)
470 {
471 const struct mfd_cell *cell = mfd_get_cell(dev);
472
473 if (cell->suspend)
474 cell->suspend(dev);
475
476 tmio_hw_stop(dev, platform_get_drvdata(dev));
477 return 0;
478 }
479
tmio_resume(struct platform_device * dev)480 static int tmio_resume(struct platform_device *dev)
481 {
482 const struct mfd_cell *cell = mfd_get_cell(dev);
483
484 /* FIXME - is this required or merely another attack of the broken
485 * SHARP platform? Looks suspicious.
486 */
487 tmio_hw_init(dev, platform_get_drvdata(dev));
488
489 if (cell->resume)
490 cell->resume(dev);
491
492 return 0;
493 }
494 #else
495 #define tmio_suspend NULL
496 #define tmio_resume NULL
497 #endif
498
499 static struct platform_driver tmio_driver = {
500 .driver.name = "tmio-nand",
501 .driver.owner = THIS_MODULE,
502 .probe = tmio_probe,
503 .remove = tmio_remove,
504 .suspend = tmio_suspend,
505 .resume = tmio_resume,
506 };
507
508 module_platform_driver(tmio_driver);
509
510 MODULE_LICENSE("GPL v2");
511 MODULE_AUTHOR("Ian Molton, Dirk Opfer, Chris Humbert, Dmitry Baryshkov");
512 MODULE_DESCRIPTION("NAND flash driver on Toshiba Mobile IO controller");
513 MODULE_ALIAS("platform:tmio-nand");
514