1 /* 2 * Copyright 2015 Amazon.com, Inc. or its affiliates. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33 #ifndef ENA_H 34 #define ENA_H 35 36 #include <linux/bitops.h> 37 #include <linux/etherdevice.h> 38 #include <linux/inetdevice.h> 39 #include <linux/interrupt.h> 40 #include <linux/netdevice.h> 41 #include <linux/skbuff.h> 42 43 #include "ena_com.h" 44 #include "ena_eth_com.h" 45 46 #define DRV_MODULE_VER_MAJOR 1 47 #define DRV_MODULE_VER_MINOR 5 48 #define DRV_MODULE_VER_SUBMINOR 0 49 50 #define DRV_MODULE_NAME "ena" 51 #ifndef DRV_MODULE_VERSION 52 #define DRV_MODULE_VERSION \ 53 __stringify(DRV_MODULE_VER_MAJOR) "." \ 54 __stringify(DRV_MODULE_VER_MINOR) "." \ 55 __stringify(DRV_MODULE_VER_SUBMINOR) "K" 56 #endif 57 58 #define DEVICE_NAME "Elastic Network Adapter (ENA)" 59 60 /* 1 for AENQ + ADMIN */ 61 #define ENA_ADMIN_MSIX_VEC 1 62 #define ENA_MAX_MSIX_VEC(io_queues) (ENA_ADMIN_MSIX_VEC + (io_queues)) 63 64 #define ENA_MIN_MSIX_VEC 2 65 66 #define ENA_REG_BAR 0 67 #define ENA_MEM_BAR 2 68 #define ENA_BAR_MASK (BIT(ENA_REG_BAR) | BIT(ENA_MEM_BAR)) 69 70 #define ENA_DEFAULT_RING_SIZE (1024) 71 72 #define ENA_TX_WAKEUP_THRESH (MAX_SKB_FRAGS + 2) 73 #define ENA_DEFAULT_RX_COPYBREAK (128 - NET_IP_ALIGN) 74 75 /* limit the buffer size to 600 bytes to handle MTU changes from very 76 * small to very large, in which case the number of buffers per packet 77 * could exceed ENA_PKT_MAX_BUFS 78 */ 79 #define ENA_DEFAULT_MIN_RX_BUFF_ALLOC_SIZE 600 80 81 #define ENA_MIN_MTU 128 82 83 #define ENA_NAME_MAX_LEN 20 84 #define ENA_IRQNAME_SIZE 40 85 86 #define ENA_PKT_MAX_BUFS 19 87 88 #define ENA_RX_RSS_TABLE_LOG_SIZE 7 89 #define ENA_RX_RSS_TABLE_SIZE (1 << ENA_RX_RSS_TABLE_LOG_SIZE) 90 91 #define ENA_HASH_KEY_SIZE 40 92 93 /* The number of tx packet completions that will be handled each NAPI poll 94 * cycle is ring_size / ENA_TX_POLL_BUDGET_DIVIDER. 95 */ 96 #define ENA_TX_POLL_BUDGET_DIVIDER 4 97 98 /* Refill Rx queue when number of available descriptors is below 99 * QUEUE_SIZE / ENA_RX_REFILL_THRESH_DIVIDER 100 */ 101 #define ENA_RX_REFILL_THRESH_DIVIDER 8 102 103 /* Number of queues to check for missing queues per timer service */ 104 #define ENA_MONITORED_TX_QUEUES 4 105 /* Max timeout packets before device reset */ 106 #define MAX_NUM_OF_TIMEOUTED_PACKETS 128 107 108 #define ENA_TX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 109 110 #define ENA_RX_RING_IDX_NEXT(idx, ring_size) (((idx) + 1) & ((ring_size) - 1)) 111 #define ENA_RX_RING_IDX_ADD(idx, n, ring_size) \ 112 (((idx) + (n)) & ((ring_size) - 1)) 113 114 #define ENA_IO_TXQ_IDX(q) (2 * (q)) 115 #define ENA_IO_RXQ_IDX(q) (2 * (q) + 1) 116 #define ENA_IO_TXQ_IDX_TO_COMBINED_IDX(q) ((q) / 2) 117 #define ENA_IO_RXQ_IDX_TO_COMBINED_IDX(q) (((q) - 1) / 2) 118 119 #define ENA_MGMNT_IRQ_IDX 0 120 #define ENA_IO_IRQ_FIRST_IDX 1 121 #define ENA_IO_IRQ_IDX(q) (ENA_IO_IRQ_FIRST_IDX + (q)) 122 123 /* ENA device should send keep alive msg every 1 sec. 124 * We wait for 6 sec just to be on the safe side. 125 */ 126 #define ENA_DEVICE_KALIVE_TIMEOUT (6 * HZ) 127 #define ENA_MAX_NO_INTERRUPT_ITERATIONS 3 128 129 #define ENA_MMIO_DISABLE_REG_READ BIT(0) 130 131 struct ena_irq { 132 irq_handler_t handler; 133 void *data; 134 int cpu; 135 u32 vector; 136 cpumask_t affinity_hint_mask; 137 char name[ENA_IRQNAME_SIZE]; 138 }; 139 140 struct ena_napi { 141 struct napi_struct napi ____cacheline_aligned; 142 struct ena_ring *tx_ring; 143 struct ena_ring *rx_ring; 144 u32 qid; 145 }; 146 147 struct ena_tx_buffer { 148 struct sk_buff *skb; 149 /* num of ena desc for this specific skb 150 * (includes data desc and metadata desc) 151 */ 152 u32 tx_descs; 153 /* num of buffers used by this skb */ 154 u32 num_of_bufs; 155 156 /* Used for detect missing tx packets to limit the number of prints */ 157 u32 print_once; 158 /* Save the last jiffies to detect missing tx packets 159 * 160 * sets to non zero value on ena_start_xmit and set to zero on 161 * napi and timer_Service_routine. 162 * 163 * while this value is not protected by lock, 164 * a given packet is not expected to be handled by ena_start_xmit 165 * and by napi/timer_service at the same time. 166 */ 167 unsigned long last_jiffies; 168 struct ena_com_buf bufs[ENA_PKT_MAX_BUFS]; 169 } ____cacheline_aligned; 170 171 struct ena_rx_buffer { 172 struct sk_buff *skb; 173 struct page *page; 174 u32 page_offset; 175 struct ena_com_buf ena_buf; 176 } ____cacheline_aligned; 177 178 struct ena_stats_tx { 179 u64 cnt; 180 u64 bytes; 181 u64 queue_stop; 182 u64 prepare_ctx_err; 183 u64 queue_wakeup; 184 u64 dma_mapping_err; 185 u64 linearize; 186 u64 linearize_failed; 187 u64 napi_comp; 188 u64 tx_poll; 189 u64 doorbells; 190 u64 bad_req_id; 191 u64 missed_tx; 192 }; 193 194 struct ena_stats_rx { 195 u64 cnt; 196 u64 bytes; 197 u64 refil_partial; 198 u64 bad_csum; 199 u64 page_alloc_fail; 200 u64 skb_alloc_fail; 201 u64 dma_mapping_err; 202 u64 bad_desc_num; 203 u64 rx_copybreak_pkt; 204 u64 bad_req_id; 205 u64 empty_rx_ring; 206 }; 207 208 struct ena_ring { 209 union { 210 /* Holds the empty requests for TX/RX 211 * out of order completions 212 */ 213 u16 *free_tx_ids; 214 u16 *free_rx_ids; 215 }; 216 217 union { 218 struct ena_tx_buffer *tx_buffer_info; 219 struct ena_rx_buffer *rx_buffer_info; 220 }; 221 222 /* cache ptr to avoid using the adapter */ 223 struct device *dev; 224 struct pci_dev *pdev; 225 struct napi_struct *napi; 226 struct net_device *netdev; 227 struct ena_com_dev *ena_dev; 228 struct ena_adapter *adapter; 229 struct ena_com_io_cq *ena_com_io_cq; 230 struct ena_com_io_sq *ena_com_io_sq; 231 232 u16 next_to_use; 233 u16 next_to_clean; 234 u16 rx_copybreak; 235 u16 qid; 236 u16 mtu; 237 u16 sgl_size; 238 239 /* The maximum header length the device can handle */ 240 u8 tx_max_header_size; 241 242 bool first_interrupt; 243 u16 no_interrupt_event_cnt; 244 245 /* cpu for TPH */ 246 int cpu; 247 /* number of tx/rx_buffer_info's entries */ 248 int ring_size; 249 250 enum ena_admin_placement_policy_type tx_mem_queue_type; 251 252 struct ena_com_rx_buf_info ena_bufs[ENA_PKT_MAX_BUFS]; 253 u32 smoothed_interval; 254 u32 per_napi_packets; 255 u32 per_napi_bytes; 256 enum ena_intr_moder_level moder_tbl_idx; 257 struct u64_stats_sync syncp; 258 union { 259 struct ena_stats_tx tx_stats; 260 struct ena_stats_rx rx_stats; 261 }; 262 int empty_rx_queue; 263 } ____cacheline_aligned; 264 265 struct ena_stats_dev { 266 u64 tx_timeout; 267 u64 suspend; 268 u64 resume; 269 u64 wd_expired; 270 u64 interface_up; 271 u64 interface_down; 272 u64 admin_q_pause; 273 u64 rx_drops; 274 }; 275 276 enum ena_flags_t { 277 ENA_FLAG_DEVICE_RUNNING, 278 ENA_FLAG_DEV_UP, 279 ENA_FLAG_LINK_UP, 280 ENA_FLAG_MSIX_ENABLED, 281 ENA_FLAG_TRIGGER_RESET, 282 ENA_FLAG_ONGOING_RESET 283 }; 284 285 /* adapter specific private data structure */ 286 struct ena_adapter { 287 struct ena_com_dev *ena_dev; 288 /* OS defined structs */ 289 struct net_device *netdev; 290 struct pci_dev *pdev; 291 292 /* rx packets that shorter that this len will be copied to the skb 293 * header 294 */ 295 u32 rx_copybreak; 296 u32 max_mtu; 297 298 int num_queues; 299 300 int msix_vecs; 301 302 u32 missing_tx_completion_threshold; 303 304 u32 tx_usecs, rx_usecs; /* interrupt moderation */ 305 u32 tx_frames, rx_frames; /* interrupt moderation */ 306 307 u32 tx_ring_size; 308 u32 rx_ring_size; 309 310 u32 msg_enable; 311 312 u16 max_tx_sgl_size; 313 u16 max_rx_sgl_size; 314 315 u8 mac_addr[ETH_ALEN]; 316 317 unsigned long keep_alive_timeout; 318 unsigned long missing_tx_completion_to; 319 320 char name[ENA_NAME_MAX_LEN]; 321 322 unsigned long flags; 323 /* TX */ 324 struct ena_ring tx_ring[ENA_MAX_NUM_IO_QUEUES] 325 ____cacheline_aligned_in_smp; 326 327 /* RX */ 328 struct ena_ring rx_ring[ENA_MAX_NUM_IO_QUEUES] 329 ____cacheline_aligned_in_smp; 330 331 struct ena_napi ena_napi[ENA_MAX_NUM_IO_QUEUES]; 332 333 struct ena_irq irq_tbl[ENA_MAX_MSIX_VEC(ENA_MAX_NUM_IO_QUEUES)]; 334 335 /* timer service */ 336 struct work_struct reset_task; 337 struct timer_list timer_service; 338 339 bool wd_state; 340 bool dev_up_before_reset; 341 unsigned long last_keep_alive_jiffies; 342 343 struct u64_stats_sync syncp; 344 struct ena_stats_dev dev_stats; 345 346 /* last queue index that was checked for uncompleted tx packets */ 347 u32 last_monitored_tx_qid; 348 349 enum ena_regs_reset_reason_types reset_reason; 350 }; 351 352 void ena_set_ethtool_ops(struct net_device *netdev); 353 354 void ena_dump_stats_to_dmesg(struct ena_adapter *adapter); 355 356 void ena_dump_stats_to_buf(struct ena_adapter *adapter, u8 *buf); 357 358 int ena_get_sset_count(struct net_device *netdev, int sset); 359 360 /* The ENA buffer length fields is 16 bit long. So when PAGE_SIZE == 64kB the 361 * driver passas 0. 362 * Since the max packet size the ENA handles is ~9kB limit the buffer length to 363 * 16kB. 364 */ 365 #if PAGE_SIZE > SZ_16K 366 #define ENA_PAGE_SIZE SZ_16K 367 #else 368 #define ENA_PAGE_SIZE PAGE_SIZE 369 #endif 370 371 #endif /* !(ENA_H) */ 372