1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2013 - 2018 Intel Corporation. */
3
4 #ifndef _I40E_H_
5 #define _I40E_H_
6
7 #include <net/tcp.h>
8 #include <net/udp.h>
9 #include <linux/types.h>
10 #include <linux/errno.h>
11 #include <linux/module.h>
12 #include <linux/pci.h>
13 #include <linux/aer.h>
14 #include <linux/netdevice.h>
15 #include <linux/ioport.h>
16 #include <linux/iommu.h>
17 #include <linux/slab.h>
18 #include <linux/list.h>
19 #include <linux/hashtable.h>
20 #include <linux/string.h>
21 #include <linux/in.h>
22 #include <linux/ip.h>
23 #include <linux/sctp.h>
24 #include <linux/pkt_sched.h>
25 #include <linux/ipv6.h>
26 #include <net/checksum.h>
27 #include <net/ip6_checksum.h>
28 #include <linux/ethtool.h>
29 #include <linux/if_vlan.h>
30 #include <linux/if_bridge.h>
31 #include <linux/clocksource.h>
32 #include <linux/net_tstamp.h>
33 #include <linux/ptp_clock_kernel.h>
34 #include <net/pkt_cls.h>
35 #include <net/tc_act/tc_gact.h>
36 #include <net/tc_act/tc_mirred.h>
37 #include "i40e_type.h"
38 #include "i40e_prototype.h"
39 #include "i40e_client.h"
40 #include <linux/avf/virtchnl.h>
41 #include "i40e_virtchnl_pf.h"
42 #include "i40e_txrx.h"
43 #include "i40e_dcb.h"
44
45 /* Useful i40e defaults */
46 #define I40E_MAX_VEB 16
47
48 #define I40E_MAX_NUM_DESCRIPTORS 4096
49 #define I40E_MAX_CSR_SPACE (4 * 1024 * 1024 - 64 * 1024)
50 #define I40E_DEFAULT_NUM_DESCRIPTORS 512
51 #define I40E_REQ_DESCRIPTOR_MULTIPLE 32
52 #define I40E_MIN_NUM_DESCRIPTORS 64
53 #define I40E_MIN_MSIX 2
54 #define I40E_DEFAULT_NUM_VMDQ_VSI 8 /* max 256 VSIs */
55 #define I40E_MIN_VSI_ALLOC 83 /* LAN, ATR, FCOE, 64 VF */
56 /* max 16 qps */
57 #define i40e_default_queues_per_vmdq(pf) \
58 (((pf)->hw_features & I40E_HW_RSS_AQ_CAPABLE) ? 4 : 1)
59 #define I40E_DEFAULT_QUEUES_PER_VF 4
60 #define I40E_MAX_VF_QUEUES 16
61 #define I40E_DEFAULT_QUEUES_PER_TC 1 /* should be a power of 2 */
62 #define i40e_pf_get_max_q_per_tc(pf) \
63 (((pf)->hw_features & I40E_HW_128_QP_RSS_CAPABLE) ? 128 : 64)
64 #define I40E_FDIR_RING 0
65 #define I40E_FDIR_RING_COUNT 32
66 #define I40E_MAX_AQ_BUF_SIZE 4096
67 #define I40E_AQ_LEN 256
68 #define I40E_AQ_WORK_LIMIT 66 /* max number of VFs + a little */
69 #define I40E_MAX_USER_PRIORITY 8
70 #define I40E_DEFAULT_TRAFFIC_CLASS BIT(0)
71 #define I40E_DEFAULT_MSG_ENABLE 4
72 #define I40E_QUEUE_WAIT_RETRY_LIMIT 10
73 #define I40E_INT_NAME_STR_LEN (IFNAMSIZ + 16)
74
75 #define I40E_NVM_VERSION_LO_SHIFT 0
76 #define I40E_NVM_VERSION_LO_MASK (0xff << I40E_NVM_VERSION_LO_SHIFT)
77 #define I40E_NVM_VERSION_HI_SHIFT 12
78 #define I40E_NVM_VERSION_HI_MASK (0xf << I40E_NVM_VERSION_HI_SHIFT)
79 #define I40E_OEM_VER_BUILD_MASK 0xffff
80 #define I40E_OEM_VER_PATCH_MASK 0xff
81 #define I40E_OEM_VER_BUILD_SHIFT 8
82 #define I40E_OEM_VER_SHIFT 24
83 #define I40E_PHY_DEBUG_ALL \
84 (I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW | \
85 I40E_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW)
86
87 #define I40E_OEM_EETRACK_ID 0xffffffff
88 #define I40E_OEM_GEN_SHIFT 24
89 #define I40E_OEM_SNAP_MASK 0x00ff0000
90 #define I40E_OEM_SNAP_SHIFT 16
91 #define I40E_OEM_RELEASE_MASK 0x0000ffff
92
93 /* The values in here are decimal coded as hex as is the case in the NVM map*/
94 #define I40E_CURRENT_NVM_VERSION_HI 0x2
95 #define I40E_CURRENT_NVM_VERSION_LO 0x40
96
97 #define I40E_RX_DESC(R, i) \
98 (&(((union i40e_32byte_rx_desc *)((R)->desc))[i]))
99 #define I40E_TX_DESC(R, i) \
100 (&(((struct i40e_tx_desc *)((R)->desc))[i]))
101 #define I40E_TX_CTXTDESC(R, i) \
102 (&(((struct i40e_tx_context_desc *)((R)->desc))[i]))
103 #define I40E_TX_FDIRDESC(R, i) \
104 (&(((struct i40e_filter_program_desc *)((R)->desc))[i]))
105
106 /* default to trying for four seconds */
107 #define I40E_TRY_LINK_TIMEOUT (4 * HZ)
108
109 /* BW rate limiting */
110 #define I40E_BW_CREDIT_DIVISOR 50 /* 50Mbps per BW credit */
111 #define I40E_BW_MBPS_DIVISOR 125000 /* rate / (1000000 / 8) Mbps */
112 #define I40E_MAX_BW_INACTIVE_ACCUM 4 /* accumulate 4 credits max */
113
114 /* driver state flags */
115 enum i40e_state_t {
116 __I40E_TESTING,
117 __I40E_CONFIG_BUSY,
118 __I40E_CONFIG_DONE,
119 __I40E_DOWN,
120 __I40E_SERVICE_SCHED,
121 __I40E_ADMINQ_EVENT_PENDING,
122 __I40E_MDD_EVENT_PENDING,
123 __I40E_VFLR_EVENT_PENDING,
124 __I40E_RESET_RECOVERY_PENDING,
125 __I40E_TIMEOUT_RECOVERY_PENDING,
126 __I40E_MISC_IRQ_REQUESTED,
127 __I40E_RESET_INTR_RECEIVED,
128 __I40E_REINIT_REQUESTED,
129 __I40E_PF_RESET_REQUESTED,
130 __I40E_CORE_RESET_REQUESTED,
131 __I40E_GLOBAL_RESET_REQUESTED,
132 __I40E_EMP_RESET_REQUESTED,
133 __I40E_EMP_RESET_INTR_RECEIVED,
134 __I40E_SUSPENDED,
135 __I40E_PTP_TX_IN_PROGRESS,
136 __I40E_BAD_EEPROM,
137 __I40E_DOWN_REQUESTED,
138 __I40E_FD_FLUSH_REQUESTED,
139 __I40E_FD_ATR_AUTO_DISABLED,
140 __I40E_FD_SB_AUTO_DISABLED,
141 __I40E_RESET_FAILED,
142 __I40E_PORT_SUSPENDED,
143 __I40E_VF_DISABLE,
144 __I40E_MACVLAN_SYNC_PENDING,
145 __I40E_UDP_FILTER_SYNC_PENDING,
146 __I40E_TEMP_LINK_POLLING,
147 __I40E_CLIENT_SERVICE_REQUESTED,
148 __I40E_CLIENT_L2_CHANGE,
149 __I40E_CLIENT_RESET,
150 /* This must be last as it determines the size of the BITMAP */
151 __I40E_STATE_SIZE__,
152 };
153
154 #define I40E_PF_RESET_FLAG BIT_ULL(__I40E_PF_RESET_REQUESTED)
155
156 /* VSI state flags */
157 enum i40e_vsi_state_t {
158 __I40E_VSI_DOWN,
159 __I40E_VSI_NEEDS_RESTART,
160 __I40E_VSI_SYNCING_FILTERS,
161 __I40E_VSI_OVERFLOW_PROMISC,
162 __I40E_VSI_REINIT_REQUESTED,
163 __I40E_VSI_DOWN_REQUESTED,
164 /* This must be last as it determines the size of the BITMAP */
165 __I40E_VSI_STATE_SIZE__,
166 };
167
168 enum i40e_interrupt_policy {
169 I40E_INTERRUPT_BEST_CASE,
170 I40E_INTERRUPT_MEDIUM,
171 I40E_INTERRUPT_LOWEST
172 };
173
174 struct i40e_lump_tracking {
175 u16 num_entries;
176 u16 search_hint;
177 u16 list[0];
178 #define I40E_PILE_VALID_BIT 0x8000
179 #define I40E_IWARP_IRQ_PILE_ID (I40E_PILE_VALID_BIT - 2)
180 };
181
182 #define I40E_DEFAULT_ATR_SAMPLE_RATE 20
183 #define I40E_FDIR_MAX_RAW_PACKET_SIZE 512
184 #define I40E_FDIR_BUFFER_FULL_MARGIN 10
185 #define I40E_FDIR_BUFFER_HEAD_ROOM 32
186 #define I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR (I40E_FDIR_BUFFER_HEAD_ROOM * 4)
187
188 #define I40E_HKEY_ARRAY_SIZE ((I40E_PFQF_HKEY_MAX_INDEX + 1) * 4)
189 #define I40E_HLUT_ARRAY_SIZE ((I40E_PFQF_HLUT_MAX_INDEX + 1) * 4)
190 #define I40E_VF_HLUT_ARRAY_SIZE ((I40E_VFQF_HLUT1_MAX_INDEX + 1) * 4)
191
192 enum i40e_fd_stat_idx {
193 I40E_FD_STAT_ATR,
194 I40E_FD_STAT_SB,
195 I40E_FD_STAT_ATR_TUNNEL,
196 I40E_FD_STAT_PF_COUNT
197 };
198 #define I40E_FD_STAT_PF_IDX(pf_id) ((pf_id) * I40E_FD_STAT_PF_COUNT)
199 #define I40E_FD_ATR_STAT_IDX(pf_id) \
200 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR)
201 #define I40E_FD_SB_STAT_IDX(pf_id) \
202 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_SB)
203 #define I40E_FD_ATR_TUNNEL_STAT_IDX(pf_id) \
204 (I40E_FD_STAT_PF_IDX(pf_id) + I40E_FD_STAT_ATR_TUNNEL)
205
206 /* The following structure contains the data parsed from the user-defined
207 * field of the ethtool_rx_flow_spec structure.
208 */
209 struct i40e_rx_flow_userdef {
210 bool flex_filter;
211 u16 flex_word;
212 u16 flex_offset;
213 };
214
215 struct i40e_fdir_filter {
216 struct hlist_node fdir_node;
217 /* filter ipnut set */
218 u8 flow_type;
219 u8 ip4_proto;
220 /* TX packet view of src and dst */
221 __be32 dst_ip;
222 __be32 src_ip;
223 __be16 src_port;
224 __be16 dst_port;
225 __be32 sctp_v_tag;
226
227 /* Flexible data to match within the packet payload */
228 __be16 flex_word;
229 u16 flex_offset;
230 bool flex_filter;
231
232 /* filter control */
233 u16 q_index;
234 u8 flex_off;
235 u8 pctype;
236 u16 dest_vsi;
237 u8 dest_ctl;
238 u8 fd_status;
239 u16 cnt_index;
240 u32 fd_id;
241 };
242
243 #define I40E_CLOUD_FIELD_OMAC 0x01
244 #define I40E_CLOUD_FIELD_IMAC 0x02
245 #define I40E_CLOUD_FIELD_IVLAN 0x04
246 #define I40E_CLOUD_FIELD_TEN_ID 0x08
247 #define I40E_CLOUD_FIELD_IIP 0x10
248
249 #define I40E_CLOUD_FILTER_FLAGS_OMAC I40E_CLOUD_FIELD_OMAC
250 #define I40E_CLOUD_FILTER_FLAGS_IMAC I40E_CLOUD_FIELD_IMAC
251 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN (I40E_CLOUD_FIELD_IMAC | \
252 I40E_CLOUD_FIELD_IVLAN)
253 #define I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
254 I40E_CLOUD_FIELD_TEN_ID)
255 #define I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC (I40E_CLOUD_FIELD_OMAC | \
256 I40E_CLOUD_FIELD_IMAC | \
257 I40E_CLOUD_FIELD_TEN_ID)
258 #define I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID (I40E_CLOUD_FIELD_IMAC | \
259 I40E_CLOUD_FIELD_IVLAN | \
260 I40E_CLOUD_FIELD_TEN_ID)
261 #define I40E_CLOUD_FILTER_FLAGS_IIP I40E_CLOUD_FIELD_IIP
262
263 struct i40e_cloud_filter {
264 struct hlist_node cloud_node;
265 unsigned long cookie;
266 /* cloud filter input set follows */
267 u8 dst_mac[ETH_ALEN];
268 u8 src_mac[ETH_ALEN];
269 __be16 vlan_id;
270 u16 seid; /* filter control */
271 __be16 dst_port;
272 __be16 src_port;
273 u32 tenant_id;
274 union {
275 struct {
276 struct in_addr dst_ip;
277 struct in_addr src_ip;
278 } v4;
279 struct {
280 struct in6_addr dst_ip6;
281 struct in6_addr src_ip6;
282 } v6;
283 } ip;
284 #define dst_ipv6 ip.v6.dst_ip6.s6_addr32
285 #define src_ipv6 ip.v6.src_ip6.s6_addr32
286 #define dst_ipv4 ip.v4.dst_ip.s_addr
287 #define src_ipv4 ip.v4.src_ip.s_addr
288 u16 n_proto; /* Ethernet Protocol */
289 u8 ip_proto; /* IPPROTO value */
290 u8 flags;
291 #define I40E_CLOUD_TNL_TYPE_NONE 0xff
292 u8 tunnel_type;
293 };
294
295 #define I40E_ETH_P_LLDP 0x88cc
296
297 #define I40E_DCB_PRIO_TYPE_STRICT 0
298 #define I40E_DCB_PRIO_TYPE_ETS 1
299 #define I40E_DCB_STRICT_PRIO_CREDITS 127
300 /* DCB per TC information data structure */
301 struct i40e_tc_info {
302 u16 qoffset; /* Queue offset from base queue */
303 u16 qcount; /* Total Queues */
304 u8 netdev_tc; /* Netdev TC index if netdev associated */
305 };
306
307 /* TC configuration data structure */
308 struct i40e_tc_configuration {
309 u8 numtc; /* Total number of enabled TCs */
310 u8 enabled_tc; /* TC map */
311 struct i40e_tc_info tc_info[I40E_MAX_TRAFFIC_CLASS];
312 };
313
314 #define I40E_UDP_PORT_INDEX_UNUSED 255
315 struct i40e_udp_port_config {
316 /* AdminQ command interface expects port number in Host byte order */
317 u16 port;
318 u8 type;
319 u8 filter_index;
320 };
321
322 /* macros related to FLX_PIT */
323 #define I40E_FLEX_SET_FSIZE(fsize) (((fsize) << \
324 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
325 I40E_PRTQF_FLX_PIT_FSIZE_MASK)
326 #define I40E_FLEX_SET_DST_WORD(dst) (((dst) << \
327 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
328 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK)
329 #define I40E_FLEX_SET_SRC_WORD(src) (((src) << \
330 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
331 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK)
332 #define I40E_FLEX_PREP_VAL(dst, fsize, src) (I40E_FLEX_SET_DST_WORD(dst) | \
333 I40E_FLEX_SET_FSIZE(fsize) | \
334 I40E_FLEX_SET_SRC_WORD(src))
335
336 #define I40E_FLEX_PIT_GET_SRC(flex) (((flex) & \
337 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) >> \
338 I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT)
339 #define I40E_FLEX_PIT_GET_DST(flex) (((flex) & \
340 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK) >> \
341 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT)
342 #define I40E_FLEX_PIT_GET_FSIZE(flex) (((flex) & \
343 I40E_PRTQF_FLX_PIT_FSIZE_MASK) >> \
344 I40E_PRTQF_FLX_PIT_FSIZE_SHIFT)
345
346 #define I40E_MAX_FLEX_SRC_OFFSET 0x1F
347
348 /* macros related to GLQF_ORT */
349 #define I40E_ORT_SET_IDX(idx) (((idx) << \
350 I40E_GLQF_ORT_PIT_INDX_SHIFT) & \
351 I40E_GLQF_ORT_PIT_INDX_MASK)
352
353 #define I40E_ORT_SET_COUNT(count) (((count) << \
354 I40E_GLQF_ORT_FIELD_CNT_SHIFT) & \
355 I40E_GLQF_ORT_FIELD_CNT_MASK)
356
357 #define I40E_ORT_SET_PAYLOAD(payload) (((payload) << \
358 I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) & \
359 I40E_GLQF_ORT_FLX_PAYLOAD_MASK)
360
361 #define I40E_ORT_PREP_VAL(idx, count, payload) (I40E_ORT_SET_IDX(idx) | \
362 I40E_ORT_SET_COUNT(count) | \
363 I40E_ORT_SET_PAYLOAD(payload))
364
365 #define I40E_L3_GLQF_ORT_IDX 34
366 #define I40E_L4_GLQF_ORT_IDX 35
367
368 /* Flex PIT register index */
369 #define I40E_FLEX_PIT_IDX_START_L2 0
370 #define I40E_FLEX_PIT_IDX_START_L3 3
371 #define I40E_FLEX_PIT_IDX_START_L4 6
372
373 #define I40E_FLEX_PIT_TABLE_SIZE 3
374
375 #define I40E_FLEX_DEST_UNUSED 63
376
377 #define I40E_FLEX_INDEX_ENTRIES 8
378
379 /* Flex MASK to disable all flexible entries */
380 #define I40E_FLEX_INPUT_MASK (I40E_FLEX_50_MASK | I40E_FLEX_51_MASK | \
381 I40E_FLEX_52_MASK | I40E_FLEX_53_MASK | \
382 I40E_FLEX_54_MASK | I40E_FLEX_55_MASK | \
383 I40E_FLEX_56_MASK | I40E_FLEX_57_MASK)
384
385 struct i40e_flex_pit {
386 struct list_head list;
387 u16 src_offset;
388 u8 pit_index;
389 };
390
391 struct i40e_channel {
392 struct list_head list;
393 bool initialized;
394 u8 type;
395 u16 vsi_number; /* Assigned VSI number from AQ 'Add VSI' response */
396 u16 stat_counter_idx;
397 u16 base_queue;
398 u16 num_queue_pairs; /* Requested by user */
399 u16 seid;
400
401 u8 enabled_tc;
402 struct i40e_aqc_vsi_properties_data info;
403
404 u64 max_tx_rate;
405
406 /* track this channel belongs to which VSI */
407 struct i40e_vsi *parent_vsi;
408 };
409
410 /* struct that defines the Ethernet device */
411 struct i40e_pf {
412 struct pci_dev *pdev;
413 struct i40e_hw hw;
414 DECLARE_BITMAP(state, __I40E_STATE_SIZE__);
415 struct msix_entry *msix_entries;
416 bool fc_autoneg_status;
417
418 u16 eeprom_version;
419 u16 num_vmdq_vsis; /* num vmdq vsis this PF has set up */
420 u16 num_vmdq_qps; /* num queue pairs per vmdq pool */
421 u16 num_vmdq_msix; /* num queue vectors per vmdq pool */
422 u16 num_req_vfs; /* num VFs requested for this PF */
423 u16 num_vf_qps; /* num queue pairs per VF */
424 u16 num_lan_qps; /* num lan queues this PF has set up */
425 u16 num_lan_msix; /* num queue vectors for the base PF vsi */
426 u16 num_fdsb_msix; /* num queue vectors for sideband Fdir */
427 u16 num_iwarp_msix; /* num of iwarp vectors for this PF */
428 int iwarp_base_vector;
429 int queues_left; /* queues left unclaimed */
430 u16 alloc_rss_size; /* allocated RSS queues */
431 u16 rss_size_max; /* HW defined max RSS queues */
432 u16 fdir_pf_filter_count; /* num of guaranteed filters for this PF */
433 u16 num_alloc_vsi; /* num VSIs this driver supports */
434 u8 atr_sample_rate;
435 bool wol_en;
436
437 struct hlist_head fdir_filter_list;
438 u16 fdir_pf_active_filters;
439 unsigned long fd_flush_timestamp;
440 u32 fd_flush_cnt;
441 u32 fd_add_err;
442 u32 fd_atr_cnt;
443
444 /* Book-keeping of side-band filter count per flow-type.
445 * This is used to detect and handle input set changes for
446 * respective flow-type.
447 */
448 u16 fd_tcp4_filter_cnt;
449 u16 fd_udp4_filter_cnt;
450 u16 fd_sctp4_filter_cnt;
451 u16 fd_ip4_filter_cnt;
452
453 /* Flexible filter table values that need to be programmed into
454 * hardware, which expects L3 and L4 to be programmed separately. We
455 * need to ensure that the values are in ascended order and don't have
456 * duplicates, so we track each L3 and L4 values in separate lists.
457 */
458 struct list_head l3_flex_pit_list;
459 struct list_head l4_flex_pit_list;
460
461 struct i40e_udp_port_config udp_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
462 u16 pending_udp_bitmap;
463
464 struct hlist_head cloud_filter_list;
465 u16 num_cloud_filters;
466
467 enum i40e_interrupt_policy int_policy;
468 u16 rx_itr_default;
469 u16 tx_itr_default;
470 u32 msg_enable;
471 char int_name[I40E_INT_NAME_STR_LEN];
472 u16 adminq_work_limit; /* num of admin receive queue desc to process */
473 unsigned long service_timer_period;
474 unsigned long service_timer_previous;
475 struct timer_list service_timer;
476 struct work_struct service_task;
477
478 u32 hw_features;
479 #define I40E_HW_RSS_AQ_CAPABLE BIT(0)
480 #define I40E_HW_128_QP_RSS_CAPABLE BIT(1)
481 #define I40E_HW_ATR_EVICT_CAPABLE BIT(2)
482 #define I40E_HW_WB_ON_ITR_CAPABLE BIT(3)
483 #define I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE BIT(4)
484 #define I40E_HW_NO_PCI_LINK_CHECK BIT(5)
485 #define I40E_HW_100M_SGMII_CAPABLE BIT(6)
486 #define I40E_HW_NO_DCB_SUPPORT BIT(7)
487 #define I40E_HW_USE_SET_LLDP_MIB BIT(8)
488 #define I40E_HW_GENEVE_OFFLOAD_CAPABLE BIT(9)
489 #define I40E_HW_PTP_L4_CAPABLE BIT(10)
490 #define I40E_HW_WOL_MC_MAGIC_PKT_WAKE BIT(11)
491 #define I40E_HW_MPLS_HDR_OFFLOAD_CAPABLE BIT(12)
492 #define I40E_HW_HAVE_CRT_RETIMER BIT(13)
493 #define I40E_HW_OUTER_UDP_CSUM_CAPABLE BIT(14)
494 #define I40E_HW_PHY_CONTROLS_LEDS BIT(15)
495 #define I40E_HW_STOP_FW_LLDP BIT(16)
496 #define I40E_HW_PORT_ID_VALID BIT(17)
497 #define I40E_HW_RESTART_AUTONEG BIT(18)
498 #define I40E_HW_STOPPABLE_FW_LLDP BIT(19)
499
500 u32 flags;
501 #define I40E_FLAG_RX_CSUM_ENABLED BIT(0)
502 #define I40E_FLAG_MSI_ENABLED BIT(1)
503 #define I40E_FLAG_MSIX_ENABLED BIT(2)
504 #define I40E_FLAG_RSS_ENABLED BIT(3)
505 #define I40E_FLAG_VMDQ_ENABLED BIT(4)
506 #define I40E_FLAG_SRIOV_ENABLED BIT(5)
507 #define I40E_FLAG_DCB_CAPABLE BIT(6)
508 #define I40E_FLAG_DCB_ENABLED BIT(7)
509 #define I40E_FLAG_FD_SB_ENABLED BIT(8)
510 #define I40E_FLAG_FD_ATR_ENABLED BIT(9)
511 #define I40E_FLAG_MFP_ENABLED BIT(10)
512 #define I40E_FLAG_HW_ATR_EVICT_ENABLED BIT(11)
513 #define I40E_FLAG_VEB_MODE_ENABLED BIT(12)
514 #define I40E_FLAG_VEB_STATS_ENABLED BIT(13)
515 #define I40E_FLAG_LINK_POLLING_ENABLED BIT(14)
516 #define I40E_FLAG_TRUE_PROMISC_SUPPORT BIT(15)
517 #define I40E_FLAG_LEGACY_RX BIT(16)
518 #define I40E_FLAG_PTP BIT(17)
519 #define I40E_FLAG_IWARP_ENABLED BIT(18)
520 #define I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED BIT(19)
521 #define I40E_FLAG_SOURCE_PRUNING_DISABLED BIT(20)
522 #define I40E_FLAG_TC_MQPRIO BIT(21)
523 #define I40E_FLAG_FD_SB_INACTIVE BIT(22)
524 #define I40E_FLAG_FD_SB_TO_CLOUD_FILTER BIT(23)
525 #define I40E_FLAG_DISABLE_FW_LLDP BIT(24)
526
527 struct i40e_client_instance *cinst;
528 bool stat_offsets_loaded;
529 struct i40e_hw_port_stats stats;
530 struct i40e_hw_port_stats stats_offsets;
531 u32 tx_timeout_count;
532 u32 tx_timeout_recovery_level;
533 unsigned long tx_timeout_last_recovery;
534 u32 tx_sluggish_count;
535 u32 hw_csum_rx_error;
536 u32 led_status;
537 u16 corer_count; /* Core reset count */
538 u16 globr_count; /* Global reset count */
539 u16 empr_count; /* EMP reset count */
540 u16 pfr_count; /* PF reset count */
541 u16 sw_int_count; /* SW interrupt count */
542
543 struct mutex switch_mutex;
544 u16 lan_vsi; /* our default LAN VSI */
545 u16 lan_veb; /* initial relay, if exists */
546 #define I40E_NO_VEB 0xffff
547 #define I40E_NO_VSI 0xffff
548 u16 next_vsi; /* Next unallocated VSI - 0-based! */
549 struct i40e_vsi **vsi;
550 struct i40e_veb *veb[I40E_MAX_VEB];
551
552 struct i40e_lump_tracking *qp_pile;
553 struct i40e_lump_tracking *irq_pile;
554
555 /* switch config info */
556 u16 pf_seid;
557 u16 main_vsi_seid;
558 u16 mac_seid;
559 struct kobject *switch_kobj;
560 #ifdef CONFIG_DEBUG_FS
561 struct dentry *i40e_dbg_pf;
562 #endif /* CONFIG_DEBUG_FS */
563 bool cur_promisc;
564
565 u16 instance; /* A unique number per i40e_pf instance in the system */
566
567 /* sr-iov config info */
568 struct i40e_vf *vf;
569 int num_alloc_vfs; /* actual number of VFs allocated */
570 u32 vf_aq_requests;
571 u32 arq_overflows; /* Not fatal, possibly indicative of problems */
572
573 /* DCBx/DCBNL capability for PF that indicates
574 * whether DCBx is managed by firmware or host
575 * based agent (LLDPAD). Also, indicates what
576 * flavor of DCBx protocol (IEEE/CEE) is supported
577 * by the device. For now we're supporting IEEE
578 * mode only.
579 */
580 u16 dcbx_cap;
581
582 struct i40e_filter_control_settings filter_settings;
583
584 struct ptp_clock *ptp_clock;
585 struct ptp_clock_info ptp_caps;
586 struct sk_buff *ptp_tx_skb;
587 unsigned long ptp_tx_start;
588 struct hwtstamp_config tstamp_config;
589 struct mutex tmreg_lock; /* Used to protect the SYSTIME registers. */
590 u32 ptp_adj_mult;
591 u32 tx_hwtstamp_timeouts;
592 u32 tx_hwtstamp_skipped;
593 u32 rx_hwtstamp_cleared;
594 u32 latch_event_flags;
595 spinlock_t ptp_rx_lock; /* Used to protect Rx timestamp registers. */
596 unsigned long latch_events[4];
597 bool ptp_tx;
598 bool ptp_rx;
599 u16 rss_table_size; /* HW RSS table size */
600 u32 max_bw;
601 u32 min_bw;
602
603 u32 ioremap_len;
604 u32 fd_inv;
605 u16 phy_led_val;
606
607 u16 override_q_count;
608 u16 last_sw_conf_flags;
609 u16 last_sw_conf_valid_flags;
610 };
611
612 /**
613 * i40e_mac_to_hkey - Convert a 6-byte MAC Address to a u64 hash key
614 * @macaddr: the MAC Address as the base key
615 *
616 * Simply copies the address and returns it as a u64 for hashing
617 **/
i40e_addr_to_hkey(const u8 * macaddr)618 static inline u64 i40e_addr_to_hkey(const u8 *macaddr)
619 {
620 u64 key = 0;
621
622 ether_addr_copy((u8 *)&key, macaddr);
623 return key;
624 }
625
626 enum i40e_filter_state {
627 I40E_FILTER_INVALID = 0, /* Invalid state */
628 I40E_FILTER_NEW, /* New, not sent to FW yet */
629 I40E_FILTER_ACTIVE, /* Added to switch by FW */
630 I40E_FILTER_FAILED, /* Rejected by FW */
631 I40E_FILTER_REMOVE, /* To be removed */
632 /* There is no 'removed' state; the filter struct is freed */
633 };
634 struct i40e_mac_filter {
635 struct hlist_node hlist;
636 u8 macaddr[ETH_ALEN];
637 #define I40E_VLAN_ANY -1
638 s16 vlan;
639 enum i40e_filter_state state;
640 };
641
642 /* Wrapper structure to keep track of filters while we are preparing to send
643 * firmware commands. We cannot send firmware commands while holding a
644 * spinlock, since it might sleep. To avoid this, we wrap the added filters in
645 * a separate structure, which will track the state change and update the real
646 * filter while under lock. We can't simply hold the filters in a separate
647 * list, as this opens a window for a race condition when adding new MAC
648 * addresses to all VLANs, or when adding new VLANs to all MAC addresses.
649 */
650 struct i40e_new_mac_filter {
651 struct hlist_node hlist;
652 struct i40e_mac_filter *f;
653
654 /* Track future changes to state separately */
655 enum i40e_filter_state state;
656 };
657
658 struct i40e_veb {
659 struct i40e_pf *pf;
660 u16 idx;
661 u16 veb_idx; /* index of VEB parent */
662 u16 seid;
663 u16 uplink_seid;
664 u16 stats_idx; /* index of VEB parent */
665 u8 enabled_tc;
666 u16 bridge_mode; /* Bridge Mode (VEB/VEPA) */
667 u16 flags;
668 u16 bw_limit;
669 u8 bw_max_quanta;
670 bool is_abs_credits;
671 u8 bw_tc_share_credits[I40E_MAX_TRAFFIC_CLASS];
672 u16 bw_tc_limit_credits[I40E_MAX_TRAFFIC_CLASS];
673 u8 bw_tc_max_quanta[I40E_MAX_TRAFFIC_CLASS];
674 struct kobject *kobj;
675 bool stat_offsets_loaded;
676 struct i40e_eth_stats stats;
677 struct i40e_eth_stats stats_offsets;
678 struct i40e_veb_tc_stats tc_stats;
679 struct i40e_veb_tc_stats tc_stats_offsets;
680 };
681
682 /* struct that defines a VSI, associated with a dev */
683 struct i40e_vsi {
684 struct net_device *netdev;
685 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
686 bool netdev_registered;
687 bool stat_offsets_loaded;
688
689 u32 current_netdev_flags;
690 DECLARE_BITMAP(state, __I40E_VSI_STATE_SIZE__);
691 #define I40E_VSI_FLAG_FILTER_CHANGED BIT(0)
692 #define I40E_VSI_FLAG_VEB_OWNER BIT(1)
693 unsigned long flags;
694
695 /* Per VSI lock to protect elements/hash (MAC filter) */
696 spinlock_t mac_filter_hash_lock;
697 /* Fixed size hash table with 2^8 buckets for MAC filters */
698 DECLARE_HASHTABLE(mac_filter_hash, 8);
699 bool has_vlan_filter;
700
701 /* VSI stats */
702 struct rtnl_link_stats64 net_stats;
703 struct rtnl_link_stats64 net_stats_offsets;
704 struct i40e_eth_stats eth_stats;
705 struct i40e_eth_stats eth_stats_offsets;
706 u32 tx_restart;
707 u32 tx_busy;
708 u64 tx_linearize;
709 u64 tx_force_wb;
710 u32 rx_buf_failed;
711 u32 rx_page_failed;
712
713 /* These are containers of ring pointers, allocated at run-time */
714 struct i40e_ring **rx_rings;
715 struct i40e_ring **tx_rings;
716 struct i40e_ring **xdp_rings; /* XDP Tx rings */
717
718 u32 active_filters;
719 u32 promisc_threshold;
720
721 u16 work_limit;
722 u16 int_rate_limit; /* value in usecs */
723
724 u16 rss_table_size; /* HW RSS table size */
725 u16 rss_size; /* Allocated RSS queues */
726 u8 *rss_hkey_user; /* User configured hash keys */
727 u8 *rss_lut_user; /* User configured lookup table entries */
728
729
730 u16 max_frame;
731 u16 rx_buf_len;
732
733 struct bpf_prog *xdp_prog;
734
735 /* List of q_vectors allocated to this VSI */
736 struct i40e_q_vector **q_vectors;
737 int num_q_vectors;
738 int base_vector;
739 bool irqs_ready;
740
741 u16 seid; /* HW index of this VSI (absolute index) */
742 u16 id; /* VSI number */
743 u16 uplink_seid;
744
745 u16 base_queue; /* vsi's first queue in hw array */
746 u16 alloc_queue_pairs; /* Allocated Tx/Rx queues */
747 u16 req_queue_pairs; /* User requested queue pairs */
748 u16 num_queue_pairs; /* Used tx and rx pairs */
749 u16 num_desc;
750 enum i40e_vsi_type type; /* VSI type, e.g., LAN, FCoE, etc */
751 s16 vf_id; /* Virtual function ID for SRIOV VSIs */
752
753 struct tc_mqprio_qopt_offload mqprio_qopt; /* queue parameters */
754 struct i40e_tc_configuration tc_config;
755 struct i40e_aqc_vsi_properties_data info;
756
757 /* VSI BW limit (absolute across all TCs) */
758 u16 bw_limit; /* VSI BW Limit (0 = disabled) */
759 u8 bw_max_quanta; /* Max Quanta when BW limit is enabled */
760
761 /* Relative TC credits across VSIs */
762 u8 bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
763 /* TC BW limit credits within VSI */
764 u16 bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
765 /* TC BW limit max quanta within VSI */
766 u8 bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
767
768 struct i40e_pf *back; /* Backreference to associated PF */
769 u16 idx; /* index in pf->vsi[] */
770 u16 veb_idx; /* index of VEB parent */
771 struct kobject *kobj; /* sysfs object */
772 bool current_isup; /* Sync 'link up' logging */
773 enum i40e_aq_link_speed current_speed; /* Sync link speed logging */
774
775 /* channel specific fields */
776 u16 cnt_q_avail; /* num of queues available for channel usage */
777 u16 orig_rss_size;
778 u16 current_rss_size;
779 bool reconfig_rss;
780
781 u16 next_base_queue; /* next queue to be used for channel setup */
782
783 struct list_head ch_list;
784 u16 tc_seid_map[I40E_MAX_TRAFFIC_CLASS];
785
786 void *priv; /* client driver data reference. */
787
788 /* VSI specific handlers */
789 irqreturn_t (*irq_handler)(int irq, void *data);
790 } ____cacheline_internodealigned_in_smp;
791
792 struct i40e_netdev_priv {
793 struct i40e_vsi *vsi;
794 };
795
796 /* struct that defines an interrupt vector */
797 struct i40e_q_vector {
798 struct i40e_vsi *vsi;
799
800 u16 v_idx; /* index in the vsi->q_vector array. */
801 u16 reg_idx; /* register index of the interrupt */
802
803 struct napi_struct napi;
804
805 struct i40e_ring_container rx;
806 struct i40e_ring_container tx;
807
808 u8 itr_countdown; /* when 0 should adjust adaptive ITR */
809 u8 num_ringpairs; /* total number of ring pairs in vector */
810
811 cpumask_t affinity_mask;
812 struct irq_affinity_notify affinity_notify;
813
814 struct rcu_head rcu; /* to avoid race with update stats on free */
815 char name[I40E_INT_NAME_STR_LEN];
816 bool arm_wb_state;
817 } ____cacheline_internodealigned_in_smp;
818
819 /* lan device */
820 struct i40e_device {
821 struct list_head list;
822 struct i40e_pf *pf;
823 };
824
825 /**
826 * i40e_nvm_version_str - format the NVM version strings
827 * @hw: ptr to the hardware info
828 **/
i40e_nvm_version_str(struct i40e_hw * hw)829 static inline char *i40e_nvm_version_str(struct i40e_hw *hw)
830 {
831 static char buf[32];
832 u32 full_ver;
833
834 full_ver = hw->nvm.oem_ver;
835
836 if (hw->nvm.eetrack == I40E_OEM_EETRACK_ID) {
837 u8 gen, snap;
838 u16 release;
839
840 gen = (u8)(full_ver >> I40E_OEM_GEN_SHIFT);
841 snap = (u8)((full_ver & I40E_OEM_SNAP_MASK) >>
842 I40E_OEM_SNAP_SHIFT);
843 release = (u16)(full_ver & I40E_OEM_RELEASE_MASK);
844
845 snprintf(buf, sizeof(buf), "%x.%x.%x", gen, snap, release);
846 } else {
847 u8 ver, patch;
848 u16 build;
849
850 ver = (u8)(full_ver >> I40E_OEM_VER_SHIFT);
851 build = (u16)((full_ver >> I40E_OEM_VER_BUILD_SHIFT) &
852 I40E_OEM_VER_BUILD_MASK);
853 patch = (u8)(full_ver & I40E_OEM_VER_PATCH_MASK);
854
855 snprintf(buf, sizeof(buf),
856 "%x.%02x 0x%x %d.%d.%d",
857 (hw->nvm.version & I40E_NVM_VERSION_HI_MASK) >>
858 I40E_NVM_VERSION_HI_SHIFT,
859 (hw->nvm.version & I40E_NVM_VERSION_LO_MASK) >>
860 I40E_NVM_VERSION_LO_SHIFT,
861 hw->nvm.eetrack, ver, build, patch);
862 }
863
864 return buf;
865 }
866
867 /**
868 * i40e_netdev_to_pf: Retrieve the PF struct for given netdev
869 * @netdev: the corresponding netdev
870 *
871 * Return the PF struct for the given netdev
872 **/
i40e_netdev_to_pf(struct net_device * netdev)873 static inline struct i40e_pf *i40e_netdev_to_pf(struct net_device *netdev)
874 {
875 struct i40e_netdev_priv *np = netdev_priv(netdev);
876 struct i40e_vsi *vsi = np->vsi;
877
878 return vsi->back;
879 }
880
i40e_vsi_setup_irqhandler(struct i40e_vsi * vsi,irqreturn_t (* irq_handler)(int,void *))881 static inline void i40e_vsi_setup_irqhandler(struct i40e_vsi *vsi,
882 irqreturn_t (*irq_handler)(int, void *))
883 {
884 vsi->irq_handler = irq_handler;
885 }
886
887 /**
888 * i40e_get_fd_cnt_all - get the total FD filter space available
889 * @pf: pointer to the PF struct
890 **/
i40e_get_fd_cnt_all(struct i40e_pf * pf)891 static inline int i40e_get_fd_cnt_all(struct i40e_pf *pf)
892 {
893 return pf->hw.fdir_shared_filter_count + pf->fdir_pf_filter_count;
894 }
895
896 /**
897 * i40e_read_fd_input_set - reads value of flow director input set register
898 * @pf: pointer to the PF struct
899 * @addr: register addr
900 *
901 * This function reads value of flow director input set register
902 * specified by 'addr' (which is specific to flow-type)
903 **/
i40e_read_fd_input_set(struct i40e_pf * pf,u16 addr)904 static inline u64 i40e_read_fd_input_set(struct i40e_pf *pf, u16 addr)
905 {
906 u64 val;
907
908 val = i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1));
909 val <<= 32;
910 val += i40e_read_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0));
911
912 return val;
913 }
914
915 /**
916 * i40e_write_fd_input_set - writes value into flow director input set register
917 * @pf: pointer to the PF struct
918 * @addr: register addr
919 * @val: value to be written
920 *
921 * This function writes specified value to the register specified by 'addr'.
922 * This register is input set register based on flow-type.
923 **/
i40e_write_fd_input_set(struct i40e_pf * pf,u16 addr,u64 val)924 static inline void i40e_write_fd_input_set(struct i40e_pf *pf,
925 u16 addr, u64 val)
926 {
927 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 1),
928 (u32)(val >> 32));
929 i40e_write_rx_ctl(&pf->hw, I40E_PRTQF_FD_INSET(addr, 0),
930 (u32)(val & 0xFFFFFFFFULL));
931 }
932
933 /* needed by i40e_ethtool.c */
934 int i40e_up(struct i40e_vsi *vsi);
935 void i40e_down(struct i40e_vsi *vsi);
936 extern const char i40e_driver_name[];
937 extern const char i40e_driver_version_str[];
938 void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags);
939 void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired);
940 int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
941 int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size);
942 void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
943 u16 rss_table_size, u16 rss_size);
944 struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id);
945 /**
946 * i40e_find_vsi_by_type - Find and return Flow Director VSI
947 * @pf: PF to search for VSI
948 * @type: Value indicating type of VSI we are looking for
949 **/
950 static inline struct i40e_vsi *
i40e_find_vsi_by_type(struct i40e_pf * pf,u16 type)951 i40e_find_vsi_by_type(struct i40e_pf *pf, u16 type)
952 {
953 int i;
954
955 for (i = 0; i < pf->num_alloc_vsi; i++) {
956 struct i40e_vsi *vsi = pf->vsi[i];
957
958 if (vsi && vsi->type == type)
959 return vsi;
960 }
961
962 return NULL;
963 }
964 void i40e_update_stats(struct i40e_vsi *vsi);
965 void i40e_update_eth_stats(struct i40e_vsi *vsi);
966 struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi);
967 int i40e_fetch_switch_configuration(struct i40e_pf *pf,
968 bool printconfig);
969
970 int i40e_add_del_fdir(struct i40e_vsi *vsi,
971 struct i40e_fdir_filter *input, bool add);
972 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
973 u32 i40e_get_current_fd_count(struct i40e_pf *pf);
974 u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
975 u32 i40e_get_current_atr_cnt(struct i40e_pf *pf);
976 u32 i40e_get_global_fd_count(struct i40e_pf *pf);
977 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
978 void i40e_set_ethtool_ops(struct net_device *netdev);
979 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
980 const u8 *macaddr, s16 vlan);
981 void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f);
982 void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan);
983 int i40e_sync_vsi_filters(struct i40e_vsi *vsi);
984 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
985 u16 uplink, u32 param1);
986 int i40e_vsi_release(struct i40e_vsi *vsi);
987 void i40e_service_event_schedule(struct i40e_pf *pf);
988 void i40e_notify_client_of_vf_msg(struct i40e_vsi *vsi, u32 vf_id,
989 u8 *msg, u16 len);
990
991 int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q, bool is_xdp,
992 bool enable);
993 int i40e_control_wait_rx_q(struct i40e_pf *pf, int pf_q, bool enable);
994 int i40e_vsi_start_rings(struct i40e_vsi *vsi);
995 void i40e_vsi_stop_rings(struct i40e_vsi *vsi);
996 void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi);
997 int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi);
998 int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count);
999 struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags, u16 uplink_seid,
1000 u16 downlink_seid, u8 enabled_tc);
1001 void i40e_veb_release(struct i40e_veb *veb);
1002
1003 int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc);
1004 int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid);
1005 void i40e_vsi_remove_pvid(struct i40e_vsi *vsi);
1006 void i40e_vsi_reset_stats(struct i40e_vsi *vsi);
1007 void i40e_pf_reset_stats(struct i40e_pf *pf);
1008 #ifdef CONFIG_DEBUG_FS
1009 void i40e_dbg_pf_init(struct i40e_pf *pf);
1010 void i40e_dbg_pf_exit(struct i40e_pf *pf);
1011 void i40e_dbg_init(void);
1012 void i40e_dbg_exit(void);
1013 #else
i40e_dbg_pf_init(struct i40e_pf * pf)1014 static inline void i40e_dbg_pf_init(struct i40e_pf *pf) {}
i40e_dbg_pf_exit(struct i40e_pf * pf)1015 static inline void i40e_dbg_pf_exit(struct i40e_pf *pf) {}
i40e_dbg_init(void)1016 static inline void i40e_dbg_init(void) {}
i40e_dbg_exit(void)1017 static inline void i40e_dbg_exit(void) {}
1018 #endif /* CONFIG_DEBUG_FS*/
1019 /* needed by client drivers */
1020 int i40e_lan_add_device(struct i40e_pf *pf);
1021 int i40e_lan_del_device(struct i40e_pf *pf);
1022 void i40e_client_subtask(struct i40e_pf *pf);
1023 void i40e_notify_client_of_l2_param_changes(struct i40e_vsi *vsi);
1024 void i40e_notify_client_of_netdev_close(struct i40e_vsi *vsi, bool reset);
1025 void i40e_notify_client_of_vf_enable(struct i40e_pf *pf, u32 num_vfs);
1026 void i40e_notify_client_of_vf_reset(struct i40e_pf *pf, u32 vf_id);
1027 void i40e_client_update_msix_info(struct i40e_pf *pf);
1028 int i40e_vf_client_capable(struct i40e_pf *pf, u32 vf_id);
1029 /**
1030 * i40e_irq_dynamic_enable - Enable default interrupt generation settings
1031 * @vsi: pointer to a vsi
1032 * @vector: enable a particular Hw Interrupt vector, without base_vector
1033 **/
i40e_irq_dynamic_enable(struct i40e_vsi * vsi,int vector)1034 static inline void i40e_irq_dynamic_enable(struct i40e_vsi *vsi, int vector)
1035 {
1036 struct i40e_pf *pf = vsi->back;
1037 struct i40e_hw *hw = &pf->hw;
1038 u32 val;
1039
1040 val = I40E_PFINT_DYN_CTLN_INTENA_MASK |
1041 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1042 (I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
1043 wr32(hw, I40E_PFINT_DYN_CTLN(vector + vsi->base_vector - 1), val);
1044 /* skip the flush */
1045 }
1046
1047 void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf);
1048 void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf);
1049 int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd);
1050 int i40e_open(struct net_device *netdev);
1051 int i40e_close(struct net_device *netdev);
1052 int i40e_vsi_open(struct i40e_vsi *vsi);
1053 void i40e_vlan_stripping_disable(struct i40e_vsi *vsi);
1054 int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1055 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid);
1056 void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid);
1057 void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid);
1058 struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1059 const u8 *macaddr);
1060 int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr);
1061 bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi);
1062 struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr);
1063 void i40e_vlan_stripping_enable(struct i40e_vsi *vsi);
1064 #ifdef CONFIG_I40E_DCB
1065 void i40e_dcbnl_flush_apps(struct i40e_pf *pf,
1066 struct i40e_dcbx_config *old_cfg,
1067 struct i40e_dcbx_config *new_cfg);
1068 void i40e_dcbnl_set_all(struct i40e_vsi *vsi);
1069 void i40e_dcbnl_setup(struct i40e_vsi *vsi);
1070 bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
1071 struct i40e_dcbx_config *old_cfg,
1072 struct i40e_dcbx_config *new_cfg);
1073 #endif /* CONFIG_I40E_DCB */
1074 void i40e_ptp_rx_hang(struct i40e_pf *pf);
1075 void i40e_ptp_tx_hang(struct i40e_pf *pf);
1076 void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf);
1077 void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index);
1078 void i40e_ptp_set_increment(struct i40e_pf *pf);
1079 int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1080 int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr);
1081 void i40e_ptp_init(struct i40e_pf *pf);
1082 void i40e_ptp_stop(struct i40e_pf *pf);
1083 int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi);
1084 i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf);
1085 i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf);
1086 i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf);
1087 void i40e_print_link_message(struct i40e_vsi *vsi, bool isup);
1088
i40e_enabled_xdp_vsi(struct i40e_vsi * vsi)1089 static inline bool i40e_enabled_xdp_vsi(struct i40e_vsi *vsi)
1090 {
1091 return !!vsi->xdp_prog;
1092 }
1093
1094 int i40e_create_queue_channel(struct i40e_vsi *vsi, struct i40e_channel *ch);
1095 int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate);
1096 int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
1097 struct i40e_cloud_filter *filter,
1098 bool add);
1099 int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
1100 struct i40e_cloud_filter *filter,
1101 bool add);
1102 #endif /* _I40E_H_ */
1103