1 /*
2 * r8169.c: RealTek 8169/8168/8101 ethernet driver.
3 *
4 * Copyright (c) 2002 ShuChen <shuchen@realtek.com.tw>
5 * Copyright (c) 2003 - 2007 Francois Romieu <romieu@fr.zoreil.com>
6 * Copyright (c) a lot of people too. Please respect their work.
7 *
8 * See MAINTAINERS file for support contact information.
9 */
10
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/netdevice.h>
15 #include <linux/etherdevice.h>
16 #include <linux/clk.h>
17 #include <linux/delay.h>
18 #include <linux/ethtool.h>
19 #include <linux/phy.h>
20 #include <linux/if_vlan.h>
21 #include <linux/crc32.h>
22 #include <linux/in.h>
23 #include <linux/io.h>
24 #include <linux/ip.h>
25 #include <linux/tcp.h>
26 #include <linux/interrupt.h>
27 #include <linux/dma-mapping.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware.h>
30 #include <linux/prefetch.h>
31 #include <linux/pci-aspm.h>
32 #include <linux/ipv6.h>
33 #include <net/ip6_checksum.h>
34
35 #define MODULENAME "r8169"
36
37 #define FIRMWARE_8168D_1 "rtl_nic/rtl8168d-1.fw"
38 #define FIRMWARE_8168D_2 "rtl_nic/rtl8168d-2.fw"
39 #define FIRMWARE_8168E_1 "rtl_nic/rtl8168e-1.fw"
40 #define FIRMWARE_8168E_2 "rtl_nic/rtl8168e-2.fw"
41 #define FIRMWARE_8168E_3 "rtl_nic/rtl8168e-3.fw"
42 #define FIRMWARE_8168F_1 "rtl_nic/rtl8168f-1.fw"
43 #define FIRMWARE_8168F_2 "rtl_nic/rtl8168f-2.fw"
44 #define FIRMWARE_8105E_1 "rtl_nic/rtl8105e-1.fw"
45 #define FIRMWARE_8402_1 "rtl_nic/rtl8402-1.fw"
46 #define FIRMWARE_8411_1 "rtl_nic/rtl8411-1.fw"
47 #define FIRMWARE_8411_2 "rtl_nic/rtl8411-2.fw"
48 #define FIRMWARE_8106E_1 "rtl_nic/rtl8106e-1.fw"
49 #define FIRMWARE_8106E_2 "rtl_nic/rtl8106e-2.fw"
50 #define FIRMWARE_8168G_2 "rtl_nic/rtl8168g-2.fw"
51 #define FIRMWARE_8168G_3 "rtl_nic/rtl8168g-3.fw"
52 #define FIRMWARE_8168H_1 "rtl_nic/rtl8168h-1.fw"
53 #define FIRMWARE_8168H_2 "rtl_nic/rtl8168h-2.fw"
54 #define FIRMWARE_8107E_1 "rtl_nic/rtl8107e-1.fw"
55 #define FIRMWARE_8107E_2 "rtl_nic/rtl8107e-2.fw"
56
57 #define R8169_MSG_DEFAULT \
58 (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN)
59
60 #define TX_SLOTS_AVAIL(tp) \
61 (tp->dirty_tx + NUM_TX_DESC - tp->cur_tx)
62
63 /* A skbuff with nr_frags needs nr_frags+1 entries in the tx queue */
64 #define TX_FRAGS_READY_FOR(tp,nr_frags) \
65 (TX_SLOTS_AVAIL(tp) >= (nr_frags + 1))
66
67 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
68 The RTL chips use a 64 element hash table based on the Ethernet CRC. */
69 static const int multicast_filter_limit = 32;
70
71 #define TX_DMA_BURST 7 /* Maximum PCI burst, '7' is unlimited */
72 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
73
74 #define R8169_REGS_SIZE 256
75 #define R8169_RX_BUF_SIZE (SZ_16K - 1)
76 #define NUM_TX_DESC 64 /* Number of Tx descriptor registers */
77 #define NUM_RX_DESC 256U /* Number of Rx descriptor registers */
78 #define R8169_TX_RING_BYTES (NUM_TX_DESC * sizeof(struct TxDesc))
79 #define R8169_RX_RING_BYTES (NUM_RX_DESC * sizeof(struct RxDesc))
80
81 #define RTL8169_TX_TIMEOUT (6*HZ)
82
83 /* write/read MMIO register */
84 #define RTL_W8(tp, reg, val8) writeb((val8), tp->mmio_addr + (reg))
85 #define RTL_W16(tp, reg, val16) writew((val16), tp->mmio_addr + (reg))
86 #define RTL_W32(tp, reg, val32) writel((val32), tp->mmio_addr + (reg))
87 #define RTL_R8(tp, reg) readb(tp->mmio_addr + (reg))
88 #define RTL_R16(tp, reg) readw(tp->mmio_addr + (reg))
89 #define RTL_R32(tp, reg) readl(tp->mmio_addr + (reg))
90
91 enum mac_version {
92 RTL_GIGA_MAC_VER_01 = 0,
93 RTL_GIGA_MAC_VER_02,
94 RTL_GIGA_MAC_VER_03,
95 RTL_GIGA_MAC_VER_04,
96 RTL_GIGA_MAC_VER_05,
97 RTL_GIGA_MAC_VER_06,
98 RTL_GIGA_MAC_VER_07,
99 RTL_GIGA_MAC_VER_08,
100 RTL_GIGA_MAC_VER_09,
101 RTL_GIGA_MAC_VER_10,
102 RTL_GIGA_MAC_VER_11,
103 RTL_GIGA_MAC_VER_12,
104 RTL_GIGA_MAC_VER_13,
105 RTL_GIGA_MAC_VER_14,
106 RTL_GIGA_MAC_VER_15,
107 RTL_GIGA_MAC_VER_16,
108 RTL_GIGA_MAC_VER_17,
109 RTL_GIGA_MAC_VER_18,
110 RTL_GIGA_MAC_VER_19,
111 RTL_GIGA_MAC_VER_20,
112 RTL_GIGA_MAC_VER_21,
113 RTL_GIGA_MAC_VER_22,
114 RTL_GIGA_MAC_VER_23,
115 RTL_GIGA_MAC_VER_24,
116 RTL_GIGA_MAC_VER_25,
117 RTL_GIGA_MAC_VER_26,
118 RTL_GIGA_MAC_VER_27,
119 RTL_GIGA_MAC_VER_28,
120 RTL_GIGA_MAC_VER_29,
121 RTL_GIGA_MAC_VER_30,
122 RTL_GIGA_MAC_VER_31,
123 RTL_GIGA_MAC_VER_32,
124 RTL_GIGA_MAC_VER_33,
125 RTL_GIGA_MAC_VER_34,
126 RTL_GIGA_MAC_VER_35,
127 RTL_GIGA_MAC_VER_36,
128 RTL_GIGA_MAC_VER_37,
129 RTL_GIGA_MAC_VER_38,
130 RTL_GIGA_MAC_VER_39,
131 RTL_GIGA_MAC_VER_40,
132 RTL_GIGA_MAC_VER_41,
133 RTL_GIGA_MAC_VER_42,
134 RTL_GIGA_MAC_VER_43,
135 RTL_GIGA_MAC_VER_44,
136 RTL_GIGA_MAC_VER_45,
137 RTL_GIGA_MAC_VER_46,
138 RTL_GIGA_MAC_VER_47,
139 RTL_GIGA_MAC_VER_48,
140 RTL_GIGA_MAC_VER_49,
141 RTL_GIGA_MAC_VER_50,
142 RTL_GIGA_MAC_VER_51,
143 RTL_GIGA_MAC_NONE = 0xff,
144 };
145
146 #define JUMBO_1K ETH_DATA_LEN
147 #define JUMBO_4K (4*1024 - ETH_HLEN - 2)
148 #define JUMBO_6K (6*1024 - ETH_HLEN - 2)
149 #define JUMBO_7K (7*1024 - ETH_HLEN - 2)
150 #define JUMBO_9K (9*1024 - ETH_HLEN - 2)
151
152 static const struct {
153 const char *name;
154 const char *fw_name;
155 } rtl_chip_infos[] = {
156 /* PCI devices. */
157 [RTL_GIGA_MAC_VER_01] = {"RTL8169" },
158 [RTL_GIGA_MAC_VER_02] = {"RTL8169s" },
159 [RTL_GIGA_MAC_VER_03] = {"RTL8110s" },
160 [RTL_GIGA_MAC_VER_04] = {"RTL8169sb/8110sb" },
161 [RTL_GIGA_MAC_VER_05] = {"RTL8169sc/8110sc" },
162 [RTL_GIGA_MAC_VER_06] = {"RTL8169sc/8110sc" },
163 /* PCI-E devices. */
164 [RTL_GIGA_MAC_VER_07] = {"RTL8102e" },
165 [RTL_GIGA_MAC_VER_08] = {"RTL8102e" },
166 [RTL_GIGA_MAC_VER_09] = {"RTL8102e" },
167 [RTL_GIGA_MAC_VER_10] = {"RTL8101e" },
168 [RTL_GIGA_MAC_VER_11] = {"RTL8168b/8111b" },
169 [RTL_GIGA_MAC_VER_12] = {"RTL8168b/8111b" },
170 [RTL_GIGA_MAC_VER_13] = {"RTL8101e" },
171 [RTL_GIGA_MAC_VER_14] = {"RTL8100e" },
172 [RTL_GIGA_MAC_VER_15] = {"RTL8100e" },
173 [RTL_GIGA_MAC_VER_16] = {"RTL8101e" },
174 [RTL_GIGA_MAC_VER_17] = {"RTL8168b/8111b" },
175 [RTL_GIGA_MAC_VER_18] = {"RTL8168cp/8111cp" },
176 [RTL_GIGA_MAC_VER_19] = {"RTL8168c/8111c" },
177 [RTL_GIGA_MAC_VER_20] = {"RTL8168c/8111c" },
178 [RTL_GIGA_MAC_VER_21] = {"RTL8168c/8111c" },
179 [RTL_GIGA_MAC_VER_22] = {"RTL8168c/8111c" },
180 [RTL_GIGA_MAC_VER_23] = {"RTL8168cp/8111cp" },
181 [RTL_GIGA_MAC_VER_24] = {"RTL8168cp/8111cp" },
182 [RTL_GIGA_MAC_VER_25] = {"RTL8168d/8111d", FIRMWARE_8168D_1},
183 [RTL_GIGA_MAC_VER_26] = {"RTL8168d/8111d", FIRMWARE_8168D_2},
184 [RTL_GIGA_MAC_VER_27] = {"RTL8168dp/8111dp" },
185 [RTL_GIGA_MAC_VER_28] = {"RTL8168dp/8111dp" },
186 [RTL_GIGA_MAC_VER_29] = {"RTL8105e", FIRMWARE_8105E_1},
187 [RTL_GIGA_MAC_VER_30] = {"RTL8105e", FIRMWARE_8105E_1},
188 [RTL_GIGA_MAC_VER_31] = {"RTL8168dp/8111dp" },
189 [RTL_GIGA_MAC_VER_32] = {"RTL8168e/8111e", FIRMWARE_8168E_1},
190 [RTL_GIGA_MAC_VER_33] = {"RTL8168e/8111e", FIRMWARE_8168E_2},
191 [RTL_GIGA_MAC_VER_34] = {"RTL8168evl/8111evl", FIRMWARE_8168E_3},
192 [RTL_GIGA_MAC_VER_35] = {"RTL8168f/8111f", FIRMWARE_8168F_1},
193 [RTL_GIGA_MAC_VER_36] = {"RTL8168f/8111f", FIRMWARE_8168F_2},
194 [RTL_GIGA_MAC_VER_37] = {"RTL8402", FIRMWARE_8402_1 },
195 [RTL_GIGA_MAC_VER_38] = {"RTL8411", FIRMWARE_8411_1 },
196 [RTL_GIGA_MAC_VER_39] = {"RTL8106e", FIRMWARE_8106E_1},
197 [RTL_GIGA_MAC_VER_40] = {"RTL8168g/8111g", FIRMWARE_8168G_2},
198 [RTL_GIGA_MAC_VER_41] = {"RTL8168g/8111g" },
199 [RTL_GIGA_MAC_VER_42] = {"RTL8168g/8111g", FIRMWARE_8168G_3},
200 [RTL_GIGA_MAC_VER_43] = {"RTL8106e", FIRMWARE_8106E_2},
201 [RTL_GIGA_MAC_VER_44] = {"RTL8411", FIRMWARE_8411_2 },
202 [RTL_GIGA_MAC_VER_45] = {"RTL8168h/8111h", FIRMWARE_8168H_1},
203 [RTL_GIGA_MAC_VER_46] = {"RTL8168h/8111h", FIRMWARE_8168H_2},
204 [RTL_GIGA_MAC_VER_47] = {"RTL8107e", FIRMWARE_8107E_1},
205 [RTL_GIGA_MAC_VER_48] = {"RTL8107e", FIRMWARE_8107E_2},
206 [RTL_GIGA_MAC_VER_49] = {"RTL8168ep/8111ep" },
207 [RTL_GIGA_MAC_VER_50] = {"RTL8168ep/8111ep" },
208 [RTL_GIGA_MAC_VER_51] = {"RTL8168ep/8111ep" },
209 };
210
211 enum cfg_version {
212 RTL_CFG_0 = 0x00,
213 RTL_CFG_1,
214 RTL_CFG_2
215 };
216
217 static const struct pci_device_id rtl8169_pci_tbl[] = {
218 { PCI_VDEVICE(REALTEK, 0x2502), RTL_CFG_1 },
219 { PCI_VDEVICE(REALTEK, 0x2600), RTL_CFG_1 },
220 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8129), 0, 0, RTL_CFG_0 },
221 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8136), 0, 0, RTL_CFG_2 },
222 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8161), 0, 0, RTL_CFG_1 },
223 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8167), 0, 0, RTL_CFG_0 },
224 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8168), 0, 0, RTL_CFG_1 },
225 { PCI_DEVICE(PCI_VENDOR_ID_NCUBE, 0x8168), 0, 0, RTL_CFG_1 },
226 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8169), 0, 0, RTL_CFG_0 },
227 { PCI_VENDOR_ID_DLINK, 0x4300,
228 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0, RTL_CFG_1 },
229 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4300), 0, 0, RTL_CFG_0 },
230 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4302), 0, 0, RTL_CFG_0 },
231 { PCI_DEVICE(PCI_VENDOR_ID_AT, 0xc107), 0, 0, RTL_CFG_0 },
232 { PCI_DEVICE(PCI_VENDOR_ID_USR, 0x0116), 0, 0, RTL_CFG_0 },
233 { PCI_VENDOR_ID_LINKSYS, 0x1032,
234 PCI_ANY_ID, 0x0024, 0, 0, RTL_CFG_0 },
235 { 0x0001, 0x8168,
236 PCI_ANY_ID, 0x2410, 0, 0, RTL_CFG_2 },
237 {0,},
238 };
239
240 MODULE_DEVICE_TABLE(pci, rtl8169_pci_tbl);
241
242 static int use_dac = -1;
243 static struct {
244 u32 msg_enable;
245 } debug = { -1 };
246
247 enum rtl_registers {
248 MAC0 = 0, /* Ethernet hardware address. */
249 MAC4 = 4,
250 MAR0 = 8, /* Multicast filter. */
251 CounterAddrLow = 0x10,
252 CounterAddrHigh = 0x14,
253 TxDescStartAddrLow = 0x20,
254 TxDescStartAddrHigh = 0x24,
255 TxHDescStartAddrLow = 0x28,
256 TxHDescStartAddrHigh = 0x2c,
257 FLASH = 0x30,
258 ERSR = 0x36,
259 ChipCmd = 0x37,
260 TxPoll = 0x38,
261 IntrMask = 0x3c,
262 IntrStatus = 0x3e,
263
264 TxConfig = 0x40,
265 #define TXCFG_AUTO_FIFO (1 << 7) /* 8111e-vl */
266 #define TXCFG_EMPTY (1 << 11) /* 8111e-vl */
267
268 RxConfig = 0x44,
269 #define RX128_INT_EN (1 << 15) /* 8111c and later */
270 #define RX_MULTI_EN (1 << 14) /* 8111c only */
271 #define RXCFG_FIFO_SHIFT 13
272 /* No threshold before first PCI xfer */
273 #define RX_FIFO_THRESH (7 << RXCFG_FIFO_SHIFT)
274 #define RX_EARLY_OFF (1 << 11)
275 #define RXCFG_DMA_SHIFT 8
276 /* Unlimited maximum PCI burst. */
277 #define RX_DMA_BURST (7 << RXCFG_DMA_SHIFT)
278
279 RxMissed = 0x4c,
280 Cfg9346 = 0x50,
281 Config0 = 0x51,
282 Config1 = 0x52,
283 Config2 = 0x53,
284 #define PME_SIGNAL (1 << 5) /* 8168c and later */
285
286 Config3 = 0x54,
287 Config4 = 0x55,
288 Config5 = 0x56,
289 MultiIntr = 0x5c,
290 PHYAR = 0x60,
291 PHYstatus = 0x6c,
292 RxMaxSize = 0xda,
293 CPlusCmd = 0xe0,
294 IntrMitigate = 0xe2,
295
296 #define RTL_COALESCE_MASK 0x0f
297 #define RTL_COALESCE_SHIFT 4
298 #define RTL_COALESCE_T_MAX (RTL_COALESCE_MASK)
299 #define RTL_COALESCE_FRAME_MAX (RTL_COALESCE_MASK << 2)
300
301 RxDescAddrLow = 0xe4,
302 RxDescAddrHigh = 0xe8,
303 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
304
305 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
306
307 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
308
309 #define TxPacketMax (8064 >> 7)
310 #define EarlySize 0x27
311
312 FuncEvent = 0xf0,
313 FuncEventMask = 0xf4,
314 FuncPresetState = 0xf8,
315 IBCR0 = 0xf8,
316 IBCR2 = 0xf9,
317 IBIMR0 = 0xfa,
318 IBISR0 = 0xfb,
319 FuncForceEvent = 0xfc,
320 };
321
322 enum rtl8168_8101_registers {
323 CSIDR = 0x64,
324 CSIAR = 0x68,
325 #define CSIAR_FLAG 0x80000000
326 #define CSIAR_WRITE_CMD 0x80000000
327 #define CSIAR_BYTE_ENABLE 0x0000f000
328 #define CSIAR_ADDR_MASK 0x00000fff
329 PMCH = 0x6f,
330 EPHYAR = 0x80,
331 #define EPHYAR_FLAG 0x80000000
332 #define EPHYAR_WRITE_CMD 0x80000000
333 #define EPHYAR_REG_MASK 0x1f
334 #define EPHYAR_REG_SHIFT 16
335 #define EPHYAR_DATA_MASK 0xffff
336 DLLPR = 0xd0,
337 #define PFM_EN (1 << 6)
338 #define TX_10M_PS_EN (1 << 7)
339 DBG_REG = 0xd1,
340 #define FIX_NAK_1 (1 << 4)
341 #define FIX_NAK_2 (1 << 3)
342 TWSI = 0xd2,
343 MCU = 0xd3,
344 #define NOW_IS_OOB (1 << 7)
345 #define TX_EMPTY (1 << 5)
346 #define RX_EMPTY (1 << 4)
347 #define RXTX_EMPTY (TX_EMPTY | RX_EMPTY)
348 #define EN_NDP (1 << 3)
349 #define EN_OOB_RESET (1 << 2)
350 #define LINK_LIST_RDY (1 << 1)
351 EFUSEAR = 0xdc,
352 #define EFUSEAR_FLAG 0x80000000
353 #define EFUSEAR_WRITE_CMD 0x80000000
354 #define EFUSEAR_READ_CMD 0x00000000
355 #define EFUSEAR_REG_MASK 0x03ff
356 #define EFUSEAR_REG_SHIFT 8
357 #define EFUSEAR_DATA_MASK 0xff
358 MISC_1 = 0xf2,
359 #define PFM_D3COLD_EN (1 << 6)
360 };
361
362 enum rtl8168_registers {
363 LED_FREQ = 0x1a,
364 EEE_LED = 0x1b,
365 ERIDR = 0x70,
366 ERIAR = 0x74,
367 #define ERIAR_FLAG 0x80000000
368 #define ERIAR_WRITE_CMD 0x80000000
369 #define ERIAR_READ_CMD 0x00000000
370 #define ERIAR_ADDR_BYTE_ALIGN 4
371 #define ERIAR_TYPE_SHIFT 16
372 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
373 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
374 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
375 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
376 #define ERIAR_MASK_SHIFT 12
377 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
378 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
379 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
380 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
381 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
382 EPHY_RXER_NUM = 0x7c,
383 OCPDR = 0xb0, /* OCP GPHY access */
384 #define OCPDR_WRITE_CMD 0x80000000
385 #define OCPDR_READ_CMD 0x00000000
386 #define OCPDR_REG_MASK 0x7f
387 #define OCPDR_GPHY_REG_SHIFT 16
388 #define OCPDR_DATA_MASK 0xffff
389 OCPAR = 0xb4,
390 #define OCPAR_FLAG 0x80000000
391 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
392 #define OCPAR_GPHY_READ_CMD 0x0000f060
393 GPHY_OCP = 0xb8,
394 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
395 MISC = 0xf0, /* 8168e only. */
396 #define TXPLA_RST (1 << 29)
397 #define DISABLE_LAN_EN (1 << 23) /* Enable GPIO pin */
398 #define PWM_EN (1 << 22)
399 #define RXDV_GATED_EN (1 << 19)
400 #define EARLY_TALLY_EN (1 << 16)
401 };
402
403 enum rtl_register_content {
404 /* InterruptStatusBits */
405 SYSErr = 0x8000,
406 PCSTimeout = 0x4000,
407 SWInt = 0x0100,
408 TxDescUnavail = 0x0080,
409 RxFIFOOver = 0x0040,
410 LinkChg = 0x0020,
411 RxOverflow = 0x0010,
412 TxErr = 0x0008,
413 TxOK = 0x0004,
414 RxErr = 0x0002,
415 RxOK = 0x0001,
416
417 /* RxStatusDesc */
418 RxBOVF = (1 << 24),
419 RxFOVF = (1 << 23),
420 RxRWT = (1 << 22),
421 RxRES = (1 << 21),
422 RxRUNT = (1 << 20),
423 RxCRC = (1 << 19),
424
425 /* ChipCmdBits */
426 StopReq = 0x80,
427 CmdReset = 0x10,
428 CmdRxEnb = 0x08,
429 CmdTxEnb = 0x04,
430 RxBufEmpty = 0x01,
431
432 /* TXPoll register p.5 */
433 HPQ = 0x80, /* Poll cmd on the high prio queue */
434 NPQ = 0x40, /* Poll cmd on the low prio queue */
435 FSWInt = 0x01, /* Forced software interrupt */
436
437 /* Cfg9346Bits */
438 Cfg9346_Lock = 0x00,
439 Cfg9346_Unlock = 0xc0,
440
441 /* rx_mode_bits */
442 AcceptErr = 0x20,
443 AcceptRunt = 0x10,
444 AcceptBroadcast = 0x08,
445 AcceptMulticast = 0x04,
446 AcceptMyPhys = 0x02,
447 AcceptAllPhys = 0x01,
448 #define RX_CONFIG_ACCEPT_MASK 0x3f
449
450 /* TxConfigBits */
451 TxInterFrameGapShift = 24,
452 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
453
454 /* Config1 register p.24 */
455 LEDS1 = (1 << 7),
456 LEDS0 = (1 << 6),
457 Speed_down = (1 << 4),
458 MEMMAP = (1 << 3),
459 IOMAP = (1 << 2),
460 VPD = (1 << 1),
461 PMEnable = (1 << 0), /* Power Management Enable */
462
463 /* Config2 register p. 25 */
464 ClkReqEn = (1 << 7), /* Clock Request Enable */
465 MSIEnable = (1 << 5), /* 8169 only. Reserved in the 8168. */
466 PCI_Clock_66MHz = 0x01,
467 PCI_Clock_33MHz = 0x00,
468
469 /* Config3 register p.25 */
470 MagicPacket = (1 << 5), /* Wake up when receives a Magic Packet */
471 LinkUp = (1 << 4), /* Wake up when the cable connection is re-established */
472 Jumbo_En0 = (1 << 2), /* 8168 only. Reserved in the 8168b */
473 Rdy_to_L23 = (1 << 1), /* L23 Enable */
474 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
475
476 /* Config4 register */
477 Jumbo_En1 = (1 << 1), /* 8168 only. Reserved in the 8168b */
478
479 /* Config5 register p.27 */
480 BWF = (1 << 6), /* Accept Broadcast wakeup frame */
481 MWF = (1 << 5), /* Accept Multicast wakeup frame */
482 UWF = (1 << 4), /* Accept Unicast wakeup frame */
483 Spi_en = (1 << 3),
484 LanWake = (1 << 1), /* LanWake enable/disable */
485 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
486 ASPM_en = (1 << 0), /* ASPM enable */
487
488 /* CPlusCmd p.31 */
489 EnableBist = (1 << 15), // 8168 8101
490 Mac_dbgo_oe = (1 << 14), // 8168 8101
491 Normal_mode = (1 << 13), // unused
492 Force_half_dup = (1 << 12), // 8168 8101
493 Force_rxflow_en = (1 << 11), // 8168 8101
494 Force_txflow_en = (1 << 10), // 8168 8101
495 Cxpl_dbg_sel = (1 << 9), // 8168 8101
496 ASF = (1 << 8), // 8168 8101
497 PktCntrDisable = (1 << 7), // 8168 8101
498 Mac_dbgo_sel = 0x001c, // 8168
499 RxVlan = (1 << 6),
500 RxChkSum = (1 << 5),
501 PCIDAC = (1 << 4),
502 PCIMulRW = (1 << 3),
503 #define INTT_MASK GENMASK(1, 0)
504 INTT_0 = 0x0000, // 8168
505 INTT_1 = 0x0001, // 8168
506 INTT_2 = 0x0002, // 8168
507 INTT_3 = 0x0003, // 8168
508
509 /* rtl8169_PHYstatus */
510 TBI_Enable = 0x80,
511 TxFlowCtrl = 0x40,
512 RxFlowCtrl = 0x20,
513 _1000bpsF = 0x10,
514 _100bps = 0x08,
515 _10bps = 0x04,
516 LinkStatus = 0x02,
517 FullDup = 0x01,
518
519 /* _TBICSRBit */
520 TBILinkOK = 0x02000000,
521
522 /* ResetCounterCommand */
523 CounterReset = 0x1,
524
525 /* DumpCounterCommand */
526 CounterDump = 0x8,
527
528 /* magic enable v2 */
529 MagicPacket_v2 = (1 << 16), /* Wake up when receives a Magic Packet */
530 };
531
532 enum rtl_desc_bit {
533 /* First doubleword. */
534 DescOwn = (1 << 31), /* Descriptor is owned by NIC */
535 RingEnd = (1 << 30), /* End of descriptor ring */
536 FirstFrag = (1 << 29), /* First segment of a packet */
537 LastFrag = (1 << 28), /* Final segment of a packet */
538 };
539
540 /* Generic case. */
541 enum rtl_tx_desc_bit {
542 /* First doubleword. */
543 TD_LSO = (1 << 27), /* Large Send Offload */
544 #define TD_MSS_MAX 0x07ffu /* MSS value */
545
546 /* Second doubleword. */
547 TxVlanTag = (1 << 17), /* Add VLAN tag */
548 };
549
550 /* 8169, 8168b and 810x except 8102e. */
551 enum rtl_tx_desc_bit_0 {
552 /* First doubleword. */
553 #define TD0_MSS_SHIFT 16 /* MSS position (11 bits) */
554 TD0_TCP_CS = (1 << 16), /* Calculate TCP/IP checksum */
555 TD0_UDP_CS = (1 << 17), /* Calculate UDP/IP checksum */
556 TD0_IP_CS = (1 << 18), /* Calculate IP checksum */
557 };
558
559 /* 8102e, 8168c and beyond. */
560 enum rtl_tx_desc_bit_1 {
561 /* First doubleword. */
562 TD1_GTSENV4 = (1 << 26), /* Giant Send for IPv4 */
563 TD1_GTSENV6 = (1 << 25), /* Giant Send for IPv6 */
564 #define GTTCPHO_SHIFT 18
565 #define GTTCPHO_MAX 0x7fU
566
567 /* Second doubleword. */
568 #define TCPHO_SHIFT 18
569 #define TCPHO_MAX 0x3ffU
570 #define TD1_MSS_SHIFT 18 /* MSS position (11 bits) */
571 TD1_IPv6_CS = (1 << 28), /* Calculate IPv6 checksum */
572 TD1_IPv4_CS = (1 << 29), /* Calculate IPv4 checksum */
573 TD1_TCP_CS = (1 << 30), /* Calculate TCP/IP checksum */
574 TD1_UDP_CS = (1 << 31), /* Calculate UDP/IP checksum */
575 };
576
577 enum rtl_rx_desc_bit {
578 /* Rx private */
579 PID1 = (1 << 18), /* Protocol ID bit 1/2 */
580 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
581
582 #define RxProtoUDP (PID1)
583 #define RxProtoTCP (PID0)
584 #define RxProtoIP (PID1 | PID0)
585 #define RxProtoMask RxProtoIP
586
587 IPFail = (1 << 16), /* IP checksum failed */
588 UDPFail = (1 << 15), /* UDP/IP checksum failed */
589 TCPFail = (1 << 14), /* TCP/IP checksum failed */
590 RxVlanTag = (1 << 16), /* VLAN tag available */
591 };
592
593 #define RsvdMask 0x3fffc000
594 #define CPCMD_QUIRK_MASK (Normal_mode | RxVlan | RxChkSum | INTT_MASK)
595
596 struct TxDesc {
597 __le32 opts1;
598 __le32 opts2;
599 __le64 addr;
600 };
601
602 struct RxDesc {
603 __le32 opts1;
604 __le32 opts2;
605 __le64 addr;
606 };
607
608 struct ring_info {
609 struct sk_buff *skb;
610 u32 len;
611 u8 __pad[sizeof(void *) - sizeof(u32)];
612 };
613
614 struct rtl8169_counters {
615 __le64 tx_packets;
616 __le64 rx_packets;
617 __le64 tx_errors;
618 __le32 rx_errors;
619 __le16 rx_missed;
620 __le16 align_errors;
621 __le32 tx_one_collision;
622 __le32 tx_multi_collision;
623 __le64 rx_unicast;
624 __le64 rx_broadcast;
625 __le32 rx_multicast;
626 __le16 tx_aborted;
627 __le16 tx_underun;
628 };
629
630 struct rtl8169_tc_offsets {
631 bool inited;
632 __le64 tx_errors;
633 __le32 tx_multi_collision;
634 __le16 tx_aborted;
635 };
636
637 enum rtl_flag {
638 RTL_FLAG_TASK_ENABLED = 0,
639 RTL_FLAG_TASK_SLOW_PENDING,
640 RTL_FLAG_TASK_RESET_PENDING,
641 RTL_FLAG_MAX
642 };
643
644 struct rtl8169_stats {
645 u64 packets;
646 u64 bytes;
647 struct u64_stats_sync syncp;
648 };
649
650 struct rtl8169_private {
651 void __iomem *mmio_addr; /* memory map physical address */
652 struct pci_dev *pci_dev;
653 struct net_device *dev;
654 struct napi_struct napi;
655 u32 msg_enable;
656 u16 mac_version;
657 u32 cur_rx; /* Index into the Rx descriptor buffer of next Rx pkt. */
658 u32 cur_tx; /* Index into the Tx descriptor buffer of next Rx pkt. */
659 u32 dirty_tx;
660 struct rtl8169_stats rx_stats;
661 struct rtl8169_stats tx_stats;
662 struct TxDesc *TxDescArray; /* 256-aligned Tx descriptor ring */
663 struct RxDesc *RxDescArray; /* 256-aligned Rx descriptor ring */
664 dma_addr_t TxPhyAddr;
665 dma_addr_t RxPhyAddr;
666 void *Rx_databuff[NUM_RX_DESC]; /* Rx data buffers */
667 struct ring_info tx_skb[NUM_TX_DESC]; /* Tx data buffers */
668 u16 cp_cmd;
669
670 u16 event_slow;
671 const struct rtl_coalesce_info *coalesce_info;
672 struct clk *clk;
673
674 struct mdio_ops {
675 void (*write)(struct rtl8169_private *, int, int);
676 int (*read)(struct rtl8169_private *, int);
677 } mdio_ops;
678
679 struct jumbo_ops {
680 void (*enable)(struct rtl8169_private *);
681 void (*disable)(struct rtl8169_private *);
682 } jumbo_ops;
683
684 void (*hw_start)(struct rtl8169_private *tp);
685 bool (*tso_csum)(struct rtl8169_private *, struct sk_buff *, u32 *);
686
687 struct {
688 DECLARE_BITMAP(flags, RTL_FLAG_MAX);
689 struct mutex mutex;
690 struct work_struct work;
691 } wk;
692
693 unsigned supports_gmii:1;
694 struct mii_bus *mii_bus;
695 dma_addr_t counters_phys_addr;
696 struct rtl8169_counters *counters;
697 struct rtl8169_tc_offsets tc_offset;
698 u32 saved_wolopts;
699
700 struct rtl_fw {
701 const struct firmware *fw;
702
703 #define RTL_VER_SIZE 32
704
705 char version[RTL_VER_SIZE];
706
707 struct rtl_fw_phy_action {
708 __le32 *code;
709 size_t size;
710 } phy_action;
711 } *rtl_fw;
712 #define RTL_FIRMWARE_UNKNOWN ERR_PTR(-EAGAIN)
713
714 u32 ocp_base;
715 };
716
717 MODULE_AUTHOR("Realtek and the Linux r8169 crew <netdev@vger.kernel.org>");
718 MODULE_DESCRIPTION("RealTek RTL-8169 Gigabit Ethernet driver");
719 module_param(use_dac, int, 0);
720 MODULE_PARM_DESC(use_dac, "Enable PCI DAC. Unsafe on 32 bit PCI slot.");
721 module_param_named(debug, debug.msg_enable, int, 0);
722 MODULE_PARM_DESC(debug, "Debug verbosity level (0=none, ..., 16=all)");
723 MODULE_SOFTDEP("pre: realtek");
724 MODULE_LICENSE("GPL");
725 MODULE_FIRMWARE(FIRMWARE_8168D_1);
726 MODULE_FIRMWARE(FIRMWARE_8168D_2);
727 MODULE_FIRMWARE(FIRMWARE_8168E_1);
728 MODULE_FIRMWARE(FIRMWARE_8168E_2);
729 MODULE_FIRMWARE(FIRMWARE_8168E_3);
730 MODULE_FIRMWARE(FIRMWARE_8105E_1);
731 MODULE_FIRMWARE(FIRMWARE_8168F_1);
732 MODULE_FIRMWARE(FIRMWARE_8168F_2);
733 MODULE_FIRMWARE(FIRMWARE_8402_1);
734 MODULE_FIRMWARE(FIRMWARE_8411_1);
735 MODULE_FIRMWARE(FIRMWARE_8411_2);
736 MODULE_FIRMWARE(FIRMWARE_8106E_1);
737 MODULE_FIRMWARE(FIRMWARE_8106E_2);
738 MODULE_FIRMWARE(FIRMWARE_8168G_2);
739 MODULE_FIRMWARE(FIRMWARE_8168G_3);
740 MODULE_FIRMWARE(FIRMWARE_8168H_1);
741 MODULE_FIRMWARE(FIRMWARE_8168H_2);
742 MODULE_FIRMWARE(FIRMWARE_8107E_1);
743 MODULE_FIRMWARE(FIRMWARE_8107E_2);
744
tp_to_dev(struct rtl8169_private * tp)745 static inline struct device *tp_to_dev(struct rtl8169_private *tp)
746 {
747 return &tp->pci_dev->dev;
748 }
749
rtl_lock_work(struct rtl8169_private * tp)750 static void rtl_lock_work(struct rtl8169_private *tp)
751 {
752 mutex_lock(&tp->wk.mutex);
753 }
754
rtl_unlock_work(struct rtl8169_private * tp)755 static void rtl_unlock_work(struct rtl8169_private *tp)
756 {
757 mutex_unlock(&tp->wk.mutex);
758 }
759
rtl_tx_performance_tweak(struct rtl8169_private * tp,u16 force)760 static void rtl_tx_performance_tweak(struct rtl8169_private *tp, u16 force)
761 {
762 pcie_capability_clear_and_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
763 PCI_EXP_DEVCTL_READRQ, force);
764 }
765
766 struct rtl_cond {
767 bool (*check)(struct rtl8169_private *);
768 const char *msg;
769 };
770
rtl_udelay(unsigned int d)771 static void rtl_udelay(unsigned int d)
772 {
773 udelay(d);
774 }
775
rtl_loop_wait(struct rtl8169_private * tp,const struct rtl_cond * c,void (* delay)(unsigned int),unsigned int d,int n,bool high)776 static bool rtl_loop_wait(struct rtl8169_private *tp, const struct rtl_cond *c,
777 void (*delay)(unsigned int), unsigned int d, int n,
778 bool high)
779 {
780 int i;
781
782 for (i = 0; i < n; i++) {
783 delay(d);
784 if (c->check(tp) == high)
785 return true;
786 }
787 netif_err(tp, drv, tp->dev, "%s == %d (loop: %d, delay: %d).\n",
788 c->msg, !high, n, d);
789 return false;
790 }
791
rtl_udelay_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)792 static bool rtl_udelay_loop_wait_high(struct rtl8169_private *tp,
793 const struct rtl_cond *c,
794 unsigned int d, int n)
795 {
796 return rtl_loop_wait(tp, c, rtl_udelay, d, n, true);
797 }
798
rtl_udelay_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)799 static bool rtl_udelay_loop_wait_low(struct rtl8169_private *tp,
800 const struct rtl_cond *c,
801 unsigned int d, int n)
802 {
803 return rtl_loop_wait(tp, c, rtl_udelay, d, n, false);
804 }
805
rtl_msleep_loop_wait_high(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)806 static bool rtl_msleep_loop_wait_high(struct rtl8169_private *tp,
807 const struct rtl_cond *c,
808 unsigned int d, int n)
809 {
810 return rtl_loop_wait(tp, c, msleep, d, n, true);
811 }
812
rtl_msleep_loop_wait_low(struct rtl8169_private * tp,const struct rtl_cond * c,unsigned int d,int n)813 static bool rtl_msleep_loop_wait_low(struct rtl8169_private *tp,
814 const struct rtl_cond *c,
815 unsigned int d, int n)
816 {
817 return rtl_loop_wait(tp, c, msleep, d, n, false);
818 }
819
820 #define DECLARE_RTL_COND(name) \
821 static bool name ## _check(struct rtl8169_private *); \
822 \
823 static const struct rtl_cond name = { \
824 .check = name ## _check, \
825 .msg = #name \
826 }; \
827 \
828 static bool name ## _check(struct rtl8169_private *tp)
829
rtl_ocp_reg_failure(struct rtl8169_private * tp,u32 reg)830 static bool rtl_ocp_reg_failure(struct rtl8169_private *tp, u32 reg)
831 {
832 if (reg & 0xffff0001) {
833 netif_err(tp, drv, tp->dev, "Invalid ocp reg %x!\n", reg);
834 return true;
835 }
836 return false;
837 }
838
DECLARE_RTL_COND(rtl_ocp_gphy_cond)839 DECLARE_RTL_COND(rtl_ocp_gphy_cond)
840 {
841 return RTL_R32(tp, GPHY_OCP) & OCPAR_FLAG;
842 }
843
r8168_phy_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)844 static void r8168_phy_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
845 {
846 if (rtl_ocp_reg_failure(tp, reg))
847 return;
848
849 RTL_W32(tp, GPHY_OCP, OCPAR_FLAG | (reg << 15) | data);
850
851 rtl_udelay_loop_wait_low(tp, &rtl_ocp_gphy_cond, 25, 10);
852 }
853
r8168_phy_ocp_read(struct rtl8169_private * tp,u32 reg)854 static u16 r8168_phy_ocp_read(struct rtl8169_private *tp, u32 reg)
855 {
856 if (rtl_ocp_reg_failure(tp, reg))
857 return 0;
858
859 RTL_W32(tp, GPHY_OCP, reg << 15);
860
861 return rtl_udelay_loop_wait_high(tp, &rtl_ocp_gphy_cond, 25, 10) ?
862 (RTL_R32(tp, GPHY_OCP) & 0xffff) : ~0;
863 }
864
r8168_mac_ocp_write(struct rtl8169_private * tp,u32 reg,u32 data)865 static void r8168_mac_ocp_write(struct rtl8169_private *tp, u32 reg, u32 data)
866 {
867 if (rtl_ocp_reg_failure(tp, reg))
868 return;
869
870 RTL_W32(tp, OCPDR, OCPAR_FLAG | (reg << 15) | data);
871 }
872
r8168_mac_ocp_read(struct rtl8169_private * tp,u32 reg)873 static u16 r8168_mac_ocp_read(struct rtl8169_private *tp, u32 reg)
874 {
875 if (rtl_ocp_reg_failure(tp, reg))
876 return 0;
877
878 RTL_W32(tp, OCPDR, reg << 15);
879
880 return RTL_R32(tp, OCPDR);
881 }
882
883 #define OCP_STD_PHY_BASE 0xa400
884
r8168g_mdio_write(struct rtl8169_private * tp,int reg,int value)885 static void r8168g_mdio_write(struct rtl8169_private *tp, int reg, int value)
886 {
887 if (reg == 0x1f) {
888 tp->ocp_base = value ? value << 4 : OCP_STD_PHY_BASE;
889 return;
890 }
891
892 if (tp->ocp_base != OCP_STD_PHY_BASE)
893 reg -= 0x10;
894
895 r8168_phy_ocp_write(tp, tp->ocp_base + reg * 2, value);
896 }
897
r8168g_mdio_read(struct rtl8169_private * tp,int reg)898 static int r8168g_mdio_read(struct rtl8169_private *tp, int reg)
899 {
900 if (tp->ocp_base != OCP_STD_PHY_BASE)
901 reg -= 0x10;
902
903 return r8168_phy_ocp_read(tp, tp->ocp_base + reg * 2);
904 }
905
mac_mcu_write(struct rtl8169_private * tp,int reg,int value)906 static void mac_mcu_write(struct rtl8169_private *tp, int reg, int value)
907 {
908 if (reg == 0x1f) {
909 tp->ocp_base = value << 4;
910 return;
911 }
912
913 r8168_mac_ocp_write(tp, tp->ocp_base + reg, value);
914 }
915
mac_mcu_read(struct rtl8169_private * tp,int reg)916 static int mac_mcu_read(struct rtl8169_private *tp, int reg)
917 {
918 return r8168_mac_ocp_read(tp, tp->ocp_base + reg);
919 }
920
DECLARE_RTL_COND(rtl_phyar_cond)921 DECLARE_RTL_COND(rtl_phyar_cond)
922 {
923 return RTL_R32(tp, PHYAR) & 0x80000000;
924 }
925
r8169_mdio_write(struct rtl8169_private * tp,int reg,int value)926 static void r8169_mdio_write(struct rtl8169_private *tp, int reg, int value)
927 {
928 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff));
929
930 rtl_udelay_loop_wait_low(tp, &rtl_phyar_cond, 25, 20);
931 /*
932 * According to hardware specs a 20us delay is required after write
933 * complete indication, but before sending next command.
934 */
935 udelay(20);
936 }
937
r8169_mdio_read(struct rtl8169_private * tp,int reg)938 static int r8169_mdio_read(struct rtl8169_private *tp, int reg)
939 {
940 int value;
941
942 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16);
943
944 value = rtl_udelay_loop_wait_high(tp, &rtl_phyar_cond, 25, 20) ?
945 RTL_R32(tp, PHYAR) & 0xffff : ~0;
946
947 /*
948 * According to hardware specs a 20us delay is required after read
949 * complete indication, but before sending next command.
950 */
951 udelay(20);
952
953 return value;
954 }
955
DECLARE_RTL_COND(rtl_ocpar_cond)956 DECLARE_RTL_COND(rtl_ocpar_cond)
957 {
958 return RTL_R32(tp, OCPAR) & OCPAR_FLAG;
959 }
960
r8168dp_1_mdio_access(struct rtl8169_private * tp,int reg,u32 data)961 static void r8168dp_1_mdio_access(struct rtl8169_private *tp, int reg, u32 data)
962 {
963 RTL_W32(tp, OCPDR, data | ((reg & OCPDR_REG_MASK) << OCPDR_GPHY_REG_SHIFT));
964 RTL_W32(tp, OCPAR, OCPAR_GPHY_WRITE_CMD);
965 RTL_W32(tp, EPHY_RXER_NUM, 0);
966
967 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 1000, 100);
968 }
969
r8168dp_1_mdio_write(struct rtl8169_private * tp,int reg,int value)970 static void r8168dp_1_mdio_write(struct rtl8169_private *tp, int reg, int value)
971 {
972 r8168dp_1_mdio_access(tp, reg,
973 OCPDR_WRITE_CMD | (value & OCPDR_DATA_MASK));
974 }
975
r8168dp_1_mdio_read(struct rtl8169_private * tp,int reg)976 static int r8168dp_1_mdio_read(struct rtl8169_private *tp, int reg)
977 {
978 r8168dp_1_mdio_access(tp, reg, OCPDR_READ_CMD);
979
980 mdelay(1);
981 RTL_W32(tp, OCPAR, OCPAR_GPHY_READ_CMD);
982 RTL_W32(tp, EPHY_RXER_NUM, 0);
983
984 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 1000, 100) ?
985 RTL_R32(tp, OCPDR) & OCPDR_DATA_MASK : ~0;
986 }
987
988 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
989
r8168dp_2_mdio_start(struct rtl8169_private * tp)990 static void r8168dp_2_mdio_start(struct rtl8169_private *tp)
991 {
992 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT);
993 }
994
r8168dp_2_mdio_stop(struct rtl8169_private * tp)995 static void r8168dp_2_mdio_stop(struct rtl8169_private *tp)
996 {
997 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT);
998 }
999
r8168dp_2_mdio_write(struct rtl8169_private * tp,int reg,int value)1000 static void r8168dp_2_mdio_write(struct rtl8169_private *tp, int reg, int value)
1001 {
1002 r8168dp_2_mdio_start(tp);
1003
1004 r8169_mdio_write(tp, reg, value);
1005
1006 r8168dp_2_mdio_stop(tp);
1007 }
1008
r8168dp_2_mdio_read(struct rtl8169_private * tp,int reg)1009 static int r8168dp_2_mdio_read(struct rtl8169_private *tp, int reg)
1010 {
1011 int value;
1012
1013 /* Work around issue with chip reporting wrong PHY ID */
1014 if (reg == MII_PHYSID2)
1015 return 0xc912;
1016
1017 r8168dp_2_mdio_start(tp);
1018
1019 value = r8169_mdio_read(tp, reg);
1020
1021 r8168dp_2_mdio_stop(tp);
1022
1023 return value;
1024 }
1025
rtl_writephy(struct rtl8169_private * tp,int location,u32 val)1026 static void rtl_writephy(struct rtl8169_private *tp, int location, u32 val)
1027 {
1028 tp->mdio_ops.write(tp, location, val);
1029 }
1030
rtl_readphy(struct rtl8169_private * tp,int location)1031 static int rtl_readphy(struct rtl8169_private *tp, int location)
1032 {
1033 return tp->mdio_ops.read(tp, location);
1034 }
1035
rtl_patchphy(struct rtl8169_private * tp,int reg_addr,int value)1036 static void rtl_patchphy(struct rtl8169_private *tp, int reg_addr, int value)
1037 {
1038 rtl_writephy(tp, reg_addr, rtl_readphy(tp, reg_addr) | value);
1039 }
1040
rtl_w0w1_phy(struct rtl8169_private * tp,int reg_addr,int p,int m)1041 static void rtl_w0w1_phy(struct rtl8169_private *tp, int reg_addr, int p, int m)
1042 {
1043 int val;
1044
1045 val = rtl_readphy(tp, reg_addr);
1046 rtl_writephy(tp, reg_addr, (val & ~m) | p);
1047 }
1048
DECLARE_RTL_COND(rtl_ephyar_cond)1049 DECLARE_RTL_COND(rtl_ephyar_cond)
1050 {
1051 return RTL_R32(tp, EPHYAR) & EPHYAR_FLAG;
1052 }
1053
rtl_ephy_write(struct rtl8169_private * tp,int reg_addr,int value)1054 static void rtl_ephy_write(struct rtl8169_private *tp, int reg_addr, int value)
1055 {
1056 RTL_W32(tp, EPHYAR, EPHYAR_WRITE_CMD | (value & EPHYAR_DATA_MASK) |
1057 (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1058
1059 rtl_udelay_loop_wait_low(tp, &rtl_ephyar_cond, 10, 100);
1060
1061 udelay(10);
1062 }
1063
rtl_ephy_read(struct rtl8169_private * tp,int reg_addr)1064 static u16 rtl_ephy_read(struct rtl8169_private *tp, int reg_addr)
1065 {
1066 RTL_W32(tp, EPHYAR, (reg_addr & EPHYAR_REG_MASK) << EPHYAR_REG_SHIFT);
1067
1068 return rtl_udelay_loop_wait_high(tp, &rtl_ephyar_cond, 10, 100) ?
1069 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0;
1070 }
1071
DECLARE_RTL_COND(rtl_eriar_cond)1072 DECLARE_RTL_COND(rtl_eriar_cond)
1073 {
1074 return RTL_R32(tp, ERIAR) & ERIAR_FLAG;
1075 }
1076
rtl_eri_write(struct rtl8169_private * tp,int addr,u32 mask,u32 val,int type)1077 static void rtl_eri_write(struct rtl8169_private *tp, int addr, u32 mask,
1078 u32 val, int type)
1079 {
1080 BUG_ON((addr & 3) || (mask == 0));
1081 RTL_W32(tp, ERIDR, val);
1082 RTL_W32(tp, ERIAR, ERIAR_WRITE_CMD | type | mask | addr);
1083
1084 rtl_udelay_loop_wait_low(tp, &rtl_eriar_cond, 100, 100);
1085 }
1086
rtl_eri_read(struct rtl8169_private * tp,int addr,int type)1087 static u32 rtl_eri_read(struct rtl8169_private *tp, int addr, int type)
1088 {
1089 RTL_W32(tp, ERIAR, ERIAR_READ_CMD | type | ERIAR_MASK_1111 | addr);
1090
1091 return rtl_udelay_loop_wait_high(tp, &rtl_eriar_cond, 100, 100) ?
1092 RTL_R32(tp, ERIDR) : ~0;
1093 }
1094
rtl_w0w1_eri(struct rtl8169_private * tp,int addr,u32 mask,u32 p,u32 m,int type)1095 static void rtl_w0w1_eri(struct rtl8169_private *tp, int addr, u32 mask, u32 p,
1096 u32 m, int type)
1097 {
1098 u32 val;
1099
1100 val = rtl_eri_read(tp, addr, type);
1101 rtl_eri_write(tp, addr, mask, (val & ~m) | p, type);
1102 }
1103
r8168dp_ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1104 static u32 r8168dp_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1105 {
1106 RTL_W32(tp, OCPAR, ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1107 return rtl_udelay_loop_wait_high(tp, &rtl_ocpar_cond, 100, 20) ?
1108 RTL_R32(tp, OCPDR) : ~0;
1109 }
1110
r8168ep_ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1111 static u32 r8168ep_ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1112 {
1113 return rtl_eri_read(tp, reg, ERIAR_OOB);
1114 }
1115
ocp_read(struct rtl8169_private * tp,u8 mask,u16 reg)1116 static u32 ocp_read(struct rtl8169_private *tp, u8 mask, u16 reg)
1117 {
1118 switch (tp->mac_version) {
1119 case RTL_GIGA_MAC_VER_27:
1120 case RTL_GIGA_MAC_VER_28:
1121 case RTL_GIGA_MAC_VER_31:
1122 return r8168dp_ocp_read(tp, mask, reg);
1123 case RTL_GIGA_MAC_VER_49:
1124 case RTL_GIGA_MAC_VER_50:
1125 case RTL_GIGA_MAC_VER_51:
1126 return r8168ep_ocp_read(tp, mask, reg);
1127 default:
1128 BUG();
1129 return ~0;
1130 }
1131 }
1132
r8168dp_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1133 static void r8168dp_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1134 u32 data)
1135 {
1136 RTL_W32(tp, OCPDR, data);
1137 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff));
1138 rtl_udelay_loop_wait_low(tp, &rtl_ocpar_cond, 100, 20);
1139 }
1140
r8168ep_ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1141 static void r8168ep_ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg,
1142 u32 data)
1143 {
1144 rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT,
1145 data, ERIAR_OOB);
1146 }
1147
ocp_write(struct rtl8169_private * tp,u8 mask,u16 reg,u32 data)1148 static void ocp_write(struct rtl8169_private *tp, u8 mask, u16 reg, u32 data)
1149 {
1150 switch (tp->mac_version) {
1151 case RTL_GIGA_MAC_VER_27:
1152 case RTL_GIGA_MAC_VER_28:
1153 case RTL_GIGA_MAC_VER_31:
1154 r8168dp_ocp_write(tp, mask, reg, data);
1155 break;
1156 case RTL_GIGA_MAC_VER_49:
1157 case RTL_GIGA_MAC_VER_50:
1158 case RTL_GIGA_MAC_VER_51:
1159 r8168ep_ocp_write(tp, mask, reg, data);
1160 break;
1161 default:
1162 BUG();
1163 break;
1164 }
1165 }
1166
rtl8168_oob_notify(struct rtl8169_private * tp,u8 cmd)1167 static void rtl8168_oob_notify(struct rtl8169_private *tp, u8 cmd)
1168 {
1169 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd, ERIAR_EXGMAC);
1170
1171 ocp_write(tp, 0x1, 0x30, 0x00000001);
1172 }
1173
1174 #define OOB_CMD_RESET 0x00
1175 #define OOB_CMD_DRIVER_START 0x05
1176 #define OOB_CMD_DRIVER_STOP 0x06
1177
rtl8168_get_ocp_reg(struct rtl8169_private * tp)1178 static u16 rtl8168_get_ocp_reg(struct rtl8169_private *tp)
1179 {
1180 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10;
1181 }
1182
DECLARE_RTL_COND(rtl_ocp_read_cond)1183 DECLARE_RTL_COND(rtl_ocp_read_cond)
1184 {
1185 u16 reg;
1186
1187 reg = rtl8168_get_ocp_reg(tp);
1188
1189 return ocp_read(tp, 0x0f, reg) & 0x00000800;
1190 }
1191
DECLARE_RTL_COND(rtl_ep_ocp_read_cond)1192 DECLARE_RTL_COND(rtl_ep_ocp_read_cond)
1193 {
1194 return ocp_read(tp, 0x0f, 0x124) & 0x00000001;
1195 }
1196
DECLARE_RTL_COND(rtl_ocp_tx_cond)1197 DECLARE_RTL_COND(rtl_ocp_tx_cond)
1198 {
1199 return RTL_R8(tp, IBISR0) & 0x20;
1200 }
1201
rtl8168ep_stop_cmac(struct rtl8169_private * tp)1202 static void rtl8168ep_stop_cmac(struct rtl8169_private *tp)
1203 {
1204 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01);
1205 rtl_msleep_loop_wait_high(tp, &rtl_ocp_tx_cond, 50, 2000);
1206 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20);
1207 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01);
1208 }
1209
rtl8168dp_driver_start(struct rtl8169_private * tp)1210 static void rtl8168dp_driver_start(struct rtl8169_private *tp)
1211 {
1212 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_START);
1213 rtl_msleep_loop_wait_high(tp, &rtl_ocp_read_cond, 10, 10);
1214 }
1215
rtl8168ep_driver_start(struct rtl8169_private * tp)1216 static void rtl8168ep_driver_start(struct rtl8169_private *tp)
1217 {
1218 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START);
1219 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1220 rtl_msleep_loop_wait_high(tp, &rtl_ep_ocp_read_cond, 10, 10);
1221 }
1222
rtl8168_driver_start(struct rtl8169_private * tp)1223 static void rtl8168_driver_start(struct rtl8169_private *tp)
1224 {
1225 switch (tp->mac_version) {
1226 case RTL_GIGA_MAC_VER_27:
1227 case RTL_GIGA_MAC_VER_28:
1228 case RTL_GIGA_MAC_VER_31:
1229 rtl8168dp_driver_start(tp);
1230 break;
1231 case RTL_GIGA_MAC_VER_49:
1232 case RTL_GIGA_MAC_VER_50:
1233 case RTL_GIGA_MAC_VER_51:
1234 rtl8168ep_driver_start(tp);
1235 break;
1236 default:
1237 BUG();
1238 break;
1239 }
1240 }
1241
rtl8168dp_driver_stop(struct rtl8169_private * tp)1242 static void rtl8168dp_driver_stop(struct rtl8169_private *tp)
1243 {
1244 rtl8168_oob_notify(tp, OOB_CMD_DRIVER_STOP);
1245 rtl_msleep_loop_wait_low(tp, &rtl_ocp_read_cond, 10, 10);
1246 }
1247
rtl8168ep_driver_stop(struct rtl8169_private * tp)1248 static void rtl8168ep_driver_stop(struct rtl8169_private *tp)
1249 {
1250 rtl8168ep_stop_cmac(tp);
1251 ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP);
1252 ocp_write(tp, 0x01, 0x30, ocp_read(tp, 0x01, 0x30) | 0x01);
1253 rtl_msleep_loop_wait_low(tp, &rtl_ep_ocp_read_cond, 10, 10);
1254 }
1255
rtl8168_driver_stop(struct rtl8169_private * tp)1256 static void rtl8168_driver_stop(struct rtl8169_private *tp)
1257 {
1258 switch (tp->mac_version) {
1259 case RTL_GIGA_MAC_VER_27:
1260 case RTL_GIGA_MAC_VER_28:
1261 case RTL_GIGA_MAC_VER_31:
1262 rtl8168dp_driver_stop(tp);
1263 break;
1264 case RTL_GIGA_MAC_VER_49:
1265 case RTL_GIGA_MAC_VER_50:
1266 case RTL_GIGA_MAC_VER_51:
1267 rtl8168ep_driver_stop(tp);
1268 break;
1269 default:
1270 BUG();
1271 break;
1272 }
1273 }
1274
r8168dp_check_dash(struct rtl8169_private * tp)1275 static bool r8168dp_check_dash(struct rtl8169_private *tp)
1276 {
1277 u16 reg = rtl8168_get_ocp_reg(tp);
1278
1279 return !!(ocp_read(tp, 0x0f, reg) & 0x00008000);
1280 }
1281
r8168ep_check_dash(struct rtl8169_private * tp)1282 static bool r8168ep_check_dash(struct rtl8169_private *tp)
1283 {
1284 return !!(ocp_read(tp, 0x0f, 0x128) & 0x00000001);
1285 }
1286
r8168_check_dash(struct rtl8169_private * tp)1287 static bool r8168_check_dash(struct rtl8169_private *tp)
1288 {
1289 switch (tp->mac_version) {
1290 case RTL_GIGA_MAC_VER_27:
1291 case RTL_GIGA_MAC_VER_28:
1292 case RTL_GIGA_MAC_VER_31:
1293 return r8168dp_check_dash(tp);
1294 case RTL_GIGA_MAC_VER_49:
1295 case RTL_GIGA_MAC_VER_50:
1296 case RTL_GIGA_MAC_VER_51:
1297 return r8168ep_check_dash(tp);
1298 default:
1299 return false;
1300 }
1301 }
1302
1303 struct exgmac_reg {
1304 u16 addr;
1305 u16 mask;
1306 u32 val;
1307 };
1308
rtl_write_exgmac_batch(struct rtl8169_private * tp,const struct exgmac_reg * r,int len)1309 static void rtl_write_exgmac_batch(struct rtl8169_private *tp,
1310 const struct exgmac_reg *r, int len)
1311 {
1312 while (len-- > 0) {
1313 rtl_eri_write(tp, r->addr, r->mask, r->val, ERIAR_EXGMAC);
1314 r++;
1315 }
1316 }
1317
DECLARE_RTL_COND(rtl_efusear_cond)1318 DECLARE_RTL_COND(rtl_efusear_cond)
1319 {
1320 return RTL_R32(tp, EFUSEAR) & EFUSEAR_FLAG;
1321 }
1322
rtl8168d_efuse_read(struct rtl8169_private * tp,int reg_addr)1323 static u8 rtl8168d_efuse_read(struct rtl8169_private *tp, int reg_addr)
1324 {
1325 RTL_W32(tp, EFUSEAR, (reg_addr & EFUSEAR_REG_MASK) << EFUSEAR_REG_SHIFT);
1326
1327 return rtl_udelay_loop_wait_high(tp, &rtl_efusear_cond, 100, 300) ?
1328 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0;
1329 }
1330
rtl_get_events(struct rtl8169_private * tp)1331 static u16 rtl_get_events(struct rtl8169_private *tp)
1332 {
1333 return RTL_R16(tp, IntrStatus);
1334 }
1335
rtl_ack_events(struct rtl8169_private * tp,u16 bits)1336 static void rtl_ack_events(struct rtl8169_private *tp, u16 bits)
1337 {
1338 RTL_W16(tp, IntrStatus, bits);
1339 mmiowb();
1340 }
1341
rtl_irq_disable(struct rtl8169_private * tp)1342 static void rtl_irq_disable(struct rtl8169_private *tp)
1343 {
1344 RTL_W16(tp, IntrMask, 0);
1345 mmiowb();
1346 }
1347
rtl_irq_enable(struct rtl8169_private * tp,u16 bits)1348 static void rtl_irq_enable(struct rtl8169_private *tp, u16 bits)
1349 {
1350 RTL_W16(tp, IntrMask, bits);
1351 }
1352
1353 #define RTL_EVENT_NAPI_RX (RxOK | RxErr)
1354 #define RTL_EVENT_NAPI_TX (TxOK | TxErr)
1355 #define RTL_EVENT_NAPI (RTL_EVENT_NAPI_RX | RTL_EVENT_NAPI_TX)
1356
rtl_irq_enable_all(struct rtl8169_private * tp)1357 static void rtl_irq_enable_all(struct rtl8169_private *tp)
1358 {
1359 rtl_irq_enable(tp, RTL_EVENT_NAPI | tp->event_slow);
1360 }
1361
rtl8169_irq_mask_and_ack(struct rtl8169_private * tp)1362 static void rtl8169_irq_mask_and_ack(struct rtl8169_private *tp)
1363 {
1364 rtl_irq_disable(tp);
1365 rtl_ack_events(tp, RTL_EVENT_NAPI | tp->event_slow);
1366 RTL_R8(tp, ChipCmd);
1367 }
1368
rtl_link_chg_patch(struct rtl8169_private * tp)1369 static void rtl_link_chg_patch(struct rtl8169_private *tp)
1370 {
1371 struct net_device *dev = tp->dev;
1372 struct phy_device *phydev = dev->phydev;
1373
1374 if (!netif_running(dev))
1375 return;
1376
1377 if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
1378 tp->mac_version == RTL_GIGA_MAC_VER_38) {
1379 if (phydev->speed == SPEED_1000) {
1380 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1381 ERIAR_EXGMAC);
1382 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1383 ERIAR_EXGMAC);
1384 } else if (phydev->speed == SPEED_100) {
1385 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1386 ERIAR_EXGMAC);
1387 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1388 ERIAR_EXGMAC);
1389 } else {
1390 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1391 ERIAR_EXGMAC);
1392 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1393 ERIAR_EXGMAC);
1394 }
1395 /* Reset packet filter */
1396 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01,
1397 ERIAR_EXGMAC);
1398 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00,
1399 ERIAR_EXGMAC);
1400 } else if (tp->mac_version == RTL_GIGA_MAC_VER_35 ||
1401 tp->mac_version == RTL_GIGA_MAC_VER_36) {
1402 if (phydev->speed == SPEED_1000) {
1403 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011,
1404 ERIAR_EXGMAC);
1405 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005,
1406 ERIAR_EXGMAC);
1407 } else {
1408 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f,
1409 ERIAR_EXGMAC);
1410 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f,
1411 ERIAR_EXGMAC);
1412 }
1413 } else if (tp->mac_version == RTL_GIGA_MAC_VER_37) {
1414 if (phydev->speed == SPEED_10) {
1415 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02,
1416 ERIAR_EXGMAC);
1417 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060,
1418 ERIAR_EXGMAC);
1419 } else {
1420 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000,
1421 ERIAR_EXGMAC);
1422 }
1423 }
1424 }
1425
1426 #define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST)
1427
__rtl8169_get_wol(struct rtl8169_private * tp)1428 static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
1429 {
1430 u8 options;
1431 u32 wolopts = 0;
1432
1433 options = RTL_R8(tp, Config1);
1434 if (!(options & PMEnable))
1435 return 0;
1436
1437 options = RTL_R8(tp, Config3);
1438 if (options & LinkUp)
1439 wolopts |= WAKE_PHY;
1440 switch (tp->mac_version) {
1441 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1442 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1443 if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
1444 wolopts |= WAKE_MAGIC;
1445 break;
1446 default:
1447 if (options & MagicPacket)
1448 wolopts |= WAKE_MAGIC;
1449 break;
1450 }
1451
1452 options = RTL_R8(tp, Config5);
1453 if (options & UWF)
1454 wolopts |= WAKE_UCAST;
1455 if (options & BWF)
1456 wolopts |= WAKE_BCAST;
1457 if (options & MWF)
1458 wolopts |= WAKE_MCAST;
1459
1460 return wolopts;
1461 }
1462
rtl8169_get_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1463 static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1464 {
1465 struct rtl8169_private *tp = netdev_priv(dev);
1466
1467 rtl_lock_work(tp);
1468 wol->supported = WAKE_ANY;
1469 wol->wolopts = tp->saved_wolopts;
1470 rtl_unlock_work(tp);
1471 }
1472
__rtl8169_set_wol(struct rtl8169_private * tp,u32 wolopts)1473 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
1474 {
1475 unsigned int i, tmp;
1476 static const struct {
1477 u32 opt;
1478 u16 reg;
1479 u8 mask;
1480 } cfg[] = {
1481 { WAKE_PHY, Config3, LinkUp },
1482 { WAKE_UCAST, Config5, UWF },
1483 { WAKE_BCAST, Config5, BWF },
1484 { WAKE_MCAST, Config5, MWF },
1485 { WAKE_ANY, Config5, LanWake },
1486 { WAKE_MAGIC, Config3, MagicPacket }
1487 };
1488 u8 options;
1489
1490 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
1491
1492 switch (tp->mac_version) {
1493 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
1494 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
1495 tmp = ARRAY_SIZE(cfg) - 1;
1496 if (wolopts & WAKE_MAGIC)
1497 rtl_w0w1_eri(tp,
1498 0x0dc,
1499 ERIAR_MASK_0100,
1500 MagicPacket_v2,
1501 0x0000,
1502 ERIAR_EXGMAC);
1503 else
1504 rtl_w0w1_eri(tp,
1505 0x0dc,
1506 ERIAR_MASK_0100,
1507 0x0000,
1508 MagicPacket_v2,
1509 ERIAR_EXGMAC);
1510 break;
1511 default:
1512 tmp = ARRAY_SIZE(cfg);
1513 break;
1514 }
1515
1516 for (i = 0; i < tmp; i++) {
1517 options = RTL_R8(tp, cfg[i].reg) & ~cfg[i].mask;
1518 if (wolopts & cfg[i].opt)
1519 options |= cfg[i].mask;
1520 RTL_W8(tp, cfg[i].reg, options);
1521 }
1522
1523 switch (tp->mac_version) {
1524 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_17:
1525 options = RTL_R8(tp, Config1) & ~PMEnable;
1526 if (wolopts)
1527 options |= PMEnable;
1528 RTL_W8(tp, Config1, options);
1529 break;
1530 default:
1531 options = RTL_R8(tp, Config2) & ~PME_SIGNAL;
1532 if (wolopts)
1533 options |= PME_SIGNAL;
1534 RTL_W8(tp, Config2, options);
1535 break;
1536 }
1537
1538 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
1539
1540 device_set_wakeup_enable(tp_to_dev(tp), wolopts);
1541 }
1542
rtl8169_set_wol(struct net_device * dev,struct ethtool_wolinfo * wol)1543 static int rtl8169_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
1544 {
1545 struct rtl8169_private *tp = netdev_priv(dev);
1546 struct device *d = tp_to_dev(tp);
1547
1548 if (wol->wolopts & ~WAKE_ANY)
1549 return -EINVAL;
1550
1551 pm_runtime_get_noresume(d);
1552
1553 rtl_lock_work(tp);
1554
1555 tp->saved_wolopts = wol->wolopts;
1556
1557 if (pm_runtime_active(d))
1558 __rtl8169_set_wol(tp, tp->saved_wolopts);
1559
1560 rtl_unlock_work(tp);
1561
1562 pm_runtime_put_noidle(d);
1563
1564 return 0;
1565 }
1566
rtl_lookup_firmware_name(struct rtl8169_private * tp)1567 static const char *rtl_lookup_firmware_name(struct rtl8169_private *tp)
1568 {
1569 return rtl_chip_infos[tp->mac_version].fw_name;
1570 }
1571
rtl8169_get_drvinfo(struct net_device * dev,struct ethtool_drvinfo * info)1572 static void rtl8169_get_drvinfo(struct net_device *dev,
1573 struct ethtool_drvinfo *info)
1574 {
1575 struct rtl8169_private *tp = netdev_priv(dev);
1576 struct rtl_fw *rtl_fw = tp->rtl_fw;
1577
1578 strlcpy(info->driver, MODULENAME, sizeof(info->driver));
1579 strlcpy(info->bus_info, pci_name(tp->pci_dev), sizeof(info->bus_info));
1580 BUILD_BUG_ON(sizeof(info->fw_version) < sizeof(rtl_fw->version));
1581 if (!IS_ERR_OR_NULL(rtl_fw))
1582 strlcpy(info->fw_version, rtl_fw->version,
1583 sizeof(info->fw_version));
1584 }
1585
rtl8169_get_regs_len(struct net_device * dev)1586 static int rtl8169_get_regs_len(struct net_device *dev)
1587 {
1588 return R8169_REGS_SIZE;
1589 }
1590
rtl8169_fix_features(struct net_device * dev,netdev_features_t features)1591 static netdev_features_t rtl8169_fix_features(struct net_device *dev,
1592 netdev_features_t features)
1593 {
1594 struct rtl8169_private *tp = netdev_priv(dev);
1595
1596 if (dev->mtu > TD_MSS_MAX)
1597 features &= ~NETIF_F_ALL_TSO;
1598
1599 if (dev->mtu > JUMBO_1K &&
1600 tp->mac_version > RTL_GIGA_MAC_VER_06)
1601 features &= ~NETIF_F_IP_CSUM;
1602
1603 return features;
1604 }
1605
rtl8169_set_features(struct net_device * dev,netdev_features_t features)1606 static int rtl8169_set_features(struct net_device *dev,
1607 netdev_features_t features)
1608 {
1609 struct rtl8169_private *tp = netdev_priv(dev);
1610 u32 rx_config;
1611
1612 rtl_lock_work(tp);
1613
1614 rx_config = RTL_R32(tp, RxConfig);
1615 if (features & NETIF_F_RXALL)
1616 rx_config |= (AcceptErr | AcceptRunt);
1617 else
1618 rx_config &= ~(AcceptErr | AcceptRunt);
1619
1620 RTL_W32(tp, RxConfig, rx_config);
1621
1622 if (features & NETIF_F_RXCSUM)
1623 tp->cp_cmd |= RxChkSum;
1624 else
1625 tp->cp_cmd &= ~RxChkSum;
1626
1627 if (features & NETIF_F_HW_VLAN_CTAG_RX)
1628 tp->cp_cmd |= RxVlan;
1629 else
1630 tp->cp_cmd &= ~RxVlan;
1631
1632 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
1633 RTL_R16(tp, CPlusCmd);
1634
1635 rtl_unlock_work(tp);
1636
1637 return 0;
1638 }
1639
rtl8169_tx_vlan_tag(struct sk_buff * skb)1640 static inline u32 rtl8169_tx_vlan_tag(struct sk_buff *skb)
1641 {
1642 return (skb_vlan_tag_present(skb)) ?
1643 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00;
1644 }
1645
rtl8169_rx_vlan_tag(struct RxDesc * desc,struct sk_buff * skb)1646 static void rtl8169_rx_vlan_tag(struct RxDesc *desc, struct sk_buff *skb)
1647 {
1648 u32 opts2 = le32_to_cpu(desc->opts2);
1649
1650 if (opts2 & RxVlanTag)
1651 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff));
1652 }
1653
rtl8169_get_regs(struct net_device * dev,struct ethtool_regs * regs,void * p)1654 static void rtl8169_get_regs(struct net_device *dev, struct ethtool_regs *regs,
1655 void *p)
1656 {
1657 struct rtl8169_private *tp = netdev_priv(dev);
1658 u32 __iomem *data = tp->mmio_addr;
1659 u32 *dw = p;
1660 int i;
1661
1662 rtl_lock_work(tp);
1663 for (i = 0; i < R8169_REGS_SIZE; i += 4)
1664 memcpy_fromio(dw++, data++, 4);
1665 rtl_unlock_work(tp);
1666 }
1667
rtl8169_get_msglevel(struct net_device * dev)1668 static u32 rtl8169_get_msglevel(struct net_device *dev)
1669 {
1670 struct rtl8169_private *tp = netdev_priv(dev);
1671
1672 return tp->msg_enable;
1673 }
1674
rtl8169_set_msglevel(struct net_device * dev,u32 value)1675 static void rtl8169_set_msglevel(struct net_device *dev, u32 value)
1676 {
1677 struct rtl8169_private *tp = netdev_priv(dev);
1678
1679 tp->msg_enable = value;
1680 }
1681
1682 static const char rtl8169_gstrings[][ETH_GSTRING_LEN] = {
1683 "tx_packets",
1684 "rx_packets",
1685 "tx_errors",
1686 "rx_errors",
1687 "rx_missed",
1688 "align_errors",
1689 "tx_single_collisions",
1690 "tx_multi_collisions",
1691 "unicast",
1692 "broadcast",
1693 "multicast",
1694 "tx_aborted",
1695 "tx_underrun",
1696 };
1697
rtl8169_get_sset_count(struct net_device * dev,int sset)1698 static int rtl8169_get_sset_count(struct net_device *dev, int sset)
1699 {
1700 switch (sset) {
1701 case ETH_SS_STATS:
1702 return ARRAY_SIZE(rtl8169_gstrings);
1703 default:
1704 return -EOPNOTSUPP;
1705 }
1706 }
1707
DECLARE_RTL_COND(rtl_counters_cond)1708 DECLARE_RTL_COND(rtl_counters_cond)
1709 {
1710 return RTL_R32(tp, CounterAddrLow) & (CounterReset | CounterDump);
1711 }
1712
rtl8169_do_counters(struct rtl8169_private * tp,u32 counter_cmd)1713 static bool rtl8169_do_counters(struct rtl8169_private *tp, u32 counter_cmd)
1714 {
1715 dma_addr_t paddr = tp->counters_phys_addr;
1716 u32 cmd;
1717
1718 RTL_W32(tp, CounterAddrHigh, (u64)paddr >> 32);
1719 RTL_R32(tp, CounterAddrHigh);
1720 cmd = (u64)paddr & DMA_BIT_MASK(32);
1721 RTL_W32(tp, CounterAddrLow, cmd);
1722 RTL_W32(tp, CounterAddrLow, cmd | counter_cmd);
1723
1724 return rtl_udelay_loop_wait_low(tp, &rtl_counters_cond, 10, 1000);
1725 }
1726
rtl8169_reset_counters(struct rtl8169_private * tp)1727 static bool rtl8169_reset_counters(struct rtl8169_private *tp)
1728 {
1729 /*
1730 * Versions prior to RTL_GIGA_MAC_VER_19 don't support resetting the
1731 * tally counters.
1732 */
1733 if (tp->mac_version < RTL_GIGA_MAC_VER_19)
1734 return true;
1735
1736 return rtl8169_do_counters(tp, CounterReset);
1737 }
1738
rtl8169_update_counters(struct rtl8169_private * tp)1739 static bool rtl8169_update_counters(struct rtl8169_private *tp)
1740 {
1741 u8 val = RTL_R8(tp, ChipCmd);
1742
1743 /*
1744 * Some chips are unable to dump tally counters when the receiver
1745 * is disabled. If 0xff chip may be in a PCI power-save state.
1746 */
1747 if (!(val & CmdRxEnb) || val == 0xff)
1748 return true;
1749
1750 return rtl8169_do_counters(tp, CounterDump);
1751 }
1752
rtl8169_init_counter_offsets(struct rtl8169_private * tp)1753 static bool rtl8169_init_counter_offsets(struct rtl8169_private *tp)
1754 {
1755 struct rtl8169_counters *counters = tp->counters;
1756 bool ret = false;
1757
1758 /*
1759 * rtl8169_init_counter_offsets is called from rtl_open. On chip
1760 * versions prior to RTL_GIGA_MAC_VER_19 the tally counters are only
1761 * reset by a power cycle, while the counter values collected by the
1762 * driver are reset at every driver unload/load cycle.
1763 *
1764 * To make sure the HW values returned by @get_stats64 match the SW
1765 * values, we collect the initial values at first open(*) and use them
1766 * as offsets to normalize the values returned by @get_stats64.
1767 *
1768 * (*) We can't call rtl8169_init_counter_offsets from rtl_init_one
1769 * for the reason stated in rtl8169_update_counters; CmdRxEnb is only
1770 * set at open time by rtl_hw_start.
1771 */
1772
1773 if (tp->tc_offset.inited)
1774 return true;
1775
1776 /* If both, reset and update fail, propagate to caller. */
1777 if (rtl8169_reset_counters(tp))
1778 ret = true;
1779
1780 if (rtl8169_update_counters(tp))
1781 ret = true;
1782
1783 tp->tc_offset.tx_errors = counters->tx_errors;
1784 tp->tc_offset.tx_multi_collision = counters->tx_multi_collision;
1785 tp->tc_offset.tx_aborted = counters->tx_aborted;
1786 tp->tc_offset.inited = true;
1787
1788 return ret;
1789 }
1790
rtl8169_get_ethtool_stats(struct net_device * dev,struct ethtool_stats * stats,u64 * data)1791 static void rtl8169_get_ethtool_stats(struct net_device *dev,
1792 struct ethtool_stats *stats, u64 *data)
1793 {
1794 struct rtl8169_private *tp = netdev_priv(dev);
1795 struct device *d = tp_to_dev(tp);
1796 struct rtl8169_counters *counters = tp->counters;
1797
1798 ASSERT_RTNL();
1799
1800 pm_runtime_get_noresume(d);
1801
1802 if (pm_runtime_active(d))
1803 rtl8169_update_counters(tp);
1804
1805 pm_runtime_put_noidle(d);
1806
1807 data[0] = le64_to_cpu(counters->tx_packets);
1808 data[1] = le64_to_cpu(counters->rx_packets);
1809 data[2] = le64_to_cpu(counters->tx_errors);
1810 data[3] = le32_to_cpu(counters->rx_errors);
1811 data[4] = le16_to_cpu(counters->rx_missed);
1812 data[5] = le16_to_cpu(counters->align_errors);
1813 data[6] = le32_to_cpu(counters->tx_one_collision);
1814 data[7] = le32_to_cpu(counters->tx_multi_collision);
1815 data[8] = le64_to_cpu(counters->rx_unicast);
1816 data[9] = le64_to_cpu(counters->rx_broadcast);
1817 data[10] = le32_to_cpu(counters->rx_multicast);
1818 data[11] = le16_to_cpu(counters->tx_aborted);
1819 data[12] = le16_to_cpu(counters->tx_underun);
1820 }
1821
rtl8169_get_strings(struct net_device * dev,u32 stringset,u8 * data)1822 static void rtl8169_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1823 {
1824 switch(stringset) {
1825 case ETH_SS_STATS:
1826 memcpy(data, *rtl8169_gstrings, sizeof(rtl8169_gstrings));
1827 break;
1828 }
1829 }
1830
1831 /*
1832 * Interrupt coalescing
1833 *
1834 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1835 * > 8169, 8168 and 810x line of chipsets
1836 *
1837 * 8169, 8168, and 8136(810x) serial chipsets support it.
1838 *
1839 * > 2 - the Tx timer unit at gigabit speed
1840 *
1841 * The unit of the timer depends on both the speed and the setting of CPlusCmd
1842 * (0xe0) bit 1 and bit 0.
1843 *
1844 * For 8169
1845 * bit[1:0] \ speed 1000M 100M 10M
1846 * 0 0 320ns 2.56us 40.96us
1847 * 0 1 2.56us 20.48us 327.7us
1848 * 1 0 5.12us 40.96us 655.4us
1849 * 1 1 10.24us 81.92us 1.31ms
1850 *
1851 * For the other
1852 * bit[1:0] \ speed 1000M 100M 10M
1853 * 0 0 5us 2.56us 40.96us
1854 * 0 1 40us 20.48us 327.7us
1855 * 1 0 80us 40.96us 655.4us
1856 * 1 1 160us 81.92us 1.31ms
1857 */
1858
1859 /* rx/tx scale factors for one particular CPlusCmd[0:1] value */
1860 struct rtl_coalesce_scale {
1861 /* Rx / Tx */
1862 u32 nsecs[2];
1863 };
1864
1865 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1866 struct rtl_coalesce_info {
1867 u32 speed;
1868 struct rtl_coalesce_scale scalev[4]; /* each CPlusCmd[0:1] case */
1869 };
1870
1871 /* produce (r,t) pairs with each being in series of *1, *8, *8*2, *8*2*2 */
1872 #define rxtx_x1822(r, t) { \
1873 {{(r), (t)}}, \
1874 {{(r)*8, (t)*8}}, \
1875 {{(r)*8*2, (t)*8*2}}, \
1876 {{(r)*8*2*2, (t)*8*2*2}}, \
1877 }
1878 static const struct rtl_coalesce_info rtl_coalesce_info_8169[] = {
1879 /* speed delays: rx00 tx00 */
1880 { SPEED_10, rxtx_x1822(40960, 40960) },
1881 { SPEED_100, rxtx_x1822( 2560, 2560) },
1882 { SPEED_1000, rxtx_x1822( 320, 320) },
1883 { 0 },
1884 };
1885
1886 static const struct rtl_coalesce_info rtl_coalesce_info_8168_8136[] = {
1887 /* speed delays: rx00 tx00 */
1888 { SPEED_10, rxtx_x1822(40960, 40960) },
1889 { SPEED_100, rxtx_x1822( 2560, 2560) },
1890 { SPEED_1000, rxtx_x1822( 5000, 5000) },
1891 { 0 },
1892 };
1893 #undef rxtx_x1822
1894
1895 /* get rx/tx scale vector corresponding to current speed */
rtl_coalesce_info(struct net_device * dev)1896 static const struct rtl_coalesce_info *rtl_coalesce_info(struct net_device *dev)
1897 {
1898 struct rtl8169_private *tp = netdev_priv(dev);
1899 struct ethtool_link_ksettings ecmd;
1900 const struct rtl_coalesce_info *ci;
1901 int rc;
1902
1903 rc = phy_ethtool_get_link_ksettings(dev, &ecmd);
1904 if (rc < 0)
1905 return ERR_PTR(rc);
1906
1907 for (ci = tp->coalesce_info; ci->speed != 0; ci++) {
1908 if (ecmd.base.speed == ci->speed) {
1909 return ci;
1910 }
1911 }
1912
1913 return ERR_PTR(-ELNRNG);
1914 }
1915
rtl_get_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)1916 static int rtl_get_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1917 {
1918 struct rtl8169_private *tp = netdev_priv(dev);
1919 const struct rtl_coalesce_info *ci;
1920 const struct rtl_coalesce_scale *scale;
1921 struct {
1922 u32 *max_frames;
1923 u32 *usecs;
1924 } coal_settings [] = {
1925 { &ec->rx_max_coalesced_frames, &ec->rx_coalesce_usecs },
1926 { &ec->tx_max_coalesced_frames, &ec->tx_coalesce_usecs }
1927 }, *p = coal_settings;
1928 int i;
1929 u16 w;
1930
1931 memset(ec, 0, sizeof(*ec));
1932
1933 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */
1934 ci = rtl_coalesce_info(dev);
1935 if (IS_ERR(ci))
1936 return PTR_ERR(ci);
1937
1938 scale = &ci->scalev[tp->cp_cmd & INTT_MASK];
1939
1940 /* read IntrMitigate and adjust according to scale */
1941 for (w = RTL_R16(tp, IntrMitigate); w; w >>= RTL_COALESCE_SHIFT, p++) {
1942 *p->max_frames = (w & RTL_COALESCE_MASK) << 2;
1943 w >>= RTL_COALESCE_SHIFT;
1944 *p->usecs = w & RTL_COALESCE_MASK;
1945 }
1946
1947 for (i = 0; i < 2; i++) {
1948 p = coal_settings + i;
1949 *p->usecs = (*p->usecs * scale->nsecs[i]) / 1000;
1950
1951 /*
1952 * ethtool_coalesce says it is illegal to set both usecs and
1953 * max_frames to 0.
1954 */
1955 if (!*p->usecs && !*p->max_frames)
1956 *p->max_frames = 1;
1957 }
1958
1959 return 0;
1960 }
1961
1962 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, nsec) */
rtl_coalesce_choose_scale(struct net_device * dev,u32 nsec,u16 * cp01)1963 static const struct rtl_coalesce_scale *rtl_coalesce_choose_scale(
1964 struct net_device *dev, u32 nsec, u16 *cp01)
1965 {
1966 const struct rtl_coalesce_info *ci;
1967 u16 i;
1968
1969 ci = rtl_coalesce_info(dev);
1970 if (IS_ERR(ci))
1971 return ERR_CAST(ci);
1972
1973 for (i = 0; i < 4; i++) {
1974 u32 rxtx_maxscale = max(ci->scalev[i].nsecs[0],
1975 ci->scalev[i].nsecs[1]);
1976 if (nsec <= rxtx_maxscale * RTL_COALESCE_T_MAX) {
1977 *cp01 = i;
1978 return &ci->scalev[i];
1979 }
1980 }
1981
1982 return ERR_PTR(-EINVAL);
1983 }
1984
rtl_set_coalesce(struct net_device * dev,struct ethtool_coalesce * ec)1985 static int rtl_set_coalesce(struct net_device *dev, struct ethtool_coalesce *ec)
1986 {
1987 struct rtl8169_private *tp = netdev_priv(dev);
1988 const struct rtl_coalesce_scale *scale;
1989 struct {
1990 u32 frames;
1991 u32 usecs;
1992 } coal_settings [] = {
1993 { ec->rx_max_coalesced_frames, ec->rx_coalesce_usecs },
1994 { ec->tx_max_coalesced_frames, ec->tx_coalesce_usecs }
1995 }, *p = coal_settings;
1996 u16 w = 0, cp01;
1997 int i;
1998
1999 scale = rtl_coalesce_choose_scale(dev,
2000 max(p[0].usecs, p[1].usecs) * 1000, &cp01);
2001 if (IS_ERR(scale))
2002 return PTR_ERR(scale);
2003
2004 for (i = 0; i < 2; i++, p++) {
2005 u32 units;
2006
2007 /*
2008 * accept max_frames=1 we returned in rtl_get_coalesce.
2009 * accept it not only when usecs=0 because of e.g. the following scenario:
2010 *
2011 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX)
2012 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1
2013 * - then user does `ethtool -C eth0 rx-usecs 100`
2014 *
2015 * since ethtool sends to kernel whole ethtool_coalesce
2016 * settings, if we do not handle rx_usecs=!0, rx_frames=1
2017 * we'll reject it below in `frames % 4 != 0`.
2018 */
2019 if (p->frames == 1) {
2020 p->frames = 0;
2021 }
2022
2023 units = p->usecs * 1000 / scale->nsecs[i];
2024 if (p->frames > RTL_COALESCE_FRAME_MAX || p->frames % 4)
2025 return -EINVAL;
2026
2027 w <<= RTL_COALESCE_SHIFT;
2028 w |= units;
2029 w <<= RTL_COALESCE_SHIFT;
2030 w |= p->frames >> 2;
2031 }
2032
2033 rtl_lock_work(tp);
2034
2035 RTL_W16(tp, IntrMitigate, swab16(w));
2036
2037 tp->cp_cmd = (tp->cp_cmd & ~INTT_MASK) | cp01;
2038 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
2039 RTL_R16(tp, CPlusCmd);
2040
2041 rtl_unlock_work(tp);
2042
2043 return 0;
2044 }
2045
2046 static const struct ethtool_ops rtl8169_ethtool_ops = {
2047 .get_drvinfo = rtl8169_get_drvinfo,
2048 .get_regs_len = rtl8169_get_regs_len,
2049 .get_link = ethtool_op_get_link,
2050 .get_coalesce = rtl_get_coalesce,
2051 .set_coalesce = rtl_set_coalesce,
2052 .get_msglevel = rtl8169_get_msglevel,
2053 .set_msglevel = rtl8169_set_msglevel,
2054 .get_regs = rtl8169_get_regs,
2055 .get_wol = rtl8169_get_wol,
2056 .set_wol = rtl8169_set_wol,
2057 .get_strings = rtl8169_get_strings,
2058 .get_sset_count = rtl8169_get_sset_count,
2059 .get_ethtool_stats = rtl8169_get_ethtool_stats,
2060 .get_ts_info = ethtool_op_get_ts_info,
2061 .nway_reset = phy_ethtool_nway_reset,
2062 .get_link_ksettings = phy_ethtool_get_link_ksettings,
2063 .set_link_ksettings = phy_ethtool_set_link_ksettings,
2064 };
2065
rtl8169_get_mac_version(struct rtl8169_private * tp,u8 default_version)2066 static void rtl8169_get_mac_version(struct rtl8169_private *tp,
2067 u8 default_version)
2068 {
2069 /*
2070 * The driver currently handles the 8168Bf and the 8168Be identically
2071 * but they can be identified more specifically through the test below
2072 * if needed:
2073 *
2074 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be
2075 *
2076 * Same thing for the 8101Eb and the 8101Ec:
2077 *
2078 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec
2079 */
2080 static const struct rtl_mac_info {
2081 u32 mask;
2082 u32 val;
2083 int mac_version;
2084 } mac_info[] = {
2085 /* 8168EP family. */
2086 { 0x7cf00000, 0x50200000, RTL_GIGA_MAC_VER_51 },
2087 { 0x7cf00000, 0x50100000, RTL_GIGA_MAC_VER_50 },
2088 { 0x7cf00000, 0x50000000, RTL_GIGA_MAC_VER_49 },
2089
2090 /* 8168H family. */
2091 { 0x7cf00000, 0x54100000, RTL_GIGA_MAC_VER_46 },
2092 { 0x7cf00000, 0x54000000, RTL_GIGA_MAC_VER_45 },
2093
2094 /* 8168G family. */
2095 { 0x7cf00000, 0x5c800000, RTL_GIGA_MAC_VER_44 },
2096 { 0x7cf00000, 0x50900000, RTL_GIGA_MAC_VER_42 },
2097 { 0x7cf00000, 0x4c100000, RTL_GIGA_MAC_VER_41 },
2098 { 0x7cf00000, 0x4c000000, RTL_GIGA_MAC_VER_40 },
2099
2100 /* 8168F family. */
2101 { 0x7c800000, 0x48800000, RTL_GIGA_MAC_VER_38 },
2102 { 0x7cf00000, 0x48100000, RTL_GIGA_MAC_VER_36 },
2103 { 0x7cf00000, 0x48000000, RTL_GIGA_MAC_VER_35 },
2104
2105 /* 8168E family. */
2106 { 0x7c800000, 0x2c800000, RTL_GIGA_MAC_VER_34 },
2107 { 0x7cf00000, 0x2c100000, RTL_GIGA_MAC_VER_32 },
2108 { 0x7c800000, 0x2c000000, RTL_GIGA_MAC_VER_33 },
2109
2110 /* 8168D family. */
2111 { 0x7cf00000, 0x28100000, RTL_GIGA_MAC_VER_25 },
2112 { 0x7c800000, 0x28000000, RTL_GIGA_MAC_VER_26 },
2113
2114 /* 8168DP family. */
2115 { 0x7cf00000, 0x28800000, RTL_GIGA_MAC_VER_27 },
2116 { 0x7cf00000, 0x28a00000, RTL_GIGA_MAC_VER_28 },
2117 { 0x7cf00000, 0x28b00000, RTL_GIGA_MAC_VER_31 },
2118
2119 /* 8168C family. */
2120 { 0x7cf00000, 0x3c900000, RTL_GIGA_MAC_VER_23 },
2121 { 0x7cf00000, 0x3c800000, RTL_GIGA_MAC_VER_18 },
2122 { 0x7c800000, 0x3c800000, RTL_GIGA_MAC_VER_24 },
2123 { 0x7cf00000, 0x3c000000, RTL_GIGA_MAC_VER_19 },
2124 { 0x7cf00000, 0x3c200000, RTL_GIGA_MAC_VER_20 },
2125 { 0x7cf00000, 0x3c300000, RTL_GIGA_MAC_VER_21 },
2126 { 0x7c800000, 0x3c000000, RTL_GIGA_MAC_VER_22 },
2127
2128 /* 8168B family. */
2129 { 0x7cf00000, 0x38000000, RTL_GIGA_MAC_VER_12 },
2130 { 0x7c800000, 0x38000000, RTL_GIGA_MAC_VER_17 },
2131 { 0x7c800000, 0x30000000, RTL_GIGA_MAC_VER_11 },
2132
2133 /* 8101 family. */
2134 { 0x7c800000, 0x44800000, RTL_GIGA_MAC_VER_39 },
2135 { 0x7c800000, 0x44000000, RTL_GIGA_MAC_VER_37 },
2136 { 0x7cf00000, 0x40900000, RTL_GIGA_MAC_VER_29 },
2137 { 0x7c800000, 0x40800000, RTL_GIGA_MAC_VER_30 },
2138 { 0x7cf00000, 0x34900000, RTL_GIGA_MAC_VER_08 },
2139 { 0x7cf00000, 0x24900000, RTL_GIGA_MAC_VER_08 },
2140 { 0x7cf00000, 0x34800000, RTL_GIGA_MAC_VER_07 },
2141 { 0x7cf00000, 0x24800000, RTL_GIGA_MAC_VER_07 },
2142 { 0x7cf00000, 0x34000000, RTL_GIGA_MAC_VER_13 },
2143 { 0x7cf00000, 0x34300000, RTL_GIGA_MAC_VER_10 },
2144 { 0x7cf00000, 0x34200000, RTL_GIGA_MAC_VER_16 },
2145 { 0x7c800000, 0x34800000, RTL_GIGA_MAC_VER_09 },
2146 { 0x7c800000, 0x24800000, RTL_GIGA_MAC_VER_09 },
2147 { 0x7c800000, 0x34000000, RTL_GIGA_MAC_VER_16 },
2148 /* FIXME: where did these entries come from ? -- FR */
2149 { 0xfc800000, 0x38800000, RTL_GIGA_MAC_VER_15 },
2150 { 0xfc800000, 0x30800000, RTL_GIGA_MAC_VER_14 },
2151
2152 /* 8110 family. */
2153 { 0xfc800000, 0x98000000, RTL_GIGA_MAC_VER_06 },
2154 { 0xfc800000, 0x18000000, RTL_GIGA_MAC_VER_05 },
2155 { 0xfc800000, 0x10000000, RTL_GIGA_MAC_VER_04 },
2156 { 0xfc800000, 0x04000000, RTL_GIGA_MAC_VER_03 },
2157 { 0xfc800000, 0x00800000, RTL_GIGA_MAC_VER_02 },
2158 { 0xfc800000, 0x00000000, RTL_GIGA_MAC_VER_01 },
2159
2160 /* Catch-all */
2161 { 0x00000000, 0x00000000, RTL_GIGA_MAC_NONE }
2162 };
2163 const struct rtl_mac_info *p = mac_info;
2164 u32 reg;
2165
2166 reg = RTL_R32(tp, TxConfig);
2167 while ((reg & p->mask) != p->val)
2168 p++;
2169 tp->mac_version = p->mac_version;
2170
2171 if (tp->mac_version == RTL_GIGA_MAC_NONE) {
2172 dev_notice(tp_to_dev(tp),
2173 "unknown MAC, using family default\n");
2174 tp->mac_version = default_version;
2175 } else if (tp->mac_version == RTL_GIGA_MAC_VER_42) {
2176 tp->mac_version = tp->supports_gmii ?
2177 RTL_GIGA_MAC_VER_42 :
2178 RTL_GIGA_MAC_VER_43;
2179 } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
2180 tp->mac_version = tp->supports_gmii ?
2181 RTL_GIGA_MAC_VER_45 :
2182 RTL_GIGA_MAC_VER_47;
2183 } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
2184 tp->mac_version = tp->supports_gmii ?
2185 RTL_GIGA_MAC_VER_46 :
2186 RTL_GIGA_MAC_VER_48;
2187 }
2188 }
2189
rtl8169_print_mac_version(struct rtl8169_private * tp)2190 static void rtl8169_print_mac_version(struct rtl8169_private *tp)
2191 {
2192 netif_dbg(tp, drv, tp->dev, "mac_version = 0x%02x\n", tp->mac_version);
2193 }
2194
2195 struct phy_reg {
2196 u16 reg;
2197 u16 val;
2198 };
2199
rtl_writephy_batch(struct rtl8169_private * tp,const struct phy_reg * regs,int len)2200 static void rtl_writephy_batch(struct rtl8169_private *tp,
2201 const struct phy_reg *regs, int len)
2202 {
2203 while (len-- > 0) {
2204 rtl_writephy(tp, regs->reg, regs->val);
2205 regs++;
2206 }
2207 }
2208
2209 #define PHY_READ 0x00000000
2210 #define PHY_DATA_OR 0x10000000
2211 #define PHY_DATA_AND 0x20000000
2212 #define PHY_BJMPN 0x30000000
2213 #define PHY_MDIO_CHG 0x40000000
2214 #define PHY_CLEAR_READCOUNT 0x70000000
2215 #define PHY_WRITE 0x80000000
2216 #define PHY_READCOUNT_EQ_SKIP 0x90000000
2217 #define PHY_COMP_EQ_SKIPN 0xa0000000
2218 #define PHY_COMP_NEQ_SKIPN 0xb0000000
2219 #define PHY_WRITE_PREVIOUS 0xc0000000
2220 #define PHY_SKIPN 0xd0000000
2221 #define PHY_DELAY_MS 0xe0000000
2222
2223 struct fw_info {
2224 u32 magic;
2225 char version[RTL_VER_SIZE];
2226 __le32 fw_start;
2227 __le32 fw_len;
2228 u8 chksum;
2229 } __packed;
2230
2231 #define FW_OPCODE_SIZE sizeof(typeof(*((struct rtl_fw_phy_action *)0)->code))
2232
rtl_fw_format_ok(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2233 static bool rtl_fw_format_ok(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2234 {
2235 const struct firmware *fw = rtl_fw->fw;
2236 struct fw_info *fw_info = (struct fw_info *)fw->data;
2237 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2238 char *version = rtl_fw->version;
2239 bool rc = false;
2240
2241 if (fw->size < FW_OPCODE_SIZE)
2242 goto out;
2243
2244 if (!fw_info->magic) {
2245 size_t i, size, start;
2246 u8 checksum = 0;
2247
2248 if (fw->size < sizeof(*fw_info))
2249 goto out;
2250
2251 for (i = 0; i < fw->size; i++)
2252 checksum += fw->data[i];
2253 if (checksum != 0)
2254 goto out;
2255
2256 start = le32_to_cpu(fw_info->fw_start);
2257 if (start > fw->size)
2258 goto out;
2259
2260 size = le32_to_cpu(fw_info->fw_len);
2261 if (size > (fw->size - start) / FW_OPCODE_SIZE)
2262 goto out;
2263
2264 memcpy(version, fw_info->version, RTL_VER_SIZE);
2265
2266 pa->code = (__le32 *)(fw->data + start);
2267 pa->size = size;
2268 } else {
2269 if (fw->size % FW_OPCODE_SIZE)
2270 goto out;
2271
2272 strlcpy(version, rtl_lookup_firmware_name(tp), RTL_VER_SIZE);
2273
2274 pa->code = (__le32 *)fw->data;
2275 pa->size = fw->size / FW_OPCODE_SIZE;
2276 }
2277 version[RTL_VER_SIZE - 1] = 0;
2278
2279 rc = true;
2280 out:
2281 return rc;
2282 }
2283
rtl_fw_data_ok(struct rtl8169_private * tp,struct net_device * dev,struct rtl_fw_phy_action * pa)2284 static bool rtl_fw_data_ok(struct rtl8169_private *tp, struct net_device *dev,
2285 struct rtl_fw_phy_action *pa)
2286 {
2287 bool rc = false;
2288 size_t index;
2289
2290 for (index = 0; index < pa->size; index++) {
2291 u32 action = le32_to_cpu(pa->code[index]);
2292 u32 regno = (action & 0x0fff0000) >> 16;
2293
2294 switch(action & 0xf0000000) {
2295 case PHY_READ:
2296 case PHY_DATA_OR:
2297 case PHY_DATA_AND:
2298 case PHY_MDIO_CHG:
2299 case PHY_CLEAR_READCOUNT:
2300 case PHY_WRITE:
2301 case PHY_WRITE_PREVIOUS:
2302 case PHY_DELAY_MS:
2303 break;
2304
2305 case PHY_BJMPN:
2306 if (regno > index) {
2307 netif_err(tp, ifup, tp->dev,
2308 "Out of range of firmware\n");
2309 goto out;
2310 }
2311 break;
2312 case PHY_READCOUNT_EQ_SKIP:
2313 if (index + 2 >= pa->size) {
2314 netif_err(tp, ifup, tp->dev,
2315 "Out of range of firmware\n");
2316 goto out;
2317 }
2318 break;
2319 case PHY_COMP_EQ_SKIPN:
2320 case PHY_COMP_NEQ_SKIPN:
2321 case PHY_SKIPN:
2322 if (index + 1 + regno >= pa->size) {
2323 netif_err(tp, ifup, tp->dev,
2324 "Out of range of firmware\n");
2325 goto out;
2326 }
2327 break;
2328
2329 default:
2330 netif_err(tp, ifup, tp->dev,
2331 "Invalid action 0x%08x\n", action);
2332 goto out;
2333 }
2334 }
2335 rc = true;
2336 out:
2337 return rc;
2338 }
2339
rtl_check_firmware(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2340 static int rtl_check_firmware(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2341 {
2342 struct net_device *dev = tp->dev;
2343 int rc = -EINVAL;
2344
2345 if (!rtl_fw_format_ok(tp, rtl_fw)) {
2346 netif_err(tp, ifup, dev, "invalid firmware\n");
2347 goto out;
2348 }
2349
2350 if (rtl_fw_data_ok(tp, dev, &rtl_fw->phy_action))
2351 rc = 0;
2352 out:
2353 return rc;
2354 }
2355
rtl_phy_write_fw(struct rtl8169_private * tp,struct rtl_fw * rtl_fw)2356 static void rtl_phy_write_fw(struct rtl8169_private *tp, struct rtl_fw *rtl_fw)
2357 {
2358 struct rtl_fw_phy_action *pa = &rtl_fw->phy_action;
2359 struct mdio_ops org, *ops = &tp->mdio_ops;
2360 u32 predata, count;
2361 size_t index;
2362
2363 predata = count = 0;
2364 org.write = ops->write;
2365 org.read = ops->read;
2366
2367 for (index = 0; index < pa->size; ) {
2368 u32 action = le32_to_cpu(pa->code[index]);
2369 u32 data = action & 0x0000ffff;
2370 u32 regno = (action & 0x0fff0000) >> 16;
2371
2372 if (!action)
2373 break;
2374
2375 switch(action & 0xf0000000) {
2376 case PHY_READ:
2377 predata = rtl_readphy(tp, regno);
2378 count++;
2379 index++;
2380 break;
2381 case PHY_DATA_OR:
2382 predata |= data;
2383 index++;
2384 break;
2385 case PHY_DATA_AND:
2386 predata &= data;
2387 index++;
2388 break;
2389 case PHY_BJMPN:
2390 index -= regno;
2391 break;
2392 case PHY_MDIO_CHG:
2393 if (data == 0) {
2394 ops->write = org.write;
2395 ops->read = org.read;
2396 } else if (data == 1) {
2397 ops->write = mac_mcu_write;
2398 ops->read = mac_mcu_read;
2399 }
2400
2401 index++;
2402 break;
2403 case PHY_CLEAR_READCOUNT:
2404 count = 0;
2405 index++;
2406 break;
2407 case PHY_WRITE:
2408 rtl_writephy(tp, regno, data);
2409 index++;
2410 break;
2411 case PHY_READCOUNT_EQ_SKIP:
2412 index += (count == data) ? 2 : 1;
2413 break;
2414 case PHY_COMP_EQ_SKIPN:
2415 if (predata == data)
2416 index += regno;
2417 index++;
2418 break;
2419 case PHY_COMP_NEQ_SKIPN:
2420 if (predata != data)
2421 index += regno;
2422 index++;
2423 break;
2424 case PHY_WRITE_PREVIOUS:
2425 rtl_writephy(tp, regno, predata);
2426 index++;
2427 break;
2428 case PHY_SKIPN:
2429 index += regno + 1;
2430 break;
2431 case PHY_DELAY_MS:
2432 mdelay(data);
2433 index++;
2434 break;
2435
2436 default:
2437 BUG();
2438 }
2439 }
2440
2441 ops->write = org.write;
2442 ops->read = org.read;
2443 }
2444
rtl_release_firmware(struct rtl8169_private * tp)2445 static void rtl_release_firmware(struct rtl8169_private *tp)
2446 {
2447 if (!IS_ERR_OR_NULL(tp->rtl_fw)) {
2448 release_firmware(tp->rtl_fw->fw);
2449 kfree(tp->rtl_fw);
2450 }
2451 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
2452 }
2453
rtl_apply_firmware(struct rtl8169_private * tp)2454 static void rtl_apply_firmware(struct rtl8169_private *tp)
2455 {
2456 struct rtl_fw *rtl_fw = tp->rtl_fw;
2457
2458 /* TODO: release firmware once rtl_phy_write_fw signals failures. */
2459 if (!IS_ERR_OR_NULL(rtl_fw))
2460 rtl_phy_write_fw(tp, rtl_fw);
2461 }
2462
rtl_apply_firmware_cond(struct rtl8169_private * tp,u8 reg,u16 val)2463 static void rtl_apply_firmware_cond(struct rtl8169_private *tp, u8 reg, u16 val)
2464 {
2465 if (rtl_readphy(tp, reg) != val)
2466 netif_warn(tp, hw, tp->dev, "chipset not ready for firmware\n");
2467 else
2468 rtl_apply_firmware(tp);
2469 }
2470
rtl8169s_hw_phy_config(struct rtl8169_private * tp)2471 static void rtl8169s_hw_phy_config(struct rtl8169_private *tp)
2472 {
2473 static const struct phy_reg phy_reg_init[] = {
2474 { 0x1f, 0x0001 },
2475 { 0x06, 0x006e },
2476 { 0x08, 0x0708 },
2477 { 0x15, 0x4000 },
2478 { 0x18, 0x65c7 },
2479
2480 { 0x1f, 0x0001 },
2481 { 0x03, 0x00a1 },
2482 { 0x02, 0x0008 },
2483 { 0x01, 0x0120 },
2484 { 0x00, 0x1000 },
2485 { 0x04, 0x0800 },
2486 { 0x04, 0x0000 },
2487
2488 { 0x03, 0xff41 },
2489 { 0x02, 0xdf60 },
2490 { 0x01, 0x0140 },
2491 { 0x00, 0x0077 },
2492 { 0x04, 0x7800 },
2493 { 0x04, 0x7000 },
2494
2495 { 0x03, 0x802f },
2496 { 0x02, 0x4f02 },
2497 { 0x01, 0x0409 },
2498 { 0x00, 0xf0f9 },
2499 { 0x04, 0x9800 },
2500 { 0x04, 0x9000 },
2501
2502 { 0x03, 0xdf01 },
2503 { 0x02, 0xdf20 },
2504 { 0x01, 0xff95 },
2505 { 0x00, 0xba00 },
2506 { 0x04, 0xa800 },
2507 { 0x04, 0xa000 },
2508
2509 { 0x03, 0xff41 },
2510 { 0x02, 0xdf20 },
2511 { 0x01, 0x0140 },
2512 { 0x00, 0x00bb },
2513 { 0x04, 0xb800 },
2514 { 0x04, 0xb000 },
2515
2516 { 0x03, 0xdf41 },
2517 { 0x02, 0xdc60 },
2518 { 0x01, 0x6340 },
2519 { 0x00, 0x007d },
2520 { 0x04, 0xd800 },
2521 { 0x04, 0xd000 },
2522
2523 { 0x03, 0xdf01 },
2524 { 0x02, 0xdf20 },
2525 { 0x01, 0x100a },
2526 { 0x00, 0xa0ff },
2527 { 0x04, 0xf800 },
2528 { 0x04, 0xf000 },
2529
2530 { 0x1f, 0x0000 },
2531 { 0x0b, 0x0000 },
2532 { 0x00, 0x9200 }
2533 };
2534
2535 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2536 }
2537
rtl8169sb_hw_phy_config(struct rtl8169_private * tp)2538 static void rtl8169sb_hw_phy_config(struct rtl8169_private *tp)
2539 {
2540 static const struct phy_reg phy_reg_init[] = {
2541 { 0x1f, 0x0002 },
2542 { 0x01, 0x90d0 },
2543 { 0x1f, 0x0000 }
2544 };
2545
2546 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2547 }
2548
rtl8169scd_hw_phy_config_quirk(struct rtl8169_private * tp)2549 static void rtl8169scd_hw_phy_config_quirk(struct rtl8169_private *tp)
2550 {
2551 struct pci_dev *pdev = tp->pci_dev;
2552
2553 if ((pdev->subsystem_vendor != PCI_VENDOR_ID_GIGABYTE) ||
2554 (pdev->subsystem_device != 0xe000))
2555 return;
2556
2557 rtl_writephy(tp, 0x1f, 0x0001);
2558 rtl_writephy(tp, 0x10, 0xf01b);
2559 rtl_writephy(tp, 0x1f, 0x0000);
2560 }
2561
rtl8169scd_hw_phy_config(struct rtl8169_private * tp)2562 static void rtl8169scd_hw_phy_config(struct rtl8169_private *tp)
2563 {
2564 static const struct phy_reg phy_reg_init[] = {
2565 { 0x1f, 0x0001 },
2566 { 0x04, 0x0000 },
2567 { 0x03, 0x00a1 },
2568 { 0x02, 0x0008 },
2569 { 0x01, 0x0120 },
2570 { 0x00, 0x1000 },
2571 { 0x04, 0x0800 },
2572 { 0x04, 0x9000 },
2573 { 0x03, 0x802f },
2574 { 0x02, 0x4f02 },
2575 { 0x01, 0x0409 },
2576 { 0x00, 0xf099 },
2577 { 0x04, 0x9800 },
2578 { 0x04, 0xa000 },
2579 { 0x03, 0xdf01 },
2580 { 0x02, 0xdf20 },
2581 { 0x01, 0xff95 },
2582 { 0x00, 0xba00 },
2583 { 0x04, 0xa800 },
2584 { 0x04, 0xf000 },
2585 { 0x03, 0xdf01 },
2586 { 0x02, 0xdf20 },
2587 { 0x01, 0x101a },
2588 { 0x00, 0xa0ff },
2589 { 0x04, 0xf800 },
2590 { 0x04, 0x0000 },
2591 { 0x1f, 0x0000 },
2592
2593 { 0x1f, 0x0001 },
2594 { 0x10, 0xf41b },
2595 { 0x14, 0xfb54 },
2596 { 0x18, 0xf5c7 },
2597 { 0x1f, 0x0000 },
2598
2599 { 0x1f, 0x0001 },
2600 { 0x17, 0x0cc0 },
2601 { 0x1f, 0x0000 }
2602 };
2603
2604 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2605
2606 rtl8169scd_hw_phy_config_quirk(tp);
2607 }
2608
rtl8169sce_hw_phy_config(struct rtl8169_private * tp)2609 static void rtl8169sce_hw_phy_config(struct rtl8169_private *tp)
2610 {
2611 static const struct phy_reg phy_reg_init[] = {
2612 { 0x1f, 0x0001 },
2613 { 0x04, 0x0000 },
2614 { 0x03, 0x00a1 },
2615 { 0x02, 0x0008 },
2616 { 0x01, 0x0120 },
2617 { 0x00, 0x1000 },
2618 { 0x04, 0x0800 },
2619 { 0x04, 0x9000 },
2620 { 0x03, 0x802f },
2621 { 0x02, 0x4f02 },
2622 { 0x01, 0x0409 },
2623 { 0x00, 0xf099 },
2624 { 0x04, 0x9800 },
2625 { 0x04, 0xa000 },
2626 { 0x03, 0xdf01 },
2627 { 0x02, 0xdf20 },
2628 { 0x01, 0xff95 },
2629 { 0x00, 0xba00 },
2630 { 0x04, 0xa800 },
2631 { 0x04, 0xf000 },
2632 { 0x03, 0xdf01 },
2633 { 0x02, 0xdf20 },
2634 { 0x01, 0x101a },
2635 { 0x00, 0xa0ff },
2636 { 0x04, 0xf800 },
2637 { 0x04, 0x0000 },
2638 { 0x1f, 0x0000 },
2639
2640 { 0x1f, 0x0001 },
2641 { 0x0b, 0x8480 },
2642 { 0x1f, 0x0000 },
2643
2644 { 0x1f, 0x0001 },
2645 { 0x18, 0x67c7 },
2646 { 0x04, 0x2000 },
2647 { 0x03, 0x002f },
2648 { 0x02, 0x4360 },
2649 { 0x01, 0x0109 },
2650 { 0x00, 0x3022 },
2651 { 0x04, 0x2800 },
2652 { 0x1f, 0x0000 },
2653
2654 { 0x1f, 0x0001 },
2655 { 0x17, 0x0cc0 },
2656 { 0x1f, 0x0000 }
2657 };
2658
2659 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2660 }
2661
rtl8168bb_hw_phy_config(struct rtl8169_private * tp)2662 static void rtl8168bb_hw_phy_config(struct rtl8169_private *tp)
2663 {
2664 static const struct phy_reg phy_reg_init[] = {
2665 { 0x10, 0xf41b },
2666 { 0x1f, 0x0000 }
2667 };
2668
2669 rtl_writephy(tp, 0x1f, 0x0001);
2670 rtl_patchphy(tp, 0x16, 1 << 0);
2671
2672 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2673 }
2674
rtl8168bef_hw_phy_config(struct rtl8169_private * tp)2675 static void rtl8168bef_hw_phy_config(struct rtl8169_private *tp)
2676 {
2677 static const struct phy_reg phy_reg_init[] = {
2678 { 0x1f, 0x0001 },
2679 { 0x10, 0xf41b },
2680 { 0x1f, 0x0000 }
2681 };
2682
2683 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2684 }
2685
rtl8168cp_1_hw_phy_config(struct rtl8169_private * tp)2686 static void rtl8168cp_1_hw_phy_config(struct rtl8169_private *tp)
2687 {
2688 static const struct phy_reg phy_reg_init[] = {
2689 { 0x1f, 0x0000 },
2690 { 0x1d, 0x0f00 },
2691 { 0x1f, 0x0002 },
2692 { 0x0c, 0x1ec8 },
2693 { 0x1f, 0x0000 }
2694 };
2695
2696 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2697 }
2698
rtl8168cp_2_hw_phy_config(struct rtl8169_private * tp)2699 static void rtl8168cp_2_hw_phy_config(struct rtl8169_private *tp)
2700 {
2701 static const struct phy_reg phy_reg_init[] = {
2702 { 0x1f, 0x0001 },
2703 { 0x1d, 0x3d98 },
2704 { 0x1f, 0x0000 }
2705 };
2706
2707 rtl_writephy(tp, 0x1f, 0x0000);
2708 rtl_patchphy(tp, 0x14, 1 << 5);
2709 rtl_patchphy(tp, 0x0d, 1 << 5);
2710
2711 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2712 }
2713
rtl8168c_1_hw_phy_config(struct rtl8169_private * tp)2714 static void rtl8168c_1_hw_phy_config(struct rtl8169_private *tp)
2715 {
2716 static const struct phy_reg phy_reg_init[] = {
2717 { 0x1f, 0x0001 },
2718 { 0x12, 0x2300 },
2719 { 0x1f, 0x0002 },
2720 { 0x00, 0x88d4 },
2721 { 0x01, 0x82b1 },
2722 { 0x03, 0x7002 },
2723 { 0x08, 0x9e30 },
2724 { 0x09, 0x01f0 },
2725 { 0x0a, 0x5500 },
2726 { 0x0c, 0x00c8 },
2727 { 0x1f, 0x0003 },
2728 { 0x12, 0xc096 },
2729 { 0x16, 0x000a },
2730 { 0x1f, 0x0000 },
2731 { 0x1f, 0x0000 },
2732 { 0x09, 0x2000 },
2733 { 0x09, 0x0000 }
2734 };
2735
2736 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2737
2738 rtl_patchphy(tp, 0x14, 1 << 5);
2739 rtl_patchphy(tp, 0x0d, 1 << 5);
2740 rtl_writephy(tp, 0x1f, 0x0000);
2741 }
2742
rtl8168c_2_hw_phy_config(struct rtl8169_private * tp)2743 static void rtl8168c_2_hw_phy_config(struct rtl8169_private *tp)
2744 {
2745 static const struct phy_reg phy_reg_init[] = {
2746 { 0x1f, 0x0001 },
2747 { 0x12, 0x2300 },
2748 { 0x03, 0x802f },
2749 { 0x02, 0x4f02 },
2750 { 0x01, 0x0409 },
2751 { 0x00, 0xf099 },
2752 { 0x04, 0x9800 },
2753 { 0x04, 0x9000 },
2754 { 0x1d, 0x3d98 },
2755 { 0x1f, 0x0002 },
2756 { 0x0c, 0x7eb8 },
2757 { 0x06, 0x0761 },
2758 { 0x1f, 0x0003 },
2759 { 0x16, 0x0f0a },
2760 { 0x1f, 0x0000 }
2761 };
2762
2763 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2764
2765 rtl_patchphy(tp, 0x16, 1 << 0);
2766 rtl_patchphy(tp, 0x14, 1 << 5);
2767 rtl_patchphy(tp, 0x0d, 1 << 5);
2768 rtl_writephy(tp, 0x1f, 0x0000);
2769 }
2770
rtl8168c_3_hw_phy_config(struct rtl8169_private * tp)2771 static void rtl8168c_3_hw_phy_config(struct rtl8169_private *tp)
2772 {
2773 static const struct phy_reg phy_reg_init[] = {
2774 { 0x1f, 0x0001 },
2775 { 0x12, 0x2300 },
2776 { 0x1d, 0x3d98 },
2777 { 0x1f, 0x0002 },
2778 { 0x0c, 0x7eb8 },
2779 { 0x06, 0x5461 },
2780 { 0x1f, 0x0003 },
2781 { 0x16, 0x0f0a },
2782 { 0x1f, 0x0000 }
2783 };
2784
2785 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2786
2787 rtl_patchphy(tp, 0x16, 1 << 0);
2788 rtl_patchphy(tp, 0x14, 1 << 5);
2789 rtl_patchphy(tp, 0x0d, 1 << 5);
2790 rtl_writephy(tp, 0x1f, 0x0000);
2791 }
2792
rtl8168c_4_hw_phy_config(struct rtl8169_private * tp)2793 static void rtl8168c_4_hw_phy_config(struct rtl8169_private *tp)
2794 {
2795 rtl8168c_3_hw_phy_config(tp);
2796 }
2797
rtl8168d_1_hw_phy_config(struct rtl8169_private * tp)2798 static void rtl8168d_1_hw_phy_config(struct rtl8169_private *tp)
2799 {
2800 static const struct phy_reg phy_reg_init_0[] = {
2801 /* Channel Estimation */
2802 { 0x1f, 0x0001 },
2803 { 0x06, 0x4064 },
2804 { 0x07, 0x2863 },
2805 { 0x08, 0x059c },
2806 { 0x09, 0x26b4 },
2807 { 0x0a, 0x6a19 },
2808 { 0x0b, 0xdcc8 },
2809 { 0x10, 0xf06d },
2810 { 0x14, 0x7f68 },
2811 { 0x18, 0x7fd9 },
2812 { 0x1c, 0xf0ff },
2813 { 0x1d, 0x3d9c },
2814 { 0x1f, 0x0003 },
2815 { 0x12, 0xf49f },
2816 { 0x13, 0x070b },
2817 { 0x1a, 0x05ad },
2818 { 0x14, 0x94c0 },
2819
2820 /*
2821 * Tx Error Issue
2822 * Enhance line driver power
2823 */
2824 { 0x1f, 0x0002 },
2825 { 0x06, 0x5561 },
2826 { 0x1f, 0x0005 },
2827 { 0x05, 0x8332 },
2828 { 0x06, 0x5561 },
2829
2830 /*
2831 * Can not link to 1Gbps with bad cable
2832 * Decrease SNR threshold form 21.07dB to 19.04dB
2833 */
2834 { 0x1f, 0x0001 },
2835 { 0x17, 0x0cc0 },
2836
2837 { 0x1f, 0x0000 },
2838 { 0x0d, 0xf880 }
2839 };
2840
2841 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2842
2843 /*
2844 * Rx Error Issue
2845 * Fine Tune Switching regulator parameter
2846 */
2847 rtl_writephy(tp, 0x1f, 0x0002);
2848 rtl_w0w1_phy(tp, 0x0b, 0x0010, 0x00ef);
2849 rtl_w0w1_phy(tp, 0x0c, 0xa200, 0x5d00);
2850
2851 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2852 static const struct phy_reg phy_reg_init[] = {
2853 { 0x1f, 0x0002 },
2854 { 0x05, 0x669a },
2855 { 0x1f, 0x0005 },
2856 { 0x05, 0x8330 },
2857 { 0x06, 0x669a },
2858 { 0x1f, 0x0002 }
2859 };
2860 int val;
2861
2862 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2863
2864 val = rtl_readphy(tp, 0x0d);
2865
2866 if ((val & 0x00ff) != 0x006c) {
2867 static const u32 set[] = {
2868 0x0065, 0x0066, 0x0067, 0x0068,
2869 0x0069, 0x006a, 0x006b, 0x006c
2870 };
2871 int i;
2872
2873 rtl_writephy(tp, 0x1f, 0x0002);
2874
2875 val &= 0xff00;
2876 for (i = 0; i < ARRAY_SIZE(set); i++)
2877 rtl_writephy(tp, 0x0d, val | set[i]);
2878 }
2879 } else {
2880 static const struct phy_reg phy_reg_init[] = {
2881 { 0x1f, 0x0002 },
2882 { 0x05, 0x6662 },
2883 { 0x1f, 0x0005 },
2884 { 0x05, 0x8330 },
2885 { 0x06, 0x6662 }
2886 };
2887
2888 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2889 }
2890
2891 /* RSET couple improve */
2892 rtl_writephy(tp, 0x1f, 0x0002);
2893 rtl_patchphy(tp, 0x0d, 0x0300);
2894 rtl_patchphy(tp, 0x0f, 0x0010);
2895
2896 /* Fine tune PLL performance */
2897 rtl_writephy(tp, 0x1f, 0x0002);
2898 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2899 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2900
2901 rtl_writephy(tp, 0x1f, 0x0005);
2902 rtl_writephy(tp, 0x05, 0x001b);
2903
2904 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xbf00);
2905
2906 rtl_writephy(tp, 0x1f, 0x0000);
2907 }
2908
rtl8168d_2_hw_phy_config(struct rtl8169_private * tp)2909 static void rtl8168d_2_hw_phy_config(struct rtl8169_private *tp)
2910 {
2911 static const struct phy_reg phy_reg_init_0[] = {
2912 /* Channel Estimation */
2913 { 0x1f, 0x0001 },
2914 { 0x06, 0x4064 },
2915 { 0x07, 0x2863 },
2916 { 0x08, 0x059c },
2917 { 0x09, 0x26b4 },
2918 { 0x0a, 0x6a19 },
2919 { 0x0b, 0xdcc8 },
2920 { 0x10, 0xf06d },
2921 { 0x14, 0x7f68 },
2922 { 0x18, 0x7fd9 },
2923 { 0x1c, 0xf0ff },
2924 { 0x1d, 0x3d9c },
2925 { 0x1f, 0x0003 },
2926 { 0x12, 0xf49f },
2927 { 0x13, 0x070b },
2928 { 0x1a, 0x05ad },
2929 { 0x14, 0x94c0 },
2930
2931 /*
2932 * Tx Error Issue
2933 * Enhance line driver power
2934 */
2935 { 0x1f, 0x0002 },
2936 { 0x06, 0x5561 },
2937 { 0x1f, 0x0005 },
2938 { 0x05, 0x8332 },
2939 { 0x06, 0x5561 },
2940
2941 /*
2942 * Can not link to 1Gbps with bad cable
2943 * Decrease SNR threshold form 21.07dB to 19.04dB
2944 */
2945 { 0x1f, 0x0001 },
2946 { 0x17, 0x0cc0 },
2947
2948 { 0x1f, 0x0000 },
2949 { 0x0d, 0xf880 }
2950 };
2951
2952 rtl_writephy_batch(tp, phy_reg_init_0, ARRAY_SIZE(phy_reg_init_0));
2953
2954 if (rtl8168d_efuse_read(tp, 0x01) == 0xb1) {
2955 static const struct phy_reg phy_reg_init[] = {
2956 { 0x1f, 0x0002 },
2957 { 0x05, 0x669a },
2958 { 0x1f, 0x0005 },
2959 { 0x05, 0x8330 },
2960 { 0x06, 0x669a },
2961
2962 { 0x1f, 0x0002 }
2963 };
2964 int val;
2965
2966 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2967
2968 val = rtl_readphy(tp, 0x0d);
2969 if ((val & 0x00ff) != 0x006c) {
2970 static const u32 set[] = {
2971 0x0065, 0x0066, 0x0067, 0x0068,
2972 0x0069, 0x006a, 0x006b, 0x006c
2973 };
2974 int i;
2975
2976 rtl_writephy(tp, 0x1f, 0x0002);
2977
2978 val &= 0xff00;
2979 for (i = 0; i < ARRAY_SIZE(set); i++)
2980 rtl_writephy(tp, 0x0d, val | set[i]);
2981 }
2982 } else {
2983 static const struct phy_reg phy_reg_init[] = {
2984 { 0x1f, 0x0002 },
2985 { 0x05, 0x2642 },
2986 { 0x1f, 0x0005 },
2987 { 0x05, 0x8330 },
2988 { 0x06, 0x2642 }
2989 };
2990
2991 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
2992 }
2993
2994 /* Fine tune PLL performance */
2995 rtl_writephy(tp, 0x1f, 0x0002);
2996 rtl_w0w1_phy(tp, 0x02, 0x0100, 0x0600);
2997 rtl_w0w1_phy(tp, 0x03, 0x0000, 0xe000);
2998
2999 /* Switching regulator Slew rate */
3000 rtl_writephy(tp, 0x1f, 0x0002);
3001 rtl_patchphy(tp, 0x0f, 0x0017);
3002
3003 rtl_writephy(tp, 0x1f, 0x0005);
3004 rtl_writephy(tp, 0x05, 0x001b);
3005
3006 rtl_apply_firmware_cond(tp, MII_EXPANSION, 0xb300);
3007
3008 rtl_writephy(tp, 0x1f, 0x0000);
3009 }
3010
rtl8168d_3_hw_phy_config(struct rtl8169_private * tp)3011 static void rtl8168d_3_hw_phy_config(struct rtl8169_private *tp)
3012 {
3013 static const struct phy_reg phy_reg_init[] = {
3014 { 0x1f, 0x0002 },
3015 { 0x10, 0x0008 },
3016 { 0x0d, 0x006c },
3017
3018 { 0x1f, 0x0000 },
3019 { 0x0d, 0xf880 },
3020
3021 { 0x1f, 0x0001 },
3022 { 0x17, 0x0cc0 },
3023
3024 { 0x1f, 0x0001 },
3025 { 0x0b, 0xa4d8 },
3026 { 0x09, 0x281c },
3027 { 0x07, 0x2883 },
3028 { 0x0a, 0x6b35 },
3029 { 0x1d, 0x3da4 },
3030 { 0x1c, 0xeffd },
3031 { 0x14, 0x7f52 },
3032 { 0x18, 0x7fc6 },
3033 { 0x08, 0x0601 },
3034 { 0x06, 0x4063 },
3035 { 0x10, 0xf074 },
3036 { 0x1f, 0x0003 },
3037 { 0x13, 0x0789 },
3038 { 0x12, 0xf4bd },
3039 { 0x1a, 0x04fd },
3040 { 0x14, 0x84b0 },
3041 { 0x1f, 0x0000 },
3042 { 0x00, 0x9200 },
3043
3044 { 0x1f, 0x0005 },
3045 { 0x01, 0x0340 },
3046 { 0x1f, 0x0001 },
3047 { 0x04, 0x4000 },
3048 { 0x03, 0x1d21 },
3049 { 0x02, 0x0c32 },
3050 { 0x01, 0x0200 },
3051 { 0x00, 0x5554 },
3052 { 0x04, 0x4800 },
3053 { 0x04, 0x4000 },
3054 { 0x04, 0xf000 },
3055 { 0x03, 0xdf01 },
3056 { 0x02, 0xdf20 },
3057 { 0x01, 0x101a },
3058 { 0x00, 0xa0ff },
3059 { 0x04, 0xf800 },
3060 { 0x04, 0xf000 },
3061 { 0x1f, 0x0000 },
3062
3063 { 0x1f, 0x0007 },
3064 { 0x1e, 0x0023 },
3065 { 0x16, 0x0000 },
3066 { 0x1f, 0x0000 }
3067 };
3068
3069 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3070 }
3071
rtl8168d_4_hw_phy_config(struct rtl8169_private * tp)3072 static void rtl8168d_4_hw_phy_config(struct rtl8169_private *tp)
3073 {
3074 static const struct phy_reg phy_reg_init[] = {
3075 { 0x1f, 0x0001 },
3076 { 0x17, 0x0cc0 },
3077
3078 { 0x1f, 0x0007 },
3079 { 0x1e, 0x002d },
3080 { 0x18, 0x0040 },
3081 { 0x1f, 0x0000 }
3082 };
3083
3084 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3085 rtl_patchphy(tp, 0x0d, 1 << 5);
3086 }
3087
rtl8168e_1_hw_phy_config(struct rtl8169_private * tp)3088 static void rtl8168e_1_hw_phy_config(struct rtl8169_private *tp)
3089 {
3090 static const struct phy_reg phy_reg_init[] = {
3091 /* Enable Delay cap */
3092 { 0x1f, 0x0005 },
3093 { 0x05, 0x8b80 },
3094 { 0x06, 0xc896 },
3095 { 0x1f, 0x0000 },
3096
3097 /* Channel estimation fine tune */
3098 { 0x1f, 0x0001 },
3099 { 0x0b, 0x6c20 },
3100 { 0x07, 0x2872 },
3101 { 0x1c, 0xefff },
3102 { 0x1f, 0x0003 },
3103 { 0x14, 0x6420 },
3104 { 0x1f, 0x0000 },
3105
3106 /* Update PFM & 10M TX idle timer */
3107 { 0x1f, 0x0007 },
3108 { 0x1e, 0x002f },
3109 { 0x15, 0x1919 },
3110 { 0x1f, 0x0000 },
3111
3112 { 0x1f, 0x0007 },
3113 { 0x1e, 0x00ac },
3114 { 0x18, 0x0006 },
3115 { 0x1f, 0x0000 }
3116 };
3117
3118 rtl_apply_firmware(tp);
3119
3120 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3121
3122 /* DCO enable for 10M IDLE Power */
3123 rtl_writephy(tp, 0x1f, 0x0007);
3124 rtl_writephy(tp, 0x1e, 0x0023);
3125 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3126 rtl_writephy(tp, 0x1f, 0x0000);
3127
3128 /* For impedance matching */
3129 rtl_writephy(tp, 0x1f, 0x0002);
3130 rtl_w0w1_phy(tp, 0x08, 0x8000, 0x7f00);
3131 rtl_writephy(tp, 0x1f, 0x0000);
3132
3133 /* PHY auto speed down */
3134 rtl_writephy(tp, 0x1f, 0x0007);
3135 rtl_writephy(tp, 0x1e, 0x002d);
3136 rtl_w0w1_phy(tp, 0x18, 0x0050, 0x0000);
3137 rtl_writephy(tp, 0x1f, 0x0000);
3138 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3139
3140 rtl_writephy(tp, 0x1f, 0x0005);
3141 rtl_writephy(tp, 0x05, 0x8b86);
3142 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3143 rtl_writephy(tp, 0x1f, 0x0000);
3144
3145 rtl_writephy(tp, 0x1f, 0x0005);
3146 rtl_writephy(tp, 0x05, 0x8b85);
3147 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3148 rtl_writephy(tp, 0x1f, 0x0007);
3149 rtl_writephy(tp, 0x1e, 0x0020);
3150 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x1100);
3151 rtl_writephy(tp, 0x1f, 0x0006);
3152 rtl_writephy(tp, 0x00, 0x5a00);
3153 rtl_writephy(tp, 0x1f, 0x0000);
3154 rtl_writephy(tp, 0x0d, 0x0007);
3155 rtl_writephy(tp, 0x0e, 0x003c);
3156 rtl_writephy(tp, 0x0d, 0x4007);
3157 rtl_writephy(tp, 0x0e, 0x0000);
3158 rtl_writephy(tp, 0x0d, 0x0000);
3159 }
3160
rtl_rar_exgmac_set(struct rtl8169_private * tp,u8 * addr)3161 static void rtl_rar_exgmac_set(struct rtl8169_private *tp, u8 *addr)
3162 {
3163 const u16 w[] = {
3164 addr[0] | (addr[1] << 8),
3165 addr[2] | (addr[3] << 8),
3166 addr[4] | (addr[5] << 8)
3167 };
3168 const struct exgmac_reg e[] = {
3169 { .addr = 0xe0, ERIAR_MASK_1111, .val = w[0] | (w[1] << 16) },
3170 { .addr = 0xe4, ERIAR_MASK_1111, .val = w[2] },
3171 { .addr = 0xf0, ERIAR_MASK_1111, .val = w[0] << 16 },
3172 { .addr = 0xf4, ERIAR_MASK_1111, .val = w[1] | (w[2] << 16) }
3173 };
3174
3175 rtl_write_exgmac_batch(tp, e, ARRAY_SIZE(e));
3176 }
3177
rtl8168e_2_hw_phy_config(struct rtl8169_private * tp)3178 static void rtl8168e_2_hw_phy_config(struct rtl8169_private *tp)
3179 {
3180 static const struct phy_reg phy_reg_init[] = {
3181 /* Enable Delay cap */
3182 { 0x1f, 0x0004 },
3183 { 0x1f, 0x0007 },
3184 { 0x1e, 0x00ac },
3185 { 0x18, 0x0006 },
3186 { 0x1f, 0x0002 },
3187 { 0x1f, 0x0000 },
3188 { 0x1f, 0x0000 },
3189
3190 /* Channel estimation fine tune */
3191 { 0x1f, 0x0003 },
3192 { 0x09, 0xa20f },
3193 { 0x1f, 0x0000 },
3194 { 0x1f, 0x0000 },
3195
3196 /* Green Setting */
3197 { 0x1f, 0x0005 },
3198 { 0x05, 0x8b5b },
3199 { 0x06, 0x9222 },
3200 { 0x05, 0x8b6d },
3201 { 0x06, 0x8000 },
3202 { 0x05, 0x8b76 },
3203 { 0x06, 0x8000 },
3204 { 0x1f, 0x0000 }
3205 };
3206
3207 rtl_apply_firmware(tp);
3208
3209 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3210
3211 /* For 4-corner performance improve */
3212 rtl_writephy(tp, 0x1f, 0x0005);
3213 rtl_writephy(tp, 0x05, 0x8b80);
3214 rtl_w0w1_phy(tp, 0x17, 0x0006, 0x0000);
3215 rtl_writephy(tp, 0x1f, 0x0000);
3216
3217 /* PHY auto speed down */
3218 rtl_writephy(tp, 0x1f, 0x0004);
3219 rtl_writephy(tp, 0x1f, 0x0007);
3220 rtl_writephy(tp, 0x1e, 0x002d);
3221 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3222 rtl_writephy(tp, 0x1f, 0x0002);
3223 rtl_writephy(tp, 0x1f, 0x0000);
3224 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3225
3226 /* improve 10M EEE waveform */
3227 rtl_writephy(tp, 0x1f, 0x0005);
3228 rtl_writephy(tp, 0x05, 0x8b86);
3229 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3230 rtl_writephy(tp, 0x1f, 0x0000);
3231
3232 /* Improve 2-pair detection performance */
3233 rtl_writephy(tp, 0x1f, 0x0005);
3234 rtl_writephy(tp, 0x05, 0x8b85);
3235 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3236 rtl_writephy(tp, 0x1f, 0x0000);
3237
3238 /* EEE setting */
3239 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_1111, 0x0003, 0x0000, ERIAR_EXGMAC);
3240 rtl_writephy(tp, 0x1f, 0x0005);
3241 rtl_writephy(tp, 0x05, 0x8b85);
3242 rtl_w0w1_phy(tp, 0x06, 0x2000, 0x0000);
3243 rtl_writephy(tp, 0x1f, 0x0004);
3244 rtl_writephy(tp, 0x1f, 0x0007);
3245 rtl_writephy(tp, 0x1e, 0x0020);
3246 rtl_w0w1_phy(tp, 0x15, 0x0100, 0x0000);
3247 rtl_writephy(tp, 0x1f, 0x0002);
3248 rtl_writephy(tp, 0x1f, 0x0000);
3249 rtl_writephy(tp, 0x0d, 0x0007);
3250 rtl_writephy(tp, 0x0e, 0x003c);
3251 rtl_writephy(tp, 0x0d, 0x4007);
3252 rtl_writephy(tp, 0x0e, 0x0006);
3253 rtl_writephy(tp, 0x0d, 0x0000);
3254
3255 /* Green feature */
3256 rtl_writephy(tp, 0x1f, 0x0003);
3257 rtl_w0w1_phy(tp, 0x19, 0x0001, 0x0000);
3258 rtl_w0w1_phy(tp, 0x10, 0x0400, 0x0000);
3259 rtl_writephy(tp, 0x1f, 0x0000);
3260 rtl_writephy(tp, 0x1f, 0x0005);
3261 rtl_w0w1_phy(tp, 0x01, 0x0100, 0x0000);
3262 rtl_writephy(tp, 0x1f, 0x0000);
3263
3264 /* Broken BIOS workaround: feed GigaMAC registers with MAC address. */
3265 rtl_rar_exgmac_set(tp, tp->dev->dev_addr);
3266 }
3267
rtl8168f_hw_phy_config(struct rtl8169_private * tp)3268 static void rtl8168f_hw_phy_config(struct rtl8169_private *tp)
3269 {
3270 /* For 4-corner performance improve */
3271 rtl_writephy(tp, 0x1f, 0x0005);
3272 rtl_writephy(tp, 0x05, 0x8b80);
3273 rtl_w0w1_phy(tp, 0x06, 0x0006, 0x0000);
3274 rtl_writephy(tp, 0x1f, 0x0000);
3275
3276 /* PHY auto speed down */
3277 rtl_writephy(tp, 0x1f, 0x0007);
3278 rtl_writephy(tp, 0x1e, 0x002d);
3279 rtl_w0w1_phy(tp, 0x18, 0x0010, 0x0000);
3280 rtl_writephy(tp, 0x1f, 0x0000);
3281 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3282
3283 /* Improve 10M EEE waveform */
3284 rtl_writephy(tp, 0x1f, 0x0005);
3285 rtl_writephy(tp, 0x05, 0x8b86);
3286 rtl_w0w1_phy(tp, 0x06, 0x0001, 0x0000);
3287 rtl_writephy(tp, 0x1f, 0x0000);
3288 }
3289
rtl8168f_1_hw_phy_config(struct rtl8169_private * tp)3290 static void rtl8168f_1_hw_phy_config(struct rtl8169_private *tp)
3291 {
3292 static const struct phy_reg phy_reg_init[] = {
3293 /* Channel estimation fine tune */
3294 { 0x1f, 0x0003 },
3295 { 0x09, 0xa20f },
3296 { 0x1f, 0x0000 },
3297
3298 /* Modify green table for giga & fnet */
3299 { 0x1f, 0x0005 },
3300 { 0x05, 0x8b55 },
3301 { 0x06, 0x0000 },
3302 { 0x05, 0x8b5e },
3303 { 0x06, 0x0000 },
3304 { 0x05, 0x8b67 },
3305 { 0x06, 0x0000 },
3306 { 0x05, 0x8b70 },
3307 { 0x06, 0x0000 },
3308 { 0x1f, 0x0000 },
3309 { 0x1f, 0x0007 },
3310 { 0x1e, 0x0078 },
3311 { 0x17, 0x0000 },
3312 { 0x19, 0x00fb },
3313 { 0x1f, 0x0000 },
3314
3315 /* Modify green table for 10M */
3316 { 0x1f, 0x0005 },
3317 { 0x05, 0x8b79 },
3318 { 0x06, 0xaa00 },
3319 { 0x1f, 0x0000 },
3320
3321 /* Disable hiimpedance detection (RTCT) */
3322 { 0x1f, 0x0003 },
3323 { 0x01, 0x328a },
3324 { 0x1f, 0x0000 }
3325 };
3326
3327 rtl_apply_firmware(tp);
3328
3329 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3330
3331 rtl8168f_hw_phy_config(tp);
3332
3333 /* Improve 2-pair detection performance */
3334 rtl_writephy(tp, 0x1f, 0x0005);
3335 rtl_writephy(tp, 0x05, 0x8b85);
3336 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3337 rtl_writephy(tp, 0x1f, 0x0000);
3338 }
3339
rtl8168f_2_hw_phy_config(struct rtl8169_private * tp)3340 static void rtl8168f_2_hw_phy_config(struct rtl8169_private *tp)
3341 {
3342 rtl_apply_firmware(tp);
3343
3344 rtl8168f_hw_phy_config(tp);
3345 }
3346
rtl8411_hw_phy_config(struct rtl8169_private * tp)3347 static void rtl8411_hw_phy_config(struct rtl8169_private *tp)
3348 {
3349 static const struct phy_reg phy_reg_init[] = {
3350 /* Channel estimation fine tune */
3351 { 0x1f, 0x0003 },
3352 { 0x09, 0xa20f },
3353 { 0x1f, 0x0000 },
3354
3355 /* Modify green table for giga & fnet */
3356 { 0x1f, 0x0005 },
3357 { 0x05, 0x8b55 },
3358 { 0x06, 0x0000 },
3359 { 0x05, 0x8b5e },
3360 { 0x06, 0x0000 },
3361 { 0x05, 0x8b67 },
3362 { 0x06, 0x0000 },
3363 { 0x05, 0x8b70 },
3364 { 0x06, 0x0000 },
3365 { 0x1f, 0x0000 },
3366 { 0x1f, 0x0007 },
3367 { 0x1e, 0x0078 },
3368 { 0x17, 0x0000 },
3369 { 0x19, 0x00aa },
3370 { 0x1f, 0x0000 },
3371
3372 /* Modify green table for 10M */
3373 { 0x1f, 0x0005 },
3374 { 0x05, 0x8b79 },
3375 { 0x06, 0xaa00 },
3376 { 0x1f, 0x0000 },
3377
3378 /* Disable hiimpedance detection (RTCT) */
3379 { 0x1f, 0x0003 },
3380 { 0x01, 0x328a },
3381 { 0x1f, 0x0000 }
3382 };
3383
3384
3385 rtl_apply_firmware(tp);
3386
3387 rtl8168f_hw_phy_config(tp);
3388
3389 /* Improve 2-pair detection performance */
3390 rtl_writephy(tp, 0x1f, 0x0005);
3391 rtl_writephy(tp, 0x05, 0x8b85);
3392 rtl_w0w1_phy(tp, 0x06, 0x4000, 0x0000);
3393 rtl_writephy(tp, 0x1f, 0x0000);
3394
3395 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3396
3397 /* Modify green table for giga */
3398 rtl_writephy(tp, 0x1f, 0x0005);
3399 rtl_writephy(tp, 0x05, 0x8b54);
3400 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3401 rtl_writephy(tp, 0x05, 0x8b5d);
3402 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0800);
3403 rtl_writephy(tp, 0x05, 0x8a7c);
3404 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3405 rtl_writephy(tp, 0x05, 0x8a7f);
3406 rtl_w0w1_phy(tp, 0x06, 0x0100, 0x0000);
3407 rtl_writephy(tp, 0x05, 0x8a82);
3408 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3409 rtl_writephy(tp, 0x05, 0x8a85);
3410 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3411 rtl_writephy(tp, 0x05, 0x8a88);
3412 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x0100);
3413 rtl_writephy(tp, 0x1f, 0x0000);
3414
3415 /* uc same-seed solution */
3416 rtl_writephy(tp, 0x1f, 0x0005);
3417 rtl_writephy(tp, 0x05, 0x8b85);
3418 rtl_w0w1_phy(tp, 0x06, 0x8000, 0x0000);
3419 rtl_writephy(tp, 0x1f, 0x0000);
3420
3421 /* eee setting */
3422 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x00, 0x03, ERIAR_EXGMAC);
3423 rtl_writephy(tp, 0x1f, 0x0005);
3424 rtl_writephy(tp, 0x05, 0x8b85);
3425 rtl_w0w1_phy(tp, 0x06, 0x0000, 0x2000);
3426 rtl_writephy(tp, 0x1f, 0x0004);
3427 rtl_writephy(tp, 0x1f, 0x0007);
3428 rtl_writephy(tp, 0x1e, 0x0020);
3429 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0100);
3430 rtl_writephy(tp, 0x1f, 0x0000);
3431 rtl_writephy(tp, 0x0d, 0x0007);
3432 rtl_writephy(tp, 0x0e, 0x003c);
3433 rtl_writephy(tp, 0x0d, 0x4007);
3434 rtl_writephy(tp, 0x0e, 0x0000);
3435 rtl_writephy(tp, 0x0d, 0x0000);
3436
3437 /* Green feature */
3438 rtl_writephy(tp, 0x1f, 0x0003);
3439 rtl_w0w1_phy(tp, 0x19, 0x0000, 0x0001);
3440 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0400);
3441 rtl_writephy(tp, 0x1f, 0x0000);
3442 }
3443
rtl8168g_1_hw_phy_config(struct rtl8169_private * tp)3444 static void rtl8168g_1_hw_phy_config(struct rtl8169_private *tp)
3445 {
3446 rtl_apply_firmware(tp);
3447
3448 rtl_writephy(tp, 0x1f, 0x0a46);
3449 if (rtl_readphy(tp, 0x10) & 0x0100) {
3450 rtl_writephy(tp, 0x1f, 0x0bcc);
3451 rtl_w0w1_phy(tp, 0x12, 0x0000, 0x8000);
3452 } else {
3453 rtl_writephy(tp, 0x1f, 0x0bcc);
3454 rtl_w0w1_phy(tp, 0x12, 0x8000, 0x0000);
3455 }
3456
3457 rtl_writephy(tp, 0x1f, 0x0a46);
3458 if (rtl_readphy(tp, 0x13) & 0x0100) {
3459 rtl_writephy(tp, 0x1f, 0x0c41);
3460 rtl_w0w1_phy(tp, 0x15, 0x0002, 0x0000);
3461 } else {
3462 rtl_writephy(tp, 0x1f, 0x0c41);
3463 rtl_w0w1_phy(tp, 0x15, 0x0000, 0x0002);
3464 }
3465
3466 /* Enable PHY auto speed down */
3467 rtl_writephy(tp, 0x1f, 0x0a44);
3468 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3469
3470 rtl_writephy(tp, 0x1f, 0x0bcc);
3471 rtl_w0w1_phy(tp, 0x14, 0x0100, 0x0000);
3472 rtl_writephy(tp, 0x1f, 0x0a44);
3473 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3474 rtl_writephy(tp, 0x1f, 0x0a43);
3475 rtl_writephy(tp, 0x13, 0x8084);
3476 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3477 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3478
3479 /* EEE auto-fallback function */
3480 rtl_writephy(tp, 0x1f, 0x0a4b);
3481 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3482
3483 /* Enable UC LPF tune function */
3484 rtl_writephy(tp, 0x1f, 0x0a43);
3485 rtl_writephy(tp, 0x13, 0x8012);
3486 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3487
3488 rtl_writephy(tp, 0x1f, 0x0c42);
3489 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3490
3491 /* Improve SWR Efficiency */
3492 rtl_writephy(tp, 0x1f, 0x0bcd);
3493 rtl_writephy(tp, 0x14, 0x5065);
3494 rtl_writephy(tp, 0x14, 0xd065);
3495 rtl_writephy(tp, 0x1f, 0x0bc8);
3496 rtl_writephy(tp, 0x11, 0x5655);
3497 rtl_writephy(tp, 0x1f, 0x0bcd);
3498 rtl_writephy(tp, 0x14, 0x1065);
3499 rtl_writephy(tp, 0x14, 0x9065);
3500 rtl_writephy(tp, 0x14, 0x1065);
3501
3502 /* Check ALDPS bit, disable it if enabled */
3503 rtl_writephy(tp, 0x1f, 0x0a43);
3504 if (rtl_readphy(tp, 0x10) & 0x0004)
3505 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3506
3507 rtl_writephy(tp, 0x1f, 0x0000);
3508 }
3509
rtl8168g_2_hw_phy_config(struct rtl8169_private * tp)3510 static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
3511 {
3512 rtl_apply_firmware(tp);
3513 }
3514
rtl8168h_1_hw_phy_config(struct rtl8169_private * tp)3515 static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
3516 {
3517 u16 dout_tapbin;
3518 u32 data;
3519
3520 rtl_apply_firmware(tp);
3521
3522 /* CHN EST parameters adjust - giga master */
3523 rtl_writephy(tp, 0x1f, 0x0a43);
3524 rtl_writephy(tp, 0x13, 0x809b);
3525 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xf800);
3526 rtl_writephy(tp, 0x13, 0x80a2);
3527 rtl_w0w1_phy(tp, 0x14, 0x8000, 0xff00);
3528 rtl_writephy(tp, 0x13, 0x80a4);
3529 rtl_w0w1_phy(tp, 0x14, 0x8500, 0xff00);
3530 rtl_writephy(tp, 0x13, 0x809c);
3531 rtl_w0w1_phy(tp, 0x14, 0xbd00, 0xff00);
3532 rtl_writephy(tp, 0x1f, 0x0000);
3533
3534 /* CHN EST parameters adjust - giga slave */
3535 rtl_writephy(tp, 0x1f, 0x0a43);
3536 rtl_writephy(tp, 0x13, 0x80ad);
3537 rtl_w0w1_phy(tp, 0x14, 0x7000, 0xf800);
3538 rtl_writephy(tp, 0x13, 0x80b4);
3539 rtl_w0w1_phy(tp, 0x14, 0x5000, 0xff00);
3540 rtl_writephy(tp, 0x13, 0x80ac);
3541 rtl_w0w1_phy(tp, 0x14, 0x4000, 0xff00);
3542 rtl_writephy(tp, 0x1f, 0x0000);
3543
3544 /* CHN EST parameters adjust - fnet */
3545 rtl_writephy(tp, 0x1f, 0x0a43);
3546 rtl_writephy(tp, 0x13, 0x808e);
3547 rtl_w0w1_phy(tp, 0x14, 0x1200, 0xff00);
3548 rtl_writephy(tp, 0x13, 0x8090);
3549 rtl_w0w1_phy(tp, 0x14, 0xe500, 0xff00);
3550 rtl_writephy(tp, 0x13, 0x8092);
3551 rtl_w0w1_phy(tp, 0x14, 0x9f00, 0xff00);
3552 rtl_writephy(tp, 0x1f, 0x0000);
3553
3554 /* enable R-tune & PGA-retune function */
3555 dout_tapbin = 0;
3556 rtl_writephy(tp, 0x1f, 0x0a46);
3557 data = rtl_readphy(tp, 0x13);
3558 data &= 3;
3559 data <<= 2;
3560 dout_tapbin |= data;
3561 data = rtl_readphy(tp, 0x12);
3562 data &= 0xc000;
3563 data >>= 14;
3564 dout_tapbin |= data;
3565 dout_tapbin = ~(dout_tapbin^0x08);
3566 dout_tapbin <<= 12;
3567 dout_tapbin &= 0xf000;
3568 rtl_writephy(tp, 0x1f, 0x0a43);
3569 rtl_writephy(tp, 0x13, 0x827a);
3570 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3571 rtl_writephy(tp, 0x13, 0x827b);
3572 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3573 rtl_writephy(tp, 0x13, 0x827c);
3574 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3575 rtl_writephy(tp, 0x13, 0x827d);
3576 rtl_w0w1_phy(tp, 0x14, dout_tapbin, 0xf000);
3577
3578 rtl_writephy(tp, 0x1f, 0x0a43);
3579 rtl_writephy(tp, 0x13, 0x0811);
3580 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3581 rtl_writephy(tp, 0x1f, 0x0a42);
3582 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3583 rtl_writephy(tp, 0x1f, 0x0000);
3584
3585 /* enable GPHY 10M */
3586 rtl_writephy(tp, 0x1f, 0x0a44);
3587 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3588 rtl_writephy(tp, 0x1f, 0x0000);
3589
3590 /* SAR ADC performance */
3591 rtl_writephy(tp, 0x1f, 0x0bca);
3592 rtl_w0w1_phy(tp, 0x17, 0x4000, 0x3000);
3593 rtl_writephy(tp, 0x1f, 0x0000);
3594
3595 rtl_writephy(tp, 0x1f, 0x0a43);
3596 rtl_writephy(tp, 0x13, 0x803f);
3597 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3598 rtl_writephy(tp, 0x13, 0x8047);
3599 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3600 rtl_writephy(tp, 0x13, 0x804f);
3601 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3602 rtl_writephy(tp, 0x13, 0x8057);
3603 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3604 rtl_writephy(tp, 0x13, 0x805f);
3605 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3606 rtl_writephy(tp, 0x13, 0x8067);
3607 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3608 rtl_writephy(tp, 0x13, 0x806f);
3609 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x3000);
3610 rtl_writephy(tp, 0x1f, 0x0000);
3611
3612 /* disable phy pfm mode */
3613 rtl_writephy(tp, 0x1f, 0x0a44);
3614 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3615 rtl_writephy(tp, 0x1f, 0x0000);
3616
3617 /* Check ALDPS bit, disable it if enabled */
3618 rtl_writephy(tp, 0x1f, 0x0a43);
3619 if (rtl_readphy(tp, 0x10) & 0x0004)
3620 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3621
3622 rtl_writephy(tp, 0x1f, 0x0000);
3623 }
3624
rtl8168h_2_hw_phy_config(struct rtl8169_private * tp)3625 static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
3626 {
3627 u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
3628 u16 rlen;
3629 u32 data;
3630
3631 rtl_apply_firmware(tp);
3632
3633 /* CHIN EST parameter update */
3634 rtl_writephy(tp, 0x1f, 0x0a43);
3635 rtl_writephy(tp, 0x13, 0x808a);
3636 rtl_w0w1_phy(tp, 0x14, 0x000a, 0x003f);
3637 rtl_writephy(tp, 0x1f, 0x0000);
3638
3639 /* enable R-tune & PGA-retune function */
3640 rtl_writephy(tp, 0x1f, 0x0a43);
3641 rtl_writephy(tp, 0x13, 0x0811);
3642 rtl_w0w1_phy(tp, 0x14, 0x0800, 0x0000);
3643 rtl_writephy(tp, 0x1f, 0x0a42);
3644 rtl_w0w1_phy(tp, 0x16, 0x0002, 0x0000);
3645 rtl_writephy(tp, 0x1f, 0x0000);
3646
3647 /* enable GPHY 10M */
3648 rtl_writephy(tp, 0x1f, 0x0a44);
3649 rtl_w0w1_phy(tp, 0x11, 0x0800, 0x0000);
3650 rtl_writephy(tp, 0x1f, 0x0000);
3651
3652 r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
3653 data = r8168_mac_ocp_read(tp, 0xdd02);
3654 ioffset_p3 = ((data & 0x80)>>7);
3655 ioffset_p3 <<= 3;
3656
3657 data = r8168_mac_ocp_read(tp, 0xdd00);
3658 ioffset_p3 |= ((data & (0xe000))>>13);
3659 ioffset_p2 = ((data & (0x1e00))>>9);
3660 ioffset_p1 = ((data & (0x01e0))>>5);
3661 ioffset_p0 = ((data & 0x0010)>>4);
3662 ioffset_p0 <<= 3;
3663 ioffset_p0 |= (data & (0x07));
3664 data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
3665
3666 if ((ioffset_p3 != 0x0f) || (ioffset_p2 != 0x0f) ||
3667 (ioffset_p1 != 0x0f) || (ioffset_p0 != 0x0f)) {
3668 rtl_writephy(tp, 0x1f, 0x0bcf);
3669 rtl_writephy(tp, 0x16, data);
3670 rtl_writephy(tp, 0x1f, 0x0000);
3671 }
3672
3673 /* Modify rlen (TX LPF corner frequency) level */
3674 rtl_writephy(tp, 0x1f, 0x0bcd);
3675 data = rtl_readphy(tp, 0x16);
3676 data &= 0x000f;
3677 rlen = 0;
3678 if (data > 3)
3679 rlen = data - 3;
3680 data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
3681 rtl_writephy(tp, 0x17, data);
3682 rtl_writephy(tp, 0x1f, 0x0bcd);
3683 rtl_writephy(tp, 0x1f, 0x0000);
3684
3685 /* disable phy pfm mode */
3686 rtl_writephy(tp, 0x1f, 0x0a44);
3687 rtl_w0w1_phy(tp, 0x11, 0x0000, 0x0080);
3688 rtl_writephy(tp, 0x1f, 0x0000);
3689
3690 /* Check ALDPS bit, disable it if enabled */
3691 rtl_writephy(tp, 0x1f, 0x0a43);
3692 if (rtl_readphy(tp, 0x10) & 0x0004)
3693 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3694
3695 rtl_writephy(tp, 0x1f, 0x0000);
3696 }
3697
rtl8168ep_1_hw_phy_config(struct rtl8169_private * tp)3698 static void rtl8168ep_1_hw_phy_config(struct rtl8169_private *tp)
3699 {
3700 /* Enable PHY auto speed down */
3701 rtl_writephy(tp, 0x1f, 0x0a44);
3702 rtl_w0w1_phy(tp, 0x11, 0x000c, 0x0000);
3703 rtl_writephy(tp, 0x1f, 0x0000);
3704
3705 /* patch 10M & ALDPS */
3706 rtl_writephy(tp, 0x1f, 0x0bcc);
3707 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3708 rtl_writephy(tp, 0x1f, 0x0a44);
3709 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3710 rtl_writephy(tp, 0x1f, 0x0a43);
3711 rtl_writephy(tp, 0x13, 0x8084);
3712 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3713 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3714 rtl_writephy(tp, 0x1f, 0x0000);
3715
3716 /* Enable EEE auto-fallback function */
3717 rtl_writephy(tp, 0x1f, 0x0a4b);
3718 rtl_w0w1_phy(tp, 0x11, 0x0004, 0x0000);
3719 rtl_writephy(tp, 0x1f, 0x0000);
3720
3721 /* Enable UC LPF tune function */
3722 rtl_writephy(tp, 0x1f, 0x0a43);
3723 rtl_writephy(tp, 0x13, 0x8012);
3724 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3725 rtl_writephy(tp, 0x1f, 0x0000);
3726
3727 /* set rg_sel_sdm_rate */
3728 rtl_writephy(tp, 0x1f, 0x0c42);
3729 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3730 rtl_writephy(tp, 0x1f, 0x0000);
3731
3732 /* Check ALDPS bit, disable it if enabled */
3733 rtl_writephy(tp, 0x1f, 0x0a43);
3734 if (rtl_readphy(tp, 0x10) & 0x0004)
3735 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3736
3737 rtl_writephy(tp, 0x1f, 0x0000);
3738 }
3739
rtl8168ep_2_hw_phy_config(struct rtl8169_private * tp)3740 static void rtl8168ep_2_hw_phy_config(struct rtl8169_private *tp)
3741 {
3742 /* patch 10M & ALDPS */
3743 rtl_writephy(tp, 0x1f, 0x0bcc);
3744 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x0100);
3745 rtl_writephy(tp, 0x1f, 0x0a44);
3746 rtl_w0w1_phy(tp, 0x11, 0x00c0, 0x0000);
3747 rtl_writephy(tp, 0x1f, 0x0a43);
3748 rtl_writephy(tp, 0x13, 0x8084);
3749 rtl_w0w1_phy(tp, 0x14, 0x0000, 0x6000);
3750 rtl_w0w1_phy(tp, 0x10, 0x1003, 0x0000);
3751 rtl_writephy(tp, 0x1f, 0x0000);
3752
3753 /* Enable UC LPF tune function */
3754 rtl_writephy(tp, 0x1f, 0x0a43);
3755 rtl_writephy(tp, 0x13, 0x8012);
3756 rtl_w0w1_phy(tp, 0x14, 0x8000, 0x0000);
3757 rtl_writephy(tp, 0x1f, 0x0000);
3758
3759 /* Set rg_sel_sdm_rate */
3760 rtl_writephy(tp, 0x1f, 0x0c42);
3761 rtl_w0w1_phy(tp, 0x11, 0x4000, 0x2000);
3762 rtl_writephy(tp, 0x1f, 0x0000);
3763
3764 /* Channel estimation parameters */
3765 rtl_writephy(tp, 0x1f, 0x0a43);
3766 rtl_writephy(tp, 0x13, 0x80f3);
3767 rtl_w0w1_phy(tp, 0x14, 0x8b00, ~0x8bff);
3768 rtl_writephy(tp, 0x13, 0x80f0);
3769 rtl_w0w1_phy(tp, 0x14, 0x3a00, ~0x3aff);
3770 rtl_writephy(tp, 0x13, 0x80ef);
3771 rtl_w0w1_phy(tp, 0x14, 0x0500, ~0x05ff);
3772 rtl_writephy(tp, 0x13, 0x80f6);
3773 rtl_w0w1_phy(tp, 0x14, 0x6e00, ~0x6eff);
3774 rtl_writephy(tp, 0x13, 0x80ec);
3775 rtl_w0w1_phy(tp, 0x14, 0x6800, ~0x68ff);
3776 rtl_writephy(tp, 0x13, 0x80ed);
3777 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3778 rtl_writephy(tp, 0x13, 0x80f2);
3779 rtl_w0w1_phy(tp, 0x14, 0xf400, ~0xf4ff);
3780 rtl_writephy(tp, 0x13, 0x80f4);
3781 rtl_w0w1_phy(tp, 0x14, 0x8500, ~0x85ff);
3782 rtl_writephy(tp, 0x1f, 0x0a43);
3783 rtl_writephy(tp, 0x13, 0x8110);
3784 rtl_w0w1_phy(tp, 0x14, 0xa800, ~0xa8ff);
3785 rtl_writephy(tp, 0x13, 0x810f);
3786 rtl_w0w1_phy(tp, 0x14, 0x1d00, ~0x1dff);
3787 rtl_writephy(tp, 0x13, 0x8111);
3788 rtl_w0w1_phy(tp, 0x14, 0xf500, ~0xf5ff);
3789 rtl_writephy(tp, 0x13, 0x8113);
3790 rtl_w0w1_phy(tp, 0x14, 0x6100, ~0x61ff);
3791 rtl_writephy(tp, 0x13, 0x8115);
3792 rtl_w0w1_phy(tp, 0x14, 0x9200, ~0x92ff);
3793 rtl_writephy(tp, 0x13, 0x810e);
3794 rtl_w0w1_phy(tp, 0x14, 0x0400, ~0x04ff);
3795 rtl_writephy(tp, 0x13, 0x810c);
3796 rtl_w0w1_phy(tp, 0x14, 0x7c00, ~0x7cff);
3797 rtl_writephy(tp, 0x13, 0x810b);
3798 rtl_w0w1_phy(tp, 0x14, 0x5a00, ~0x5aff);
3799 rtl_writephy(tp, 0x1f, 0x0a43);
3800 rtl_writephy(tp, 0x13, 0x80d1);
3801 rtl_w0w1_phy(tp, 0x14, 0xff00, ~0xffff);
3802 rtl_writephy(tp, 0x13, 0x80cd);
3803 rtl_w0w1_phy(tp, 0x14, 0x9e00, ~0x9eff);
3804 rtl_writephy(tp, 0x13, 0x80d3);
3805 rtl_w0w1_phy(tp, 0x14, 0x0e00, ~0x0eff);
3806 rtl_writephy(tp, 0x13, 0x80d5);
3807 rtl_w0w1_phy(tp, 0x14, 0xca00, ~0xcaff);
3808 rtl_writephy(tp, 0x13, 0x80d7);
3809 rtl_w0w1_phy(tp, 0x14, 0x8400, ~0x84ff);
3810
3811 /* Force PWM-mode */
3812 rtl_writephy(tp, 0x1f, 0x0bcd);
3813 rtl_writephy(tp, 0x14, 0x5065);
3814 rtl_writephy(tp, 0x14, 0xd065);
3815 rtl_writephy(tp, 0x1f, 0x0bc8);
3816 rtl_writephy(tp, 0x12, 0x00ed);
3817 rtl_writephy(tp, 0x1f, 0x0bcd);
3818 rtl_writephy(tp, 0x14, 0x1065);
3819 rtl_writephy(tp, 0x14, 0x9065);
3820 rtl_writephy(tp, 0x14, 0x1065);
3821 rtl_writephy(tp, 0x1f, 0x0000);
3822
3823 /* Check ALDPS bit, disable it if enabled */
3824 rtl_writephy(tp, 0x1f, 0x0a43);
3825 if (rtl_readphy(tp, 0x10) & 0x0004)
3826 rtl_w0w1_phy(tp, 0x10, 0x0000, 0x0004);
3827
3828 rtl_writephy(tp, 0x1f, 0x0000);
3829 }
3830
rtl8102e_hw_phy_config(struct rtl8169_private * tp)3831 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
3832 {
3833 static const struct phy_reg phy_reg_init[] = {
3834 { 0x1f, 0x0003 },
3835 { 0x08, 0x441d },
3836 { 0x01, 0x9100 },
3837 { 0x1f, 0x0000 }
3838 };
3839
3840 rtl_writephy(tp, 0x1f, 0x0000);
3841 rtl_patchphy(tp, 0x11, 1 << 12);
3842 rtl_patchphy(tp, 0x19, 1 << 13);
3843 rtl_patchphy(tp, 0x10, 1 << 15);
3844
3845 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3846 }
3847
rtl8105e_hw_phy_config(struct rtl8169_private * tp)3848 static void rtl8105e_hw_phy_config(struct rtl8169_private *tp)
3849 {
3850 static const struct phy_reg phy_reg_init[] = {
3851 { 0x1f, 0x0005 },
3852 { 0x1a, 0x0000 },
3853 { 0x1f, 0x0000 },
3854
3855 { 0x1f, 0x0004 },
3856 { 0x1c, 0x0000 },
3857 { 0x1f, 0x0000 },
3858
3859 { 0x1f, 0x0001 },
3860 { 0x15, 0x7701 },
3861 { 0x1f, 0x0000 }
3862 };
3863
3864 /* Disable ALDPS before ram code */
3865 rtl_writephy(tp, 0x1f, 0x0000);
3866 rtl_writephy(tp, 0x18, 0x0310);
3867 msleep(100);
3868
3869 rtl_apply_firmware(tp);
3870
3871 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3872 }
3873
rtl8402_hw_phy_config(struct rtl8169_private * tp)3874 static void rtl8402_hw_phy_config(struct rtl8169_private *tp)
3875 {
3876 /* Disable ALDPS before setting firmware */
3877 rtl_writephy(tp, 0x1f, 0x0000);
3878 rtl_writephy(tp, 0x18, 0x0310);
3879 msleep(20);
3880
3881 rtl_apply_firmware(tp);
3882
3883 /* EEE setting */
3884 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3885 rtl_writephy(tp, 0x1f, 0x0004);
3886 rtl_writephy(tp, 0x10, 0x401f);
3887 rtl_writephy(tp, 0x19, 0x7030);
3888 rtl_writephy(tp, 0x1f, 0x0000);
3889 }
3890
rtl8106e_hw_phy_config(struct rtl8169_private * tp)3891 static void rtl8106e_hw_phy_config(struct rtl8169_private *tp)
3892 {
3893 static const struct phy_reg phy_reg_init[] = {
3894 { 0x1f, 0x0004 },
3895 { 0x10, 0xc07f },
3896 { 0x19, 0x7030 },
3897 { 0x1f, 0x0000 }
3898 };
3899
3900 /* Disable ALDPS before ram code */
3901 rtl_writephy(tp, 0x1f, 0x0000);
3902 rtl_writephy(tp, 0x18, 0x0310);
3903 msleep(100);
3904
3905 rtl_apply_firmware(tp);
3906
3907 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3908 rtl_writephy_batch(tp, phy_reg_init, ARRAY_SIZE(phy_reg_init));
3909
3910 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
3911 }
3912
rtl_hw_phy_config(struct net_device * dev)3913 static void rtl_hw_phy_config(struct net_device *dev)
3914 {
3915 struct rtl8169_private *tp = netdev_priv(dev);
3916
3917 rtl8169_print_mac_version(tp);
3918
3919 switch (tp->mac_version) {
3920 case RTL_GIGA_MAC_VER_01:
3921 break;
3922 case RTL_GIGA_MAC_VER_02:
3923 case RTL_GIGA_MAC_VER_03:
3924 rtl8169s_hw_phy_config(tp);
3925 break;
3926 case RTL_GIGA_MAC_VER_04:
3927 rtl8169sb_hw_phy_config(tp);
3928 break;
3929 case RTL_GIGA_MAC_VER_05:
3930 rtl8169scd_hw_phy_config(tp);
3931 break;
3932 case RTL_GIGA_MAC_VER_06:
3933 rtl8169sce_hw_phy_config(tp);
3934 break;
3935 case RTL_GIGA_MAC_VER_07:
3936 case RTL_GIGA_MAC_VER_08:
3937 case RTL_GIGA_MAC_VER_09:
3938 rtl8102e_hw_phy_config(tp);
3939 break;
3940 case RTL_GIGA_MAC_VER_11:
3941 rtl8168bb_hw_phy_config(tp);
3942 break;
3943 case RTL_GIGA_MAC_VER_12:
3944 rtl8168bef_hw_phy_config(tp);
3945 break;
3946 case RTL_GIGA_MAC_VER_17:
3947 rtl8168bef_hw_phy_config(tp);
3948 break;
3949 case RTL_GIGA_MAC_VER_18:
3950 rtl8168cp_1_hw_phy_config(tp);
3951 break;
3952 case RTL_GIGA_MAC_VER_19:
3953 rtl8168c_1_hw_phy_config(tp);
3954 break;
3955 case RTL_GIGA_MAC_VER_20:
3956 rtl8168c_2_hw_phy_config(tp);
3957 break;
3958 case RTL_GIGA_MAC_VER_21:
3959 rtl8168c_3_hw_phy_config(tp);
3960 break;
3961 case RTL_GIGA_MAC_VER_22:
3962 rtl8168c_4_hw_phy_config(tp);
3963 break;
3964 case RTL_GIGA_MAC_VER_23:
3965 case RTL_GIGA_MAC_VER_24:
3966 rtl8168cp_2_hw_phy_config(tp);
3967 break;
3968 case RTL_GIGA_MAC_VER_25:
3969 rtl8168d_1_hw_phy_config(tp);
3970 break;
3971 case RTL_GIGA_MAC_VER_26:
3972 rtl8168d_2_hw_phy_config(tp);
3973 break;
3974 case RTL_GIGA_MAC_VER_27:
3975 rtl8168d_3_hw_phy_config(tp);
3976 break;
3977 case RTL_GIGA_MAC_VER_28:
3978 rtl8168d_4_hw_phy_config(tp);
3979 break;
3980 case RTL_GIGA_MAC_VER_29:
3981 case RTL_GIGA_MAC_VER_30:
3982 rtl8105e_hw_phy_config(tp);
3983 break;
3984 case RTL_GIGA_MAC_VER_31:
3985 /* None. */
3986 break;
3987 case RTL_GIGA_MAC_VER_32:
3988 case RTL_GIGA_MAC_VER_33:
3989 rtl8168e_1_hw_phy_config(tp);
3990 break;
3991 case RTL_GIGA_MAC_VER_34:
3992 rtl8168e_2_hw_phy_config(tp);
3993 break;
3994 case RTL_GIGA_MAC_VER_35:
3995 rtl8168f_1_hw_phy_config(tp);
3996 break;
3997 case RTL_GIGA_MAC_VER_36:
3998 rtl8168f_2_hw_phy_config(tp);
3999 break;
4000
4001 case RTL_GIGA_MAC_VER_37:
4002 rtl8402_hw_phy_config(tp);
4003 break;
4004
4005 case RTL_GIGA_MAC_VER_38:
4006 rtl8411_hw_phy_config(tp);
4007 break;
4008
4009 case RTL_GIGA_MAC_VER_39:
4010 rtl8106e_hw_phy_config(tp);
4011 break;
4012
4013 case RTL_GIGA_MAC_VER_40:
4014 rtl8168g_1_hw_phy_config(tp);
4015 break;
4016 case RTL_GIGA_MAC_VER_42:
4017 case RTL_GIGA_MAC_VER_43:
4018 case RTL_GIGA_MAC_VER_44:
4019 rtl8168g_2_hw_phy_config(tp);
4020 break;
4021 case RTL_GIGA_MAC_VER_45:
4022 case RTL_GIGA_MAC_VER_47:
4023 rtl8168h_1_hw_phy_config(tp);
4024 break;
4025 case RTL_GIGA_MAC_VER_46:
4026 case RTL_GIGA_MAC_VER_48:
4027 rtl8168h_2_hw_phy_config(tp);
4028 break;
4029
4030 case RTL_GIGA_MAC_VER_49:
4031 rtl8168ep_1_hw_phy_config(tp);
4032 break;
4033 case RTL_GIGA_MAC_VER_50:
4034 case RTL_GIGA_MAC_VER_51:
4035 rtl8168ep_2_hw_phy_config(tp);
4036 break;
4037
4038 case RTL_GIGA_MAC_VER_41:
4039 default:
4040 break;
4041 }
4042 }
4043
rtl_schedule_task(struct rtl8169_private * tp,enum rtl_flag flag)4044 static void rtl_schedule_task(struct rtl8169_private *tp, enum rtl_flag flag)
4045 {
4046 if (!test_and_set_bit(flag, tp->wk.flags))
4047 schedule_work(&tp->wk.work);
4048 }
4049
rtl_tbi_enabled(struct rtl8169_private * tp)4050 static bool rtl_tbi_enabled(struct rtl8169_private *tp)
4051 {
4052 return (tp->mac_version == RTL_GIGA_MAC_VER_01) &&
4053 (RTL_R8(tp, PHYstatus) & TBI_Enable);
4054 }
4055
rtl8169_init_phy(struct net_device * dev,struct rtl8169_private * tp)4056 static void rtl8169_init_phy(struct net_device *dev, struct rtl8169_private *tp)
4057 {
4058 rtl_hw_phy_config(dev);
4059
4060 if (tp->mac_version <= RTL_GIGA_MAC_VER_06) {
4061 netif_dbg(tp, drv, dev,
4062 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4063 RTL_W8(tp, 0x82, 0x01);
4064 }
4065
4066 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40);
4067
4068 if (tp->mac_version <= RTL_GIGA_MAC_VER_06)
4069 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4070
4071 if (tp->mac_version == RTL_GIGA_MAC_VER_02) {
4072 netif_dbg(tp, drv, dev,
4073 "Set MAC Reg C+CR Offset 0x82h = 0x01h\n");
4074 RTL_W8(tp, 0x82, 0x01);
4075 netif_dbg(tp, drv, dev,
4076 "Set PHY Reg 0x0bh = 0x00h\n");
4077 rtl_writephy(tp, 0x0b, 0x0000); //w 0x0b 15 0 0
4078 }
4079
4080 /* We may have called phy_speed_down before */
4081 phy_speed_up(dev->phydev);
4082
4083 genphy_soft_reset(dev->phydev);
4084
4085 /* It was reported that several chips end up with 10MBit/Half on a
4086 * 1GBit link after resuming from S3. For whatever reason the PHY on
4087 * these chips doesn't properly start a renegotiation when soft-reset.
4088 * Explicitly requesting a renegotiation fixes this.
4089 */
4090 if (dev->phydev->autoneg == AUTONEG_ENABLE)
4091 phy_restart_aneg(dev->phydev);
4092 }
4093
rtl_rar_set(struct rtl8169_private * tp,u8 * addr)4094 static void rtl_rar_set(struct rtl8169_private *tp, u8 *addr)
4095 {
4096 rtl_lock_work(tp);
4097
4098 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4099
4100 RTL_W32(tp, MAC4, addr[4] | addr[5] << 8);
4101 RTL_R32(tp, MAC4);
4102
4103 RTL_W32(tp, MAC0, addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24);
4104 RTL_R32(tp, MAC0);
4105
4106 if (tp->mac_version == RTL_GIGA_MAC_VER_34)
4107 rtl_rar_exgmac_set(tp, addr);
4108
4109 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4110
4111 rtl_unlock_work(tp);
4112 }
4113
rtl_init_rxcfg(struct rtl8169_private * tp)4114 static void rtl_init_rxcfg(struct rtl8169_private *tp)
4115 {
4116 switch (tp->mac_version) {
4117 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4118 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
4119 RTL_W32(tp, RxConfig, RX_FIFO_THRESH | RX_DMA_BURST);
4120 break;
4121 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
4122 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
4123 case RTL_GIGA_MAC_VER_38:
4124 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST);
4125 break;
4126 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4127 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_MULTI_EN | RX_DMA_BURST | RX_EARLY_OFF);
4128 break;
4129 default:
4130 RTL_W32(tp, RxConfig, RX128_INT_EN | RX_DMA_BURST);
4131 break;
4132 }
4133 }
4134
rtl_set_mac_address(struct net_device * dev,void * p)4135 static int rtl_set_mac_address(struct net_device *dev, void *p)
4136 {
4137 struct rtl8169_private *tp = netdev_priv(dev);
4138 struct device *d = tp_to_dev(tp);
4139 int ret;
4140
4141 ret = eth_mac_addr(dev, p);
4142 if (ret)
4143 return ret;
4144
4145 pm_runtime_get_noresume(d);
4146
4147 if (pm_runtime_active(d))
4148 rtl_rar_set(tp, dev->dev_addr);
4149
4150 pm_runtime_put_noidle(d);
4151
4152 /* Reportedly at least Asus X453MA truncates packets otherwise */
4153 if (tp->mac_version == RTL_GIGA_MAC_VER_37)
4154 rtl_init_rxcfg(tp);
4155
4156 return 0;
4157 }
4158
rtl8169_ioctl(struct net_device * dev,struct ifreq * ifr,int cmd)4159 static int rtl8169_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
4160 {
4161 if (!netif_running(dev))
4162 return -ENODEV;
4163
4164 return phy_mii_ioctl(dev->phydev, ifr, cmd);
4165 }
4166
rtl_init_mdio_ops(struct rtl8169_private * tp)4167 static void rtl_init_mdio_ops(struct rtl8169_private *tp)
4168 {
4169 struct mdio_ops *ops = &tp->mdio_ops;
4170
4171 switch (tp->mac_version) {
4172 case RTL_GIGA_MAC_VER_27:
4173 ops->write = r8168dp_1_mdio_write;
4174 ops->read = r8168dp_1_mdio_read;
4175 break;
4176 case RTL_GIGA_MAC_VER_28:
4177 case RTL_GIGA_MAC_VER_31:
4178 ops->write = r8168dp_2_mdio_write;
4179 ops->read = r8168dp_2_mdio_read;
4180 break;
4181 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4182 ops->write = r8168g_mdio_write;
4183 ops->read = r8168g_mdio_read;
4184 break;
4185 default:
4186 ops->write = r8169_mdio_write;
4187 ops->read = r8169_mdio_read;
4188 break;
4189 }
4190 }
4191
rtl_wol_suspend_quirk(struct rtl8169_private * tp)4192 static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
4193 {
4194 switch (tp->mac_version) {
4195 case RTL_GIGA_MAC_VER_25:
4196 case RTL_GIGA_MAC_VER_26:
4197 case RTL_GIGA_MAC_VER_29:
4198 case RTL_GIGA_MAC_VER_30:
4199 case RTL_GIGA_MAC_VER_32:
4200 case RTL_GIGA_MAC_VER_33:
4201 case RTL_GIGA_MAC_VER_34:
4202 case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_51:
4203 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) |
4204 AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
4205 break;
4206 default:
4207 break;
4208 }
4209 }
4210
rtl_wol_pll_power_down(struct rtl8169_private * tp)4211 static bool rtl_wol_pll_power_down(struct rtl8169_private *tp)
4212 {
4213 struct phy_device *phydev;
4214
4215 if (!__rtl8169_get_wol(tp))
4216 return false;
4217
4218 /* phydev may not be attached to netdevice */
4219 phydev = mdiobus_get_phy(tp->mii_bus, 0);
4220
4221 phy_speed_down(phydev, false);
4222 rtl_wol_suspend_quirk(tp);
4223
4224 return true;
4225 }
4226
r8168_pll_power_down(struct rtl8169_private * tp)4227 static void r8168_pll_power_down(struct rtl8169_private *tp)
4228 {
4229 if (r8168_check_dash(tp))
4230 return;
4231
4232 if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
4233 tp->mac_version == RTL_GIGA_MAC_VER_33)
4234 rtl_ephy_write(tp, 0x19, 0xff64);
4235
4236 if (rtl_wol_pll_power_down(tp))
4237 return;
4238
4239 switch (tp->mac_version) {
4240 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4241 case RTL_GIGA_MAC_VER_37:
4242 case RTL_GIGA_MAC_VER_39:
4243 case RTL_GIGA_MAC_VER_43:
4244 case RTL_GIGA_MAC_VER_44:
4245 case RTL_GIGA_MAC_VER_45:
4246 case RTL_GIGA_MAC_VER_46:
4247 case RTL_GIGA_MAC_VER_47:
4248 case RTL_GIGA_MAC_VER_48:
4249 case RTL_GIGA_MAC_VER_50:
4250 case RTL_GIGA_MAC_VER_51:
4251 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4252 break;
4253 case RTL_GIGA_MAC_VER_40:
4254 case RTL_GIGA_MAC_VER_41:
4255 case RTL_GIGA_MAC_VER_49:
4256 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0x00000000,
4257 0xfc000000, ERIAR_EXGMAC);
4258 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) & ~0x80);
4259 break;
4260 }
4261 }
4262
r8168_pll_power_up(struct rtl8169_private * tp)4263 static void r8168_pll_power_up(struct rtl8169_private *tp)
4264 {
4265 switch (tp->mac_version) {
4266 case RTL_GIGA_MAC_VER_25 ... RTL_GIGA_MAC_VER_33:
4267 case RTL_GIGA_MAC_VER_37:
4268 case RTL_GIGA_MAC_VER_39:
4269 case RTL_GIGA_MAC_VER_43:
4270 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0x80);
4271 break;
4272 case RTL_GIGA_MAC_VER_44:
4273 case RTL_GIGA_MAC_VER_45:
4274 case RTL_GIGA_MAC_VER_46:
4275 case RTL_GIGA_MAC_VER_47:
4276 case RTL_GIGA_MAC_VER_48:
4277 case RTL_GIGA_MAC_VER_50:
4278 case RTL_GIGA_MAC_VER_51:
4279 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4280 break;
4281 case RTL_GIGA_MAC_VER_40:
4282 case RTL_GIGA_MAC_VER_41:
4283 case RTL_GIGA_MAC_VER_49:
4284 RTL_W8(tp, PMCH, RTL_R8(tp, PMCH) | 0xc0);
4285 rtl_w0w1_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
4286 0x00000000, ERIAR_EXGMAC);
4287 break;
4288 }
4289
4290 phy_resume(tp->dev->phydev);
4291 /* give MAC/PHY some time to resume */
4292 msleep(20);
4293 }
4294
rtl_pll_power_down(struct rtl8169_private * tp)4295 static void rtl_pll_power_down(struct rtl8169_private *tp)
4296 {
4297 switch (tp->mac_version) {
4298 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4299 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4300 break;
4301 default:
4302 r8168_pll_power_down(tp);
4303 }
4304 }
4305
rtl_pll_power_up(struct rtl8169_private * tp)4306 static void rtl_pll_power_up(struct rtl8169_private *tp)
4307 {
4308 switch (tp->mac_version) {
4309 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
4310 case RTL_GIGA_MAC_VER_13 ... RTL_GIGA_MAC_VER_15:
4311 break;
4312 default:
4313 r8168_pll_power_up(tp);
4314 }
4315 }
4316
rtl8169_init_ring_indexes(struct rtl8169_private * tp)4317 static void rtl8169_init_ring_indexes(struct rtl8169_private *tp)
4318 {
4319 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0;
4320 }
4321
rtl_hw_jumbo_enable(struct rtl8169_private * tp)4322 static void rtl_hw_jumbo_enable(struct rtl8169_private *tp)
4323 {
4324 if (tp->jumbo_ops.enable) {
4325 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4326 tp->jumbo_ops.enable(tp);
4327 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4328 }
4329 }
4330
rtl_hw_jumbo_disable(struct rtl8169_private * tp)4331 static void rtl_hw_jumbo_disable(struct rtl8169_private *tp)
4332 {
4333 if (tp->jumbo_ops.disable) {
4334 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4335 tp->jumbo_ops.disable(tp);
4336 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4337 }
4338 }
4339
r8168c_hw_jumbo_enable(struct rtl8169_private * tp)4340 static void r8168c_hw_jumbo_enable(struct rtl8169_private *tp)
4341 {
4342 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4343 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | Jumbo_En1);
4344 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4345 }
4346
r8168c_hw_jumbo_disable(struct rtl8169_private * tp)4347 static void r8168c_hw_jumbo_disable(struct rtl8169_private *tp)
4348 {
4349 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4350 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~Jumbo_En1);
4351 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4352 }
4353
r8168dp_hw_jumbo_enable(struct rtl8169_private * tp)4354 static void r8168dp_hw_jumbo_enable(struct rtl8169_private *tp)
4355 {
4356 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4357 }
4358
r8168dp_hw_jumbo_disable(struct rtl8169_private * tp)4359 static void r8168dp_hw_jumbo_disable(struct rtl8169_private *tp)
4360 {
4361 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4362 }
4363
r8168e_hw_jumbo_enable(struct rtl8169_private * tp)4364 static void r8168e_hw_jumbo_enable(struct rtl8169_private *tp)
4365 {
4366 RTL_W8(tp, MaxTxPacketSize, 0x3f);
4367 RTL_W8(tp, Config3, RTL_R8(tp, Config3) | Jumbo_En0);
4368 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | 0x01);
4369 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_512B);
4370 }
4371
r8168e_hw_jumbo_disable(struct rtl8169_private * tp)4372 static void r8168e_hw_jumbo_disable(struct rtl8169_private *tp)
4373 {
4374 RTL_W8(tp, MaxTxPacketSize, 0x0c);
4375 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Jumbo_En0);
4376 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~0x01);
4377 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4378 }
4379
r8168b_0_hw_jumbo_enable(struct rtl8169_private * tp)4380 static void r8168b_0_hw_jumbo_enable(struct rtl8169_private *tp)
4381 {
4382 rtl_tx_performance_tweak(tp,
4383 PCI_EXP_DEVCTL_READRQ_512B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4384 }
4385
r8168b_0_hw_jumbo_disable(struct rtl8169_private * tp)4386 static void r8168b_0_hw_jumbo_disable(struct rtl8169_private *tp)
4387 {
4388 rtl_tx_performance_tweak(tp,
4389 PCI_EXP_DEVCTL_READRQ_4096B | PCI_EXP_DEVCTL_NOSNOOP_EN);
4390 }
4391
r8168b_1_hw_jumbo_enable(struct rtl8169_private * tp)4392 static void r8168b_1_hw_jumbo_enable(struct rtl8169_private *tp)
4393 {
4394 r8168b_0_hw_jumbo_enable(tp);
4395
4396 RTL_W8(tp, Config4, RTL_R8(tp, Config4) | (1 << 0));
4397 }
4398
r8168b_1_hw_jumbo_disable(struct rtl8169_private * tp)4399 static void r8168b_1_hw_jumbo_disable(struct rtl8169_private *tp)
4400 {
4401 r8168b_0_hw_jumbo_disable(tp);
4402
4403 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4404 }
4405
rtl_init_jumbo_ops(struct rtl8169_private * tp)4406 static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
4407 {
4408 struct jumbo_ops *ops = &tp->jumbo_ops;
4409
4410 switch (tp->mac_version) {
4411 case RTL_GIGA_MAC_VER_11:
4412 ops->disable = r8168b_0_hw_jumbo_disable;
4413 ops->enable = r8168b_0_hw_jumbo_enable;
4414 break;
4415 case RTL_GIGA_MAC_VER_12:
4416 case RTL_GIGA_MAC_VER_17:
4417 ops->disable = r8168b_1_hw_jumbo_disable;
4418 ops->enable = r8168b_1_hw_jumbo_enable;
4419 break;
4420 case RTL_GIGA_MAC_VER_18: /* Wild guess. Needs info from Realtek. */
4421 case RTL_GIGA_MAC_VER_19:
4422 case RTL_GIGA_MAC_VER_20:
4423 case RTL_GIGA_MAC_VER_21: /* Wild guess. Needs info from Realtek. */
4424 case RTL_GIGA_MAC_VER_22:
4425 case RTL_GIGA_MAC_VER_23:
4426 case RTL_GIGA_MAC_VER_24:
4427 case RTL_GIGA_MAC_VER_25:
4428 case RTL_GIGA_MAC_VER_26:
4429 ops->disable = r8168c_hw_jumbo_disable;
4430 ops->enable = r8168c_hw_jumbo_enable;
4431 break;
4432 case RTL_GIGA_MAC_VER_27:
4433 case RTL_GIGA_MAC_VER_28:
4434 ops->disable = r8168dp_hw_jumbo_disable;
4435 ops->enable = r8168dp_hw_jumbo_enable;
4436 break;
4437 case RTL_GIGA_MAC_VER_31: /* Wild guess. Needs info from Realtek. */
4438 case RTL_GIGA_MAC_VER_32:
4439 case RTL_GIGA_MAC_VER_33:
4440 case RTL_GIGA_MAC_VER_34:
4441 ops->disable = r8168e_hw_jumbo_disable;
4442 ops->enable = r8168e_hw_jumbo_enable;
4443 break;
4444
4445 /*
4446 * No action needed for jumbo frames with 8169.
4447 * No jumbo for 810x at all.
4448 */
4449 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4450 default:
4451 ops->disable = NULL;
4452 ops->enable = NULL;
4453 break;
4454 }
4455 }
4456
DECLARE_RTL_COND(rtl_chipcmd_cond)4457 DECLARE_RTL_COND(rtl_chipcmd_cond)
4458 {
4459 return RTL_R8(tp, ChipCmd) & CmdReset;
4460 }
4461
rtl_hw_reset(struct rtl8169_private * tp)4462 static void rtl_hw_reset(struct rtl8169_private *tp)
4463 {
4464 RTL_W8(tp, ChipCmd, CmdReset);
4465
4466 rtl_udelay_loop_wait_low(tp, &rtl_chipcmd_cond, 100, 100);
4467 }
4468
rtl_request_uncached_firmware(struct rtl8169_private * tp)4469 static void rtl_request_uncached_firmware(struct rtl8169_private *tp)
4470 {
4471 struct rtl_fw *rtl_fw;
4472 const char *name;
4473 int rc = -ENOMEM;
4474
4475 name = rtl_lookup_firmware_name(tp);
4476 if (!name)
4477 goto out_no_firmware;
4478
4479 rtl_fw = kzalloc(sizeof(*rtl_fw), GFP_KERNEL);
4480 if (!rtl_fw)
4481 goto err_warn;
4482
4483 rc = request_firmware(&rtl_fw->fw, name, tp_to_dev(tp));
4484 if (rc < 0)
4485 goto err_free;
4486
4487 rc = rtl_check_firmware(tp, rtl_fw);
4488 if (rc < 0)
4489 goto err_release_firmware;
4490
4491 tp->rtl_fw = rtl_fw;
4492 out:
4493 return;
4494
4495 err_release_firmware:
4496 release_firmware(rtl_fw->fw);
4497 err_free:
4498 kfree(rtl_fw);
4499 err_warn:
4500 netif_warn(tp, ifup, tp->dev, "unable to load firmware patch %s (%d)\n",
4501 name, rc);
4502 out_no_firmware:
4503 tp->rtl_fw = NULL;
4504 goto out;
4505 }
4506
rtl_request_firmware(struct rtl8169_private * tp)4507 static void rtl_request_firmware(struct rtl8169_private *tp)
4508 {
4509 if (IS_ERR(tp->rtl_fw))
4510 rtl_request_uncached_firmware(tp);
4511 }
4512
rtl_rx_close(struct rtl8169_private * tp)4513 static void rtl_rx_close(struct rtl8169_private *tp)
4514 {
4515 RTL_W32(tp, RxConfig, RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK);
4516 }
4517
DECLARE_RTL_COND(rtl_npq_cond)4518 DECLARE_RTL_COND(rtl_npq_cond)
4519 {
4520 return RTL_R8(tp, TxPoll) & NPQ;
4521 }
4522
DECLARE_RTL_COND(rtl_txcfg_empty_cond)4523 DECLARE_RTL_COND(rtl_txcfg_empty_cond)
4524 {
4525 return RTL_R32(tp, TxConfig) & TXCFG_EMPTY;
4526 }
4527
rtl8169_hw_reset(struct rtl8169_private * tp)4528 static void rtl8169_hw_reset(struct rtl8169_private *tp)
4529 {
4530 /* Disable interrupts */
4531 rtl8169_irq_mask_and_ack(tp);
4532
4533 rtl_rx_close(tp);
4534
4535 switch (tp->mac_version) {
4536 case RTL_GIGA_MAC_VER_27:
4537 case RTL_GIGA_MAC_VER_28:
4538 case RTL_GIGA_MAC_VER_31:
4539 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
4540 break;
4541 case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_38:
4542 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
4543 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4544 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
4545 break;
4546 default:
4547 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) | StopReq);
4548 udelay(100);
4549 break;
4550 }
4551
4552 rtl_hw_reset(tp);
4553 }
4554
rtl_set_tx_config_registers(struct rtl8169_private * tp)4555 static void rtl_set_tx_config_registers(struct rtl8169_private *tp)
4556 {
4557 u32 val = TX_DMA_BURST << TxDMAShift |
4558 InterFrameGap << TxInterFrameGapShift;
4559
4560 if (tp->mac_version >= RTL_GIGA_MAC_VER_34 &&
4561 tp->mac_version != RTL_GIGA_MAC_VER_39)
4562 val |= TXCFG_AUTO_FIFO;
4563
4564 RTL_W32(tp, TxConfig, val);
4565 }
4566
rtl_set_rx_max_size(struct rtl8169_private * tp)4567 static void rtl_set_rx_max_size(struct rtl8169_private *tp)
4568 {
4569 /* Low hurts. Let's disable the filtering. */
4570 RTL_W16(tp, RxMaxSize, R8169_RX_BUF_SIZE + 1);
4571 }
4572
rtl_set_rx_tx_desc_registers(struct rtl8169_private * tp)4573 static void rtl_set_rx_tx_desc_registers(struct rtl8169_private *tp)
4574 {
4575 /*
4576 * Magic spell: some iop3xx ARM board needs the TxDescAddrHigh
4577 * register to be written before TxDescAddrLow to work.
4578 * Switching from MMIO to I/O access fixes the issue as well.
4579 */
4580 RTL_W32(tp, TxDescStartAddrHigh, ((u64) tp->TxPhyAddr) >> 32);
4581 RTL_W32(tp, TxDescStartAddrLow, ((u64) tp->TxPhyAddr) & DMA_BIT_MASK(32));
4582 RTL_W32(tp, RxDescAddrHigh, ((u64) tp->RxPhyAddr) >> 32);
4583 RTL_W32(tp, RxDescAddrLow, ((u64) tp->RxPhyAddr) & DMA_BIT_MASK(32));
4584 }
4585
rtl8169_set_magic_reg(struct rtl8169_private * tp,unsigned mac_version)4586 static void rtl8169_set_magic_reg(struct rtl8169_private *tp, unsigned mac_version)
4587 {
4588 static const struct rtl_cfg2_info {
4589 u32 mac_version;
4590 u32 clk;
4591 u32 val;
4592 } cfg2_info [] = {
4593 { RTL_GIGA_MAC_VER_05, PCI_Clock_33MHz, 0x000fff00 }, // 8110SCd
4594 { RTL_GIGA_MAC_VER_05, PCI_Clock_66MHz, 0x000fffff },
4595 { RTL_GIGA_MAC_VER_06, PCI_Clock_33MHz, 0x00ffff00 }, // 8110SCe
4596 { RTL_GIGA_MAC_VER_06, PCI_Clock_66MHz, 0x00ffffff }
4597 };
4598 const struct rtl_cfg2_info *p = cfg2_info;
4599 unsigned int i;
4600 u32 clk;
4601
4602 clk = RTL_R8(tp, Config2) & PCI_Clock_66MHz;
4603 for (i = 0; i < ARRAY_SIZE(cfg2_info); i++, p++) {
4604 if ((p->mac_version == mac_version) && (p->clk == clk)) {
4605 RTL_W32(tp, 0x7c, p->val);
4606 break;
4607 }
4608 }
4609 }
4610
rtl_set_rx_mode(struct net_device * dev)4611 static void rtl_set_rx_mode(struct net_device *dev)
4612 {
4613 struct rtl8169_private *tp = netdev_priv(dev);
4614 u32 mc_filter[2]; /* Multicast hash filter */
4615 int rx_mode;
4616 u32 tmp = 0;
4617
4618 if (dev->flags & IFF_PROMISC) {
4619 /* Unconditionally log net taps. */
4620 netif_notice(tp, link, dev, "Promiscuous mode enabled\n");
4621 rx_mode =
4622 AcceptBroadcast | AcceptMulticast | AcceptMyPhys |
4623 AcceptAllPhys;
4624 mc_filter[1] = mc_filter[0] = 0xffffffff;
4625 } else if ((netdev_mc_count(dev) > multicast_filter_limit) ||
4626 (dev->flags & IFF_ALLMULTI)) {
4627 /* Too many to filter perfectly -- accept all multicasts. */
4628 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
4629 mc_filter[1] = mc_filter[0] = 0xffffffff;
4630 } else {
4631 struct netdev_hw_addr *ha;
4632
4633 rx_mode = AcceptBroadcast | AcceptMyPhys;
4634 mc_filter[1] = mc_filter[0] = 0;
4635 netdev_for_each_mc_addr(ha, dev) {
4636 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
4637 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
4638 rx_mode |= AcceptMulticast;
4639 }
4640 }
4641
4642 if (dev->features & NETIF_F_RXALL)
4643 rx_mode |= (AcceptErr | AcceptRunt);
4644
4645 tmp = (RTL_R32(tp, RxConfig) & ~RX_CONFIG_ACCEPT_MASK) | rx_mode;
4646
4647 if (tp->mac_version > RTL_GIGA_MAC_VER_06) {
4648 u32 data = mc_filter[0];
4649
4650 mc_filter[0] = swab32(mc_filter[1]);
4651 mc_filter[1] = swab32(data);
4652 }
4653
4654 if (tp->mac_version == RTL_GIGA_MAC_VER_35)
4655 mc_filter[1] = mc_filter[0] = 0xffffffff;
4656
4657 RTL_W32(tp, MAR0 + 4, mc_filter[1]);
4658 RTL_W32(tp, MAR0 + 0, mc_filter[0]);
4659
4660 RTL_W32(tp, RxConfig, tmp);
4661 }
4662
rtl_hw_start(struct rtl8169_private * tp)4663 static void rtl_hw_start(struct rtl8169_private *tp)
4664 {
4665 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
4666
4667 tp->hw_start(tp);
4668
4669 rtl_set_rx_max_size(tp);
4670 rtl_set_rx_tx_desc_registers(tp);
4671 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
4672
4673 /* Initially a 10 us delay. Turned it into a PCI commit. - FR */
4674 RTL_R8(tp, IntrMask);
4675 RTL_W8(tp, ChipCmd, CmdTxEnb | CmdRxEnb);
4676 rtl_init_rxcfg(tp);
4677 rtl_set_tx_config_registers(tp);
4678
4679 rtl_set_rx_mode(tp->dev);
4680 /* no early-rx interrupts */
4681 RTL_W16(tp, MultiIntr, RTL_R16(tp, MultiIntr) & 0xf000);
4682 rtl_irq_enable_all(tp);
4683 }
4684
rtl_hw_start_8169(struct rtl8169_private * tp)4685 static void rtl_hw_start_8169(struct rtl8169_private *tp)
4686 {
4687 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
4688 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08);
4689
4690 RTL_W8(tp, EarlyTxThres, NoEarlyTx);
4691
4692 tp->cp_cmd |= PCIMulRW;
4693
4694 if (tp->mac_version == RTL_GIGA_MAC_VER_02 ||
4695 tp->mac_version == RTL_GIGA_MAC_VER_03) {
4696 netif_dbg(tp, drv, tp->dev,
4697 "Set MAC Reg C+CR Offset 0xe0. Bit 3 and Bit 14 MUST be 1\n");
4698 tp->cp_cmd |= (1 << 14);
4699 }
4700
4701 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4702
4703 rtl8169_set_magic_reg(tp, tp->mac_version);
4704
4705 /*
4706 * Undocumented corner. Supposedly:
4707 * (TxTimer << 12) | (TxPackets << 8) | (RxTimer << 4) | RxPackets
4708 */
4709 RTL_W16(tp, IntrMitigate, 0x0000);
4710
4711 RTL_W32(tp, RxMissed, 0);
4712 }
4713
DECLARE_RTL_COND(rtl_csiar_cond)4714 DECLARE_RTL_COND(rtl_csiar_cond)
4715 {
4716 return RTL_R32(tp, CSIAR) & CSIAR_FLAG;
4717 }
4718
rtl_csi_write(struct rtl8169_private * tp,int addr,int value)4719 static void rtl_csi_write(struct rtl8169_private *tp, int addr, int value)
4720 {
4721 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4722
4723 RTL_W32(tp, CSIDR, value);
4724 RTL_W32(tp, CSIAR, CSIAR_WRITE_CMD | (addr & CSIAR_ADDR_MASK) |
4725 CSIAR_BYTE_ENABLE | func << 16);
4726
4727 rtl_udelay_loop_wait_low(tp, &rtl_csiar_cond, 10, 100);
4728 }
4729
rtl_csi_read(struct rtl8169_private * tp,int addr)4730 static u32 rtl_csi_read(struct rtl8169_private *tp, int addr)
4731 {
4732 u32 func = PCI_FUNC(tp->pci_dev->devfn);
4733
4734 RTL_W32(tp, CSIAR, (addr & CSIAR_ADDR_MASK) | func << 16 |
4735 CSIAR_BYTE_ENABLE);
4736
4737 return rtl_udelay_loop_wait_high(tp, &rtl_csiar_cond, 10, 100) ?
4738 RTL_R32(tp, CSIDR) : ~0;
4739 }
4740
rtl_csi_access_enable(struct rtl8169_private * tp,u8 val)4741 static void rtl_csi_access_enable(struct rtl8169_private *tp, u8 val)
4742 {
4743 struct pci_dev *pdev = tp->pci_dev;
4744 u32 csi;
4745
4746 /* According to Realtek the value at config space address 0x070f
4747 * controls the L0s/L1 entrance latency. We try standard ECAM access
4748 * first and if it fails fall back to CSI.
4749 */
4750 if (pdev->cfg_size > 0x070f &&
4751 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL)
4752 return;
4753
4754 netdev_notice_once(tp->dev,
4755 "No native access to PCI extended config space, falling back to CSI\n");
4756 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff;
4757 rtl_csi_write(tp, 0x070c, csi | val << 24);
4758 }
4759
rtl_set_def_aspm_entry_latency(struct rtl8169_private * tp)4760 static void rtl_set_def_aspm_entry_latency(struct rtl8169_private *tp)
4761 {
4762 rtl_csi_access_enable(tp, 0x27);
4763 }
4764
4765 struct ephy_info {
4766 unsigned int offset;
4767 u16 mask;
4768 u16 bits;
4769 };
4770
rtl_ephy_init(struct rtl8169_private * tp,const struct ephy_info * e,int len)4771 static void rtl_ephy_init(struct rtl8169_private *tp, const struct ephy_info *e,
4772 int len)
4773 {
4774 u16 w;
4775
4776 while (len-- > 0) {
4777 w = (rtl_ephy_read(tp, e->offset) & ~e->mask) | e->bits;
4778 rtl_ephy_write(tp, e->offset, w);
4779 e++;
4780 }
4781 }
4782
rtl_disable_clock_request(struct rtl8169_private * tp)4783 static void rtl_disable_clock_request(struct rtl8169_private *tp)
4784 {
4785 pcie_capability_clear_word(tp->pci_dev, PCI_EXP_LNKCTL,
4786 PCI_EXP_LNKCTL_CLKREQ_EN);
4787 }
4788
rtl_enable_clock_request(struct rtl8169_private * tp)4789 static void rtl_enable_clock_request(struct rtl8169_private *tp)
4790 {
4791 pcie_capability_set_word(tp->pci_dev, PCI_EXP_LNKCTL,
4792 PCI_EXP_LNKCTL_CLKREQ_EN);
4793 }
4794
rtl_pcie_state_l2l3_enable(struct rtl8169_private * tp,bool enable)4795 static void rtl_pcie_state_l2l3_enable(struct rtl8169_private *tp, bool enable)
4796 {
4797 u8 data;
4798
4799 data = RTL_R8(tp, Config3);
4800
4801 if (enable)
4802 data |= Rdy_to_L23;
4803 else
4804 data &= ~Rdy_to_L23;
4805
4806 RTL_W8(tp, Config3, data);
4807 }
4808
rtl_hw_aspm_clkreq_enable(struct rtl8169_private * tp,bool enable)4809 static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp, bool enable)
4810 {
4811 if (enable) {
4812 RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
4813 RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
4814 } else {
4815 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
4816 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
4817 }
4818
4819 udelay(10);
4820 }
4821
rtl_hw_start_8168bb(struct rtl8169_private * tp)4822 static void rtl_hw_start_8168bb(struct rtl8169_private *tp)
4823 {
4824 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4825
4826 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4827 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4828
4829 if (tp->dev->mtu <= ETH_DATA_LEN) {
4830 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B |
4831 PCI_EXP_DEVCTL_NOSNOOP_EN);
4832 }
4833 }
4834
rtl_hw_start_8168bef(struct rtl8169_private * tp)4835 static void rtl_hw_start_8168bef(struct rtl8169_private *tp)
4836 {
4837 rtl_hw_start_8168bb(tp);
4838
4839 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4840
4841 RTL_W8(tp, Config4, RTL_R8(tp, Config4) & ~(1 << 0));
4842 }
4843
__rtl_hw_start_8168cp(struct rtl8169_private * tp)4844 static void __rtl_hw_start_8168cp(struct rtl8169_private *tp)
4845 {
4846 RTL_W8(tp, Config1, RTL_R8(tp, Config1) | Speed_down);
4847
4848 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4849
4850 if (tp->dev->mtu <= ETH_DATA_LEN)
4851 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4852
4853 rtl_disable_clock_request(tp);
4854
4855 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4856 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4857 }
4858
rtl_hw_start_8168cp_1(struct rtl8169_private * tp)4859 static void rtl_hw_start_8168cp_1(struct rtl8169_private *tp)
4860 {
4861 static const struct ephy_info e_info_8168cp[] = {
4862 { 0x01, 0, 0x0001 },
4863 { 0x02, 0x0800, 0x1000 },
4864 { 0x03, 0, 0x0042 },
4865 { 0x06, 0x0080, 0x0000 },
4866 { 0x07, 0, 0x2000 }
4867 };
4868
4869 rtl_set_def_aspm_entry_latency(tp);
4870
4871 rtl_ephy_init(tp, e_info_8168cp, ARRAY_SIZE(e_info_8168cp));
4872
4873 __rtl_hw_start_8168cp(tp);
4874 }
4875
rtl_hw_start_8168cp_2(struct rtl8169_private * tp)4876 static void rtl_hw_start_8168cp_2(struct rtl8169_private *tp)
4877 {
4878 rtl_set_def_aspm_entry_latency(tp);
4879
4880 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4881
4882 if (tp->dev->mtu <= ETH_DATA_LEN)
4883 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4884
4885 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4886 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4887 }
4888
rtl_hw_start_8168cp_3(struct rtl8169_private * tp)4889 static void rtl_hw_start_8168cp_3(struct rtl8169_private *tp)
4890 {
4891 rtl_set_def_aspm_entry_latency(tp);
4892
4893 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
4894
4895 /* Magic. */
4896 RTL_W8(tp, DBG_REG, 0x20);
4897
4898 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4899
4900 if (tp->dev->mtu <= ETH_DATA_LEN)
4901 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4902
4903 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4904 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4905 }
4906
rtl_hw_start_8168c_1(struct rtl8169_private * tp)4907 static void rtl_hw_start_8168c_1(struct rtl8169_private *tp)
4908 {
4909 static const struct ephy_info e_info_8168c_1[] = {
4910 { 0x02, 0x0800, 0x1000 },
4911 { 0x03, 0, 0x0002 },
4912 { 0x06, 0x0080, 0x0000 }
4913 };
4914
4915 rtl_set_def_aspm_entry_latency(tp);
4916
4917 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2);
4918
4919 rtl_ephy_init(tp, e_info_8168c_1, ARRAY_SIZE(e_info_8168c_1));
4920
4921 __rtl_hw_start_8168cp(tp);
4922 }
4923
rtl_hw_start_8168c_2(struct rtl8169_private * tp)4924 static void rtl_hw_start_8168c_2(struct rtl8169_private *tp)
4925 {
4926 static const struct ephy_info e_info_8168c_2[] = {
4927 { 0x01, 0, 0x0001 },
4928 { 0x03, 0x0400, 0x0220 }
4929 };
4930
4931 rtl_set_def_aspm_entry_latency(tp);
4932
4933 rtl_ephy_init(tp, e_info_8168c_2, ARRAY_SIZE(e_info_8168c_2));
4934
4935 __rtl_hw_start_8168cp(tp);
4936 }
4937
rtl_hw_start_8168c_3(struct rtl8169_private * tp)4938 static void rtl_hw_start_8168c_3(struct rtl8169_private *tp)
4939 {
4940 rtl_hw_start_8168c_2(tp);
4941 }
4942
rtl_hw_start_8168c_4(struct rtl8169_private * tp)4943 static void rtl_hw_start_8168c_4(struct rtl8169_private *tp)
4944 {
4945 rtl_set_def_aspm_entry_latency(tp);
4946
4947 __rtl_hw_start_8168cp(tp);
4948 }
4949
rtl_hw_start_8168d(struct rtl8169_private * tp)4950 static void rtl_hw_start_8168d(struct rtl8169_private *tp)
4951 {
4952 rtl_set_def_aspm_entry_latency(tp);
4953
4954 rtl_disable_clock_request(tp);
4955
4956 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4957
4958 if (tp->dev->mtu <= ETH_DATA_LEN)
4959 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4960
4961 tp->cp_cmd &= CPCMD_QUIRK_MASK;
4962 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
4963 }
4964
rtl_hw_start_8168dp(struct rtl8169_private * tp)4965 static void rtl_hw_start_8168dp(struct rtl8169_private *tp)
4966 {
4967 rtl_set_def_aspm_entry_latency(tp);
4968
4969 if (tp->dev->mtu <= ETH_DATA_LEN)
4970 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4971
4972 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4973
4974 rtl_disable_clock_request(tp);
4975 }
4976
rtl_hw_start_8168d_4(struct rtl8169_private * tp)4977 static void rtl_hw_start_8168d_4(struct rtl8169_private *tp)
4978 {
4979 static const struct ephy_info e_info_8168d_4[] = {
4980 { 0x0b, 0x0000, 0x0048 },
4981 { 0x19, 0x0020, 0x0050 },
4982 { 0x0c, 0x0100, 0x0020 }
4983 };
4984
4985 rtl_set_def_aspm_entry_latency(tp);
4986
4987 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
4988
4989 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
4990
4991 rtl_ephy_init(tp, e_info_8168d_4, ARRAY_SIZE(e_info_8168d_4));
4992
4993 rtl_enable_clock_request(tp);
4994 }
4995
rtl_hw_start_8168e_1(struct rtl8169_private * tp)4996 static void rtl_hw_start_8168e_1(struct rtl8169_private *tp)
4997 {
4998 static const struct ephy_info e_info_8168e_1[] = {
4999 { 0x00, 0x0200, 0x0100 },
5000 { 0x00, 0x0000, 0x0004 },
5001 { 0x06, 0x0002, 0x0001 },
5002 { 0x06, 0x0000, 0x0030 },
5003 { 0x07, 0x0000, 0x2000 },
5004 { 0x00, 0x0000, 0x0020 },
5005 { 0x03, 0x5800, 0x2000 },
5006 { 0x03, 0x0000, 0x0001 },
5007 { 0x01, 0x0800, 0x1000 },
5008 { 0x07, 0x0000, 0x4000 },
5009 { 0x1e, 0x0000, 0x2000 },
5010 { 0x19, 0xffff, 0xfe6c },
5011 { 0x0a, 0x0000, 0x0040 }
5012 };
5013
5014 rtl_set_def_aspm_entry_latency(tp);
5015
5016 rtl_ephy_init(tp, e_info_8168e_1, ARRAY_SIZE(e_info_8168e_1));
5017
5018 if (tp->dev->mtu <= ETH_DATA_LEN)
5019 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5020
5021 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5022
5023 rtl_disable_clock_request(tp);
5024
5025 /* Reset tx FIFO pointer */
5026 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | TXPLA_RST);
5027 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~TXPLA_RST);
5028
5029 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5030 }
5031
rtl_hw_start_8168e_2(struct rtl8169_private * tp)5032 static void rtl_hw_start_8168e_2(struct rtl8169_private *tp)
5033 {
5034 static const struct ephy_info e_info_8168e_2[] = {
5035 { 0x09, 0x0000, 0x0080 },
5036 { 0x19, 0x0000, 0x0224 }
5037 };
5038
5039 rtl_set_def_aspm_entry_latency(tp);
5040
5041 rtl_ephy_init(tp, e_info_8168e_2, ARRAY_SIZE(e_info_8168e_2));
5042
5043 if (tp->dev->mtu <= ETH_DATA_LEN)
5044 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5045
5046 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5047 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5048 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5049 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5050 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5051 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060, ERIAR_EXGMAC);
5052 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5053 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5054
5055 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5056
5057 rtl_disable_clock_request(tp);
5058
5059 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5060
5061 /* Adjust EEE LED frequency */
5062 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5063
5064 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5065 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5066 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5067
5068 rtl_hw_aspm_clkreq_enable(tp, true);
5069 }
5070
rtl_hw_start_8168f(struct rtl8169_private * tp)5071 static void rtl_hw_start_8168f(struct rtl8169_private *tp)
5072 {
5073 rtl_set_def_aspm_entry_latency(tp);
5074
5075 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5076
5077 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5078 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5079 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00100002, ERIAR_EXGMAC);
5080 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5081 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5082 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5083 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5084 rtl_w0w1_eri(tp, 0x1d0, ERIAR_MASK_0001, 0x10, 0x00, ERIAR_EXGMAC);
5085 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050, ERIAR_EXGMAC);
5086 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060, ERIAR_EXGMAC);
5087
5088 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5089
5090 rtl_disable_clock_request(tp);
5091
5092 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5093 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5094 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | PWM_EN);
5095 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~Spi_en);
5096 }
5097
rtl_hw_start_8168f_1(struct rtl8169_private * tp)5098 static void rtl_hw_start_8168f_1(struct rtl8169_private *tp)
5099 {
5100 static const struct ephy_info e_info_8168f_1[] = {
5101 { 0x06, 0x00c0, 0x0020 },
5102 { 0x08, 0x0001, 0x0002 },
5103 { 0x09, 0x0000, 0x0080 },
5104 { 0x19, 0x0000, 0x0224 }
5105 };
5106
5107 rtl_hw_start_8168f(tp);
5108
5109 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5110
5111 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0xff00, ERIAR_EXGMAC);
5112
5113 /* Adjust EEE LED frequency */
5114 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5115 }
5116
rtl_hw_start_8411(struct rtl8169_private * tp)5117 static void rtl_hw_start_8411(struct rtl8169_private *tp)
5118 {
5119 static const struct ephy_info e_info_8168f_1[] = {
5120 { 0x06, 0x00c0, 0x0020 },
5121 { 0x0f, 0xffff, 0x5200 },
5122 { 0x1e, 0x0000, 0x4000 },
5123 { 0x19, 0x0000, 0x0224 }
5124 };
5125
5126 rtl_hw_start_8168f(tp);
5127 rtl_pcie_state_l2l3_enable(tp, false);
5128
5129 rtl_ephy_init(tp, e_info_8168f_1, ARRAY_SIZE(e_info_8168f_1));
5130
5131 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0c00, 0x0000, ERIAR_EXGMAC);
5132 }
5133
rtl_hw_start_8168g(struct rtl8169_private * tp)5134 static void rtl_hw_start_8168g(struct rtl8169_private *tp)
5135 {
5136 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x080002, ERIAR_EXGMAC);
5137 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5138 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5139 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5140
5141 rtl_set_def_aspm_entry_latency(tp);
5142
5143 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5144
5145 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5146 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5147 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f, ERIAR_EXGMAC);
5148
5149 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5150 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5151
5152 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5153 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5154
5155 /* Adjust EEE LED frequency */
5156 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5157
5158 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5159 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5160
5161 rtl_pcie_state_l2l3_enable(tp, false);
5162 }
5163
rtl_hw_start_8168g_1(struct rtl8169_private * tp)5164 static void rtl_hw_start_8168g_1(struct rtl8169_private *tp)
5165 {
5166 static const struct ephy_info e_info_8168g_1[] = {
5167 { 0x00, 0x0000, 0x0008 },
5168 { 0x0c, 0x37d0, 0x0820 },
5169 { 0x1e, 0x0000, 0x0001 },
5170 { 0x19, 0x8000, 0x0000 }
5171 };
5172
5173 rtl_hw_start_8168g(tp);
5174
5175 /* disable aspm and clock request before access ephy */
5176 rtl_hw_aspm_clkreq_enable(tp, false);
5177 rtl_ephy_init(tp, e_info_8168g_1, ARRAY_SIZE(e_info_8168g_1));
5178 rtl_hw_aspm_clkreq_enable(tp, true);
5179 }
5180
rtl_hw_start_8168g_2(struct rtl8169_private * tp)5181 static void rtl_hw_start_8168g_2(struct rtl8169_private *tp)
5182 {
5183 static const struct ephy_info e_info_8168g_2[] = {
5184 { 0x00, 0x0000, 0x0008 },
5185 { 0x0c, 0x3df0, 0x0200 },
5186 { 0x19, 0xffff, 0xfc00 },
5187 { 0x1e, 0xffff, 0x20eb }
5188 };
5189
5190 rtl_hw_start_8168g(tp);
5191
5192 /* disable aspm and clock request before access ephy */
5193 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
5194 RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
5195 rtl_ephy_init(tp, e_info_8168g_2, ARRAY_SIZE(e_info_8168g_2));
5196 }
5197
rtl_hw_start_8411_2(struct rtl8169_private * tp)5198 static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
5199 {
5200 static const struct ephy_info e_info_8411_2[] = {
5201 { 0x00, 0x0000, 0x0008 },
5202 { 0x0c, 0x3df0, 0x0200 },
5203 { 0x0f, 0xffff, 0x5200 },
5204 { 0x19, 0x0020, 0x0000 },
5205 { 0x1e, 0x0000, 0x2000 }
5206 };
5207
5208 rtl_hw_start_8168g(tp);
5209
5210 /* disable aspm and clock request before access ephy */
5211 rtl_hw_aspm_clkreq_enable(tp, false);
5212 rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
5213
5214 /* The following Realtek-provided magic fixes an issue with the RX unit
5215 * getting confused after the PHY having been powered-down.
5216 */
5217 r8168_mac_ocp_write(tp, 0xFC28, 0x0000);
5218 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000);
5219 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000);
5220 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000);
5221 r8168_mac_ocp_write(tp, 0xFC30, 0x0000);
5222 r8168_mac_ocp_write(tp, 0xFC32, 0x0000);
5223 r8168_mac_ocp_write(tp, 0xFC34, 0x0000);
5224 r8168_mac_ocp_write(tp, 0xFC36, 0x0000);
5225 mdelay(3);
5226 r8168_mac_ocp_write(tp, 0xFC26, 0x0000);
5227
5228 r8168_mac_ocp_write(tp, 0xF800, 0xE008);
5229 r8168_mac_ocp_write(tp, 0xF802, 0xE00A);
5230 r8168_mac_ocp_write(tp, 0xF804, 0xE00C);
5231 r8168_mac_ocp_write(tp, 0xF806, 0xE00E);
5232 r8168_mac_ocp_write(tp, 0xF808, 0xE027);
5233 r8168_mac_ocp_write(tp, 0xF80A, 0xE04F);
5234 r8168_mac_ocp_write(tp, 0xF80C, 0xE05E);
5235 r8168_mac_ocp_write(tp, 0xF80E, 0xE065);
5236 r8168_mac_ocp_write(tp, 0xF810, 0xC602);
5237 r8168_mac_ocp_write(tp, 0xF812, 0xBE00);
5238 r8168_mac_ocp_write(tp, 0xF814, 0x0000);
5239 r8168_mac_ocp_write(tp, 0xF816, 0xC502);
5240 r8168_mac_ocp_write(tp, 0xF818, 0xBD00);
5241 r8168_mac_ocp_write(tp, 0xF81A, 0x074C);
5242 r8168_mac_ocp_write(tp, 0xF81C, 0xC302);
5243 r8168_mac_ocp_write(tp, 0xF81E, 0xBB00);
5244 r8168_mac_ocp_write(tp, 0xF820, 0x080A);
5245 r8168_mac_ocp_write(tp, 0xF822, 0x6420);
5246 r8168_mac_ocp_write(tp, 0xF824, 0x48C2);
5247 r8168_mac_ocp_write(tp, 0xF826, 0x8C20);
5248 r8168_mac_ocp_write(tp, 0xF828, 0xC516);
5249 r8168_mac_ocp_write(tp, 0xF82A, 0x64A4);
5250 r8168_mac_ocp_write(tp, 0xF82C, 0x49C0);
5251 r8168_mac_ocp_write(tp, 0xF82E, 0xF009);
5252 r8168_mac_ocp_write(tp, 0xF830, 0x74A2);
5253 r8168_mac_ocp_write(tp, 0xF832, 0x8CA5);
5254 r8168_mac_ocp_write(tp, 0xF834, 0x74A0);
5255 r8168_mac_ocp_write(tp, 0xF836, 0xC50E);
5256 r8168_mac_ocp_write(tp, 0xF838, 0x9CA2);
5257 r8168_mac_ocp_write(tp, 0xF83A, 0x1C11);
5258 r8168_mac_ocp_write(tp, 0xF83C, 0x9CA0);
5259 r8168_mac_ocp_write(tp, 0xF83E, 0xE006);
5260 r8168_mac_ocp_write(tp, 0xF840, 0x74F8);
5261 r8168_mac_ocp_write(tp, 0xF842, 0x48C4);
5262 r8168_mac_ocp_write(tp, 0xF844, 0x8CF8);
5263 r8168_mac_ocp_write(tp, 0xF846, 0xC404);
5264 r8168_mac_ocp_write(tp, 0xF848, 0xBC00);
5265 r8168_mac_ocp_write(tp, 0xF84A, 0xC403);
5266 r8168_mac_ocp_write(tp, 0xF84C, 0xBC00);
5267 r8168_mac_ocp_write(tp, 0xF84E, 0x0BF2);
5268 r8168_mac_ocp_write(tp, 0xF850, 0x0C0A);
5269 r8168_mac_ocp_write(tp, 0xF852, 0xE434);
5270 r8168_mac_ocp_write(tp, 0xF854, 0xD3C0);
5271 r8168_mac_ocp_write(tp, 0xF856, 0x49D9);
5272 r8168_mac_ocp_write(tp, 0xF858, 0xF01F);
5273 r8168_mac_ocp_write(tp, 0xF85A, 0xC526);
5274 r8168_mac_ocp_write(tp, 0xF85C, 0x64A5);
5275 r8168_mac_ocp_write(tp, 0xF85E, 0x1400);
5276 r8168_mac_ocp_write(tp, 0xF860, 0xF007);
5277 r8168_mac_ocp_write(tp, 0xF862, 0x0C01);
5278 r8168_mac_ocp_write(tp, 0xF864, 0x8CA5);
5279 r8168_mac_ocp_write(tp, 0xF866, 0x1C15);
5280 r8168_mac_ocp_write(tp, 0xF868, 0xC51B);
5281 r8168_mac_ocp_write(tp, 0xF86A, 0x9CA0);
5282 r8168_mac_ocp_write(tp, 0xF86C, 0xE013);
5283 r8168_mac_ocp_write(tp, 0xF86E, 0xC519);
5284 r8168_mac_ocp_write(tp, 0xF870, 0x74A0);
5285 r8168_mac_ocp_write(tp, 0xF872, 0x48C4);
5286 r8168_mac_ocp_write(tp, 0xF874, 0x8CA0);
5287 r8168_mac_ocp_write(tp, 0xF876, 0xC516);
5288 r8168_mac_ocp_write(tp, 0xF878, 0x74A4);
5289 r8168_mac_ocp_write(tp, 0xF87A, 0x48C8);
5290 r8168_mac_ocp_write(tp, 0xF87C, 0x48CA);
5291 r8168_mac_ocp_write(tp, 0xF87E, 0x9CA4);
5292 r8168_mac_ocp_write(tp, 0xF880, 0xC512);
5293 r8168_mac_ocp_write(tp, 0xF882, 0x1B00);
5294 r8168_mac_ocp_write(tp, 0xF884, 0x9BA0);
5295 r8168_mac_ocp_write(tp, 0xF886, 0x1B1C);
5296 r8168_mac_ocp_write(tp, 0xF888, 0x483F);
5297 r8168_mac_ocp_write(tp, 0xF88A, 0x9BA2);
5298 r8168_mac_ocp_write(tp, 0xF88C, 0x1B04);
5299 r8168_mac_ocp_write(tp, 0xF88E, 0xC508);
5300 r8168_mac_ocp_write(tp, 0xF890, 0x9BA0);
5301 r8168_mac_ocp_write(tp, 0xF892, 0xC505);
5302 r8168_mac_ocp_write(tp, 0xF894, 0xBD00);
5303 r8168_mac_ocp_write(tp, 0xF896, 0xC502);
5304 r8168_mac_ocp_write(tp, 0xF898, 0xBD00);
5305 r8168_mac_ocp_write(tp, 0xF89A, 0x0300);
5306 r8168_mac_ocp_write(tp, 0xF89C, 0x051E);
5307 r8168_mac_ocp_write(tp, 0xF89E, 0xE434);
5308 r8168_mac_ocp_write(tp, 0xF8A0, 0xE018);
5309 r8168_mac_ocp_write(tp, 0xF8A2, 0xE092);
5310 r8168_mac_ocp_write(tp, 0xF8A4, 0xDE20);
5311 r8168_mac_ocp_write(tp, 0xF8A6, 0xD3C0);
5312 r8168_mac_ocp_write(tp, 0xF8A8, 0xC50F);
5313 r8168_mac_ocp_write(tp, 0xF8AA, 0x76A4);
5314 r8168_mac_ocp_write(tp, 0xF8AC, 0x49E3);
5315 r8168_mac_ocp_write(tp, 0xF8AE, 0xF007);
5316 r8168_mac_ocp_write(tp, 0xF8B0, 0x49C0);
5317 r8168_mac_ocp_write(tp, 0xF8B2, 0xF103);
5318 r8168_mac_ocp_write(tp, 0xF8B4, 0xC607);
5319 r8168_mac_ocp_write(tp, 0xF8B6, 0xBE00);
5320 r8168_mac_ocp_write(tp, 0xF8B8, 0xC606);
5321 r8168_mac_ocp_write(tp, 0xF8BA, 0xBE00);
5322 r8168_mac_ocp_write(tp, 0xF8BC, 0xC602);
5323 r8168_mac_ocp_write(tp, 0xF8BE, 0xBE00);
5324 r8168_mac_ocp_write(tp, 0xF8C0, 0x0C4C);
5325 r8168_mac_ocp_write(tp, 0xF8C2, 0x0C28);
5326 r8168_mac_ocp_write(tp, 0xF8C4, 0x0C2C);
5327 r8168_mac_ocp_write(tp, 0xF8C6, 0xDC00);
5328 r8168_mac_ocp_write(tp, 0xF8C8, 0xC707);
5329 r8168_mac_ocp_write(tp, 0xF8CA, 0x1D00);
5330 r8168_mac_ocp_write(tp, 0xF8CC, 0x8DE2);
5331 r8168_mac_ocp_write(tp, 0xF8CE, 0x48C1);
5332 r8168_mac_ocp_write(tp, 0xF8D0, 0xC502);
5333 r8168_mac_ocp_write(tp, 0xF8D2, 0xBD00);
5334 r8168_mac_ocp_write(tp, 0xF8D4, 0x00AA);
5335 r8168_mac_ocp_write(tp, 0xF8D6, 0xE0C0);
5336 r8168_mac_ocp_write(tp, 0xF8D8, 0xC502);
5337 r8168_mac_ocp_write(tp, 0xF8DA, 0xBD00);
5338 r8168_mac_ocp_write(tp, 0xF8DC, 0x0132);
5339
5340 r8168_mac_ocp_write(tp, 0xFC26, 0x8000);
5341
5342 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743);
5343 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801);
5344 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9);
5345 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD);
5346 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25);
5347 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9);
5348 r8168_mac_ocp_write(tp, 0xFC36, 0x012D);
5349
5350 rtl_hw_aspm_clkreq_enable(tp, true);
5351 }
5352
rtl_hw_start_8168h_1(struct rtl8169_private * tp)5353 static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
5354 {
5355 int rg_saw_cnt;
5356 u32 data;
5357 static const struct ephy_info e_info_8168h_1[] = {
5358 { 0x1e, 0x0800, 0x0001 },
5359 { 0x1d, 0x0000, 0x0800 },
5360 { 0x05, 0xffff, 0x2089 },
5361 { 0x06, 0xffff, 0x5881 },
5362 { 0x04, 0xffff, 0x154a },
5363 { 0x01, 0xffff, 0x068b }
5364 };
5365
5366 /* disable aspm and clock request before access ephy */
5367 rtl_hw_aspm_clkreq_enable(tp, false);
5368 rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
5369
5370 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5371 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
5372 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
5373 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5374
5375 rtl_set_def_aspm_entry_latency(tp);
5376
5377 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5378
5379 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5380 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5381
5382 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
5383
5384 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
5385
5386 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5387
5388 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5389 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5390
5391 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5392 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5393
5394 /* Adjust EEE LED frequency */
5395 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5396
5397 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5398 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5399
5400 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5401
5402 rtl_w0w1_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
5403
5404 rtl_pcie_state_l2l3_enable(tp, false);
5405
5406 rtl_writephy(tp, 0x1f, 0x0c42);
5407 rg_saw_cnt = (rtl_readphy(tp, 0x13) & 0x3fff);
5408 rtl_writephy(tp, 0x1f, 0x0000);
5409 if (rg_saw_cnt > 0) {
5410 u16 sw_cnt_1ms_ini;
5411
5412 sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
5413 sw_cnt_1ms_ini &= 0x0fff;
5414 data = r8168_mac_ocp_read(tp, 0xd412);
5415 data &= ~0x0fff;
5416 data |= sw_cnt_1ms_ini;
5417 r8168_mac_ocp_write(tp, 0xd412, data);
5418 }
5419
5420 data = r8168_mac_ocp_read(tp, 0xe056);
5421 data &= ~0xf0;
5422 data |= 0x70;
5423 r8168_mac_ocp_write(tp, 0xe056, data);
5424
5425 data = r8168_mac_ocp_read(tp, 0xe052);
5426 data &= ~0x6000;
5427 data |= 0x8008;
5428 r8168_mac_ocp_write(tp, 0xe052, data);
5429
5430 data = r8168_mac_ocp_read(tp, 0xe0d6);
5431 data &= ~0x01ff;
5432 data |= 0x017f;
5433 r8168_mac_ocp_write(tp, 0xe0d6, data);
5434
5435 data = r8168_mac_ocp_read(tp, 0xd420);
5436 data &= ~0x0fff;
5437 data |= 0x047f;
5438 r8168_mac_ocp_write(tp, 0xd420, data);
5439
5440 r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
5441 r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
5442 r8168_mac_ocp_write(tp, 0xc094, 0x0000);
5443 r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
5444
5445 rtl_hw_aspm_clkreq_enable(tp, true);
5446 }
5447
rtl_hw_start_8168ep(struct rtl8169_private * tp)5448 static void rtl_hw_start_8168ep(struct rtl8169_private *tp)
5449 {
5450 rtl8168ep_stop_cmac(tp);
5451
5452 rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
5453 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x2f, ERIAR_EXGMAC);
5454 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x5f, ERIAR_EXGMAC);
5455 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
5456
5457 rtl_set_def_aspm_entry_latency(tp);
5458
5459 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5460
5461 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5462 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5463
5464 rtl_w0w1_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f80, 0x00, ERIAR_EXGMAC);
5465
5466 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
5467
5468 RTL_W32(tp, MISC, RTL_R32(tp, MISC) & ~RXDV_GATED_EN);
5469 RTL_W8(tp, MaxTxPacketSize, EarlySize);
5470
5471 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5472 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5473
5474 /* Adjust EEE LED frequency */
5475 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07);
5476
5477 rtl_w0w1_eri(tp, 0x2fc, ERIAR_MASK_0001, 0x01, 0x06, ERIAR_EXGMAC);
5478
5479 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~TX_10M_PS_EN);
5480
5481 rtl_pcie_state_l2l3_enable(tp, false);
5482 }
5483
rtl_hw_start_8168ep_1(struct rtl8169_private * tp)5484 static void rtl_hw_start_8168ep_1(struct rtl8169_private *tp)
5485 {
5486 static const struct ephy_info e_info_8168ep_1[] = {
5487 { 0x00, 0xffff, 0x10ab },
5488 { 0x06, 0xffff, 0xf030 },
5489 { 0x08, 0xffff, 0x2006 },
5490 { 0x0d, 0xffff, 0x1666 },
5491 { 0x0c, 0x3ff0, 0x0000 }
5492 };
5493
5494 /* disable aspm and clock request before access ephy */
5495 rtl_hw_aspm_clkreq_enable(tp, false);
5496 rtl_ephy_init(tp, e_info_8168ep_1, ARRAY_SIZE(e_info_8168ep_1));
5497
5498 rtl_hw_start_8168ep(tp);
5499
5500 rtl_hw_aspm_clkreq_enable(tp, true);
5501 }
5502
rtl_hw_start_8168ep_2(struct rtl8169_private * tp)5503 static void rtl_hw_start_8168ep_2(struct rtl8169_private *tp)
5504 {
5505 static const struct ephy_info e_info_8168ep_2[] = {
5506 { 0x00, 0xffff, 0x10a3 },
5507 { 0x19, 0xffff, 0xfc00 },
5508 { 0x1e, 0xffff, 0x20ea }
5509 };
5510
5511 /* disable aspm and clock request before access ephy */
5512 rtl_hw_aspm_clkreq_enable(tp, false);
5513 rtl_ephy_init(tp, e_info_8168ep_2, ARRAY_SIZE(e_info_8168ep_2));
5514
5515 rtl_hw_start_8168ep(tp);
5516
5517 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5518 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5519
5520 rtl_hw_aspm_clkreq_enable(tp, true);
5521 }
5522
rtl_hw_start_8168ep_3(struct rtl8169_private * tp)5523 static void rtl_hw_start_8168ep_3(struct rtl8169_private *tp)
5524 {
5525 u32 data;
5526 static const struct ephy_info e_info_8168ep_3[] = {
5527 { 0x00, 0xffff, 0x10a3 },
5528 { 0x19, 0xffff, 0x7c00 },
5529 { 0x1e, 0xffff, 0x20eb },
5530 { 0x0d, 0xffff, 0x1666 }
5531 };
5532
5533 /* disable aspm and clock request before access ephy */
5534 rtl_hw_aspm_clkreq_enable(tp, false);
5535 rtl_ephy_init(tp, e_info_8168ep_3, ARRAY_SIZE(e_info_8168ep_3));
5536
5537 rtl_hw_start_8168ep(tp);
5538
5539 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5540 RTL_W8(tp, MISC_1, RTL_R8(tp, MISC_1) & ~PFM_D3COLD_EN);
5541
5542 data = r8168_mac_ocp_read(tp, 0xd3e2);
5543 data &= 0xf000;
5544 data |= 0x0271;
5545 r8168_mac_ocp_write(tp, 0xd3e2, data);
5546
5547 data = r8168_mac_ocp_read(tp, 0xd3e4);
5548 data &= 0xff00;
5549 r8168_mac_ocp_write(tp, 0xd3e4, data);
5550
5551 data = r8168_mac_ocp_read(tp, 0xe860);
5552 data |= 0x0080;
5553 r8168_mac_ocp_write(tp, 0xe860, data);
5554
5555 rtl_hw_aspm_clkreq_enable(tp, true);
5556 }
5557
rtl_hw_start_8168(struct rtl8169_private * tp)5558 static void rtl_hw_start_8168(struct rtl8169_private *tp)
5559 {
5560 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5561
5562 tp->cp_cmd &= ~INTT_MASK;
5563 tp->cp_cmd |= PktCntrDisable | INTT_1;
5564 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5565
5566 RTL_W16(tp, IntrMitigate, 0x5100);
5567
5568 /* Work around for RxFIFO overflow. */
5569 if (tp->mac_version == RTL_GIGA_MAC_VER_11) {
5570 tp->event_slow |= RxFIFOOver | PCSTimeout;
5571 tp->event_slow &= ~RxOverflow;
5572 }
5573
5574 switch (tp->mac_version) {
5575 case RTL_GIGA_MAC_VER_11:
5576 rtl_hw_start_8168bb(tp);
5577 break;
5578
5579 case RTL_GIGA_MAC_VER_12:
5580 case RTL_GIGA_MAC_VER_17:
5581 rtl_hw_start_8168bef(tp);
5582 break;
5583
5584 case RTL_GIGA_MAC_VER_18:
5585 rtl_hw_start_8168cp_1(tp);
5586 break;
5587
5588 case RTL_GIGA_MAC_VER_19:
5589 rtl_hw_start_8168c_1(tp);
5590 break;
5591
5592 case RTL_GIGA_MAC_VER_20:
5593 rtl_hw_start_8168c_2(tp);
5594 break;
5595
5596 case RTL_GIGA_MAC_VER_21:
5597 rtl_hw_start_8168c_3(tp);
5598 break;
5599
5600 case RTL_GIGA_MAC_VER_22:
5601 rtl_hw_start_8168c_4(tp);
5602 break;
5603
5604 case RTL_GIGA_MAC_VER_23:
5605 rtl_hw_start_8168cp_2(tp);
5606 break;
5607
5608 case RTL_GIGA_MAC_VER_24:
5609 rtl_hw_start_8168cp_3(tp);
5610 break;
5611
5612 case RTL_GIGA_MAC_VER_25:
5613 case RTL_GIGA_MAC_VER_26:
5614 case RTL_GIGA_MAC_VER_27:
5615 rtl_hw_start_8168d(tp);
5616 break;
5617
5618 case RTL_GIGA_MAC_VER_28:
5619 rtl_hw_start_8168d_4(tp);
5620 break;
5621
5622 case RTL_GIGA_MAC_VER_31:
5623 rtl_hw_start_8168dp(tp);
5624 break;
5625
5626 case RTL_GIGA_MAC_VER_32:
5627 case RTL_GIGA_MAC_VER_33:
5628 rtl_hw_start_8168e_1(tp);
5629 break;
5630 case RTL_GIGA_MAC_VER_34:
5631 rtl_hw_start_8168e_2(tp);
5632 break;
5633
5634 case RTL_GIGA_MAC_VER_35:
5635 case RTL_GIGA_MAC_VER_36:
5636 rtl_hw_start_8168f_1(tp);
5637 break;
5638
5639 case RTL_GIGA_MAC_VER_38:
5640 rtl_hw_start_8411(tp);
5641 break;
5642
5643 case RTL_GIGA_MAC_VER_40:
5644 case RTL_GIGA_MAC_VER_41:
5645 rtl_hw_start_8168g_1(tp);
5646 break;
5647 case RTL_GIGA_MAC_VER_42:
5648 rtl_hw_start_8168g_2(tp);
5649 break;
5650
5651 case RTL_GIGA_MAC_VER_44:
5652 rtl_hw_start_8411_2(tp);
5653 break;
5654
5655 case RTL_GIGA_MAC_VER_45:
5656 case RTL_GIGA_MAC_VER_46:
5657 rtl_hw_start_8168h_1(tp);
5658 break;
5659
5660 case RTL_GIGA_MAC_VER_49:
5661 rtl_hw_start_8168ep_1(tp);
5662 break;
5663
5664 case RTL_GIGA_MAC_VER_50:
5665 rtl_hw_start_8168ep_2(tp);
5666 break;
5667
5668 case RTL_GIGA_MAC_VER_51:
5669 rtl_hw_start_8168ep_3(tp);
5670 break;
5671
5672 default:
5673 netif_err(tp, drv, tp->dev,
5674 "unknown chipset (mac_version = %d)\n",
5675 tp->mac_version);
5676 break;
5677 }
5678 }
5679
rtl_hw_start_8102e_1(struct rtl8169_private * tp)5680 static void rtl_hw_start_8102e_1(struct rtl8169_private *tp)
5681 {
5682 static const struct ephy_info e_info_8102e_1[] = {
5683 { 0x01, 0, 0x6e65 },
5684 { 0x02, 0, 0x091f },
5685 { 0x03, 0, 0xc2f9 },
5686 { 0x06, 0, 0xafb5 },
5687 { 0x07, 0, 0x0e00 },
5688 { 0x19, 0, 0xec80 },
5689 { 0x01, 0, 0x2e65 },
5690 { 0x01, 0, 0x6e65 }
5691 };
5692 u8 cfg1;
5693
5694 rtl_set_def_aspm_entry_latency(tp);
5695
5696 RTL_W8(tp, DBG_REG, FIX_NAK_1);
5697
5698 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5699
5700 RTL_W8(tp, Config1,
5701 LEDS1 | LEDS0 | Speed_down | MEMMAP | IOMAP | VPD | PMEnable);
5702 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5703
5704 cfg1 = RTL_R8(tp, Config1);
5705 if ((cfg1 & LEDS0) && (cfg1 & LEDS1))
5706 RTL_W8(tp, Config1, cfg1 & ~LEDS0);
5707
5708 rtl_ephy_init(tp, e_info_8102e_1, ARRAY_SIZE(e_info_8102e_1));
5709 }
5710
rtl_hw_start_8102e_2(struct rtl8169_private * tp)5711 static void rtl_hw_start_8102e_2(struct rtl8169_private *tp)
5712 {
5713 rtl_set_def_aspm_entry_latency(tp);
5714
5715 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5716
5717 RTL_W8(tp, Config1, MEMMAP | IOMAP | VPD | PMEnable);
5718 RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Beacon_en);
5719 }
5720
rtl_hw_start_8102e_3(struct rtl8169_private * tp)5721 static void rtl_hw_start_8102e_3(struct rtl8169_private *tp)
5722 {
5723 rtl_hw_start_8102e_2(tp);
5724
5725 rtl_ephy_write(tp, 0x03, 0xc2f9);
5726 }
5727
rtl_hw_start_8105e_1(struct rtl8169_private * tp)5728 static void rtl_hw_start_8105e_1(struct rtl8169_private *tp)
5729 {
5730 static const struct ephy_info e_info_8105e_1[] = {
5731 { 0x07, 0, 0x4000 },
5732 { 0x19, 0, 0x0200 },
5733 { 0x19, 0, 0x0020 },
5734 { 0x1e, 0, 0x2000 },
5735 { 0x03, 0, 0x0001 },
5736 { 0x19, 0, 0x0100 },
5737 { 0x19, 0, 0x0004 },
5738 { 0x0a, 0, 0x0020 }
5739 };
5740
5741 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5742 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5743
5744 /* Disable Early Tally Counter */
5745 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000);
5746
5747 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5748 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) | PFM_EN);
5749
5750 rtl_ephy_init(tp, e_info_8105e_1, ARRAY_SIZE(e_info_8105e_1));
5751
5752 rtl_pcie_state_l2l3_enable(tp, false);
5753 }
5754
rtl_hw_start_8105e_2(struct rtl8169_private * tp)5755 static void rtl_hw_start_8105e_2(struct rtl8169_private *tp)
5756 {
5757 rtl_hw_start_8105e_1(tp);
5758 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000);
5759 }
5760
rtl_hw_start_8402(struct rtl8169_private * tp)5761 static void rtl_hw_start_8402(struct rtl8169_private *tp)
5762 {
5763 static const struct ephy_info e_info_8402[] = {
5764 { 0x19, 0xffff, 0xff64 },
5765 { 0x1e, 0, 0x4000 }
5766 };
5767
5768 rtl_set_def_aspm_entry_latency(tp);
5769
5770 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5771 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5772
5773 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
5774
5775 rtl_ephy_init(tp, e_info_8402, ARRAY_SIZE(e_info_8402));
5776
5777 rtl_tx_performance_tweak(tp, PCI_EXP_DEVCTL_READRQ_4096B);
5778
5779 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, 0x00000002, ERIAR_EXGMAC);
5780 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00000006, ERIAR_EXGMAC);
5781 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
5782 rtl_w0w1_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
5783 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5784 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
5785 rtl_w0w1_eri(tp, 0x0d4, ERIAR_MASK_0011, 0x0e00, 0xff00, ERIAR_EXGMAC);
5786
5787 rtl_pcie_state_l2l3_enable(tp, false);
5788 }
5789
rtl_hw_start_8106(struct rtl8169_private * tp)5790 static void rtl_hw_start_8106(struct rtl8169_private *tp)
5791 {
5792 rtl_hw_aspm_clkreq_enable(tp, false);
5793
5794 /* Force LAN exit from ASPM if Rx/Tx are not idle */
5795 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800);
5796
5797 RTL_W32(tp, MISC, (RTL_R32(tp, MISC) | DISABLE_LAN_EN) & ~EARLY_TALLY_EN);
5798 RTL_W8(tp, MCU, RTL_R8(tp, MCU) | EN_NDP | EN_OOB_RESET);
5799 RTL_W8(tp, DLLPR, RTL_R8(tp, DLLPR) & ~PFM_EN);
5800
5801 rtl_pcie_state_l2l3_enable(tp, false);
5802 rtl_hw_aspm_clkreq_enable(tp, true);
5803 }
5804
rtl_hw_start_8101(struct rtl8169_private * tp)5805 static void rtl_hw_start_8101(struct rtl8169_private *tp)
5806 {
5807 if (tp->mac_version >= RTL_GIGA_MAC_VER_30)
5808 tp->event_slow &= ~RxFIFOOver;
5809
5810 if (tp->mac_version == RTL_GIGA_MAC_VER_13 ||
5811 tp->mac_version == RTL_GIGA_MAC_VER_16)
5812 pcie_capability_set_word(tp->pci_dev, PCI_EXP_DEVCTL,
5813 PCI_EXP_DEVCTL_NOSNOOP_EN);
5814
5815 RTL_W8(tp, MaxTxPacketSize, TxPacketMax);
5816
5817 tp->cp_cmd &= CPCMD_QUIRK_MASK;
5818 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
5819
5820 switch (tp->mac_version) {
5821 case RTL_GIGA_MAC_VER_07:
5822 rtl_hw_start_8102e_1(tp);
5823 break;
5824
5825 case RTL_GIGA_MAC_VER_08:
5826 rtl_hw_start_8102e_3(tp);
5827 break;
5828
5829 case RTL_GIGA_MAC_VER_09:
5830 rtl_hw_start_8102e_2(tp);
5831 break;
5832
5833 case RTL_GIGA_MAC_VER_29:
5834 rtl_hw_start_8105e_1(tp);
5835 break;
5836 case RTL_GIGA_MAC_VER_30:
5837 rtl_hw_start_8105e_2(tp);
5838 break;
5839
5840 case RTL_GIGA_MAC_VER_37:
5841 rtl_hw_start_8402(tp);
5842 break;
5843
5844 case RTL_GIGA_MAC_VER_39:
5845 rtl_hw_start_8106(tp);
5846 break;
5847 case RTL_GIGA_MAC_VER_43:
5848 rtl_hw_start_8168g_2(tp);
5849 break;
5850 case RTL_GIGA_MAC_VER_47:
5851 case RTL_GIGA_MAC_VER_48:
5852 rtl_hw_start_8168h_1(tp);
5853 break;
5854 }
5855
5856 RTL_W16(tp, IntrMitigate, 0x0000);
5857 }
5858
rtl8169_change_mtu(struct net_device * dev,int new_mtu)5859 static int rtl8169_change_mtu(struct net_device *dev, int new_mtu)
5860 {
5861 struct rtl8169_private *tp = netdev_priv(dev);
5862
5863 if (new_mtu > ETH_DATA_LEN)
5864 rtl_hw_jumbo_enable(tp);
5865 else
5866 rtl_hw_jumbo_disable(tp);
5867
5868 dev->mtu = new_mtu;
5869 netdev_update_features(dev);
5870
5871 return 0;
5872 }
5873
rtl8169_make_unusable_by_asic(struct RxDesc * desc)5874 static inline void rtl8169_make_unusable_by_asic(struct RxDesc *desc)
5875 {
5876 desc->addr = cpu_to_le64(0x0badbadbadbadbadull);
5877 desc->opts1 &= ~cpu_to_le32(DescOwn | RsvdMask);
5878 }
5879
rtl8169_free_rx_databuff(struct rtl8169_private * tp,void ** data_buff,struct RxDesc * desc)5880 static void rtl8169_free_rx_databuff(struct rtl8169_private *tp,
5881 void **data_buff, struct RxDesc *desc)
5882 {
5883 dma_unmap_single(tp_to_dev(tp), le64_to_cpu(desc->addr),
5884 R8169_RX_BUF_SIZE, DMA_FROM_DEVICE);
5885
5886 kfree(*data_buff);
5887 *data_buff = NULL;
5888 rtl8169_make_unusable_by_asic(desc);
5889 }
5890
rtl8169_mark_to_asic(struct RxDesc * desc)5891 static inline void rtl8169_mark_to_asic(struct RxDesc *desc)
5892 {
5893 u32 eor = le32_to_cpu(desc->opts1) & RingEnd;
5894
5895 /* Force memory writes to complete before releasing descriptor */
5896 dma_wmb();
5897
5898 desc->opts1 = cpu_to_le32(DescOwn | eor | R8169_RX_BUF_SIZE);
5899 }
5900
rtl8169_align(void * data)5901 static inline void *rtl8169_align(void *data)
5902 {
5903 return (void *)ALIGN((long)data, 16);
5904 }
5905
rtl8169_alloc_rx_data(struct rtl8169_private * tp,struct RxDesc * desc)5906 static struct sk_buff *rtl8169_alloc_rx_data(struct rtl8169_private *tp,
5907 struct RxDesc *desc)
5908 {
5909 void *data;
5910 dma_addr_t mapping;
5911 struct device *d = tp_to_dev(tp);
5912 int node = dev_to_node(d);
5913
5914 data = kmalloc_node(R8169_RX_BUF_SIZE, GFP_KERNEL, node);
5915 if (!data)
5916 return NULL;
5917
5918 if (rtl8169_align(data) != data) {
5919 kfree(data);
5920 data = kmalloc_node(R8169_RX_BUF_SIZE + 15, GFP_KERNEL, node);
5921 if (!data)
5922 return NULL;
5923 }
5924
5925 mapping = dma_map_single(d, rtl8169_align(data), R8169_RX_BUF_SIZE,
5926 DMA_FROM_DEVICE);
5927 if (unlikely(dma_mapping_error(d, mapping))) {
5928 if (net_ratelimit())
5929 netif_err(tp, drv, tp->dev, "Failed to map RX DMA!\n");
5930 goto err_out;
5931 }
5932
5933 desc->addr = cpu_to_le64(mapping);
5934 rtl8169_mark_to_asic(desc);
5935 return data;
5936
5937 err_out:
5938 kfree(data);
5939 return NULL;
5940 }
5941
rtl8169_rx_clear(struct rtl8169_private * tp)5942 static void rtl8169_rx_clear(struct rtl8169_private *tp)
5943 {
5944 unsigned int i;
5945
5946 for (i = 0; i < NUM_RX_DESC; i++) {
5947 if (tp->Rx_databuff[i]) {
5948 rtl8169_free_rx_databuff(tp, tp->Rx_databuff + i,
5949 tp->RxDescArray + i);
5950 }
5951 }
5952 }
5953
rtl8169_mark_as_last_descriptor(struct RxDesc * desc)5954 static inline void rtl8169_mark_as_last_descriptor(struct RxDesc *desc)
5955 {
5956 desc->opts1 |= cpu_to_le32(RingEnd);
5957 }
5958
rtl8169_rx_fill(struct rtl8169_private * tp)5959 static int rtl8169_rx_fill(struct rtl8169_private *tp)
5960 {
5961 unsigned int i;
5962
5963 for (i = 0; i < NUM_RX_DESC; i++) {
5964 void *data;
5965
5966 data = rtl8169_alloc_rx_data(tp, tp->RxDescArray + i);
5967 if (!data) {
5968 rtl8169_make_unusable_by_asic(tp->RxDescArray + i);
5969 goto err_out;
5970 }
5971 tp->Rx_databuff[i] = data;
5972 }
5973
5974 rtl8169_mark_as_last_descriptor(tp->RxDescArray + NUM_RX_DESC - 1);
5975 return 0;
5976
5977 err_out:
5978 rtl8169_rx_clear(tp);
5979 return -ENOMEM;
5980 }
5981
rtl8169_init_ring(struct rtl8169_private * tp)5982 static int rtl8169_init_ring(struct rtl8169_private *tp)
5983 {
5984 rtl8169_init_ring_indexes(tp);
5985
5986 memset(tp->tx_skb, 0, sizeof(tp->tx_skb));
5987 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff));
5988
5989 return rtl8169_rx_fill(tp);
5990 }
5991
rtl8169_unmap_tx_skb(struct device * d,struct ring_info * tx_skb,struct TxDesc * desc)5992 static void rtl8169_unmap_tx_skb(struct device *d, struct ring_info *tx_skb,
5993 struct TxDesc *desc)
5994 {
5995 unsigned int len = tx_skb->len;
5996
5997 dma_unmap_single(d, le64_to_cpu(desc->addr), len, DMA_TO_DEVICE);
5998
5999 desc->opts1 = 0x00;
6000 desc->opts2 = 0x00;
6001 desc->addr = 0x00;
6002 tx_skb->len = 0;
6003 }
6004
rtl8169_tx_clear_range(struct rtl8169_private * tp,u32 start,unsigned int n)6005 static void rtl8169_tx_clear_range(struct rtl8169_private *tp, u32 start,
6006 unsigned int n)
6007 {
6008 unsigned int i;
6009
6010 for (i = 0; i < n; i++) {
6011 unsigned int entry = (start + i) % NUM_TX_DESC;
6012 struct ring_info *tx_skb = tp->tx_skb + entry;
6013 unsigned int len = tx_skb->len;
6014
6015 if (len) {
6016 struct sk_buff *skb = tx_skb->skb;
6017
6018 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6019 tp->TxDescArray + entry);
6020 if (skb) {
6021 dev_consume_skb_any(skb);
6022 tx_skb->skb = NULL;
6023 }
6024 }
6025 }
6026 }
6027
rtl8169_tx_clear(struct rtl8169_private * tp)6028 static void rtl8169_tx_clear(struct rtl8169_private *tp)
6029 {
6030 rtl8169_tx_clear_range(tp, tp->dirty_tx, NUM_TX_DESC);
6031 tp->cur_tx = tp->dirty_tx = 0;
6032 }
6033
rtl_reset_work(struct rtl8169_private * tp)6034 static void rtl_reset_work(struct rtl8169_private *tp)
6035 {
6036 struct net_device *dev = tp->dev;
6037 int i;
6038
6039 napi_disable(&tp->napi);
6040 netif_stop_queue(dev);
6041 synchronize_sched();
6042
6043 rtl8169_hw_reset(tp);
6044
6045 for (i = 0; i < NUM_RX_DESC; i++)
6046 rtl8169_mark_to_asic(tp->RxDescArray + i);
6047
6048 rtl8169_tx_clear(tp);
6049 rtl8169_init_ring_indexes(tp);
6050
6051 napi_enable(&tp->napi);
6052 rtl_hw_start(tp);
6053 netif_wake_queue(dev);
6054 }
6055
rtl8169_tx_timeout(struct net_device * dev)6056 static void rtl8169_tx_timeout(struct net_device *dev)
6057 {
6058 struct rtl8169_private *tp = netdev_priv(dev);
6059
6060 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6061 }
6062
rtl8169_xmit_frags(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)6063 static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
6064 u32 *opts)
6065 {
6066 struct skb_shared_info *info = skb_shinfo(skb);
6067 unsigned int cur_frag, entry;
6068 struct TxDesc *uninitialized_var(txd);
6069 struct device *d = tp_to_dev(tp);
6070
6071 entry = tp->cur_tx;
6072 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) {
6073 const skb_frag_t *frag = info->frags + cur_frag;
6074 dma_addr_t mapping;
6075 u32 status, len;
6076 void *addr;
6077
6078 entry = (entry + 1) % NUM_TX_DESC;
6079
6080 txd = tp->TxDescArray + entry;
6081 len = skb_frag_size(frag);
6082 addr = skb_frag_address(frag);
6083 mapping = dma_map_single(d, addr, len, DMA_TO_DEVICE);
6084 if (unlikely(dma_mapping_error(d, mapping))) {
6085 if (net_ratelimit())
6086 netif_err(tp, drv, tp->dev,
6087 "Failed to map TX fragments DMA!\n");
6088 goto err_out;
6089 }
6090
6091 /* Anti gcc 2.95.3 bugware (sic) */
6092 status = opts[0] | len |
6093 (RingEnd * !((entry + 1) % NUM_TX_DESC));
6094
6095 txd->opts1 = cpu_to_le32(status);
6096 txd->opts2 = cpu_to_le32(opts[1]);
6097 txd->addr = cpu_to_le64(mapping);
6098
6099 tp->tx_skb[entry].len = len;
6100 }
6101
6102 if (cur_frag) {
6103 tp->tx_skb[entry].skb = skb;
6104 txd->opts1 |= cpu_to_le32(LastFrag);
6105 }
6106
6107 return cur_frag;
6108
6109 err_out:
6110 rtl8169_tx_clear_range(tp, tp->cur_tx + 1, cur_frag);
6111 return -EIO;
6112 }
6113
rtl_test_hw_pad_bug(struct rtl8169_private * tp,struct sk_buff * skb)6114 static bool rtl_test_hw_pad_bug(struct rtl8169_private *tp, struct sk_buff *skb)
6115 {
6116 return skb->len < ETH_ZLEN && tp->mac_version == RTL_GIGA_MAC_VER_34;
6117 }
6118
6119 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6120 struct net_device *dev);
6121 /* r8169_csum_workaround()
6122 * The hw limites the value the transport offset. When the offset is out of the
6123 * range, calculate the checksum by sw.
6124 */
r8169_csum_workaround(struct rtl8169_private * tp,struct sk_buff * skb)6125 static void r8169_csum_workaround(struct rtl8169_private *tp,
6126 struct sk_buff *skb)
6127 {
6128 if (skb_shinfo(skb)->gso_size) {
6129 netdev_features_t features = tp->dev->features;
6130 struct sk_buff *segs, *nskb;
6131
6132 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6);
6133 segs = skb_gso_segment(skb, features);
6134 if (IS_ERR(segs) || !segs)
6135 goto drop;
6136
6137 do {
6138 nskb = segs;
6139 segs = segs->next;
6140 nskb->next = NULL;
6141 rtl8169_start_xmit(nskb, tp->dev);
6142 } while (segs);
6143
6144 dev_consume_skb_any(skb);
6145 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6146 if (skb_checksum_help(skb) < 0)
6147 goto drop;
6148
6149 rtl8169_start_xmit(skb, tp->dev);
6150 } else {
6151 struct net_device_stats *stats;
6152
6153 drop:
6154 stats = &tp->dev->stats;
6155 stats->tx_dropped++;
6156 dev_kfree_skb_any(skb);
6157 }
6158 }
6159
6160 /* msdn_giant_send_check()
6161 * According to the document of microsoft, the TCP Pseudo Header excludes the
6162 * packet length for IPv6 TCP large packets.
6163 */
msdn_giant_send_check(struct sk_buff * skb)6164 static int msdn_giant_send_check(struct sk_buff *skb)
6165 {
6166 const struct ipv6hdr *ipv6h;
6167 struct tcphdr *th;
6168 int ret;
6169
6170 ret = skb_cow_head(skb, 0);
6171 if (ret)
6172 return ret;
6173
6174 ipv6h = ipv6_hdr(skb);
6175 th = tcp_hdr(skb);
6176
6177 th->check = 0;
6178 th->check = ~tcp_v6_check(0, &ipv6h->saddr, &ipv6h->daddr, 0);
6179
6180 return ret;
6181 }
6182
rtl8169_tso_csum_v1(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)6183 static bool rtl8169_tso_csum_v1(struct rtl8169_private *tp,
6184 struct sk_buff *skb, u32 *opts)
6185 {
6186 u32 mss = skb_shinfo(skb)->gso_size;
6187
6188 if (mss) {
6189 opts[0] |= TD_LSO;
6190 opts[0] |= min(mss, TD_MSS_MAX) << TD0_MSS_SHIFT;
6191 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6192 const struct iphdr *ip = ip_hdr(skb);
6193
6194 if (ip->protocol == IPPROTO_TCP)
6195 opts[0] |= TD0_IP_CS | TD0_TCP_CS;
6196 else if (ip->protocol == IPPROTO_UDP)
6197 opts[0] |= TD0_IP_CS | TD0_UDP_CS;
6198 else
6199 WARN_ON_ONCE(1);
6200 }
6201
6202 return true;
6203 }
6204
rtl8169_tso_csum_v2(struct rtl8169_private * tp,struct sk_buff * skb,u32 * opts)6205 static bool rtl8169_tso_csum_v2(struct rtl8169_private *tp,
6206 struct sk_buff *skb, u32 *opts)
6207 {
6208 u32 transport_offset = (u32)skb_transport_offset(skb);
6209 u32 mss = skb_shinfo(skb)->gso_size;
6210
6211 if (mss) {
6212 if (transport_offset > GTTCPHO_MAX) {
6213 netif_warn(tp, tx_err, tp->dev,
6214 "Invalid transport offset 0x%x for TSO\n",
6215 transport_offset);
6216 return false;
6217 }
6218
6219 switch (vlan_get_protocol(skb)) {
6220 case htons(ETH_P_IP):
6221 opts[0] |= TD1_GTSENV4;
6222 break;
6223
6224 case htons(ETH_P_IPV6):
6225 if (msdn_giant_send_check(skb))
6226 return false;
6227
6228 opts[0] |= TD1_GTSENV6;
6229 break;
6230
6231 default:
6232 WARN_ON_ONCE(1);
6233 break;
6234 }
6235
6236 opts[0] |= transport_offset << GTTCPHO_SHIFT;
6237 opts[1] |= min(mss, TD_MSS_MAX) << TD1_MSS_SHIFT;
6238 } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
6239 u8 ip_protocol;
6240
6241 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6242 return !(skb_checksum_help(skb) || eth_skb_pad(skb));
6243
6244 if (transport_offset > TCPHO_MAX) {
6245 netif_warn(tp, tx_err, tp->dev,
6246 "Invalid transport offset 0x%x\n",
6247 transport_offset);
6248 return false;
6249 }
6250
6251 switch (vlan_get_protocol(skb)) {
6252 case htons(ETH_P_IP):
6253 opts[1] |= TD1_IPv4_CS;
6254 ip_protocol = ip_hdr(skb)->protocol;
6255 break;
6256
6257 case htons(ETH_P_IPV6):
6258 opts[1] |= TD1_IPv6_CS;
6259 ip_protocol = ipv6_hdr(skb)->nexthdr;
6260 break;
6261
6262 default:
6263 ip_protocol = IPPROTO_RAW;
6264 break;
6265 }
6266
6267 if (ip_protocol == IPPROTO_TCP)
6268 opts[1] |= TD1_TCP_CS;
6269 else if (ip_protocol == IPPROTO_UDP)
6270 opts[1] |= TD1_UDP_CS;
6271 else
6272 WARN_ON_ONCE(1);
6273
6274 opts[1] |= transport_offset << TCPHO_SHIFT;
6275 } else {
6276 if (unlikely(rtl_test_hw_pad_bug(tp, skb)))
6277 return !eth_skb_pad(skb);
6278 }
6279
6280 return true;
6281 }
6282
rtl8169_start_xmit(struct sk_buff * skb,struct net_device * dev)6283 static netdev_tx_t rtl8169_start_xmit(struct sk_buff *skb,
6284 struct net_device *dev)
6285 {
6286 struct rtl8169_private *tp = netdev_priv(dev);
6287 unsigned int entry = tp->cur_tx % NUM_TX_DESC;
6288 struct TxDesc *txd = tp->TxDescArray + entry;
6289 struct device *d = tp_to_dev(tp);
6290 dma_addr_t mapping;
6291 u32 status, len;
6292 u32 opts[2];
6293 int frags;
6294
6295 if (unlikely(!TX_FRAGS_READY_FOR(tp, skb_shinfo(skb)->nr_frags))) {
6296 netif_err(tp, drv, dev, "BUG! Tx Ring full when queue awake!\n");
6297 goto err_stop_0;
6298 }
6299
6300 if (unlikely(le32_to_cpu(txd->opts1) & DescOwn))
6301 goto err_stop_0;
6302
6303 opts[1] = cpu_to_le32(rtl8169_tx_vlan_tag(skb));
6304 opts[0] = DescOwn;
6305
6306 if (!tp->tso_csum(tp, skb, opts)) {
6307 r8169_csum_workaround(tp, skb);
6308 return NETDEV_TX_OK;
6309 }
6310
6311 len = skb_headlen(skb);
6312 mapping = dma_map_single(d, skb->data, len, DMA_TO_DEVICE);
6313 if (unlikely(dma_mapping_error(d, mapping))) {
6314 if (net_ratelimit())
6315 netif_err(tp, drv, dev, "Failed to map TX DMA!\n");
6316 goto err_dma_0;
6317 }
6318
6319 tp->tx_skb[entry].len = len;
6320 txd->addr = cpu_to_le64(mapping);
6321
6322 frags = rtl8169_xmit_frags(tp, skb, opts);
6323 if (frags < 0)
6324 goto err_dma_1;
6325 else if (frags)
6326 opts[0] |= FirstFrag;
6327 else {
6328 opts[0] |= FirstFrag | LastFrag;
6329 tp->tx_skb[entry].skb = skb;
6330 }
6331
6332 txd->opts2 = cpu_to_le32(opts[1]);
6333
6334 skb_tx_timestamp(skb);
6335
6336 /* Force memory writes to complete before releasing descriptor */
6337 dma_wmb();
6338
6339 /* Anti gcc 2.95.3 bugware (sic) */
6340 status = opts[0] | len | (RingEnd * !((entry + 1) % NUM_TX_DESC));
6341 txd->opts1 = cpu_to_le32(status);
6342
6343 /* Force all memory writes to complete before notifying device */
6344 wmb();
6345
6346 tp->cur_tx += frags + 1;
6347
6348 RTL_W8(tp, TxPoll, NPQ);
6349
6350 mmiowb();
6351
6352 if (!TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6353 /* Avoid wrongly optimistic queue wake-up: rtl_tx thread must
6354 * not miss a ring update when it notices a stopped queue.
6355 */
6356 smp_wmb();
6357 netif_stop_queue(dev);
6358 /* Sync with rtl_tx:
6359 * - publish queue status and cur_tx ring index (write barrier)
6360 * - refresh dirty_tx ring index (read barrier).
6361 * May the current thread have a pessimistic view of the ring
6362 * status and forget to wake up queue, a racing rtl_tx thread
6363 * can't.
6364 */
6365 smp_mb();
6366 if (TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS))
6367 netif_wake_queue(dev);
6368 }
6369
6370 return NETDEV_TX_OK;
6371
6372 err_dma_1:
6373 rtl8169_unmap_tx_skb(d, tp->tx_skb + entry, txd);
6374 err_dma_0:
6375 dev_kfree_skb_any(skb);
6376 dev->stats.tx_dropped++;
6377 return NETDEV_TX_OK;
6378
6379 err_stop_0:
6380 netif_stop_queue(dev);
6381 dev->stats.tx_dropped++;
6382 return NETDEV_TX_BUSY;
6383 }
6384
rtl8169_pcierr_interrupt(struct net_device * dev)6385 static void rtl8169_pcierr_interrupt(struct net_device *dev)
6386 {
6387 struct rtl8169_private *tp = netdev_priv(dev);
6388 struct pci_dev *pdev = tp->pci_dev;
6389 u16 pci_status, pci_cmd;
6390
6391 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
6392 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
6393
6394 netif_err(tp, intr, dev, "PCI error (cmd = 0x%04x, status = 0x%04x)\n",
6395 pci_cmd, pci_status);
6396
6397 /*
6398 * The recovery sequence below admits a very elaborated explanation:
6399 * - it seems to work;
6400 * - I did not see what else could be done;
6401 * - it makes iop3xx happy.
6402 *
6403 * Feel free to adjust to your needs.
6404 */
6405 if (pdev->broken_parity_status)
6406 pci_cmd &= ~PCI_COMMAND_PARITY;
6407 else
6408 pci_cmd |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY;
6409
6410 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd);
6411
6412 pci_write_config_word(pdev, PCI_STATUS,
6413 pci_status & (PCI_STATUS_DETECTED_PARITY |
6414 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_REC_MASTER_ABORT |
6415 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_SIG_TARGET_ABORT));
6416
6417 /* The infamous DAC f*ckup only happens at boot time */
6418 if ((tp->cp_cmd & PCIDAC) && !tp->cur_rx) {
6419 netif_info(tp, intr, dev, "disabling PCI DAC\n");
6420 tp->cp_cmd &= ~PCIDAC;
6421 RTL_W16(tp, CPlusCmd, tp->cp_cmd);
6422 dev->features &= ~NETIF_F_HIGHDMA;
6423 }
6424
6425 rtl8169_hw_reset(tp);
6426
6427 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6428 }
6429
rtl_tx(struct net_device * dev,struct rtl8169_private * tp)6430 static void rtl_tx(struct net_device *dev, struct rtl8169_private *tp)
6431 {
6432 unsigned int dirty_tx, tx_left;
6433
6434 dirty_tx = tp->dirty_tx;
6435 smp_rmb();
6436 tx_left = tp->cur_tx - dirty_tx;
6437
6438 while (tx_left > 0) {
6439 unsigned int entry = dirty_tx % NUM_TX_DESC;
6440 struct ring_info *tx_skb = tp->tx_skb + entry;
6441 u32 status;
6442
6443 status = le32_to_cpu(tp->TxDescArray[entry].opts1);
6444 if (status & DescOwn)
6445 break;
6446
6447 /* This barrier is needed to keep us from reading
6448 * any other fields out of the Tx descriptor until
6449 * we know the status of DescOwn
6450 */
6451 dma_rmb();
6452
6453 rtl8169_unmap_tx_skb(tp_to_dev(tp), tx_skb,
6454 tp->TxDescArray + entry);
6455 if (status & LastFrag) {
6456 u64_stats_update_begin(&tp->tx_stats.syncp);
6457 tp->tx_stats.packets++;
6458 tp->tx_stats.bytes += tx_skb->skb->len;
6459 u64_stats_update_end(&tp->tx_stats.syncp);
6460 dev_consume_skb_any(tx_skb->skb);
6461 tx_skb->skb = NULL;
6462 }
6463 dirty_tx++;
6464 tx_left--;
6465 }
6466
6467 if (tp->dirty_tx != dirty_tx) {
6468 tp->dirty_tx = dirty_tx;
6469 /* Sync with rtl8169_start_xmit:
6470 * - publish dirty_tx ring index (write barrier)
6471 * - refresh cur_tx ring index and queue status (read barrier)
6472 * May the current thread miss the stopped queue condition,
6473 * a racing xmit thread can only have a right view of the
6474 * ring status.
6475 */
6476 smp_mb();
6477 if (netif_queue_stopped(dev) &&
6478 TX_FRAGS_READY_FOR(tp, MAX_SKB_FRAGS)) {
6479 netif_wake_queue(dev);
6480 }
6481 /*
6482 * 8168 hack: TxPoll requests are lost when the Tx packets are
6483 * too close. Let's kick an extra TxPoll request when a burst
6484 * of start_xmit activity is detected (if it is not detected,
6485 * it is slow enough). -- FR
6486 */
6487 if (tp->cur_tx != dirty_tx)
6488 RTL_W8(tp, TxPoll, NPQ);
6489 }
6490 }
6491
rtl8169_fragmented_frame(u32 status)6492 static inline int rtl8169_fragmented_frame(u32 status)
6493 {
6494 return (status & (FirstFrag | LastFrag)) != (FirstFrag | LastFrag);
6495 }
6496
rtl8169_rx_csum(struct sk_buff * skb,u32 opts1)6497 static inline void rtl8169_rx_csum(struct sk_buff *skb, u32 opts1)
6498 {
6499 u32 status = opts1 & RxProtoMask;
6500
6501 if (((status == RxProtoTCP) && !(opts1 & TCPFail)) ||
6502 ((status == RxProtoUDP) && !(opts1 & UDPFail)))
6503 skb->ip_summed = CHECKSUM_UNNECESSARY;
6504 else
6505 skb_checksum_none_assert(skb);
6506 }
6507
rtl8169_try_rx_copy(void * data,struct rtl8169_private * tp,int pkt_size,dma_addr_t addr)6508 static struct sk_buff *rtl8169_try_rx_copy(void *data,
6509 struct rtl8169_private *tp,
6510 int pkt_size,
6511 dma_addr_t addr)
6512 {
6513 struct sk_buff *skb;
6514 struct device *d = tp_to_dev(tp);
6515
6516 data = rtl8169_align(data);
6517 dma_sync_single_for_cpu(d, addr, pkt_size, DMA_FROM_DEVICE);
6518 prefetch(data);
6519 skb = napi_alloc_skb(&tp->napi, pkt_size);
6520 if (skb)
6521 skb_copy_to_linear_data(skb, data, pkt_size);
6522 dma_sync_single_for_device(d, addr, pkt_size, DMA_FROM_DEVICE);
6523
6524 return skb;
6525 }
6526
rtl_rx(struct net_device * dev,struct rtl8169_private * tp,u32 budget)6527 static int rtl_rx(struct net_device *dev, struct rtl8169_private *tp, u32 budget)
6528 {
6529 unsigned int cur_rx, rx_left;
6530 unsigned int count;
6531
6532 cur_rx = tp->cur_rx;
6533
6534 for (rx_left = min(budget, NUM_RX_DESC); rx_left > 0; rx_left--, cur_rx++) {
6535 unsigned int entry = cur_rx % NUM_RX_DESC;
6536 struct RxDesc *desc = tp->RxDescArray + entry;
6537 u32 status;
6538
6539 status = le32_to_cpu(desc->opts1);
6540 if (status & DescOwn)
6541 break;
6542
6543 /* This barrier is needed to keep us from reading
6544 * any other fields out of the Rx descriptor until
6545 * we know the status of DescOwn
6546 */
6547 dma_rmb();
6548
6549 if (unlikely(status & RxRES)) {
6550 netif_info(tp, rx_err, dev, "Rx ERROR. status = %08x\n",
6551 status);
6552 dev->stats.rx_errors++;
6553 if (status & (RxRWT | RxRUNT))
6554 dev->stats.rx_length_errors++;
6555 if (status & RxCRC)
6556 dev->stats.rx_crc_errors++;
6557 /* RxFOVF is a reserved bit on later chip versions */
6558 if (tp->mac_version == RTL_GIGA_MAC_VER_01 &&
6559 status & RxFOVF) {
6560 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
6561 dev->stats.rx_fifo_errors++;
6562 } else if (status & (RxRUNT | RxCRC) &&
6563 !(status & RxRWT) &&
6564 dev->features & NETIF_F_RXALL) {
6565 goto process_pkt;
6566 }
6567 } else {
6568 struct sk_buff *skb;
6569 dma_addr_t addr;
6570 int pkt_size;
6571
6572 process_pkt:
6573 addr = le64_to_cpu(desc->addr);
6574 if (likely(!(dev->features & NETIF_F_RXFCS)))
6575 pkt_size = (status & 0x00003fff) - 4;
6576 else
6577 pkt_size = status & 0x00003fff;
6578
6579 /*
6580 * The driver does not support incoming fragmented
6581 * frames. They are seen as a symptom of over-mtu
6582 * sized frames.
6583 */
6584 if (unlikely(rtl8169_fragmented_frame(status))) {
6585 dev->stats.rx_dropped++;
6586 dev->stats.rx_length_errors++;
6587 goto release_descriptor;
6588 }
6589
6590 skb = rtl8169_try_rx_copy(tp->Rx_databuff[entry],
6591 tp, pkt_size, addr);
6592 if (!skb) {
6593 dev->stats.rx_dropped++;
6594 goto release_descriptor;
6595 }
6596
6597 rtl8169_rx_csum(skb, status);
6598 skb_put(skb, pkt_size);
6599 skb->protocol = eth_type_trans(skb, dev);
6600
6601 rtl8169_rx_vlan_tag(desc, skb);
6602
6603 if (skb->pkt_type == PACKET_MULTICAST)
6604 dev->stats.multicast++;
6605
6606 napi_gro_receive(&tp->napi, skb);
6607
6608 u64_stats_update_begin(&tp->rx_stats.syncp);
6609 tp->rx_stats.packets++;
6610 tp->rx_stats.bytes += pkt_size;
6611 u64_stats_update_end(&tp->rx_stats.syncp);
6612 }
6613 release_descriptor:
6614 desc->opts2 = 0;
6615 rtl8169_mark_to_asic(desc);
6616 }
6617
6618 count = cur_rx - tp->cur_rx;
6619 tp->cur_rx = cur_rx;
6620
6621 return count;
6622 }
6623
rtl8169_interrupt(int irq,void * dev_instance)6624 static irqreturn_t rtl8169_interrupt(int irq, void *dev_instance)
6625 {
6626 struct rtl8169_private *tp = dev_instance;
6627 u16 status = rtl_get_events(tp);
6628
6629 if (status == 0xffff || !(status & (RTL_EVENT_NAPI | tp->event_slow)))
6630 return IRQ_NONE;
6631
6632 rtl_irq_disable(tp);
6633 napi_schedule(&tp->napi);
6634
6635 return IRQ_HANDLED;
6636 }
6637
6638 /*
6639 * Workqueue context.
6640 */
rtl_slow_event_work(struct rtl8169_private * tp)6641 static void rtl_slow_event_work(struct rtl8169_private *tp)
6642 {
6643 struct net_device *dev = tp->dev;
6644 u16 status;
6645
6646 status = rtl_get_events(tp) & tp->event_slow;
6647 rtl_ack_events(tp, status);
6648
6649 if (unlikely(status & RxFIFOOver)) {
6650 switch (tp->mac_version) {
6651 /* Work around for rx fifo overflow */
6652 case RTL_GIGA_MAC_VER_11:
6653 netif_stop_queue(dev);
6654 /* XXX - Hack alert. See rtl_task(). */
6655 set_bit(RTL_FLAG_TASK_RESET_PENDING, tp->wk.flags);
6656 default:
6657 break;
6658 }
6659 }
6660
6661 if (unlikely(status & SYSErr))
6662 rtl8169_pcierr_interrupt(dev);
6663
6664 if (status & LinkChg)
6665 phy_mac_interrupt(dev->phydev);
6666
6667 rtl_irq_enable_all(tp);
6668 }
6669
rtl_task(struct work_struct * work)6670 static void rtl_task(struct work_struct *work)
6671 {
6672 static const struct {
6673 int bitnr;
6674 void (*action)(struct rtl8169_private *);
6675 } rtl_work[] = {
6676 /* XXX - keep rtl_slow_event_work() as first element. */
6677 { RTL_FLAG_TASK_SLOW_PENDING, rtl_slow_event_work },
6678 { RTL_FLAG_TASK_RESET_PENDING, rtl_reset_work },
6679 };
6680 struct rtl8169_private *tp =
6681 container_of(work, struct rtl8169_private, wk.work);
6682 struct net_device *dev = tp->dev;
6683 int i;
6684
6685 rtl_lock_work(tp);
6686
6687 if (!netif_running(dev) ||
6688 !test_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags))
6689 goto out_unlock;
6690
6691 for (i = 0; i < ARRAY_SIZE(rtl_work); i++) {
6692 bool pending;
6693
6694 pending = test_and_clear_bit(rtl_work[i].bitnr, tp->wk.flags);
6695 if (pending)
6696 rtl_work[i].action(tp);
6697 }
6698
6699 out_unlock:
6700 rtl_unlock_work(tp);
6701 }
6702
rtl8169_poll(struct napi_struct * napi,int budget)6703 static int rtl8169_poll(struct napi_struct *napi, int budget)
6704 {
6705 struct rtl8169_private *tp = container_of(napi, struct rtl8169_private, napi);
6706 struct net_device *dev = tp->dev;
6707 u16 enable_mask = RTL_EVENT_NAPI | tp->event_slow;
6708 int work_done;
6709 u16 status;
6710
6711 status = rtl_get_events(tp);
6712 rtl_ack_events(tp, status & ~tp->event_slow);
6713
6714 work_done = rtl_rx(dev, tp, (u32) budget);
6715
6716 rtl_tx(dev, tp);
6717
6718 if (status & tp->event_slow) {
6719 enable_mask &= ~tp->event_slow;
6720
6721 rtl_schedule_task(tp, RTL_FLAG_TASK_SLOW_PENDING);
6722 }
6723
6724 if (work_done < budget) {
6725 napi_complete_done(napi, work_done);
6726
6727 rtl_irq_enable(tp, enable_mask);
6728 mmiowb();
6729 }
6730
6731 return work_done;
6732 }
6733
rtl8169_rx_missed(struct net_device * dev)6734 static void rtl8169_rx_missed(struct net_device *dev)
6735 {
6736 struct rtl8169_private *tp = netdev_priv(dev);
6737
6738 if (tp->mac_version > RTL_GIGA_MAC_VER_06)
6739 return;
6740
6741 dev->stats.rx_missed_errors += RTL_R32(tp, RxMissed) & 0xffffff;
6742 RTL_W32(tp, RxMissed, 0);
6743 }
6744
r8169_phylink_handler(struct net_device * ndev)6745 static void r8169_phylink_handler(struct net_device *ndev)
6746 {
6747 struct rtl8169_private *tp = netdev_priv(ndev);
6748
6749 if (netif_carrier_ok(ndev)) {
6750 rtl_link_chg_patch(tp);
6751 pm_request_resume(&tp->pci_dev->dev);
6752 } else {
6753 pm_runtime_idle(&tp->pci_dev->dev);
6754 }
6755
6756 if (net_ratelimit())
6757 phy_print_status(ndev->phydev);
6758 }
6759
r8169_phy_connect(struct rtl8169_private * tp)6760 static int r8169_phy_connect(struct rtl8169_private *tp)
6761 {
6762 struct phy_device *phydev = mdiobus_get_phy(tp->mii_bus, 0);
6763 phy_interface_t phy_mode;
6764 int ret;
6765
6766 phy_mode = tp->supports_gmii ? PHY_INTERFACE_MODE_GMII :
6767 PHY_INTERFACE_MODE_MII;
6768
6769 ret = phy_connect_direct(tp->dev, phydev, r8169_phylink_handler,
6770 phy_mode);
6771 if (ret)
6772 return ret;
6773
6774 if (!tp->supports_gmii)
6775 phy_set_max_speed(phydev, SPEED_100);
6776
6777 /* Ensure to advertise everything, incl. pause */
6778 phydev->advertising = phydev->supported;
6779
6780 phy_attached_info(phydev);
6781
6782 return 0;
6783 }
6784
rtl8169_down(struct net_device * dev)6785 static void rtl8169_down(struct net_device *dev)
6786 {
6787 struct rtl8169_private *tp = netdev_priv(dev);
6788
6789 phy_stop(dev->phydev);
6790
6791 napi_disable(&tp->napi);
6792 netif_stop_queue(dev);
6793
6794 rtl8169_hw_reset(tp);
6795 /*
6796 * At this point device interrupts can not be enabled in any function,
6797 * as netif_running is not true (rtl8169_interrupt, rtl8169_reset_task)
6798 * and napi is disabled (rtl8169_poll).
6799 */
6800 rtl8169_rx_missed(dev);
6801
6802 /* Give a racing hard_start_xmit a few cycles to complete. */
6803 synchronize_sched();
6804
6805 rtl8169_tx_clear(tp);
6806
6807 rtl8169_rx_clear(tp);
6808
6809 rtl_pll_power_down(tp);
6810 }
6811
rtl8169_close(struct net_device * dev)6812 static int rtl8169_close(struct net_device *dev)
6813 {
6814 struct rtl8169_private *tp = netdev_priv(dev);
6815 struct pci_dev *pdev = tp->pci_dev;
6816
6817 pm_runtime_get_sync(&pdev->dev);
6818
6819 /* Update counters before going down */
6820 rtl8169_update_counters(tp);
6821
6822 rtl_lock_work(tp);
6823 /* Clear all task flags */
6824 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
6825
6826 rtl8169_down(dev);
6827 rtl_unlock_work(tp);
6828
6829 cancel_work_sync(&tp->wk.work);
6830
6831 phy_disconnect(dev->phydev);
6832
6833 free_irq(pci_irq_vector(pdev, 0), tp);
6834
6835 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6836 tp->RxPhyAddr);
6837 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6838 tp->TxPhyAddr);
6839 tp->TxDescArray = NULL;
6840 tp->RxDescArray = NULL;
6841
6842 pm_runtime_put_sync(&pdev->dev);
6843
6844 return 0;
6845 }
6846
6847 #ifdef CONFIG_NET_POLL_CONTROLLER
rtl8169_netpoll(struct net_device * dev)6848 static void rtl8169_netpoll(struct net_device *dev)
6849 {
6850 struct rtl8169_private *tp = netdev_priv(dev);
6851
6852 rtl8169_interrupt(pci_irq_vector(tp->pci_dev, 0), tp);
6853 }
6854 #endif
6855
rtl_open(struct net_device * dev)6856 static int rtl_open(struct net_device *dev)
6857 {
6858 struct rtl8169_private *tp = netdev_priv(dev);
6859 struct pci_dev *pdev = tp->pci_dev;
6860 int retval = -ENOMEM;
6861
6862 pm_runtime_get_sync(&pdev->dev);
6863
6864 /*
6865 * Rx and Tx descriptors needs 256 bytes alignment.
6866 * dma_alloc_coherent provides more.
6867 */
6868 tp->TxDescArray = dma_alloc_coherent(&pdev->dev, R8169_TX_RING_BYTES,
6869 &tp->TxPhyAddr, GFP_KERNEL);
6870 if (!tp->TxDescArray)
6871 goto err_pm_runtime_put;
6872
6873 tp->RxDescArray = dma_alloc_coherent(&pdev->dev, R8169_RX_RING_BYTES,
6874 &tp->RxPhyAddr, GFP_KERNEL);
6875 if (!tp->RxDescArray)
6876 goto err_free_tx_0;
6877
6878 retval = rtl8169_init_ring(tp);
6879 if (retval < 0)
6880 goto err_free_rx_1;
6881
6882 INIT_WORK(&tp->wk.work, rtl_task);
6883
6884 smp_mb();
6885
6886 rtl_request_firmware(tp);
6887
6888 retval = request_irq(pci_irq_vector(pdev, 0), rtl8169_interrupt,
6889 IRQF_SHARED, dev->name, tp);
6890 if (retval < 0)
6891 goto err_release_fw_2;
6892
6893 retval = r8169_phy_connect(tp);
6894 if (retval)
6895 goto err_free_irq;
6896
6897 rtl_lock_work(tp);
6898
6899 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
6900
6901 napi_enable(&tp->napi);
6902
6903 rtl8169_init_phy(dev, tp);
6904
6905 rtl_pll_power_up(tp);
6906
6907 rtl_hw_start(tp);
6908
6909 if (!rtl8169_init_counter_offsets(tp))
6910 netif_warn(tp, hw, dev, "counter reset/update failed\n");
6911
6912 phy_start(dev->phydev);
6913 netif_start_queue(dev);
6914
6915 rtl_unlock_work(tp);
6916
6917 pm_runtime_put_sync(&pdev->dev);
6918 out:
6919 return retval;
6920
6921 err_free_irq:
6922 free_irq(pci_irq_vector(pdev, 0), tp);
6923 err_release_fw_2:
6924 rtl_release_firmware(tp);
6925 rtl8169_rx_clear(tp);
6926 err_free_rx_1:
6927 dma_free_coherent(&pdev->dev, R8169_RX_RING_BYTES, tp->RxDescArray,
6928 tp->RxPhyAddr);
6929 tp->RxDescArray = NULL;
6930 err_free_tx_0:
6931 dma_free_coherent(&pdev->dev, R8169_TX_RING_BYTES, tp->TxDescArray,
6932 tp->TxPhyAddr);
6933 tp->TxDescArray = NULL;
6934 err_pm_runtime_put:
6935 pm_runtime_put_noidle(&pdev->dev);
6936 goto out;
6937 }
6938
6939 static void
rtl8169_get_stats64(struct net_device * dev,struct rtnl_link_stats64 * stats)6940 rtl8169_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats)
6941 {
6942 struct rtl8169_private *tp = netdev_priv(dev);
6943 struct pci_dev *pdev = tp->pci_dev;
6944 struct rtl8169_counters *counters = tp->counters;
6945 unsigned int start;
6946
6947 pm_runtime_get_noresume(&pdev->dev);
6948
6949 if (netif_running(dev) && pm_runtime_active(&pdev->dev))
6950 rtl8169_rx_missed(dev);
6951
6952 do {
6953 start = u64_stats_fetch_begin_irq(&tp->rx_stats.syncp);
6954 stats->rx_packets = tp->rx_stats.packets;
6955 stats->rx_bytes = tp->rx_stats.bytes;
6956 } while (u64_stats_fetch_retry_irq(&tp->rx_stats.syncp, start));
6957
6958 do {
6959 start = u64_stats_fetch_begin_irq(&tp->tx_stats.syncp);
6960 stats->tx_packets = tp->tx_stats.packets;
6961 stats->tx_bytes = tp->tx_stats.bytes;
6962 } while (u64_stats_fetch_retry_irq(&tp->tx_stats.syncp, start));
6963
6964 stats->rx_dropped = dev->stats.rx_dropped;
6965 stats->tx_dropped = dev->stats.tx_dropped;
6966 stats->rx_length_errors = dev->stats.rx_length_errors;
6967 stats->rx_errors = dev->stats.rx_errors;
6968 stats->rx_crc_errors = dev->stats.rx_crc_errors;
6969 stats->rx_fifo_errors = dev->stats.rx_fifo_errors;
6970 stats->rx_missed_errors = dev->stats.rx_missed_errors;
6971 stats->multicast = dev->stats.multicast;
6972
6973 /*
6974 * Fetch additonal counter values missing in stats collected by driver
6975 * from tally counters.
6976 */
6977 if (pm_runtime_active(&pdev->dev))
6978 rtl8169_update_counters(tp);
6979
6980 /*
6981 * Subtract values fetched during initalization.
6982 * See rtl8169_init_counter_offsets for a description why we do that.
6983 */
6984 stats->tx_errors = le64_to_cpu(counters->tx_errors) -
6985 le64_to_cpu(tp->tc_offset.tx_errors);
6986 stats->collisions = le32_to_cpu(counters->tx_multi_collision) -
6987 le32_to_cpu(tp->tc_offset.tx_multi_collision);
6988 stats->tx_aborted_errors = le16_to_cpu(counters->tx_aborted) -
6989 le16_to_cpu(tp->tc_offset.tx_aborted);
6990
6991 pm_runtime_put_noidle(&pdev->dev);
6992 }
6993
rtl8169_net_suspend(struct net_device * dev)6994 static void rtl8169_net_suspend(struct net_device *dev)
6995 {
6996 struct rtl8169_private *tp = netdev_priv(dev);
6997
6998 if (!netif_running(dev))
6999 return;
7000
7001 phy_stop(dev->phydev);
7002 netif_device_detach(dev);
7003 netif_stop_queue(dev);
7004
7005 rtl_lock_work(tp);
7006 napi_disable(&tp->napi);
7007 /* Clear all task flags */
7008 bitmap_zero(tp->wk.flags, RTL_FLAG_MAX);
7009
7010 rtl_unlock_work(tp);
7011
7012 rtl_pll_power_down(tp);
7013 }
7014
7015 #ifdef CONFIG_PM
7016
rtl8169_suspend(struct device * device)7017 static int rtl8169_suspend(struct device *device)
7018 {
7019 struct pci_dev *pdev = to_pci_dev(device);
7020 struct net_device *dev = pci_get_drvdata(pdev);
7021 struct rtl8169_private *tp = netdev_priv(dev);
7022
7023 rtl8169_net_suspend(dev);
7024 clk_disable_unprepare(tp->clk);
7025
7026 return 0;
7027 }
7028
__rtl8169_resume(struct net_device * dev)7029 static void __rtl8169_resume(struct net_device *dev)
7030 {
7031 struct rtl8169_private *tp = netdev_priv(dev);
7032
7033 netif_device_attach(dev);
7034
7035 rtl_pll_power_up(tp);
7036 rtl8169_init_phy(dev, tp);
7037
7038 phy_start(tp->dev->phydev);
7039
7040 rtl_lock_work(tp);
7041 napi_enable(&tp->napi);
7042 set_bit(RTL_FLAG_TASK_ENABLED, tp->wk.flags);
7043 rtl_unlock_work(tp);
7044
7045 rtl_schedule_task(tp, RTL_FLAG_TASK_RESET_PENDING);
7046 }
7047
rtl8169_resume(struct device * device)7048 static int rtl8169_resume(struct device *device)
7049 {
7050 struct pci_dev *pdev = to_pci_dev(device);
7051 struct net_device *dev = pci_get_drvdata(pdev);
7052 struct rtl8169_private *tp = netdev_priv(dev);
7053
7054 clk_prepare_enable(tp->clk);
7055
7056 if (netif_running(dev))
7057 __rtl8169_resume(dev);
7058
7059 return 0;
7060 }
7061
rtl8169_runtime_suspend(struct device * device)7062 static int rtl8169_runtime_suspend(struct device *device)
7063 {
7064 struct pci_dev *pdev = to_pci_dev(device);
7065 struct net_device *dev = pci_get_drvdata(pdev);
7066 struct rtl8169_private *tp = netdev_priv(dev);
7067
7068 if (!tp->TxDescArray)
7069 return 0;
7070
7071 rtl_lock_work(tp);
7072 __rtl8169_set_wol(tp, WAKE_ANY);
7073 rtl_unlock_work(tp);
7074
7075 rtl8169_net_suspend(dev);
7076
7077 /* Update counters before going runtime suspend */
7078 rtl8169_rx_missed(dev);
7079 rtl8169_update_counters(tp);
7080
7081 return 0;
7082 }
7083
rtl8169_runtime_resume(struct device * device)7084 static int rtl8169_runtime_resume(struct device *device)
7085 {
7086 struct pci_dev *pdev = to_pci_dev(device);
7087 struct net_device *dev = pci_get_drvdata(pdev);
7088 struct rtl8169_private *tp = netdev_priv(dev);
7089 rtl_rar_set(tp, dev->dev_addr);
7090
7091 if (!tp->TxDescArray)
7092 return 0;
7093
7094 rtl_lock_work(tp);
7095 __rtl8169_set_wol(tp, tp->saved_wolopts);
7096 rtl_unlock_work(tp);
7097
7098 __rtl8169_resume(dev);
7099
7100 return 0;
7101 }
7102
rtl8169_runtime_idle(struct device * device)7103 static int rtl8169_runtime_idle(struct device *device)
7104 {
7105 struct pci_dev *pdev = to_pci_dev(device);
7106 struct net_device *dev = pci_get_drvdata(pdev);
7107
7108 if (!netif_running(dev) || !netif_carrier_ok(dev))
7109 pm_schedule_suspend(device, 10000);
7110
7111 return -EBUSY;
7112 }
7113
7114 static const struct dev_pm_ops rtl8169_pm_ops = {
7115 .suspend = rtl8169_suspend,
7116 .resume = rtl8169_resume,
7117 .freeze = rtl8169_suspend,
7118 .thaw = rtl8169_resume,
7119 .poweroff = rtl8169_suspend,
7120 .restore = rtl8169_resume,
7121 .runtime_suspend = rtl8169_runtime_suspend,
7122 .runtime_resume = rtl8169_runtime_resume,
7123 .runtime_idle = rtl8169_runtime_idle,
7124 };
7125
7126 #define RTL8169_PM_OPS (&rtl8169_pm_ops)
7127
7128 #else /* !CONFIG_PM */
7129
7130 #define RTL8169_PM_OPS NULL
7131
7132 #endif /* !CONFIG_PM */
7133
rtl_wol_shutdown_quirk(struct rtl8169_private * tp)7134 static void rtl_wol_shutdown_quirk(struct rtl8169_private *tp)
7135 {
7136 /* WoL fails with 8168b when the receiver is disabled. */
7137 switch (tp->mac_version) {
7138 case RTL_GIGA_MAC_VER_11:
7139 case RTL_GIGA_MAC_VER_12:
7140 case RTL_GIGA_MAC_VER_17:
7141 pci_clear_master(tp->pci_dev);
7142
7143 RTL_W8(tp, ChipCmd, CmdRxEnb);
7144 /* PCI commit */
7145 RTL_R8(tp, ChipCmd);
7146 break;
7147 default:
7148 break;
7149 }
7150 }
7151
rtl_shutdown(struct pci_dev * pdev)7152 static void rtl_shutdown(struct pci_dev *pdev)
7153 {
7154 struct net_device *dev = pci_get_drvdata(pdev);
7155 struct rtl8169_private *tp = netdev_priv(dev);
7156
7157 rtl8169_net_suspend(dev);
7158
7159 /* Restore original MAC address */
7160 rtl_rar_set(tp, dev->perm_addr);
7161
7162 rtl8169_hw_reset(tp);
7163
7164 if (system_state == SYSTEM_POWER_OFF) {
7165 if (tp->saved_wolopts) {
7166 rtl_wol_suspend_quirk(tp);
7167 rtl_wol_shutdown_quirk(tp);
7168 }
7169
7170 pci_wake_from_d3(pdev, true);
7171 pci_set_power_state(pdev, PCI_D3hot);
7172 }
7173 }
7174
rtl_remove_one(struct pci_dev * pdev)7175 static void rtl_remove_one(struct pci_dev *pdev)
7176 {
7177 struct net_device *dev = pci_get_drvdata(pdev);
7178 struct rtl8169_private *tp = netdev_priv(dev);
7179
7180 if (r8168_check_dash(tp))
7181 rtl8168_driver_stop(tp);
7182
7183 netif_napi_del(&tp->napi);
7184
7185 unregister_netdev(dev);
7186 mdiobus_unregister(tp->mii_bus);
7187
7188 rtl_release_firmware(tp);
7189
7190 if (pci_dev_run_wake(pdev))
7191 pm_runtime_get_noresume(&pdev->dev);
7192
7193 /* restore original MAC address */
7194 rtl_rar_set(tp, dev->perm_addr);
7195 }
7196
7197 static const struct net_device_ops rtl_netdev_ops = {
7198 .ndo_open = rtl_open,
7199 .ndo_stop = rtl8169_close,
7200 .ndo_get_stats64 = rtl8169_get_stats64,
7201 .ndo_start_xmit = rtl8169_start_xmit,
7202 .ndo_tx_timeout = rtl8169_tx_timeout,
7203 .ndo_validate_addr = eth_validate_addr,
7204 .ndo_change_mtu = rtl8169_change_mtu,
7205 .ndo_fix_features = rtl8169_fix_features,
7206 .ndo_set_features = rtl8169_set_features,
7207 .ndo_set_mac_address = rtl_set_mac_address,
7208 .ndo_do_ioctl = rtl8169_ioctl,
7209 .ndo_set_rx_mode = rtl_set_rx_mode,
7210 #ifdef CONFIG_NET_POLL_CONTROLLER
7211 .ndo_poll_controller = rtl8169_netpoll,
7212 #endif
7213
7214 };
7215
7216 static const struct rtl_cfg_info {
7217 void (*hw_start)(struct rtl8169_private *tp);
7218 u16 event_slow;
7219 unsigned int has_gmii:1;
7220 const struct rtl_coalesce_info *coalesce_info;
7221 u8 default_ver;
7222 } rtl_cfg_infos [] = {
7223 [RTL_CFG_0] = {
7224 .hw_start = rtl_hw_start_8169,
7225 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver,
7226 .has_gmii = 1,
7227 .coalesce_info = rtl_coalesce_info_8169,
7228 .default_ver = RTL_GIGA_MAC_VER_01,
7229 },
7230 [RTL_CFG_1] = {
7231 .hw_start = rtl_hw_start_8168,
7232 .event_slow = SYSErr | LinkChg | RxOverflow,
7233 .has_gmii = 1,
7234 .coalesce_info = rtl_coalesce_info_8168_8136,
7235 .default_ver = RTL_GIGA_MAC_VER_11,
7236 },
7237 [RTL_CFG_2] = {
7238 .hw_start = rtl_hw_start_8101,
7239 .event_slow = SYSErr | LinkChg | RxOverflow | RxFIFOOver |
7240 PCSTimeout,
7241 .coalesce_info = rtl_coalesce_info_8168_8136,
7242 .default_ver = RTL_GIGA_MAC_VER_13,
7243 }
7244 };
7245
rtl_alloc_irq(struct rtl8169_private * tp)7246 static int rtl_alloc_irq(struct rtl8169_private *tp)
7247 {
7248 unsigned int flags;
7249
7250 switch (tp->mac_version) {
7251 case RTL_GIGA_MAC_VER_02 ... RTL_GIGA_MAC_VER_06:
7252 RTL_W8(tp, Cfg9346, Cfg9346_Unlock);
7253 RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~MSIEnable);
7254 RTL_W8(tp, Cfg9346, Cfg9346_Lock);
7255 /* fall through */
7256 case RTL_GIGA_MAC_VER_07 ... RTL_GIGA_MAC_VER_17:
7257 flags = PCI_IRQ_LEGACY;
7258 break;
7259 default:
7260 flags = PCI_IRQ_ALL_TYPES;
7261 break;
7262 }
7263
7264 return pci_alloc_irq_vectors(tp->pci_dev, 1, 1, flags);
7265 }
7266
DECLARE_RTL_COND(rtl_link_list_ready_cond)7267 DECLARE_RTL_COND(rtl_link_list_ready_cond)
7268 {
7269 return RTL_R8(tp, MCU) & LINK_LIST_RDY;
7270 }
7271
DECLARE_RTL_COND(rtl_rxtx_empty_cond)7272 DECLARE_RTL_COND(rtl_rxtx_empty_cond)
7273 {
7274 return (RTL_R8(tp, MCU) & RXTX_EMPTY) == RXTX_EMPTY;
7275 }
7276
r8169_mdio_read_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg)7277 static int r8169_mdio_read_reg(struct mii_bus *mii_bus, int phyaddr, int phyreg)
7278 {
7279 struct rtl8169_private *tp = mii_bus->priv;
7280
7281 if (phyaddr > 0)
7282 return -ENODEV;
7283
7284 return rtl_readphy(tp, phyreg);
7285 }
7286
r8169_mdio_write_reg(struct mii_bus * mii_bus,int phyaddr,int phyreg,u16 val)7287 static int r8169_mdio_write_reg(struct mii_bus *mii_bus, int phyaddr,
7288 int phyreg, u16 val)
7289 {
7290 struct rtl8169_private *tp = mii_bus->priv;
7291
7292 if (phyaddr > 0)
7293 return -ENODEV;
7294
7295 rtl_writephy(tp, phyreg, val);
7296
7297 return 0;
7298 }
7299
r8169_mdio_register(struct rtl8169_private * tp)7300 static int r8169_mdio_register(struct rtl8169_private *tp)
7301 {
7302 struct pci_dev *pdev = tp->pci_dev;
7303 struct phy_device *phydev;
7304 struct mii_bus *new_bus;
7305 int ret;
7306
7307 new_bus = devm_mdiobus_alloc(&pdev->dev);
7308 if (!new_bus)
7309 return -ENOMEM;
7310
7311 new_bus->name = "r8169";
7312 new_bus->priv = tp;
7313 new_bus->parent = &pdev->dev;
7314 new_bus->irq[0] = PHY_IGNORE_INTERRUPT;
7315 snprintf(new_bus->id, MII_BUS_ID_SIZE, "r8169-%x",
7316 PCI_DEVID(pdev->bus->number, pdev->devfn));
7317
7318 new_bus->read = r8169_mdio_read_reg;
7319 new_bus->write = r8169_mdio_write_reg;
7320
7321 ret = mdiobus_register(new_bus);
7322 if (ret)
7323 return ret;
7324
7325 phydev = mdiobus_get_phy(new_bus, 0);
7326 if (!phydev) {
7327 mdiobus_unregister(new_bus);
7328 return -ENODEV;
7329 }
7330
7331 /* PHY will be woken up in rtl_open() */
7332 phy_suspend(phydev);
7333
7334 tp->mii_bus = new_bus;
7335
7336 return 0;
7337 }
7338
rtl_hw_init_8168g(struct rtl8169_private * tp)7339 static void rtl_hw_init_8168g(struct rtl8169_private *tp)
7340 {
7341 u32 data;
7342
7343 tp->ocp_base = OCP_STD_PHY_BASE;
7344
7345 RTL_W32(tp, MISC, RTL_R32(tp, MISC) | RXDV_GATED_EN);
7346
7347 if (!rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 42))
7348 return;
7349
7350 if (!rtl_udelay_loop_wait_high(tp, &rtl_rxtx_empty_cond, 100, 42))
7351 return;
7352
7353 RTL_W8(tp, ChipCmd, RTL_R8(tp, ChipCmd) & ~(CmdTxEnb | CmdRxEnb));
7354 msleep(1);
7355 RTL_W8(tp, MCU, RTL_R8(tp, MCU) & ~NOW_IS_OOB);
7356
7357 data = r8168_mac_ocp_read(tp, 0xe8de);
7358 data &= ~(1 << 14);
7359 r8168_mac_ocp_write(tp, 0xe8de, data);
7360
7361 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7362 return;
7363
7364 data = r8168_mac_ocp_read(tp, 0xe8de);
7365 data |= (1 << 15);
7366 r8168_mac_ocp_write(tp, 0xe8de, data);
7367
7368 if (!rtl_udelay_loop_wait_high(tp, &rtl_link_list_ready_cond, 100, 42))
7369 return;
7370 }
7371
rtl_hw_init_8168ep(struct rtl8169_private * tp)7372 static void rtl_hw_init_8168ep(struct rtl8169_private *tp)
7373 {
7374 rtl8168ep_stop_cmac(tp);
7375 rtl_hw_init_8168g(tp);
7376 }
7377
rtl_hw_initialize(struct rtl8169_private * tp)7378 static void rtl_hw_initialize(struct rtl8169_private *tp)
7379 {
7380 switch (tp->mac_version) {
7381 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_48:
7382 rtl_hw_init_8168g(tp);
7383 break;
7384 case RTL_GIGA_MAC_VER_49 ... RTL_GIGA_MAC_VER_51:
7385 rtl_hw_init_8168ep(tp);
7386 break;
7387 default:
7388 break;
7389 }
7390 }
7391
7392 /* Versions RTL8102e and from RTL8168c onwards support csum_v2 */
rtl_chip_supports_csum_v2(struct rtl8169_private * tp)7393 static bool rtl_chip_supports_csum_v2(struct rtl8169_private *tp)
7394 {
7395 switch (tp->mac_version) {
7396 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7397 case RTL_GIGA_MAC_VER_10 ... RTL_GIGA_MAC_VER_17:
7398 return false;
7399 default:
7400 return true;
7401 }
7402 }
7403
rtl_jumbo_max(struct rtl8169_private * tp)7404 static int rtl_jumbo_max(struct rtl8169_private *tp)
7405 {
7406 /* Non-GBit versions don't support jumbo frames */
7407 if (!tp->supports_gmii)
7408 return JUMBO_1K;
7409
7410 switch (tp->mac_version) {
7411 /* RTL8169 */
7412 case RTL_GIGA_MAC_VER_01 ... RTL_GIGA_MAC_VER_06:
7413 return JUMBO_7K;
7414 /* RTL8168b */
7415 case RTL_GIGA_MAC_VER_11:
7416 case RTL_GIGA_MAC_VER_12:
7417 case RTL_GIGA_MAC_VER_17:
7418 return JUMBO_4K;
7419 /* RTL8168c */
7420 case RTL_GIGA_MAC_VER_18 ... RTL_GIGA_MAC_VER_24:
7421 return JUMBO_6K;
7422 default:
7423 return JUMBO_9K;
7424 }
7425 }
7426
rtl_disable_clk(void * data)7427 static void rtl_disable_clk(void *data)
7428 {
7429 clk_disable_unprepare(data);
7430 }
7431
rtl_init_one(struct pci_dev * pdev,const struct pci_device_id * ent)7432 static int rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
7433 {
7434 const struct rtl_cfg_info *cfg = rtl_cfg_infos + ent->driver_data;
7435 struct rtl8169_private *tp;
7436 struct net_device *dev;
7437 int chipset, region, i;
7438 int jumbo_max, rc;
7439
7440 dev = devm_alloc_etherdev(&pdev->dev, sizeof (*tp));
7441 if (!dev)
7442 return -ENOMEM;
7443
7444 SET_NETDEV_DEV(dev, &pdev->dev);
7445 dev->netdev_ops = &rtl_netdev_ops;
7446 tp = netdev_priv(dev);
7447 tp->dev = dev;
7448 tp->pci_dev = pdev;
7449 tp->msg_enable = netif_msg_init(debug.msg_enable, R8169_MSG_DEFAULT);
7450 tp->supports_gmii = cfg->has_gmii;
7451
7452 /* Get the *optional* external "ether_clk" used on some boards */
7453 tp->clk = devm_clk_get(&pdev->dev, "ether_clk");
7454 if (IS_ERR(tp->clk)) {
7455 rc = PTR_ERR(tp->clk);
7456 if (rc == -ENOENT) {
7457 /* clk-core allows NULL (for suspend / resume) */
7458 tp->clk = NULL;
7459 } else if (rc == -EPROBE_DEFER) {
7460 return rc;
7461 } else {
7462 dev_err(&pdev->dev, "failed to get clk: %d\n", rc);
7463 return rc;
7464 }
7465 } else {
7466 rc = clk_prepare_enable(tp->clk);
7467 if (rc) {
7468 dev_err(&pdev->dev, "failed to enable clk: %d\n", rc);
7469 return rc;
7470 }
7471
7472 rc = devm_add_action_or_reset(&pdev->dev, rtl_disable_clk,
7473 tp->clk);
7474 if (rc)
7475 return rc;
7476 }
7477
7478 /* Disable ASPM completely as that cause random device stop working
7479 * problems as well as full system hangs for some PCIe devices users.
7480 */
7481 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1);
7482
7483 /* enable device (incl. PCI PM wakeup and hotplug setup) */
7484 rc = pcim_enable_device(pdev);
7485 if (rc < 0) {
7486 dev_err(&pdev->dev, "enable failure\n");
7487 return rc;
7488 }
7489
7490 if (pcim_set_mwi(pdev) < 0)
7491 dev_info(&pdev->dev, "Mem-Wr-Inval unavailable\n");
7492
7493 /* use first MMIO region */
7494 region = ffs(pci_select_bars(pdev, IORESOURCE_MEM)) - 1;
7495 if (region < 0) {
7496 dev_err(&pdev->dev, "no MMIO resource found\n");
7497 return -ENODEV;
7498 }
7499
7500 /* check for weird/broken PCI region reporting */
7501 if (pci_resource_len(pdev, region) < R8169_REGS_SIZE) {
7502 dev_err(&pdev->dev, "Invalid PCI region size(s), aborting\n");
7503 return -ENODEV;
7504 }
7505
7506 rc = pcim_iomap_regions(pdev, BIT(region), MODULENAME);
7507 if (rc < 0) {
7508 dev_err(&pdev->dev, "cannot remap MMIO, aborting\n");
7509 return rc;
7510 }
7511
7512 tp->mmio_addr = pcim_iomap_table(pdev)[region];
7513
7514 if (!pci_is_pcie(pdev))
7515 dev_info(&pdev->dev, "not PCI Express\n");
7516
7517 /* Identify chip attached to board */
7518 rtl8169_get_mac_version(tp, cfg->default_ver);
7519
7520 if (rtl_tbi_enabled(tp)) {
7521 dev_err(&pdev->dev, "TBI fiber mode not supported\n");
7522 return -ENODEV;
7523 }
7524
7525 tp->cp_cmd = RTL_R16(tp, CPlusCmd);
7526
7527 if ((sizeof(dma_addr_t) > 4) &&
7528 (use_dac == 1 || (use_dac == -1 && pci_is_pcie(pdev) &&
7529 tp->mac_version >= RTL_GIGA_MAC_VER_18)) &&
7530 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) &&
7531 !pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
7532
7533 /* CPlusCmd Dual Access Cycle is only needed for non-PCIe */
7534 if (!pci_is_pcie(pdev))
7535 tp->cp_cmd |= PCIDAC;
7536 dev->features |= NETIF_F_HIGHDMA;
7537 } else {
7538 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7539 if (rc < 0) {
7540 dev_err(&pdev->dev, "DMA configuration failed\n");
7541 return rc;
7542 }
7543 }
7544
7545 rtl_init_rxcfg(tp);
7546
7547 rtl_irq_disable(tp);
7548
7549 rtl_hw_initialize(tp);
7550
7551 rtl_hw_reset(tp);
7552
7553 rtl_ack_events(tp, 0xffff);
7554
7555 pci_set_master(pdev);
7556
7557 rtl_init_mdio_ops(tp);
7558 rtl_init_jumbo_ops(tp);
7559
7560 rtl8169_print_mac_version(tp);
7561
7562 chipset = tp->mac_version;
7563
7564 rc = rtl_alloc_irq(tp);
7565 if (rc < 0) {
7566 dev_err(&pdev->dev, "Can't allocate interrupt\n");
7567 return rc;
7568 }
7569
7570 tp->saved_wolopts = __rtl8169_get_wol(tp);
7571
7572 mutex_init(&tp->wk.mutex);
7573 u64_stats_init(&tp->rx_stats.syncp);
7574 u64_stats_init(&tp->tx_stats.syncp);
7575
7576 /* Get MAC address */
7577 switch (tp->mac_version) {
7578 u8 mac_addr[ETH_ALEN] __aligned(4);
7579 case RTL_GIGA_MAC_VER_35 ... RTL_GIGA_MAC_VER_38:
7580 case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_51:
7581 *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xe0, ERIAR_EXGMAC);
7582 *(u16 *)&mac_addr[4] = rtl_eri_read(tp, 0xe4, ERIAR_EXGMAC);
7583
7584 if (is_valid_ether_addr(mac_addr))
7585 rtl_rar_set(tp, mac_addr);
7586 break;
7587 default:
7588 break;
7589 }
7590 for (i = 0; i < ETH_ALEN; i++)
7591 dev->dev_addr[i] = RTL_R8(tp, MAC0 + i);
7592
7593 dev->ethtool_ops = &rtl8169_ethtool_ops;
7594 dev->watchdog_timeo = RTL8169_TX_TIMEOUT;
7595
7596 netif_napi_add(dev, &tp->napi, rtl8169_poll, NAPI_POLL_WEIGHT);
7597
7598 /* don't enable SG, IP_CSUM and TSO by default - it might not work
7599 * properly for all devices */
7600 dev->features |= NETIF_F_RXCSUM |
7601 NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX;
7602
7603 dev->hw_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7604 NETIF_F_RXCSUM | NETIF_F_HW_VLAN_CTAG_TX |
7605 NETIF_F_HW_VLAN_CTAG_RX;
7606 dev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO |
7607 NETIF_F_HIGHDMA;
7608 dev->priv_flags |= IFF_LIVE_ADDR_CHANGE;
7609
7610 tp->cp_cmd |= RxChkSum | RxVlan;
7611
7612 /*
7613 * Pretend we are using VLANs; This bypasses a nasty bug where
7614 * Interrupts stop flowing on high load on 8110SCd controllers.
7615 */
7616 if (tp->mac_version == RTL_GIGA_MAC_VER_05)
7617 /* Disallow toggling */
7618 dev->hw_features &= ~NETIF_F_HW_VLAN_CTAG_RX;
7619
7620 if (rtl_chip_supports_csum_v2(tp)) {
7621 tp->tso_csum = rtl8169_tso_csum_v2;
7622 dev->hw_features |= NETIF_F_IPV6_CSUM | NETIF_F_TSO6;
7623 } else {
7624 tp->tso_csum = rtl8169_tso_csum_v1;
7625 }
7626
7627 dev->hw_features |= NETIF_F_RXALL;
7628 dev->hw_features |= NETIF_F_RXFCS;
7629
7630 /* MTU range: 60 - hw-specific max */
7631 dev->min_mtu = ETH_ZLEN;
7632 jumbo_max = rtl_jumbo_max(tp);
7633 dev->max_mtu = jumbo_max;
7634
7635 tp->hw_start = cfg->hw_start;
7636 tp->event_slow = cfg->event_slow;
7637 tp->coalesce_info = cfg->coalesce_info;
7638
7639 tp->rtl_fw = RTL_FIRMWARE_UNKNOWN;
7640
7641 tp->counters = dmam_alloc_coherent (&pdev->dev, sizeof(*tp->counters),
7642 &tp->counters_phys_addr,
7643 GFP_KERNEL);
7644 if (!tp->counters)
7645 return -ENOMEM;
7646
7647 pci_set_drvdata(pdev, dev);
7648
7649 rc = r8169_mdio_register(tp);
7650 if (rc)
7651 return rc;
7652
7653 /* chip gets powered up in rtl_open() */
7654 rtl_pll_power_down(tp);
7655
7656 rc = register_netdev(dev);
7657 if (rc)
7658 goto err_mdio_unregister;
7659
7660 netif_info(tp, probe, dev, "%s, %pM, XID %08x, IRQ %d\n",
7661 rtl_chip_infos[chipset].name, dev->dev_addr,
7662 (u32)(RTL_R32(tp, TxConfig) & 0xfcf0f8ff),
7663 pci_irq_vector(pdev, 0));
7664
7665 if (jumbo_max > JUMBO_1K)
7666 netif_info(tp, probe, dev,
7667 "jumbo features [frames: %d bytes, tx checksumming: %s]\n",
7668 jumbo_max, tp->mac_version <= RTL_GIGA_MAC_VER_06 ?
7669 "ok" : "ko");
7670
7671 if (r8168_check_dash(tp))
7672 rtl8168_driver_start(tp);
7673
7674 if (pci_dev_run_wake(pdev))
7675 pm_runtime_put_sync(&pdev->dev);
7676
7677 return 0;
7678
7679 err_mdio_unregister:
7680 mdiobus_unregister(tp->mii_bus);
7681 return rc;
7682 }
7683
7684 static struct pci_driver rtl8169_pci_driver = {
7685 .name = MODULENAME,
7686 .id_table = rtl8169_pci_tbl,
7687 .probe = rtl_init_one,
7688 .remove = rtl_remove_one,
7689 .shutdown = rtl_shutdown,
7690 .driver.pm = RTL8169_PM_OPS,
7691 };
7692
7693 module_pci_driver(rtl8169_pci_driver);
7694