1 // SPDX-License-Identifier: GPL-2.0
2 /* Renesas Ethernet AVB device driver
3 *
4 * Copyright (C) 2014-2019 Renesas Electronics Corporation
5 * Copyright (C) 2015 Renesas Solutions Corp.
6 * Copyright (C) 2015-2016 Cogent Embedded, Inc. <source@cogentembedded.com>
7 *
8 * Based on the SuperH Ethernet driver
9 */
10
11 #include <linux/cache.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/err.h>
16 #include <linux/etherdevice.h>
17 #include <linux/ethtool.h>
18 #include <linux/if_vlan.h>
19 #include <linux/kernel.h>
20 #include <linux/list.h>
21 #include <linux/module.h>
22 #include <linux/net_tstamp.h>
23 #include <linux/of.h>
24 #include <linux/of_device.h>
25 #include <linux/of_irq.h>
26 #include <linux/of_mdio.h>
27 #include <linux/of_net.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/sys_soc.h>
32
33 #include <asm/div64.h>
34
35 #include "ravb.h"
36
37 #define RAVB_DEF_MSG_ENABLE \
38 (NETIF_MSG_LINK | \
39 NETIF_MSG_TIMER | \
40 NETIF_MSG_RX_ERR | \
41 NETIF_MSG_TX_ERR)
42
43 static const char *ravb_rx_irqs[NUM_RX_QUEUE] = {
44 "ch0", /* RAVB_BE */
45 "ch1", /* RAVB_NC */
46 };
47
48 static const char *ravb_tx_irqs[NUM_TX_QUEUE] = {
49 "ch18", /* RAVB_BE */
50 "ch19", /* RAVB_NC */
51 };
52
ravb_modify(struct net_device * ndev,enum ravb_reg reg,u32 clear,u32 set)53 void ravb_modify(struct net_device *ndev, enum ravb_reg reg, u32 clear,
54 u32 set)
55 {
56 ravb_write(ndev, (ravb_read(ndev, reg) & ~clear) | set, reg);
57 }
58
ravb_wait(struct net_device * ndev,enum ravb_reg reg,u32 mask,u32 value)59 int ravb_wait(struct net_device *ndev, enum ravb_reg reg, u32 mask, u32 value)
60 {
61 int i;
62
63 for (i = 0; i < 10000; i++) {
64 if ((ravb_read(ndev, reg) & mask) == value)
65 return 0;
66 udelay(10);
67 }
68 return -ETIMEDOUT;
69 }
70
ravb_config(struct net_device * ndev)71 static int ravb_config(struct net_device *ndev)
72 {
73 int error;
74
75 /* Set config mode */
76 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
77 /* Check if the operating mode is changed to the config mode */
78 error = ravb_wait(ndev, CSR, CSR_OPS, CSR_OPS_CONFIG);
79 if (error)
80 netdev_err(ndev, "failed to switch device to config mode\n");
81
82 return error;
83 }
84
ravb_set_rate(struct net_device * ndev)85 static void ravb_set_rate(struct net_device *ndev)
86 {
87 struct ravb_private *priv = netdev_priv(ndev);
88
89 switch (priv->speed) {
90 case 100: /* 100BASE */
91 ravb_write(ndev, GECMR_SPEED_100, GECMR);
92 break;
93 case 1000: /* 1000BASE */
94 ravb_write(ndev, GECMR_SPEED_1000, GECMR);
95 break;
96 }
97 }
98
ravb_set_buffer_align(struct sk_buff * skb)99 static void ravb_set_buffer_align(struct sk_buff *skb)
100 {
101 u32 reserve = (unsigned long)skb->data & (RAVB_ALIGN - 1);
102
103 if (reserve)
104 skb_reserve(skb, RAVB_ALIGN - reserve);
105 }
106
107 /* Get MAC address from the MAC address registers
108 *
109 * Ethernet AVB device doesn't have ROM for MAC address.
110 * This function gets the MAC address that was used by a bootloader.
111 */
ravb_read_mac_address(struct net_device * ndev,const u8 * mac)112 static void ravb_read_mac_address(struct net_device *ndev, const u8 *mac)
113 {
114 if (mac) {
115 ether_addr_copy(ndev->dev_addr, mac);
116 } else {
117 u32 mahr = ravb_read(ndev, MAHR);
118 u32 malr = ravb_read(ndev, MALR);
119
120 ndev->dev_addr[0] = (mahr >> 24) & 0xFF;
121 ndev->dev_addr[1] = (mahr >> 16) & 0xFF;
122 ndev->dev_addr[2] = (mahr >> 8) & 0xFF;
123 ndev->dev_addr[3] = (mahr >> 0) & 0xFF;
124 ndev->dev_addr[4] = (malr >> 8) & 0xFF;
125 ndev->dev_addr[5] = (malr >> 0) & 0xFF;
126 }
127 }
128
ravb_mdio_ctrl(struct mdiobb_ctrl * ctrl,u32 mask,int set)129 static void ravb_mdio_ctrl(struct mdiobb_ctrl *ctrl, u32 mask, int set)
130 {
131 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
132 mdiobb);
133
134 ravb_modify(priv->ndev, PIR, mask, set ? mask : 0);
135 }
136
137 /* MDC pin control */
ravb_set_mdc(struct mdiobb_ctrl * ctrl,int level)138 static void ravb_set_mdc(struct mdiobb_ctrl *ctrl, int level)
139 {
140 ravb_mdio_ctrl(ctrl, PIR_MDC, level);
141 }
142
143 /* Data I/O pin control */
ravb_set_mdio_dir(struct mdiobb_ctrl * ctrl,int output)144 static void ravb_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
145 {
146 ravb_mdio_ctrl(ctrl, PIR_MMD, output);
147 }
148
149 /* Set data bit */
ravb_set_mdio_data(struct mdiobb_ctrl * ctrl,int value)150 static void ravb_set_mdio_data(struct mdiobb_ctrl *ctrl, int value)
151 {
152 ravb_mdio_ctrl(ctrl, PIR_MDO, value);
153 }
154
155 /* Get data bit */
ravb_get_mdio_data(struct mdiobb_ctrl * ctrl)156 static int ravb_get_mdio_data(struct mdiobb_ctrl *ctrl)
157 {
158 struct ravb_private *priv = container_of(ctrl, struct ravb_private,
159 mdiobb);
160
161 return (ravb_read(priv->ndev, PIR) & PIR_MDI) != 0;
162 }
163
164 /* MDIO bus control struct */
165 static struct mdiobb_ops bb_ops = {
166 .owner = THIS_MODULE,
167 .set_mdc = ravb_set_mdc,
168 .set_mdio_dir = ravb_set_mdio_dir,
169 .set_mdio_data = ravb_set_mdio_data,
170 .get_mdio_data = ravb_get_mdio_data,
171 };
172
173 /* Free TX skb function for AVB-IP */
ravb_tx_free(struct net_device * ndev,int q,bool free_txed_only)174 static int ravb_tx_free(struct net_device *ndev, int q, bool free_txed_only)
175 {
176 struct ravb_private *priv = netdev_priv(ndev);
177 struct net_device_stats *stats = &priv->stats[q];
178 struct ravb_tx_desc *desc;
179 int free_num = 0;
180 int entry;
181 u32 size;
182
183 for (; priv->cur_tx[q] - priv->dirty_tx[q] > 0; priv->dirty_tx[q]++) {
184 bool txed;
185
186 entry = priv->dirty_tx[q] % (priv->num_tx_ring[q] *
187 NUM_TX_DESC);
188 desc = &priv->tx_ring[q][entry];
189 txed = desc->die_dt == DT_FEMPTY;
190 if (free_txed_only && !txed)
191 break;
192 /* Descriptor type must be checked before all other reads */
193 dma_rmb();
194 size = le16_to_cpu(desc->ds_tagl) & TX_DS;
195 /* Free the original skb. */
196 if (priv->tx_skb[q][entry / NUM_TX_DESC]) {
197 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
198 size, DMA_TO_DEVICE);
199 /* Last packet descriptor? */
200 if (entry % NUM_TX_DESC == NUM_TX_DESC - 1) {
201 entry /= NUM_TX_DESC;
202 dev_kfree_skb_any(priv->tx_skb[q][entry]);
203 priv->tx_skb[q][entry] = NULL;
204 if (txed)
205 stats->tx_packets++;
206 }
207 free_num++;
208 }
209 if (txed)
210 stats->tx_bytes += size;
211 desc->die_dt = DT_EEMPTY;
212 }
213 return free_num;
214 }
215
216 /* Free skb's and DMA buffers for Ethernet AVB */
ravb_ring_free(struct net_device * ndev,int q)217 static void ravb_ring_free(struct net_device *ndev, int q)
218 {
219 struct ravb_private *priv = netdev_priv(ndev);
220 int ring_size;
221 int i;
222
223 if (priv->rx_ring[q]) {
224 for (i = 0; i < priv->num_rx_ring[q]; i++) {
225 struct ravb_ex_rx_desc *desc = &priv->rx_ring[q][i];
226
227 if (!dma_mapping_error(ndev->dev.parent,
228 le32_to_cpu(desc->dptr)))
229 dma_unmap_single(ndev->dev.parent,
230 le32_to_cpu(desc->dptr),
231 priv->rx_buf_sz,
232 DMA_FROM_DEVICE);
233 }
234 ring_size = sizeof(struct ravb_ex_rx_desc) *
235 (priv->num_rx_ring[q] + 1);
236 dma_free_coherent(ndev->dev.parent, ring_size, priv->rx_ring[q],
237 priv->rx_desc_dma[q]);
238 priv->rx_ring[q] = NULL;
239 }
240
241 if (priv->tx_ring[q]) {
242 ravb_tx_free(ndev, q, false);
243
244 ring_size = sizeof(struct ravb_tx_desc) *
245 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
246 dma_free_coherent(ndev->dev.parent, ring_size, priv->tx_ring[q],
247 priv->tx_desc_dma[q]);
248 priv->tx_ring[q] = NULL;
249 }
250
251 /* Free RX skb ringbuffer */
252 if (priv->rx_skb[q]) {
253 for (i = 0; i < priv->num_rx_ring[q]; i++)
254 dev_kfree_skb(priv->rx_skb[q][i]);
255 }
256 kfree(priv->rx_skb[q]);
257 priv->rx_skb[q] = NULL;
258
259 /* Free aligned TX buffers */
260 kfree(priv->tx_align[q]);
261 priv->tx_align[q] = NULL;
262
263 /* Free TX skb ringbuffer.
264 * SKBs are freed by ravb_tx_free() call above.
265 */
266 kfree(priv->tx_skb[q]);
267 priv->tx_skb[q] = NULL;
268 }
269
270 /* Format skb and descriptor buffer for Ethernet AVB */
ravb_ring_format(struct net_device * ndev,int q)271 static void ravb_ring_format(struct net_device *ndev, int q)
272 {
273 struct ravb_private *priv = netdev_priv(ndev);
274 struct ravb_ex_rx_desc *rx_desc;
275 struct ravb_tx_desc *tx_desc;
276 struct ravb_desc *desc;
277 int rx_ring_size = sizeof(*rx_desc) * priv->num_rx_ring[q];
278 int tx_ring_size = sizeof(*tx_desc) * priv->num_tx_ring[q] *
279 NUM_TX_DESC;
280 dma_addr_t dma_addr;
281 int i;
282
283 priv->cur_rx[q] = 0;
284 priv->cur_tx[q] = 0;
285 priv->dirty_rx[q] = 0;
286 priv->dirty_tx[q] = 0;
287
288 memset(priv->rx_ring[q], 0, rx_ring_size);
289 /* Build RX ring buffer */
290 for (i = 0; i < priv->num_rx_ring[q]; i++) {
291 /* RX descriptor */
292 rx_desc = &priv->rx_ring[q][i];
293 rx_desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
294 dma_addr = dma_map_single(ndev->dev.parent, priv->rx_skb[q][i]->data,
295 priv->rx_buf_sz,
296 DMA_FROM_DEVICE);
297 /* We just set the data size to 0 for a failed mapping which
298 * should prevent DMA from happening...
299 */
300 if (dma_mapping_error(ndev->dev.parent, dma_addr))
301 rx_desc->ds_cc = cpu_to_le16(0);
302 rx_desc->dptr = cpu_to_le32(dma_addr);
303 rx_desc->die_dt = DT_FEMPTY;
304 }
305 rx_desc = &priv->rx_ring[q][i];
306 rx_desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
307 rx_desc->die_dt = DT_LINKFIX; /* type */
308
309 memset(priv->tx_ring[q], 0, tx_ring_size);
310 /* Build TX ring buffer */
311 for (i = 0, tx_desc = priv->tx_ring[q]; i < priv->num_tx_ring[q];
312 i++, tx_desc++) {
313 tx_desc->die_dt = DT_EEMPTY;
314 tx_desc++;
315 tx_desc->die_dt = DT_EEMPTY;
316 }
317 tx_desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
318 tx_desc->die_dt = DT_LINKFIX; /* type */
319
320 /* RX descriptor base address for best effort */
321 desc = &priv->desc_bat[RX_QUEUE_OFFSET + q];
322 desc->die_dt = DT_LINKFIX; /* type */
323 desc->dptr = cpu_to_le32((u32)priv->rx_desc_dma[q]);
324
325 /* TX descriptor base address for best effort */
326 desc = &priv->desc_bat[q];
327 desc->die_dt = DT_LINKFIX; /* type */
328 desc->dptr = cpu_to_le32((u32)priv->tx_desc_dma[q]);
329 }
330
331 /* Init skb and descriptor buffer for Ethernet AVB */
ravb_ring_init(struct net_device * ndev,int q)332 static int ravb_ring_init(struct net_device *ndev, int q)
333 {
334 struct ravb_private *priv = netdev_priv(ndev);
335 struct sk_buff *skb;
336 int ring_size;
337 int i;
338
339 priv->rx_buf_sz = (ndev->mtu <= 1492 ? PKT_BUF_SZ : ndev->mtu) +
340 ETH_HLEN + VLAN_HLEN + sizeof(__sum16);
341
342 /* Allocate RX and TX skb rings */
343 priv->rx_skb[q] = kcalloc(priv->num_rx_ring[q],
344 sizeof(*priv->rx_skb[q]), GFP_KERNEL);
345 priv->tx_skb[q] = kcalloc(priv->num_tx_ring[q],
346 sizeof(*priv->tx_skb[q]), GFP_KERNEL);
347 if (!priv->rx_skb[q] || !priv->tx_skb[q])
348 goto error;
349
350 for (i = 0; i < priv->num_rx_ring[q]; i++) {
351 skb = netdev_alloc_skb(ndev, priv->rx_buf_sz + RAVB_ALIGN - 1);
352 if (!skb)
353 goto error;
354 ravb_set_buffer_align(skb);
355 priv->rx_skb[q][i] = skb;
356 }
357
358 /* Allocate rings for the aligned buffers */
359 priv->tx_align[q] = kmalloc(DPTR_ALIGN * priv->num_tx_ring[q] +
360 DPTR_ALIGN - 1, GFP_KERNEL);
361 if (!priv->tx_align[q])
362 goto error;
363
364 /* Allocate all RX descriptors. */
365 ring_size = sizeof(struct ravb_ex_rx_desc) * (priv->num_rx_ring[q] + 1);
366 priv->rx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
367 &priv->rx_desc_dma[q],
368 GFP_KERNEL);
369 if (!priv->rx_ring[q])
370 goto error;
371
372 priv->dirty_rx[q] = 0;
373
374 /* Allocate all TX descriptors. */
375 ring_size = sizeof(struct ravb_tx_desc) *
376 (priv->num_tx_ring[q] * NUM_TX_DESC + 1);
377 priv->tx_ring[q] = dma_alloc_coherent(ndev->dev.parent, ring_size,
378 &priv->tx_desc_dma[q],
379 GFP_KERNEL);
380 if (!priv->tx_ring[q])
381 goto error;
382
383 return 0;
384
385 error:
386 ravb_ring_free(ndev, q);
387
388 return -ENOMEM;
389 }
390
391 /* E-MAC init function */
ravb_emac_init(struct net_device * ndev)392 static void ravb_emac_init(struct net_device *ndev)
393 {
394 /* Receive frame limit set register */
395 ravb_write(ndev, ndev->mtu + ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN, RFLR);
396
397 /* EMAC Mode: PAUSE prohibition; Duplex; RX Checksum; TX; RX */
398 ravb_write(ndev, ECMR_ZPF | ECMR_DM |
399 (ndev->features & NETIF_F_RXCSUM ? ECMR_RCSC : 0) |
400 ECMR_TE | ECMR_RE, ECMR);
401
402 ravb_set_rate(ndev);
403
404 /* Set MAC address */
405 ravb_write(ndev,
406 (ndev->dev_addr[0] << 24) | (ndev->dev_addr[1] << 16) |
407 (ndev->dev_addr[2] << 8) | (ndev->dev_addr[3]), MAHR);
408 ravb_write(ndev,
409 (ndev->dev_addr[4] << 8) | (ndev->dev_addr[5]), MALR);
410
411 /* E-MAC status register clear */
412 ravb_write(ndev, ECSR_ICD | ECSR_MPD, ECSR);
413
414 /* E-MAC interrupt enable register */
415 ravb_write(ndev, ECSIPR_ICDIP | ECSIPR_MPDIP | ECSIPR_LCHNGIP, ECSIPR);
416 }
417
418 /* Device init function for Ethernet AVB */
ravb_dmac_init(struct net_device * ndev)419 static int ravb_dmac_init(struct net_device *ndev)
420 {
421 struct ravb_private *priv = netdev_priv(ndev);
422 int error;
423
424 /* Set CONFIG mode */
425 error = ravb_config(ndev);
426 if (error)
427 return error;
428
429 error = ravb_ring_init(ndev, RAVB_BE);
430 if (error)
431 return error;
432 error = ravb_ring_init(ndev, RAVB_NC);
433 if (error) {
434 ravb_ring_free(ndev, RAVB_BE);
435 return error;
436 }
437
438 /* Descriptor format */
439 ravb_ring_format(ndev, RAVB_BE);
440 ravb_ring_format(ndev, RAVB_NC);
441
442 #if defined(__LITTLE_ENDIAN)
443 ravb_modify(ndev, CCC, CCC_BOC, 0);
444 #else
445 ravb_modify(ndev, CCC, CCC_BOC, CCC_BOC);
446 #endif
447
448 /* Set AVB RX */
449 ravb_write(ndev,
450 RCR_EFFS | RCR_ENCF | RCR_ETS0 | RCR_ESF | 0x18000000, RCR);
451
452 /* Set FIFO size */
453 ravb_write(ndev, TGC_TQP_AVBMODE1 | 0x00112200, TGC);
454
455 /* Timestamp enable */
456 ravb_write(ndev, TCCR_TFEN, TCCR);
457
458 /* Interrupt init: */
459 if (priv->chip_id == RCAR_GEN3) {
460 /* Clear DIL.DPLx */
461 ravb_write(ndev, 0, DIL);
462 /* Set queue specific interrupt */
463 ravb_write(ndev, CIE_CRIE | CIE_CTIE | CIE_CL0M, CIE);
464 }
465 /* Frame receive */
466 ravb_write(ndev, RIC0_FRE0 | RIC0_FRE1, RIC0);
467 /* Disable FIFO full warning */
468 ravb_write(ndev, 0, RIC1);
469 /* Receive FIFO full error, descriptor empty */
470 ravb_write(ndev, RIC2_QFE0 | RIC2_QFE1 | RIC2_RFFE, RIC2);
471 /* Frame transmitted, timestamp FIFO updated */
472 ravb_write(ndev, TIC_FTE0 | TIC_FTE1 | TIC_TFUE, TIC);
473
474 /* Setting the control will start the AVB-DMAC process. */
475 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_OPERATION);
476
477 return 0;
478 }
479
ravb_get_tx_tstamp(struct net_device * ndev)480 static void ravb_get_tx_tstamp(struct net_device *ndev)
481 {
482 struct ravb_private *priv = netdev_priv(ndev);
483 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
484 struct skb_shared_hwtstamps shhwtstamps;
485 struct sk_buff *skb;
486 struct timespec64 ts;
487 u16 tag, tfa_tag;
488 int count;
489 u32 tfa2;
490
491 count = (ravb_read(ndev, TSR) & TSR_TFFL) >> 8;
492 while (count--) {
493 tfa2 = ravb_read(ndev, TFA2);
494 tfa_tag = (tfa2 & TFA2_TST) >> 16;
495 ts.tv_nsec = (u64)ravb_read(ndev, TFA0);
496 ts.tv_sec = ((u64)(tfa2 & TFA2_TSV) << 32) |
497 ravb_read(ndev, TFA1);
498 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
499 shhwtstamps.hwtstamp = timespec64_to_ktime(ts);
500 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list,
501 list) {
502 skb = ts_skb->skb;
503 tag = ts_skb->tag;
504 list_del(&ts_skb->list);
505 kfree(ts_skb);
506 if (tag == tfa_tag) {
507 skb_tstamp_tx(skb, &shhwtstamps);
508 dev_consume_skb_any(skb);
509 break;
510 } else {
511 dev_kfree_skb_any(skb);
512 }
513 }
514 ravb_modify(ndev, TCCR, TCCR_TFR, TCCR_TFR);
515 }
516 }
517
ravb_rx_csum(struct sk_buff * skb)518 static void ravb_rx_csum(struct sk_buff *skb)
519 {
520 u8 *hw_csum;
521
522 /* The hardware checksum is contained in sizeof(__sum16) (2) bytes
523 * appended to packet data
524 */
525 if (unlikely(skb->len < sizeof(__sum16)))
526 return;
527 hw_csum = skb_tail_pointer(skb) - sizeof(__sum16);
528 skb->csum = csum_unfold((__force __sum16)get_unaligned_le16(hw_csum));
529 skb->ip_summed = CHECKSUM_COMPLETE;
530 skb_trim(skb, skb->len - sizeof(__sum16));
531 }
532
533 /* Packet receive function for Ethernet AVB */
ravb_rx(struct net_device * ndev,int * quota,int q)534 static bool ravb_rx(struct net_device *ndev, int *quota, int q)
535 {
536 struct ravb_private *priv = netdev_priv(ndev);
537 int entry = priv->cur_rx[q] % priv->num_rx_ring[q];
538 int boguscnt = (priv->dirty_rx[q] + priv->num_rx_ring[q]) -
539 priv->cur_rx[q];
540 struct net_device_stats *stats = &priv->stats[q];
541 struct ravb_ex_rx_desc *desc;
542 struct sk_buff *skb;
543 dma_addr_t dma_addr;
544 struct timespec64 ts;
545 u8 desc_status;
546 u16 pkt_len;
547 int limit;
548
549 boguscnt = min(boguscnt, *quota);
550 limit = boguscnt;
551 desc = &priv->rx_ring[q][entry];
552 while (desc->die_dt != DT_FEMPTY) {
553 /* Descriptor type must be checked before all other reads */
554 dma_rmb();
555 desc_status = desc->msc;
556 pkt_len = le16_to_cpu(desc->ds_cc) & RX_DS;
557
558 if (--boguscnt < 0)
559 break;
560
561 /* We use 0-byte descriptors to mark the DMA mapping errors */
562 if (!pkt_len)
563 continue;
564
565 if (desc_status & MSC_MC)
566 stats->multicast++;
567
568 if (desc_status & (MSC_CRC | MSC_RFE | MSC_RTSF | MSC_RTLF |
569 MSC_CEEF)) {
570 stats->rx_errors++;
571 if (desc_status & MSC_CRC)
572 stats->rx_crc_errors++;
573 if (desc_status & MSC_RFE)
574 stats->rx_frame_errors++;
575 if (desc_status & (MSC_RTLF | MSC_RTSF))
576 stats->rx_length_errors++;
577 if (desc_status & MSC_CEEF)
578 stats->rx_missed_errors++;
579 } else {
580 u32 get_ts = priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE;
581
582 skb = priv->rx_skb[q][entry];
583 priv->rx_skb[q][entry] = NULL;
584 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
585 priv->rx_buf_sz,
586 DMA_FROM_DEVICE);
587 get_ts &= (q == RAVB_NC) ?
588 RAVB_RXTSTAMP_TYPE_V2_L2_EVENT :
589 ~RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
590 if (get_ts) {
591 struct skb_shared_hwtstamps *shhwtstamps;
592
593 shhwtstamps = skb_hwtstamps(skb);
594 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
595 ts.tv_sec = ((u64) le16_to_cpu(desc->ts_sh) <<
596 32) | le32_to_cpu(desc->ts_sl);
597 ts.tv_nsec = le32_to_cpu(desc->ts_n);
598 shhwtstamps->hwtstamp = timespec64_to_ktime(ts);
599 }
600
601 skb_put(skb, pkt_len);
602 skb->protocol = eth_type_trans(skb, ndev);
603 if (ndev->features & NETIF_F_RXCSUM)
604 ravb_rx_csum(skb);
605 napi_gro_receive(&priv->napi[q], skb);
606 stats->rx_packets++;
607 stats->rx_bytes += pkt_len;
608 }
609
610 entry = (++priv->cur_rx[q]) % priv->num_rx_ring[q];
611 desc = &priv->rx_ring[q][entry];
612 }
613
614 /* Refill the RX ring buffers. */
615 for (; priv->cur_rx[q] - priv->dirty_rx[q] > 0; priv->dirty_rx[q]++) {
616 entry = priv->dirty_rx[q] % priv->num_rx_ring[q];
617 desc = &priv->rx_ring[q][entry];
618 desc->ds_cc = cpu_to_le16(priv->rx_buf_sz);
619
620 if (!priv->rx_skb[q][entry]) {
621 skb = netdev_alloc_skb(ndev,
622 priv->rx_buf_sz +
623 RAVB_ALIGN - 1);
624 if (!skb)
625 break; /* Better luck next round. */
626 ravb_set_buffer_align(skb);
627 dma_addr = dma_map_single(ndev->dev.parent, skb->data,
628 le16_to_cpu(desc->ds_cc),
629 DMA_FROM_DEVICE);
630 skb_checksum_none_assert(skb);
631 /* We just set the data size to 0 for a failed mapping
632 * which should prevent DMA from happening...
633 */
634 if (dma_mapping_error(ndev->dev.parent, dma_addr))
635 desc->ds_cc = cpu_to_le16(0);
636 desc->dptr = cpu_to_le32(dma_addr);
637 priv->rx_skb[q][entry] = skb;
638 }
639 /* Descriptor type must be set after all the above writes */
640 dma_wmb();
641 desc->die_dt = DT_FEMPTY;
642 }
643
644 *quota -= limit - (++boguscnt);
645
646 return boguscnt <= 0;
647 }
648
ravb_rcv_snd_disable(struct net_device * ndev)649 static void ravb_rcv_snd_disable(struct net_device *ndev)
650 {
651 /* Disable TX and RX */
652 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, 0);
653 }
654
ravb_rcv_snd_enable(struct net_device * ndev)655 static void ravb_rcv_snd_enable(struct net_device *ndev)
656 {
657 /* Enable TX and RX */
658 ravb_modify(ndev, ECMR, ECMR_RE | ECMR_TE, ECMR_RE | ECMR_TE);
659 }
660
661 /* function for waiting dma process finished */
ravb_stop_dma(struct net_device * ndev)662 static int ravb_stop_dma(struct net_device *ndev)
663 {
664 int error;
665
666 /* Wait for stopping the hardware TX process */
667 error = ravb_wait(ndev, TCCR,
668 TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3, 0);
669 if (error)
670 return error;
671
672 error = ravb_wait(ndev, CSR, CSR_TPO0 | CSR_TPO1 | CSR_TPO2 | CSR_TPO3,
673 0);
674 if (error)
675 return error;
676
677 /* Stop the E-MAC's RX/TX processes. */
678 ravb_rcv_snd_disable(ndev);
679
680 /* Wait for stopping the RX DMA process */
681 error = ravb_wait(ndev, CSR, CSR_RPO, 0);
682 if (error)
683 return error;
684
685 /* Stop AVB-DMAC process */
686 return ravb_config(ndev);
687 }
688
689 /* E-MAC interrupt handler */
ravb_emac_interrupt_unlocked(struct net_device * ndev)690 static void ravb_emac_interrupt_unlocked(struct net_device *ndev)
691 {
692 struct ravb_private *priv = netdev_priv(ndev);
693 u32 ecsr, psr;
694
695 ecsr = ravb_read(ndev, ECSR);
696 ravb_write(ndev, ecsr, ECSR); /* clear interrupt */
697
698 if (ecsr & ECSR_MPD)
699 pm_wakeup_event(&priv->pdev->dev, 0);
700 if (ecsr & ECSR_ICD)
701 ndev->stats.tx_carrier_errors++;
702 if (ecsr & ECSR_LCHNG) {
703 /* Link changed */
704 if (priv->no_avb_link)
705 return;
706 psr = ravb_read(ndev, PSR);
707 if (priv->avb_link_active_low)
708 psr ^= PSR_LMON;
709 if (!(psr & PSR_LMON)) {
710 /* DIsable RX and TX */
711 ravb_rcv_snd_disable(ndev);
712 } else {
713 /* Enable RX and TX */
714 ravb_rcv_snd_enable(ndev);
715 }
716 }
717 }
718
ravb_emac_interrupt(int irq,void * dev_id)719 static irqreturn_t ravb_emac_interrupt(int irq, void *dev_id)
720 {
721 struct net_device *ndev = dev_id;
722 struct ravb_private *priv = netdev_priv(ndev);
723
724 spin_lock(&priv->lock);
725 ravb_emac_interrupt_unlocked(ndev);
726 mmiowb();
727 spin_unlock(&priv->lock);
728 return IRQ_HANDLED;
729 }
730
731 /* Error interrupt handler */
ravb_error_interrupt(struct net_device * ndev)732 static void ravb_error_interrupt(struct net_device *ndev)
733 {
734 struct ravb_private *priv = netdev_priv(ndev);
735 u32 eis, ris2;
736
737 eis = ravb_read(ndev, EIS);
738 ravb_write(ndev, ~(EIS_QFS | EIS_RESERVED), EIS);
739 if (eis & EIS_QFS) {
740 ris2 = ravb_read(ndev, RIS2);
741 ravb_write(ndev, ~(RIS2_QFF0 | RIS2_RFFF | RIS2_RESERVED),
742 RIS2);
743
744 /* Receive Descriptor Empty int */
745 if (ris2 & RIS2_QFF0)
746 priv->stats[RAVB_BE].rx_over_errors++;
747
748 /* Receive Descriptor Empty int */
749 if (ris2 & RIS2_QFF1)
750 priv->stats[RAVB_NC].rx_over_errors++;
751
752 /* Receive FIFO Overflow int */
753 if (ris2 & RIS2_RFFF)
754 priv->rx_fifo_errors++;
755 }
756 }
757
ravb_queue_interrupt(struct net_device * ndev,int q)758 static bool ravb_queue_interrupt(struct net_device *ndev, int q)
759 {
760 struct ravb_private *priv = netdev_priv(ndev);
761 u32 ris0 = ravb_read(ndev, RIS0);
762 u32 ric0 = ravb_read(ndev, RIC0);
763 u32 tis = ravb_read(ndev, TIS);
764 u32 tic = ravb_read(ndev, TIC);
765
766 if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
767 if (napi_schedule_prep(&priv->napi[q])) {
768 /* Mask RX and TX interrupts */
769 if (priv->chip_id == RCAR_GEN2) {
770 ravb_write(ndev, ric0 & ~BIT(q), RIC0);
771 ravb_write(ndev, tic & ~BIT(q), TIC);
772 } else {
773 ravb_write(ndev, BIT(q), RID0);
774 ravb_write(ndev, BIT(q), TID);
775 }
776 __napi_schedule(&priv->napi[q]);
777 } else {
778 netdev_warn(ndev,
779 "ignoring interrupt, rx status 0x%08x, rx mask 0x%08x,\n",
780 ris0, ric0);
781 netdev_warn(ndev,
782 " tx status 0x%08x, tx mask 0x%08x.\n",
783 tis, tic);
784 }
785 return true;
786 }
787 return false;
788 }
789
ravb_timestamp_interrupt(struct net_device * ndev)790 static bool ravb_timestamp_interrupt(struct net_device *ndev)
791 {
792 u32 tis = ravb_read(ndev, TIS);
793
794 if (tis & TIS_TFUF) {
795 ravb_write(ndev, ~(TIS_TFUF | TIS_RESERVED), TIS);
796 ravb_get_tx_tstamp(ndev);
797 return true;
798 }
799 return false;
800 }
801
ravb_interrupt(int irq,void * dev_id)802 static irqreturn_t ravb_interrupt(int irq, void *dev_id)
803 {
804 struct net_device *ndev = dev_id;
805 struct ravb_private *priv = netdev_priv(ndev);
806 irqreturn_t result = IRQ_NONE;
807 u32 iss;
808
809 spin_lock(&priv->lock);
810 /* Get interrupt status */
811 iss = ravb_read(ndev, ISS);
812
813 /* Received and transmitted interrupts */
814 if (iss & (ISS_FRS | ISS_FTS | ISS_TFUS)) {
815 int q;
816
817 /* Timestamp updated */
818 if (ravb_timestamp_interrupt(ndev))
819 result = IRQ_HANDLED;
820
821 /* Network control and best effort queue RX/TX */
822 for (q = RAVB_NC; q >= RAVB_BE; q--) {
823 if (ravb_queue_interrupt(ndev, q))
824 result = IRQ_HANDLED;
825 }
826 }
827
828 /* E-MAC status summary */
829 if (iss & ISS_MS) {
830 ravb_emac_interrupt_unlocked(ndev);
831 result = IRQ_HANDLED;
832 }
833
834 /* Error status summary */
835 if (iss & ISS_ES) {
836 ravb_error_interrupt(ndev);
837 result = IRQ_HANDLED;
838 }
839
840 /* gPTP interrupt status summary */
841 if (iss & ISS_CGIS) {
842 ravb_ptp_interrupt(ndev);
843 result = IRQ_HANDLED;
844 }
845
846 mmiowb();
847 spin_unlock(&priv->lock);
848 return result;
849 }
850
851 /* Timestamp/Error/gPTP interrupt handler */
ravb_multi_interrupt(int irq,void * dev_id)852 static irqreturn_t ravb_multi_interrupt(int irq, void *dev_id)
853 {
854 struct net_device *ndev = dev_id;
855 struct ravb_private *priv = netdev_priv(ndev);
856 irqreturn_t result = IRQ_NONE;
857 u32 iss;
858
859 spin_lock(&priv->lock);
860 /* Get interrupt status */
861 iss = ravb_read(ndev, ISS);
862
863 /* Timestamp updated */
864 if ((iss & ISS_TFUS) && ravb_timestamp_interrupt(ndev))
865 result = IRQ_HANDLED;
866
867 /* Error status summary */
868 if (iss & ISS_ES) {
869 ravb_error_interrupt(ndev);
870 result = IRQ_HANDLED;
871 }
872
873 /* gPTP interrupt status summary */
874 if (iss & ISS_CGIS) {
875 ravb_ptp_interrupt(ndev);
876 result = IRQ_HANDLED;
877 }
878
879 mmiowb();
880 spin_unlock(&priv->lock);
881 return result;
882 }
883
ravb_dma_interrupt(int irq,void * dev_id,int q)884 static irqreturn_t ravb_dma_interrupt(int irq, void *dev_id, int q)
885 {
886 struct net_device *ndev = dev_id;
887 struct ravb_private *priv = netdev_priv(ndev);
888 irqreturn_t result = IRQ_NONE;
889
890 spin_lock(&priv->lock);
891
892 /* Network control/Best effort queue RX/TX */
893 if (ravb_queue_interrupt(ndev, q))
894 result = IRQ_HANDLED;
895
896 mmiowb();
897 spin_unlock(&priv->lock);
898 return result;
899 }
900
ravb_be_interrupt(int irq,void * dev_id)901 static irqreturn_t ravb_be_interrupt(int irq, void *dev_id)
902 {
903 return ravb_dma_interrupt(irq, dev_id, RAVB_BE);
904 }
905
ravb_nc_interrupt(int irq,void * dev_id)906 static irqreturn_t ravb_nc_interrupt(int irq, void *dev_id)
907 {
908 return ravb_dma_interrupt(irq, dev_id, RAVB_NC);
909 }
910
ravb_poll(struct napi_struct * napi,int budget)911 static int ravb_poll(struct napi_struct *napi, int budget)
912 {
913 struct net_device *ndev = napi->dev;
914 struct ravb_private *priv = netdev_priv(ndev);
915 unsigned long flags;
916 int q = napi - priv->napi;
917 int mask = BIT(q);
918 int quota = budget;
919 u32 ris0, tis;
920
921 for (;;) {
922 tis = ravb_read(ndev, TIS);
923 ris0 = ravb_read(ndev, RIS0);
924 if (!((ris0 & mask) || (tis & mask)))
925 break;
926
927 /* Processing RX Descriptor Ring */
928 if (ris0 & mask) {
929 /* Clear RX interrupt */
930 ravb_write(ndev, ~(mask | RIS0_RESERVED), RIS0);
931 if (ravb_rx(ndev, "a, q))
932 goto out;
933 }
934 /* Processing TX Descriptor Ring */
935 if (tis & mask) {
936 spin_lock_irqsave(&priv->lock, flags);
937 /* Clear TX interrupt */
938 ravb_write(ndev, ~(mask | TIS_RESERVED), TIS);
939 ravb_tx_free(ndev, q, true);
940 netif_wake_subqueue(ndev, q);
941 mmiowb();
942 spin_unlock_irqrestore(&priv->lock, flags);
943 }
944 }
945
946 napi_complete(napi);
947
948 /* Re-enable RX/TX interrupts */
949 spin_lock_irqsave(&priv->lock, flags);
950 if (priv->chip_id == RCAR_GEN2) {
951 ravb_modify(ndev, RIC0, mask, mask);
952 ravb_modify(ndev, TIC, mask, mask);
953 } else {
954 ravb_write(ndev, mask, RIE0);
955 ravb_write(ndev, mask, TIE);
956 }
957 mmiowb();
958 spin_unlock_irqrestore(&priv->lock, flags);
959
960 /* Receive error message handling */
961 priv->rx_over_errors = priv->stats[RAVB_BE].rx_over_errors;
962 priv->rx_over_errors += priv->stats[RAVB_NC].rx_over_errors;
963 if (priv->rx_over_errors != ndev->stats.rx_over_errors)
964 ndev->stats.rx_over_errors = priv->rx_over_errors;
965 if (priv->rx_fifo_errors != ndev->stats.rx_fifo_errors)
966 ndev->stats.rx_fifo_errors = priv->rx_fifo_errors;
967 out:
968 return budget - quota;
969 }
970
971 /* PHY state control function */
ravb_adjust_link(struct net_device * ndev)972 static void ravb_adjust_link(struct net_device *ndev)
973 {
974 struct ravb_private *priv = netdev_priv(ndev);
975 struct phy_device *phydev = ndev->phydev;
976 bool new_state = false;
977 unsigned long flags;
978
979 spin_lock_irqsave(&priv->lock, flags);
980
981 /* Disable TX and RX right over here, if E-MAC change is ignored */
982 if (priv->no_avb_link)
983 ravb_rcv_snd_disable(ndev);
984
985 if (phydev->link) {
986 if (phydev->speed != priv->speed) {
987 new_state = true;
988 priv->speed = phydev->speed;
989 ravb_set_rate(ndev);
990 }
991 if (!priv->link) {
992 ravb_modify(ndev, ECMR, ECMR_TXF, 0);
993 new_state = true;
994 priv->link = phydev->link;
995 }
996 } else if (priv->link) {
997 new_state = true;
998 priv->link = 0;
999 priv->speed = 0;
1000 }
1001
1002 /* Enable TX and RX right over here, if E-MAC change is ignored */
1003 if (priv->no_avb_link && phydev->link)
1004 ravb_rcv_snd_enable(ndev);
1005
1006 mmiowb();
1007 spin_unlock_irqrestore(&priv->lock, flags);
1008
1009 if (new_state && netif_msg_link(priv))
1010 phy_print_status(phydev);
1011 }
1012
1013 static const struct soc_device_attribute r8a7795es10[] = {
1014 { .soc_id = "r8a7795", .revision = "ES1.0", },
1015 { /* sentinel */ }
1016 };
1017
1018 /* PHY init function */
ravb_phy_init(struct net_device * ndev)1019 static int ravb_phy_init(struct net_device *ndev)
1020 {
1021 struct device_node *np = ndev->dev.parent->of_node;
1022 struct ravb_private *priv = netdev_priv(ndev);
1023 struct phy_device *phydev;
1024 struct device_node *pn;
1025 int err;
1026
1027 priv->link = 0;
1028 priv->speed = 0;
1029
1030 /* Try connecting to PHY */
1031 pn = of_parse_phandle(np, "phy-handle", 0);
1032 if (!pn) {
1033 /* In the case of a fixed PHY, the DT node associated
1034 * to the PHY is the Ethernet MAC DT node.
1035 */
1036 if (of_phy_is_fixed_link(np)) {
1037 err = of_phy_register_fixed_link(np);
1038 if (err)
1039 return err;
1040 }
1041 pn = of_node_get(np);
1042 }
1043 phydev = of_phy_connect(ndev, pn, ravb_adjust_link, 0,
1044 priv->phy_interface);
1045 of_node_put(pn);
1046 if (!phydev) {
1047 netdev_err(ndev, "failed to connect PHY\n");
1048 err = -ENOENT;
1049 goto err_deregister_fixed_link;
1050 }
1051
1052 /* This driver only support 10/100Mbit speeds on R-Car H3 ES1.0
1053 * at this time.
1054 */
1055 if (soc_device_match(r8a7795es10)) {
1056 err = phy_set_max_speed(phydev, SPEED_100);
1057 if (err) {
1058 netdev_err(ndev, "failed to limit PHY to 100Mbit/s\n");
1059 goto err_phy_disconnect;
1060 }
1061
1062 netdev_info(ndev, "limited PHY to 100Mbit/s\n");
1063 }
1064
1065 /* 10BASE is not supported */
1066 phydev->supported &= ~PHY_10BT_FEATURES;
1067
1068 phy_attached_info(phydev);
1069
1070 return 0;
1071
1072 err_phy_disconnect:
1073 phy_disconnect(phydev);
1074 err_deregister_fixed_link:
1075 if (of_phy_is_fixed_link(np))
1076 of_phy_deregister_fixed_link(np);
1077
1078 return err;
1079 }
1080
1081 /* PHY control start function */
ravb_phy_start(struct net_device * ndev)1082 static int ravb_phy_start(struct net_device *ndev)
1083 {
1084 int error;
1085
1086 error = ravb_phy_init(ndev);
1087 if (error)
1088 return error;
1089
1090 phy_start(ndev->phydev);
1091
1092 return 0;
1093 }
1094
ravb_get_msglevel(struct net_device * ndev)1095 static u32 ravb_get_msglevel(struct net_device *ndev)
1096 {
1097 struct ravb_private *priv = netdev_priv(ndev);
1098
1099 return priv->msg_enable;
1100 }
1101
ravb_set_msglevel(struct net_device * ndev,u32 value)1102 static void ravb_set_msglevel(struct net_device *ndev, u32 value)
1103 {
1104 struct ravb_private *priv = netdev_priv(ndev);
1105
1106 priv->msg_enable = value;
1107 }
1108
1109 static const char ravb_gstrings_stats[][ETH_GSTRING_LEN] = {
1110 "rx_queue_0_current",
1111 "tx_queue_0_current",
1112 "rx_queue_0_dirty",
1113 "tx_queue_0_dirty",
1114 "rx_queue_0_packets",
1115 "tx_queue_0_packets",
1116 "rx_queue_0_bytes",
1117 "tx_queue_0_bytes",
1118 "rx_queue_0_mcast_packets",
1119 "rx_queue_0_errors",
1120 "rx_queue_0_crc_errors",
1121 "rx_queue_0_frame_errors",
1122 "rx_queue_0_length_errors",
1123 "rx_queue_0_missed_errors",
1124 "rx_queue_0_over_errors",
1125
1126 "rx_queue_1_current",
1127 "tx_queue_1_current",
1128 "rx_queue_1_dirty",
1129 "tx_queue_1_dirty",
1130 "rx_queue_1_packets",
1131 "tx_queue_1_packets",
1132 "rx_queue_1_bytes",
1133 "tx_queue_1_bytes",
1134 "rx_queue_1_mcast_packets",
1135 "rx_queue_1_errors",
1136 "rx_queue_1_crc_errors",
1137 "rx_queue_1_frame_errors",
1138 "rx_queue_1_length_errors",
1139 "rx_queue_1_missed_errors",
1140 "rx_queue_1_over_errors",
1141 };
1142
1143 #define RAVB_STATS_LEN ARRAY_SIZE(ravb_gstrings_stats)
1144
ravb_get_sset_count(struct net_device * netdev,int sset)1145 static int ravb_get_sset_count(struct net_device *netdev, int sset)
1146 {
1147 switch (sset) {
1148 case ETH_SS_STATS:
1149 return RAVB_STATS_LEN;
1150 default:
1151 return -EOPNOTSUPP;
1152 }
1153 }
1154
ravb_get_ethtool_stats(struct net_device * ndev,struct ethtool_stats * estats,u64 * data)1155 static void ravb_get_ethtool_stats(struct net_device *ndev,
1156 struct ethtool_stats *estats, u64 *data)
1157 {
1158 struct ravb_private *priv = netdev_priv(ndev);
1159 int i = 0;
1160 int q;
1161
1162 /* Device-specific stats */
1163 for (q = RAVB_BE; q < NUM_RX_QUEUE; q++) {
1164 struct net_device_stats *stats = &priv->stats[q];
1165
1166 data[i++] = priv->cur_rx[q];
1167 data[i++] = priv->cur_tx[q];
1168 data[i++] = priv->dirty_rx[q];
1169 data[i++] = priv->dirty_tx[q];
1170 data[i++] = stats->rx_packets;
1171 data[i++] = stats->tx_packets;
1172 data[i++] = stats->rx_bytes;
1173 data[i++] = stats->tx_bytes;
1174 data[i++] = stats->multicast;
1175 data[i++] = stats->rx_errors;
1176 data[i++] = stats->rx_crc_errors;
1177 data[i++] = stats->rx_frame_errors;
1178 data[i++] = stats->rx_length_errors;
1179 data[i++] = stats->rx_missed_errors;
1180 data[i++] = stats->rx_over_errors;
1181 }
1182 }
1183
ravb_get_strings(struct net_device * ndev,u32 stringset,u8 * data)1184 static void ravb_get_strings(struct net_device *ndev, u32 stringset, u8 *data)
1185 {
1186 switch (stringset) {
1187 case ETH_SS_STATS:
1188 memcpy(data, ravb_gstrings_stats, sizeof(ravb_gstrings_stats));
1189 break;
1190 }
1191 }
1192
ravb_get_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1193 static void ravb_get_ringparam(struct net_device *ndev,
1194 struct ethtool_ringparam *ring)
1195 {
1196 struct ravb_private *priv = netdev_priv(ndev);
1197
1198 ring->rx_max_pending = BE_RX_RING_MAX;
1199 ring->tx_max_pending = BE_TX_RING_MAX;
1200 ring->rx_pending = priv->num_rx_ring[RAVB_BE];
1201 ring->tx_pending = priv->num_tx_ring[RAVB_BE];
1202 }
1203
ravb_set_ringparam(struct net_device * ndev,struct ethtool_ringparam * ring)1204 static int ravb_set_ringparam(struct net_device *ndev,
1205 struct ethtool_ringparam *ring)
1206 {
1207 struct ravb_private *priv = netdev_priv(ndev);
1208 int error;
1209
1210 if (ring->tx_pending > BE_TX_RING_MAX ||
1211 ring->rx_pending > BE_RX_RING_MAX ||
1212 ring->tx_pending < BE_TX_RING_MIN ||
1213 ring->rx_pending < BE_RX_RING_MIN)
1214 return -EINVAL;
1215 if (ring->rx_mini_pending || ring->rx_jumbo_pending)
1216 return -EINVAL;
1217
1218 if (netif_running(ndev)) {
1219 netif_device_detach(ndev);
1220 /* Stop PTP Clock driver */
1221 if (priv->chip_id == RCAR_GEN2)
1222 ravb_ptp_stop(ndev);
1223 /* Wait for DMA stopping */
1224 error = ravb_stop_dma(ndev);
1225 if (error) {
1226 netdev_err(ndev,
1227 "cannot set ringparam! Any AVB processes are still running?\n");
1228 return error;
1229 }
1230 synchronize_irq(ndev->irq);
1231
1232 /* Free all the skb's in the RX queue and the DMA buffers. */
1233 ravb_ring_free(ndev, RAVB_BE);
1234 ravb_ring_free(ndev, RAVB_NC);
1235 }
1236
1237 /* Set new parameters */
1238 priv->num_rx_ring[RAVB_BE] = ring->rx_pending;
1239 priv->num_tx_ring[RAVB_BE] = ring->tx_pending;
1240
1241 if (netif_running(ndev)) {
1242 error = ravb_dmac_init(ndev);
1243 if (error) {
1244 netdev_err(ndev,
1245 "%s: ravb_dmac_init() failed, error %d\n",
1246 __func__, error);
1247 return error;
1248 }
1249
1250 ravb_emac_init(ndev);
1251
1252 /* Initialise PTP Clock driver */
1253 if (priv->chip_id == RCAR_GEN2)
1254 ravb_ptp_init(ndev, priv->pdev);
1255
1256 netif_device_attach(ndev);
1257 }
1258
1259 return 0;
1260 }
1261
ravb_get_ts_info(struct net_device * ndev,struct ethtool_ts_info * info)1262 static int ravb_get_ts_info(struct net_device *ndev,
1263 struct ethtool_ts_info *info)
1264 {
1265 struct ravb_private *priv = netdev_priv(ndev);
1266
1267 info->so_timestamping =
1268 SOF_TIMESTAMPING_TX_SOFTWARE |
1269 SOF_TIMESTAMPING_RX_SOFTWARE |
1270 SOF_TIMESTAMPING_SOFTWARE |
1271 SOF_TIMESTAMPING_TX_HARDWARE |
1272 SOF_TIMESTAMPING_RX_HARDWARE |
1273 SOF_TIMESTAMPING_RAW_HARDWARE;
1274 info->tx_types = (1 << HWTSTAMP_TX_OFF) | (1 << HWTSTAMP_TX_ON);
1275 info->rx_filters =
1276 (1 << HWTSTAMP_FILTER_NONE) |
1277 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
1278 (1 << HWTSTAMP_FILTER_ALL);
1279 info->phc_index = ptp_clock_index(priv->ptp.clock);
1280
1281 return 0;
1282 }
1283
ravb_get_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1284 static void ravb_get_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1285 {
1286 struct ravb_private *priv = netdev_priv(ndev);
1287
1288 wol->supported = WAKE_MAGIC;
1289 wol->wolopts = priv->wol_enabled ? WAKE_MAGIC : 0;
1290 }
1291
ravb_set_wol(struct net_device * ndev,struct ethtool_wolinfo * wol)1292 static int ravb_set_wol(struct net_device *ndev, struct ethtool_wolinfo *wol)
1293 {
1294 struct ravb_private *priv = netdev_priv(ndev);
1295
1296 if (wol->wolopts & ~WAKE_MAGIC)
1297 return -EOPNOTSUPP;
1298
1299 priv->wol_enabled = !!(wol->wolopts & WAKE_MAGIC);
1300
1301 device_set_wakeup_enable(&priv->pdev->dev, priv->wol_enabled);
1302
1303 return 0;
1304 }
1305
1306 static const struct ethtool_ops ravb_ethtool_ops = {
1307 .nway_reset = phy_ethtool_nway_reset,
1308 .get_msglevel = ravb_get_msglevel,
1309 .set_msglevel = ravb_set_msglevel,
1310 .get_link = ethtool_op_get_link,
1311 .get_strings = ravb_get_strings,
1312 .get_ethtool_stats = ravb_get_ethtool_stats,
1313 .get_sset_count = ravb_get_sset_count,
1314 .get_ringparam = ravb_get_ringparam,
1315 .set_ringparam = ravb_set_ringparam,
1316 .get_ts_info = ravb_get_ts_info,
1317 .get_link_ksettings = phy_ethtool_get_link_ksettings,
1318 .set_link_ksettings = phy_ethtool_set_link_ksettings,
1319 .get_wol = ravb_get_wol,
1320 .set_wol = ravb_set_wol,
1321 };
1322
ravb_hook_irq(unsigned int irq,irq_handler_t handler,struct net_device * ndev,struct device * dev,const char * ch)1323 static inline int ravb_hook_irq(unsigned int irq, irq_handler_t handler,
1324 struct net_device *ndev, struct device *dev,
1325 const char *ch)
1326 {
1327 char *name;
1328 int error;
1329
1330 name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", ndev->name, ch);
1331 if (!name)
1332 return -ENOMEM;
1333 error = request_irq(irq, handler, 0, name, ndev);
1334 if (error)
1335 netdev_err(ndev, "cannot request IRQ %s\n", name);
1336
1337 return error;
1338 }
1339
1340 /* Network device open function for Ethernet AVB */
ravb_open(struct net_device * ndev)1341 static int ravb_open(struct net_device *ndev)
1342 {
1343 struct ravb_private *priv = netdev_priv(ndev);
1344 struct platform_device *pdev = priv->pdev;
1345 struct device *dev = &pdev->dev;
1346 int error;
1347
1348 napi_enable(&priv->napi[RAVB_BE]);
1349 napi_enable(&priv->napi[RAVB_NC]);
1350
1351 if (priv->chip_id == RCAR_GEN2) {
1352 error = request_irq(ndev->irq, ravb_interrupt, IRQF_SHARED,
1353 ndev->name, ndev);
1354 if (error) {
1355 netdev_err(ndev, "cannot request IRQ\n");
1356 goto out_napi_off;
1357 }
1358 } else {
1359 error = ravb_hook_irq(ndev->irq, ravb_multi_interrupt, ndev,
1360 dev, "ch22:multi");
1361 if (error)
1362 goto out_napi_off;
1363 error = ravb_hook_irq(priv->emac_irq, ravb_emac_interrupt, ndev,
1364 dev, "ch24:emac");
1365 if (error)
1366 goto out_free_irq;
1367 error = ravb_hook_irq(priv->rx_irqs[RAVB_BE], ravb_be_interrupt,
1368 ndev, dev, "ch0:rx_be");
1369 if (error)
1370 goto out_free_irq_emac;
1371 error = ravb_hook_irq(priv->tx_irqs[RAVB_BE], ravb_be_interrupt,
1372 ndev, dev, "ch18:tx_be");
1373 if (error)
1374 goto out_free_irq_be_rx;
1375 error = ravb_hook_irq(priv->rx_irqs[RAVB_NC], ravb_nc_interrupt,
1376 ndev, dev, "ch1:rx_nc");
1377 if (error)
1378 goto out_free_irq_be_tx;
1379 error = ravb_hook_irq(priv->tx_irqs[RAVB_NC], ravb_nc_interrupt,
1380 ndev, dev, "ch19:tx_nc");
1381 if (error)
1382 goto out_free_irq_nc_rx;
1383 }
1384
1385 /* Device init */
1386 error = ravb_dmac_init(ndev);
1387 if (error)
1388 goto out_free_irq_nc_tx;
1389 ravb_emac_init(ndev);
1390
1391 /* Initialise PTP Clock driver */
1392 if (priv->chip_id == RCAR_GEN2)
1393 ravb_ptp_init(ndev, priv->pdev);
1394
1395 netif_tx_start_all_queues(ndev);
1396
1397 /* PHY control start */
1398 error = ravb_phy_start(ndev);
1399 if (error)
1400 goto out_ptp_stop;
1401
1402 return 0;
1403
1404 out_ptp_stop:
1405 /* Stop PTP Clock driver */
1406 if (priv->chip_id == RCAR_GEN2)
1407 ravb_ptp_stop(ndev);
1408 out_free_irq_nc_tx:
1409 if (priv->chip_id == RCAR_GEN2)
1410 goto out_free_irq;
1411 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1412 out_free_irq_nc_rx:
1413 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1414 out_free_irq_be_tx:
1415 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1416 out_free_irq_be_rx:
1417 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1418 out_free_irq_emac:
1419 free_irq(priv->emac_irq, ndev);
1420 out_free_irq:
1421 free_irq(ndev->irq, ndev);
1422 out_napi_off:
1423 napi_disable(&priv->napi[RAVB_NC]);
1424 napi_disable(&priv->napi[RAVB_BE]);
1425 return error;
1426 }
1427
1428 /* Timeout function for Ethernet AVB */
ravb_tx_timeout(struct net_device * ndev)1429 static void ravb_tx_timeout(struct net_device *ndev)
1430 {
1431 struct ravb_private *priv = netdev_priv(ndev);
1432
1433 netif_err(priv, tx_err, ndev,
1434 "transmit timed out, status %08x, resetting...\n",
1435 ravb_read(ndev, ISS));
1436
1437 /* tx_errors count up */
1438 ndev->stats.tx_errors++;
1439
1440 schedule_work(&priv->work);
1441 }
1442
ravb_tx_timeout_work(struct work_struct * work)1443 static void ravb_tx_timeout_work(struct work_struct *work)
1444 {
1445 struct ravb_private *priv = container_of(work, struct ravb_private,
1446 work);
1447 struct net_device *ndev = priv->ndev;
1448 int error;
1449
1450 netif_tx_stop_all_queues(ndev);
1451
1452 /* Stop PTP Clock driver */
1453 if (priv->chip_id == RCAR_GEN2)
1454 ravb_ptp_stop(ndev);
1455
1456 /* Wait for DMA stopping */
1457 if (ravb_stop_dma(ndev)) {
1458 /* If ravb_stop_dma() fails, the hardware is still operating
1459 * for TX and/or RX. So, this should not call the following
1460 * functions because ravb_dmac_init() is possible to fail too.
1461 * Also, this should not retry ravb_stop_dma() again and again
1462 * here because it's possible to wait forever. So, this just
1463 * re-enables the TX and RX and skip the following
1464 * re-initialization procedure.
1465 */
1466 ravb_rcv_snd_enable(ndev);
1467 goto out;
1468 }
1469
1470 ravb_ring_free(ndev, RAVB_BE);
1471 ravb_ring_free(ndev, RAVB_NC);
1472
1473 /* Device init */
1474 error = ravb_dmac_init(ndev);
1475 if (error) {
1476 /* If ravb_dmac_init() fails, descriptors are freed. So, this
1477 * should return here to avoid re-enabling the TX and RX in
1478 * ravb_emac_init().
1479 */
1480 netdev_err(ndev, "%s: ravb_dmac_init() failed, error %d\n",
1481 __func__, error);
1482 return;
1483 }
1484 ravb_emac_init(ndev);
1485
1486 out:
1487 /* Initialise PTP Clock driver */
1488 if (priv->chip_id == RCAR_GEN2)
1489 ravb_ptp_init(ndev, priv->pdev);
1490
1491 netif_tx_start_all_queues(ndev);
1492 }
1493
1494 /* Packet transmit function for Ethernet AVB */
ravb_start_xmit(struct sk_buff * skb,struct net_device * ndev)1495 static netdev_tx_t ravb_start_xmit(struct sk_buff *skb, struct net_device *ndev)
1496 {
1497 struct ravb_private *priv = netdev_priv(ndev);
1498 u16 q = skb_get_queue_mapping(skb);
1499 struct ravb_tstamp_skb *ts_skb;
1500 struct ravb_tx_desc *desc;
1501 unsigned long flags;
1502 u32 dma_addr;
1503 void *buffer;
1504 u32 entry;
1505 u32 len;
1506
1507 spin_lock_irqsave(&priv->lock, flags);
1508 if (priv->cur_tx[q] - priv->dirty_tx[q] > (priv->num_tx_ring[q] - 1) *
1509 NUM_TX_DESC) {
1510 netif_err(priv, tx_queued, ndev,
1511 "still transmitting with the full ring!\n");
1512 netif_stop_subqueue(ndev, q);
1513 spin_unlock_irqrestore(&priv->lock, flags);
1514 return NETDEV_TX_BUSY;
1515 }
1516
1517 if (skb_put_padto(skb, ETH_ZLEN))
1518 goto exit;
1519
1520 entry = priv->cur_tx[q] % (priv->num_tx_ring[q] * NUM_TX_DESC);
1521 priv->tx_skb[q][entry / NUM_TX_DESC] = skb;
1522
1523 buffer = PTR_ALIGN(priv->tx_align[q], DPTR_ALIGN) +
1524 entry / NUM_TX_DESC * DPTR_ALIGN;
1525 len = PTR_ALIGN(skb->data, DPTR_ALIGN) - skb->data;
1526 /* Zero length DMA descriptors are problematic as they seem to
1527 * terminate DMA transfers. Avoid them by simply using a length of
1528 * DPTR_ALIGN (4) when skb data is aligned to DPTR_ALIGN.
1529 *
1530 * As skb is guaranteed to have at least ETH_ZLEN (60) bytes of
1531 * data by the call to skb_put_padto() above this is safe with
1532 * respect to both the length of the first DMA descriptor (len)
1533 * overflowing the available data and the length of the second DMA
1534 * descriptor (skb->len - len) being negative.
1535 */
1536 if (len == 0)
1537 len = DPTR_ALIGN;
1538
1539 memcpy(buffer, skb->data, len);
1540 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1541 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1542 goto drop;
1543
1544 desc = &priv->tx_ring[q][entry];
1545 desc->ds_tagl = cpu_to_le16(len);
1546 desc->dptr = cpu_to_le32(dma_addr);
1547
1548 buffer = skb->data + len;
1549 len = skb->len - len;
1550 dma_addr = dma_map_single(ndev->dev.parent, buffer, len, DMA_TO_DEVICE);
1551 if (dma_mapping_error(ndev->dev.parent, dma_addr))
1552 goto unmap;
1553
1554 desc++;
1555 desc->ds_tagl = cpu_to_le16(len);
1556 desc->dptr = cpu_to_le32(dma_addr);
1557
1558 /* TX timestamp required */
1559 if (q == RAVB_NC) {
1560 ts_skb = kmalloc(sizeof(*ts_skb), GFP_ATOMIC);
1561 if (!ts_skb) {
1562 desc--;
1563 dma_unmap_single(ndev->dev.parent, dma_addr, len,
1564 DMA_TO_DEVICE);
1565 goto unmap;
1566 }
1567 ts_skb->skb = skb_get(skb);
1568 ts_skb->tag = priv->ts_skb_tag++;
1569 priv->ts_skb_tag &= 0x3ff;
1570 list_add_tail(&ts_skb->list, &priv->ts_skb_list);
1571
1572 /* TAG and timestamp required flag */
1573 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
1574 desc->tagh_tsr = (ts_skb->tag >> 4) | TX_TSR;
1575 desc->ds_tagl |= cpu_to_le16(ts_skb->tag << 12);
1576 }
1577
1578 skb_tx_timestamp(skb);
1579 /* Descriptor type must be set after all the above writes */
1580 dma_wmb();
1581 desc->die_dt = DT_FEND;
1582 desc--;
1583 desc->die_dt = DT_FSTART;
1584
1585 ravb_modify(ndev, TCCR, TCCR_TSRQ0 << q, TCCR_TSRQ0 << q);
1586
1587 priv->cur_tx[q] += NUM_TX_DESC;
1588 if (priv->cur_tx[q] - priv->dirty_tx[q] >
1589 (priv->num_tx_ring[q] - 1) * NUM_TX_DESC &&
1590 !ravb_tx_free(ndev, q, true))
1591 netif_stop_subqueue(ndev, q);
1592
1593 exit:
1594 mmiowb();
1595 spin_unlock_irqrestore(&priv->lock, flags);
1596 return NETDEV_TX_OK;
1597
1598 unmap:
1599 dma_unmap_single(ndev->dev.parent, le32_to_cpu(desc->dptr),
1600 le16_to_cpu(desc->ds_tagl), DMA_TO_DEVICE);
1601 drop:
1602 dev_kfree_skb_any(skb);
1603 priv->tx_skb[q][entry / NUM_TX_DESC] = NULL;
1604 goto exit;
1605 }
1606
ravb_select_queue(struct net_device * ndev,struct sk_buff * skb,struct net_device * sb_dev,select_queue_fallback_t fallback)1607 static u16 ravb_select_queue(struct net_device *ndev, struct sk_buff *skb,
1608 struct net_device *sb_dev,
1609 select_queue_fallback_t fallback)
1610 {
1611 /* If skb needs TX timestamp, it is handled in network control queue */
1612 return (skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) ? RAVB_NC :
1613 RAVB_BE;
1614
1615 }
1616
ravb_get_stats(struct net_device * ndev)1617 static struct net_device_stats *ravb_get_stats(struct net_device *ndev)
1618 {
1619 struct ravb_private *priv = netdev_priv(ndev);
1620 struct net_device_stats *nstats, *stats0, *stats1;
1621
1622 nstats = &ndev->stats;
1623 stats0 = &priv->stats[RAVB_BE];
1624 stats1 = &priv->stats[RAVB_NC];
1625
1626 nstats->tx_dropped += ravb_read(ndev, TROCR);
1627 ravb_write(ndev, 0, TROCR); /* (write clear) */
1628 nstats->collisions += ravb_read(ndev, CDCR);
1629 ravb_write(ndev, 0, CDCR); /* (write clear) */
1630 nstats->tx_carrier_errors += ravb_read(ndev, LCCR);
1631 ravb_write(ndev, 0, LCCR); /* (write clear) */
1632
1633 nstats->tx_carrier_errors += ravb_read(ndev, CERCR);
1634 ravb_write(ndev, 0, CERCR); /* (write clear) */
1635 nstats->tx_carrier_errors += ravb_read(ndev, CEECR);
1636 ravb_write(ndev, 0, CEECR); /* (write clear) */
1637
1638 nstats->rx_packets = stats0->rx_packets + stats1->rx_packets;
1639 nstats->tx_packets = stats0->tx_packets + stats1->tx_packets;
1640 nstats->rx_bytes = stats0->rx_bytes + stats1->rx_bytes;
1641 nstats->tx_bytes = stats0->tx_bytes + stats1->tx_bytes;
1642 nstats->multicast = stats0->multicast + stats1->multicast;
1643 nstats->rx_errors = stats0->rx_errors + stats1->rx_errors;
1644 nstats->rx_crc_errors = stats0->rx_crc_errors + stats1->rx_crc_errors;
1645 nstats->rx_frame_errors =
1646 stats0->rx_frame_errors + stats1->rx_frame_errors;
1647 nstats->rx_length_errors =
1648 stats0->rx_length_errors + stats1->rx_length_errors;
1649 nstats->rx_missed_errors =
1650 stats0->rx_missed_errors + stats1->rx_missed_errors;
1651 nstats->rx_over_errors =
1652 stats0->rx_over_errors + stats1->rx_over_errors;
1653
1654 return nstats;
1655 }
1656
1657 /* Update promiscuous bit */
ravb_set_rx_mode(struct net_device * ndev)1658 static void ravb_set_rx_mode(struct net_device *ndev)
1659 {
1660 struct ravb_private *priv = netdev_priv(ndev);
1661 unsigned long flags;
1662
1663 spin_lock_irqsave(&priv->lock, flags);
1664 ravb_modify(ndev, ECMR, ECMR_PRM,
1665 ndev->flags & IFF_PROMISC ? ECMR_PRM : 0);
1666 mmiowb();
1667 spin_unlock_irqrestore(&priv->lock, flags);
1668 }
1669
1670 /* Device close function for Ethernet AVB */
ravb_close(struct net_device * ndev)1671 static int ravb_close(struct net_device *ndev)
1672 {
1673 struct device_node *np = ndev->dev.parent->of_node;
1674 struct ravb_private *priv = netdev_priv(ndev);
1675 struct ravb_tstamp_skb *ts_skb, *ts_skb2;
1676
1677 netif_tx_stop_all_queues(ndev);
1678
1679 /* Disable interrupts by clearing the interrupt masks. */
1680 ravb_write(ndev, 0, RIC0);
1681 ravb_write(ndev, 0, RIC2);
1682 ravb_write(ndev, 0, TIC);
1683
1684 /* Stop PTP Clock driver */
1685 if (priv->chip_id == RCAR_GEN2)
1686 ravb_ptp_stop(ndev);
1687
1688 /* Set the config mode to stop the AVB-DMAC's processes */
1689 if (ravb_stop_dma(ndev) < 0)
1690 netdev_err(ndev,
1691 "device will be stopped after h/w processes are done.\n");
1692
1693 /* Clear the timestamp list */
1694 list_for_each_entry_safe(ts_skb, ts_skb2, &priv->ts_skb_list, list) {
1695 list_del(&ts_skb->list);
1696 kfree_skb(ts_skb->skb);
1697 kfree(ts_skb);
1698 }
1699
1700 /* PHY disconnect */
1701 if (ndev->phydev) {
1702 phy_stop(ndev->phydev);
1703 phy_disconnect(ndev->phydev);
1704 if (of_phy_is_fixed_link(np))
1705 of_phy_deregister_fixed_link(np);
1706 }
1707
1708 if (priv->chip_id != RCAR_GEN2) {
1709 free_irq(priv->tx_irqs[RAVB_NC], ndev);
1710 free_irq(priv->rx_irqs[RAVB_NC], ndev);
1711 free_irq(priv->tx_irqs[RAVB_BE], ndev);
1712 free_irq(priv->rx_irqs[RAVB_BE], ndev);
1713 free_irq(priv->emac_irq, ndev);
1714 }
1715 free_irq(ndev->irq, ndev);
1716
1717 napi_disable(&priv->napi[RAVB_NC]);
1718 napi_disable(&priv->napi[RAVB_BE]);
1719
1720 /* Free all the skb's in the RX queue and the DMA buffers. */
1721 ravb_ring_free(ndev, RAVB_BE);
1722 ravb_ring_free(ndev, RAVB_NC);
1723
1724 return 0;
1725 }
1726
ravb_hwtstamp_get(struct net_device * ndev,struct ifreq * req)1727 static int ravb_hwtstamp_get(struct net_device *ndev, struct ifreq *req)
1728 {
1729 struct ravb_private *priv = netdev_priv(ndev);
1730 struct hwtstamp_config config;
1731
1732 config.flags = 0;
1733 config.tx_type = priv->tstamp_tx_ctrl ? HWTSTAMP_TX_ON :
1734 HWTSTAMP_TX_OFF;
1735 switch (priv->tstamp_rx_ctrl & RAVB_RXTSTAMP_TYPE) {
1736 case RAVB_RXTSTAMP_TYPE_V2_L2_EVENT:
1737 config.rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
1738 break;
1739 case RAVB_RXTSTAMP_TYPE_ALL:
1740 config.rx_filter = HWTSTAMP_FILTER_ALL;
1741 break;
1742 default:
1743 config.rx_filter = HWTSTAMP_FILTER_NONE;
1744 }
1745
1746 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1747 -EFAULT : 0;
1748 }
1749
1750 /* Control hardware time stamping */
ravb_hwtstamp_set(struct net_device * ndev,struct ifreq * req)1751 static int ravb_hwtstamp_set(struct net_device *ndev, struct ifreq *req)
1752 {
1753 struct ravb_private *priv = netdev_priv(ndev);
1754 struct hwtstamp_config config;
1755 u32 tstamp_rx_ctrl = RAVB_RXTSTAMP_ENABLED;
1756 u32 tstamp_tx_ctrl;
1757
1758 if (copy_from_user(&config, req->ifr_data, sizeof(config)))
1759 return -EFAULT;
1760
1761 /* Reserved for future extensions */
1762 if (config.flags)
1763 return -EINVAL;
1764
1765 switch (config.tx_type) {
1766 case HWTSTAMP_TX_OFF:
1767 tstamp_tx_ctrl = 0;
1768 break;
1769 case HWTSTAMP_TX_ON:
1770 tstamp_tx_ctrl = RAVB_TXTSTAMP_ENABLED;
1771 break;
1772 default:
1773 return -ERANGE;
1774 }
1775
1776 switch (config.rx_filter) {
1777 case HWTSTAMP_FILTER_NONE:
1778 tstamp_rx_ctrl = 0;
1779 break;
1780 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
1781 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_V2_L2_EVENT;
1782 break;
1783 default:
1784 config.rx_filter = HWTSTAMP_FILTER_ALL;
1785 tstamp_rx_ctrl |= RAVB_RXTSTAMP_TYPE_ALL;
1786 }
1787
1788 priv->tstamp_tx_ctrl = tstamp_tx_ctrl;
1789 priv->tstamp_rx_ctrl = tstamp_rx_ctrl;
1790
1791 return copy_to_user(req->ifr_data, &config, sizeof(config)) ?
1792 -EFAULT : 0;
1793 }
1794
1795 /* ioctl to device function */
ravb_do_ioctl(struct net_device * ndev,struct ifreq * req,int cmd)1796 static int ravb_do_ioctl(struct net_device *ndev, struct ifreq *req, int cmd)
1797 {
1798 struct phy_device *phydev = ndev->phydev;
1799
1800 if (!netif_running(ndev))
1801 return -EINVAL;
1802
1803 if (!phydev)
1804 return -ENODEV;
1805
1806 switch (cmd) {
1807 case SIOCGHWTSTAMP:
1808 return ravb_hwtstamp_get(ndev, req);
1809 case SIOCSHWTSTAMP:
1810 return ravb_hwtstamp_set(ndev, req);
1811 }
1812
1813 return phy_mii_ioctl(phydev, req, cmd);
1814 }
1815
ravb_change_mtu(struct net_device * ndev,int new_mtu)1816 static int ravb_change_mtu(struct net_device *ndev, int new_mtu)
1817 {
1818 if (netif_running(ndev))
1819 return -EBUSY;
1820
1821 ndev->mtu = new_mtu;
1822 netdev_update_features(ndev);
1823
1824 return 0;
1825 }
1826
ravb_set_rx_csum(struct net_device * ndev,bool enable)1827 static void ravb_set_rx_csum(struct net_device *ndev, bool enable)
1828 {
1829 struct ravb_private *priv = netdev_priv(ndev);
1830 unsigned long flags;
1831
1832 spin_lock_irqsave(&priv->lock, flags);
1833
1834 /* Disable TX and RX */
1835 ravb_rcv_snd_disable(ndev);
1836
1837 /* Modify RX Checksum setting */
1838 ravb_modify(ndev, ECMR, ECMR_RCSC, enable ? ECMR_RCSC : 0);
1839
1840 /* Enable TX and RX */
1841 ravb_rcv_snd_enable(ndev);
1842
1843 spin_unlock_irqrestore(&priv->lock, flags);
1844 }
1845
ravb_set_features(struct net_device * ndev,netdev_features_t features)1846 static int ravb_set_features(struct net_device *ndev,
1847 netdev_features_t features)
1848 {
1849 netdev_features_t changed = ndev->features ^ features;
1850
1851 if (changed & NETIF_F_RXCSUM)
1852 ravb_set_rx_csum(ndev, features & NETIF_F_RXCSUM);
1853
1854 ndev->features = features;
1855
1856 return 0;
1857 }
1858
1859 static const struct net_device_ops ravb_netdev_ops = {
1860 .ndo_open = ravb_open,
1861 .ndo_stop = ravb_close,
1862 .ndo_start_xmit = ravb_start_xmit,
1863 .ndo_select_queue = ravb_select_queue,
1864 .ndo_get_stats = ravb_get_stats,
1865 .ndo_set_rx_mode = ravb_set_rx_mode,
1866 .ndo_tx_timeout = ravb_tx_timeout,
1867 .ndo_do_ioctl = ravb_do_ioctl,
1868 .ndo_change_mtu = ravb_change_mtu,
1869 .ndo_validate_addr = eth_validate_addr,
1870 .ndo_set_mac_address = eth_mac_addr,
1871 .ndo_set_features = ravb_set_features,
1872 };
1873
1874 /* MDIO bus init function */
ravb_mdio_init(struct ravb_private * priv)1875 static int ravb_mdio_init(struct ravb_private *priv)
1876 {
1877 struct platform_device *pdev = priv->pdev;
1878 struct device *dev = &pdev->dev;
1879 int error;
1880
1881 /* Bitbang init */
1882 priv->mdiobb.ops = &bb_ops;
1883
1884 /* MII controller setting */
1885 priv->mii_bus = alloc_mdio_bitbang(&priv->mdiobb);
1886 if (!priv->mii_bus)
1887 return -ENOMEM;
1888
1889 /* Hook up MII support for ethtool */
1890 priv->mii_bus->name = "ravb_mii";
1891 priv->mii_bus->parent = dev;
1892 snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
1893 pdev->name, pdev->id);
1894
1895 /* Register MDIO bus */
1896 error = of_mdiobus_register(priv->mii_bus, dev->of_node);
1897 if (error)
1898 goto out_free_bus;
1899
1900 return 0;
1901
1902 out_free_bus:
1903 free_mdio_bitbang(priv->mii_bus);
1904 return error;
1905 }
1906
1907 /* MDIO bus release function */
ravb_mdio_release(struct ravb_private * priv)1908 static int ravb_mdio_release(struct ravb_private *priv)
1909 {
1910 /* Unregister mdio bus */
1911 mdiobus_unregister(priv->mii_bus);
1912
1913 /* Free bitbang info */
1914 free_mdio_bitbang(priv->mii_bus);
1915
1916 return 0;
1917 }
1918
1919 static const struct of_device_id ravb_match_table[] = {
1920 { .compatible = "renesas,etheravb-r8a7790", .data = (void *)RCAR_GEN2 },
1921 { .compatible = "renesas,etheravb-r8a7794", .data = (void *)RCAR_GEN2 },
1922 { .compatible = "renesas,etheravb-rcar-gen2", .data = (void *)RCAR_GEN2 },
1923 { .compatible = "renesas,etheravb-r8a7795", .data = (void *)RCAR_GEN3 },
1924 { .compatible = "renesas,etheravb-rcar-gen3", .data = (void *)RCAR_GEN3 },
1925 { }
1926 };
1927 MODULE_DEVICE_TABLE(of, ravb_match_table);
1928
ravb_set_gti(struct net_device * ndev)1929 static int ravb_set_gti(struct net_device *ndev)
1930 {
1931 struct ravb_private *priv = netdev_priv(ndev);
1932 struct device *dev = ndev->dev.parent;
1933 unsigned long rate;
1934 uint64_t inc;
1935
1936 rate = clk_get_rate(priv->clk);
1937 if (!rate)
1938 return -EINVAL;
1939
1940 inc = 1000000000ULL << 20;
1941 do_div(inc, rate);
1942
1943 if (inc < GTI_TIV_MIN || inc > GTI_TIV_MAX) {
1944 dev_err(dev, "gti.tiv increment 0x%llx is outside the range 0x%x - 0x%x\n",
1945 inc, GTI_TIV_MIN, GTI_TIV_MAX);
1946 return -EINVAL;
1947 }
1948
1949 ravb_write(ndev, inc, GTI);
1950
1951 return 0;
1952 }
1953
ravb_set_config_mode(struct net_device * ndev)1954 static void ravb_set_config_mode(struct net_device *ndev)
1955 {
1956 struct ravb_private *priv = netdev_priv(ndev);
1957
1958 if (priv->chip_id == RCAR_GEN2) {
1959 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG);
1960 /* Set CSEL value */
1961 ravb_modify(ndev, CCC, CCC_CSEL, CCC_CSEL_HPB);
1962 } else {
1963 ravb_modify(ndev, CCC, CCC_OPC, CCC_OPC_CONFIG |
1964 CCC_GAC | CCC_CSEL_HPB);
1965 }
1966 }
1967
1968 /* Set tx and rx clock internal delay modes */
ravb_set_delay_mode(struct net_device * ndev)1969 static void ravb_set_delay_mode(struct net_device *ndev)
1970 {
1971 struct ravb_private *priv = netdev_priv(ndev);
1972 int set = 0;
1973
1974 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1975 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_RXID)
1976 set |= APSR_DM_RDM;
1977
1978 if (priv->phy_interface == PHY_INTERFACE_MODE_RGMII_ID ||
1979 priv->phy_interface == PHY_INTERFACE_MODE_RGMII_TXID)
1980 set |= APSR_DM_TDM;
1981
1982 ravb_modify(ndev, APSR, APSR_DM, set);
1983 }
1984
ravb_probe(struct platform_device * pdev)1985 static int ravb_probe(struct platform_device *pdev)
1986 {
1987 struct device_node *np = pdev->dev.of_node;
1988 struct ravb_private *priv;
1989 enum ravb_chip_id chip_id;
1990 struct net_device *ndev;
1991 int error, irq, q;
1992 struct resource *res;
1993 int i;
1994
1995 if (!np) {
1996 dev_err(&pdev->dev,
1997 "this driver is required to be instantiated from device tree\n");
1998 return -EINVAL;
1999 }
2000
2001 /* Get base address */
2002 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2003 if (!res) {
2004 dev_err(&pdev->dev, "invalid resource\n");
2005 return -EINVAL;
2006 }
2007
2008 ndev = alloc_etherdev_mqs(sizeof(struct ravb_private),
2009 NUM_TX_QUEUE, NUM_RX_QUEUE);
2010 if (!ndev)
2011 return -ENOMEM;
2012
2013 ndev->features = NETIF_F_RXCSUM;
2014 ndev->hw_features = NETIF_F_RXCSUM;
2015
2016 pm_runtime_enable(&pdev->dev);
2017 pm_runtime_get_sync(&pdev->dev);
2018
2019 /* The Ether-specific entries in the device structure. */
2020 ndev->base_addr = res->start;
2021
2022 chip_id = (enum ravb_chip_id)of_device_get_match_data(&pdev->dev);
2023
2024 if (chip_id == RCAR_GEN3)
2025 irq = platform_get_irq_byname(pdev, "ch22");
2026 else
2027 irq = platform_get_irq(pdev, 0);
2028 if (irq < 0) {
2029 error = irq;
2030 goto out_release;
2031 }
2032 ndev->irq = irq;
2033
2034 SET_NETDEV_DEV(ndev, &pdev->dev);
2035
2036 priv = netdev_priv(ndev);
2037 priv->ndev = ndev;
2038 priv->pdev = pdev;
2039 priv->num_tx_ring[RAVB_BE] = BE_TX_RING_SIZE;
2040 priv->num_rx_ring[RAVB_BE] = BE_RX_RING_SIZE;
2041 priv->num_tx_ring[RAVB_NC] = NC_TX_RING_SIZE;
2042 priv->num_rx_ring[RAVB_NC] = NC_RX_RING_SIZE;
2043 priv->addr = devm_ioremap_resource(&pdev->dev, res);
2044 if (IS_ERR(priv->addr)) {
2045 error = PTR_ERR(priv->addr);
2046 goto out_release;
2047 }
2048
2049 spin_lock_init(&priv->lock);
2050 INIT_WORK(&priv->work, ravb_tx_timeout_work);
2051
2052 priv->phy_interface = of_get_phy_mode(np);
2053
2054 priv->no_avb_link = of_property_read_bool(np, "renesas,no-ether-link");
2055 priv->avb_link_active_low =
2056 of_property_read_bool(np, "renesas,ether-link-active-low");
2057
2058 if (chip_id == RCAR_GEN3) {
2059 irq = platform_get_irq_byname(pdev, "ch24");
2060 if (irq < 0) {
2061 error = irq;
2062 goto out_release;
2063 }
2064 priv->emac_irq = irq;
2065 for (i = 0; i < NUM_RX_QUEUE; i++) {
2066 irq = platform_get_irq_byname(pdev, ravb_rx_irqs[i]);
2067 if (irq < 0) {
2068 error = irq;
2069 goto out_release;
2070 }
2071 priv->rx_irqs[i] = irq;
2072 }
2073 for (i = 0; i < NUM_TX_QUEUE; i++) {
2074 irq = platform_get_irq_byname(pdev, ravb_tx_irqs[i]);
2075 if (irq < 0) {
2076 error = irq;
2077 goto out_release;
2078 }
2079 priv->tx_irqs[i] = irq;
2080 }
2081 }
2082
2083 priv->chip_id = chip_id;
2084
2085 priv->clk = devm_clk_get(&pdev->dev, NULL);
2086 if (IS_ERR(priv->clk)) {
2087 error = PTR_ERR(priv->clk);
2088 goto out_release;
2089 }
2090
2091 ndev->max_mtu = 2048 - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
2092 ndev->min_mtu = ETH_MIN_MTU;
2093
2094 /* Set function */
2095 ndev->netdev_ops = &ravb_netdev_ops;
2096 ndev->ethtool_ops = &ravb_ethtool_ops;
2097
2098 /* Set AVB config mode */
2099 ravb_set_config_mode(ndev);
2100
2101 /* Set GTI value */
2102 error = ravb_set_gti(ndev);
2103 if (error)
2104 goto out_release;
2105
2106 /* Request GTI loading */
2107 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2108
2109 if (priv->chip_id != RCAR_GEN2)
2110 ravb_set_delay_mode(ndev);
2111
2112 /* Allocate descriptor base address table */
2113 priv->desc_bat_size = sizeof(struct ravb_desc) * DBAT_ENTRY_NUM;
2114 priv->desc_bat = dma_alloc_coherent(ndev->dev.parent, priv->desc_bat_size,
2115 &priv->desc_bat_dma, GFP_KERNEL);
2116 if (!priv->desc_bat) {
2117 dev_err(&pdev->dev,
2118 "Cannot allocate desc base address table (size %d bytes)\n",
2119 priv->desc_bat_size);
2120 error = -ENOMEM;
2121 goto out_release;
2122 }
2123 for (q = RAVB_BE; q < DBAT_ENTRY_NUM; q++)
2124 priv->desc_bat[q].die_dt = DT_EOS;
2125 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2126
2127 /* Initialise HW timestamp list */
2128 INIT_LIST_HEAD(&priv->ts_skb_list);
2129
2130 /* Initialise PTP Clock driver */
2131 if (chip_id != RCAR_GEN2)
2132 ravb_ptp_init(ndev, pdev);
2133
2134 /* Debug message level */
2135 priv->msg_enable = RAVB_DEF_MSG_ENABLE;
2136
2137 /* Read and set MAC address */
2138 ravb_read_mac_address(ndev, of_get_mac_address(np));
2139 if (!is_valid_ether_addr(ndev->dev_addr)) {
2140 dev_warn(&pdev->dev,
2141 "no valid MAC address supplied, using a random one\n");
2142 eth_hw_addr_random(ndev);
2143 }
2144
2145 /* MDIO bus init */
2146 error = ravb_mdio_init(priv);
2147 if (error) {
2148 dev_err(&pdev->dev, "failed to initialize MDIO\n");
2149 goto out_dma_free;
2150 }
2151
2152 netif_napi_add(ndev, &priv->napi[RAVB_BE], ravb_poll, 64);
2153 netif_napi_add(ndev, &priv->napi[RAVB_NC], ravb_poll, 64);
2154
2155 /* Network device register */
2156 error = register_netdev(ndev);
2157 if (error)
2158 goto out_napi_del;
2159
2160 device_set_wakeup_capable(&pdev->dev, 1);
2161
2162 /* Print device information */
2163 netdev_info(ndev, "Base address at %#x, %pM, IRQ %d.\n",
2164 (u32)ndev->base_addr, ndev->dev_addr, ndev->irq);
2165
2166 platform_set_drvdata(pdev, ndev);
2167
2168 return 0;
2169
2170 out_napi_del:
2171 netif_napi_del(&priv->napi[RAVB_NC]);
2172 netif_napi_del(&priv->napi[RAVB_BE]);
2173 ravb_mdio_release(priv);
2174 out_dma_free:
2175 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2176 priv->desc_bat_dma);
2177
2178 /* Stop PTP Clock driver */
2179 if (chip_id != RCAR_GEN2)
2180 ravb_ptp_stop(ndev);
2181 out_release:
2182 free_netdev(ndev);
2183
2184 pm_runtime_put(&pdev->dev);
2185 pm_runtime_disable(&pdev->dev);
2186 return error;
2187 }
2188
ravb_remove(struct platform_device * pdev)2189 static int ravb_remove(struct platform_device *pdev)
2190 {
2191 struct net_device *ndev = platform_get_drvdata(pdev);
2192 struct ravb_private *priv = netdev_priv(ndev);
2193
2194 /* Stop PTP Clock driver */
2195 if (priv->chip_id != RCAR_GEN2)
2196 ravb_ptp_stop(ndev);
2197
2198 dma_free_coherent(ndev->dev.parent, priv->desc_bat_size, priv->desc_bat,
2199 priv->desc_bat_dma);
2200 /* Set reset mode */
2201 ravb_write(ndev, CCC_OPC_RESET, CCC);
2202 pm_runtime_put_sync(&pdev->dev);
2203 unregister_netdev(ndev);
2204 netif_napi_del(&priv->napi[RAVB_NC]);
2205 netif_napi_del(&priv->napi[RAVB_BE]);
2206 ravb_mdio_release(priv);
2207 pm_runtime_disable(&pdev->dev);
2208 free_netdev(ndev);
2209 platform_set_drvdata(pdev, NULL);
2210
2211 return 0;
2212 }
2213
ravb_wol_setup(struct net_device * ndev)2214 static int ravb_wol_setup(struct net_device *ndev)
2215 {
2216 struct ravb_private *priv = netdev_priv(ndev);
2217
2218 /* Disable interrupts by clearing the interrupt masks. */
2219 ravb_write(ndev, 0, RIC0);
2220 ravb_write(ndev, 0, RIC2);
2221 ravb_write(ndev, 0, TIC);
2222
2223 /* Only allow ECI interrupts */
2224 synchronize_irq(priv->emac_irq);
2225 napi_disable(&priv->napi[RAVB_NC]);
2226 napi_disable(&priv->napi[RAVB_BE]);
2227 ravb_write(ndev, ECSIPR_MPDIP, ECSIPR);
2228
2229 /* Enable MagicPacket */
2230 ravb_modify(ndev, ECMR, ECMR_MPDE, ECMR_MPDE);
2231
2232 return enable_irq_wake(priv->emac_irq);
2233 }
2234
ravb_wol_restore(struct net_device * ndev)2235 static int ravb_wol_restore(struct net_device *ndev)
2236 {
2237 struct ravb_private *priv = netdev_priv(ndev);
2238 int ret;
2239
2240 napi_enable(&priv->napi[RAVB_NC]);
2241 napi_enable(&priv->napi[RAVB_BE]);
2242
2243 /* Disable MagicPacket */
2244 ravb_modify(ndev, ECMR, ECMR_MPDE, 0);
2245
2246 ret = ravb_close(ndev);
2247 if (ret < 0)
2248 return ret;
2249
2250 return disable_irq_wake(priv->emac_irq);
2251 }
2252
ravb_suspend(struct device * dev)2253 static int __maybe_unused ravb_suspend(struct device *dev)
2254 {
2255 struct net_device *ndev = dev_get_drvdata(dev);
2256 struct ravb_private *priv = netdev_priv(ndev);
2257 int ret;
2258
2259 if (!netif_running(ndev))
2260 return 0;
2261
2262 netif_device_detach(ndev);
2263
2264 if (priv->wol_enabled)
2265 ret = ravb_wol_setup(ndev);
2266 else
2267 ret = ravb_close(ndev);
2268
2269 return ret;
2270 }
2271
ravb_resume(struct device * dev)2272 static int __maybe_unused ravb_resume(struct device *dev)
2273 {
2274 struct net_device *ndev = dev_get_drvdata(dev);
2275 struct ravb_private *priv = netdev_priv(ndev);
2276 int ret = 0;
2277
2278 /* If WoL is enabled set reset mode to rearm the WoL logic */
2279 if (priv->wol_enabled)
2280 ravb_write(ndev, CCC_OPC_RESET, CCC);
2281
2282 /* All register have been reset to default values.
2283 * Restore all registers which where setup at probe time and
2284 * reopen device if it was running before system suspended.
2285 */
2286
2287 /* Set AVB config mode */
2288 ravb_set_config_mode(ndev);
2289
2290 /* Set GTI value */
2291 ret = ravb_set_gti(ndev);
2292 if (ret)
2293 return ret;
2294
2295 /* Request GTI loading */
2296 ravb_modify(ndev, GCCR, GCCR_LTI, GCCR_LTI);
2297
2298 if (priv->chip_id != RCAR_GEN2)
2299 ravb_set_delay_mode(ndev);
2300
2301 /* Restore descriptor base address table */
2302 ravb_write(ndev, priv->desc_bat_dma, DBAT);
2303
2304 if (netif_running(ndev)) {
2305 if (priv->wol_enabled) {
2306 ret = ravb_wol_restore(ndev);
2307 if (ret)
2308 return ret;
2309 }
2310 ret = ravb_open(ndev);
2311 if (ret < 0)
2312 return ret;
2313 netif_device_attach(ndev);
2314 }
2315
2316 return ret;
2317 }
2318
ravb_runtime_nop(struct device * dev)2319 static int __maybe_unused ravb_runtime_nop(struct device *dev)
2320 {
2321 /* Runtime PM callback shared between ->runtime_suspend()
2322 * and ->runtime_resume(). Simply returns success.
2323 *
2324 * This driver re-initializes all registers after
2325 * pm_runtime_get_sync() anyway so there is no need
2326 * to save and restore registers here.
2327 */
2328 return 0;
2329 }
2330
2331 static const struct dev_pm_ops ravb_dev_pm_ops = {
2332 SET_SYSTEM_SLEEP_PM_OPS(ravb_suspend, ravb_resume)
2333 SET_RUNTIME_PM_OPS(ravb_runtime_nop, ravb_runtime_nop, NULL)
2334 };
2335
2336 static struct platform_driver ravb_driver = {
2337 .probe = ravb_probe,
2338 .remove = ravb_remove,
2339 .driver = {
2340 .name = "ravb",
2341 .pm = &ravb_dev_pm_ops,
2342 .of_match_table = ravb_match_table,
2343 },
2344 };
2345
2346 module_platform_driver(ravb_driver);
2347
2348 MODULE_AUTHOR("Mitsuhiro Kimura, Masaru Nagai");
2349 MODULE_DESCRIPTION("Renesas Ethernet AVB driver");
2350 MODULE_LICENSE("GPL v2");
2351