1 /*******************************************************************************
2 Copyright (C) 2013 Vayavya Labs Pvt Ltd
3
4 This implements all the API for managing HW timestamp & PTP.
5
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
9
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 more details.
14
15 The full GNU General Public License is included in this distribution in
16 the file called "COPYING".
17
18 Author: Rayagond Kokatanur <rayagond@vayavyalabs.com>
19 Author: Giuseppe Cavallaro <peppe.cavallaro@st.com>
20 *******************************************************************************/
21
22 #include <linux/io.h>
23 #include <linux/delay.h>
24 #include "common.h"
25 #include "stmmac_ptp.h"
26
config_hw_tstamping(void __iomem * ioaddr,u32 data)27 static void config_hw_tstamping(void __iomem *ioaddr, u32 data)
28 {
29 writel(data, ioaddr + PTP_TCR);
30 }
31
config_sub_second_increment(void __iomem * ioaddr,u32 ptp_clock,int gmac4,u32 * ssinc)32 static void config_sub_second_increment(void __iomem *ioaddr,
33 u32 ptp_clock, int gmac4, u32 *ssinc)
34 {
35 u32 value = readl(ioaddr + PTP_TCR);
36 unsigned long data;
37 u32 reg_value;
38
39 /* For GMAC3.x, 4.x versions, in "fine adjustement mode" set sub-second
40 * increment to twice the number of nanoseconds of a clock cycle.
41 * The calculation of the default_addend value by the caller will set it
42 * to mid-range = 2^31 when the remainder of this division is zero,
43 * which will make the accumulator overflow once every 2 ptp_clock
44 * cycles, adding twice the number of nanoseconds of a clock cycle :
45 * 2000000000ULL / ptp_clock.
46 */
47 if (value & PTP_TCR_TSCFUPDT)
48 data = (2000000000ULL / ptp_clock);
49 else
50 data = (1000000000ULL / ptp_clock);
51
52 /* 0.465ns accuracy */
53 if (!(value & PTP_TCR_TSCTRLSSR))
54 data = (data * 1000) / 465;
55
56 data &= PTP_SSIR_SSINC_MASK;
57
58 reg_value = data;
59 if (gmac4)
60 reg_value <<= GMAC4_PTP_SSIR_SSINC_SHIFT;
61
62 writel(reg_value, ioaddr + PTP_SSIR);
63
64 if (ssinc)
65 *ssinc = data;
66 }
67
init_systime(void __iomem * ioaddr,u32 sec,u32 nsec)68 static int init_systime(void __iomem *ioaddr, u32 sec, u32 nsec)
69 {
70 int limit;
71 u32 value;
72
73 writel(sec, ioaddr + PTP_STSUR);
74 writel(nsec, ioaddr + PTP_STNSUR);
75 /* issue command to initialize the system time value */
76 value = readl(ioaddr + PTP_TCR);
77 value |= PTP_TCR_TSINIT;
78 writel(value, ioaddr + PTP_TCR);
79
80 /* wait for present system time initialize to complete */
81 limit = 10;
82 while (limit--) {
83 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSINIT))
84 break;
85 mdelay(10);
86 }
87 if (limit < 0)
88 return -EBUSY;
89
90 return 0;
91 }
92
config_addend(void __iomem * ioaddr,u32 addend)93 static int config_addend(void __iomem *ioaddr, u32 addend)
94 {
95 u32 value;
96 int limit;
97
98 writel(addend, ioaddr + PTP_TAR);
99 /* issue command to update the addend value */
100 value = readl(ioaddr + PTP_TCR);
101 value |= PTP_TCR_TSADDREG;
102 writel(value, ioaddr + PTP_TCR);
103
104 /* wait for present addend update to complete */
105 limit = 10;
106 while (limit--) {
107 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSADDREG))
108 break;
109 mdelay(10);
110 }
111 if (limit < 0)
112 return -EBUSY;
113
114 return 0;
115 }
116
adjust_systime(void __iomem * ioaddr,u32 sec,u32 nsec,int add_sub,int gmac4)117 static int adjust_systime(void __iomem *ioaddr, u32 sec, u32 nsec,
118 int add_sub, int gmac4)
119 {
120 u32 value;
121 int limit;
122
123 if (add_sub) {
124 /* If the new sec value needs to be subtracted with
125 * the system time, then MAC_STSUR reg should be
126 * programmed with (2^32 – <new_sec_value>)
127 */
128 if (gmac4)
129 sec = -sec;
130
131 value = readl(ioaddr + PTP_TCR);
132 if (value & PTP_TCR_TSCTRLSSR)
133 nsec = (PTP_DIGITAL_ROLLOVER_MODE - nsec);
134 else
135 nsec = (PTP_BINARY_ROLLOVER_MODE - nsec);
136 }
137
138 writel(sec, ioaddr + PTP_STSUR);
139 value = (add_sub << PTP_STNSUR_ADDSUB_SHIFT) | nsec;
140 writel(value, ioaddr + PTP_STNSUR);
141
142 /* issue command to initialize the system time value */
143 value = readl(ioaddr + PTP_TCR);
144 value |= PTP_TCR_TSUPDT;
145 writel(value, ioaddr + PTP_TCR);
146
147 /* wait for present system time adjust/update to complete */
148 limit = 10;
149 while (limit--) {
150 if (!(readl(ioaddr + PTP_TCR) & PTP_TCR_TSUPDT))
151 break;
152 mdelay(10);
153 }
154 if (limit < 0)
155 return -EBUSY;
156
157 return 0;
158 }
159
get_systime(void __iomem * ioaddr,u64 * systime)160 static void get_systime(void __iomem *ioaddr, u64 *systime)
161 {
162 u64 ns;
163
164 /* Get the TSSS value */
165 ns = readl(ioaddr + PTP_STNSR);
166 /* Get the TSS and convert sec time value to nanosecond */
167 ns += readl(ioaddr + PTP_STSR) * 1000000000ULL;
168
169 if (systime)
170 *systime = ns;
171 }
172
173 const struct stmmac_hwtimestamp stmmac_ptp = {
174 .config_hw_tstamping = config_hw_tstamping,
175 .init_systime = init_systime,
176 .config_sub_second_increment = config_sub_second_increment,
177 .config_addend = config_addend,
178 .adjust_systime = adjust_systime,
179 .get_systime = get_systime,
180 };
181