1 /*
2 * DaVinci MDIO Module driver
3 *
4 * Copyright (C) 2010 Texas Instruments.
5 *
6 * Shamelessly ripped out of davinci_emac.c, original copyrights follow:
7 *
8 * Copyright (C) 2009 Texas Instruments.
9 *
10 * ---------------------------------------------------------------------------
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 * ---------------------------------------------------------------------------
26 */
27 #include <linux/module.h>
28 #include <linux/kernel.h>
29 #include <linux/platform_device.h>
30 #include <linux/delay.h>
31 #include <linux/sched.h>
32 #include <linux/slab.h>
33 #include <linux/phy.h>
34 #include <linux/clk.h>
35 #include <linux/err.h>
36 #include <linux/io.h>
37 #include <linux/iopoll.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/davinci_emac.h>
40 #include <linux/of.h>
41 #include <linux/of_device.h>
42 #include <linux/of_mdio.h>
43 #include <linux/pinctrl/consumer.h>
44
45 /*
46 * This timeout definition is a worst-case ultra defensive measure against
47 * unexpected controller lock ups. Ideally, we should never ever hit this
48 * scenario in practice.
49 */
50 #define MDIO_TIMEOUT 100 /* msecs */
51
52 #define PHY_REG_MASK 0x1f
53 #define PHY_ID_MASK 0x1f
54
55 #define DEF_OUT_FREQ 2200000 /* 2.2 MHz */
56
57 struct davinci_mdio_of_param {
58 int autosuspend_delay_ms;
59 };
60
61 struct davinci_mdio_regs {
62 u32 version;
63 u32 control;
64 #define CONTROL_IDLE BIT(31)
65 #define CONTROL_ENABLE BIT(30)
66 #define CONTROL_MAX_DIV (0xffff)
67
68 u32 alive;
69 u32 link;
70 u32 linkintraw;
71 u32 linkintmasked;
72 u32 __reserved_0[2];
73 u32 userintraw;
74 u32 userintmasked;
75 u32 userintmaskset;
76 u32 userintmaskclr;
77 u32 __reserved_1[20];
78
79 struct {
80 u32 access;
81 #define USERACCESS_GO BIT(31)
82 #define USERACCESS_WRITE BIT(30)
83 #define USERACCESS_ACK BIT(29)
84 #define USERACCESS_READ (0)
85 #define USERACCESS_DATA (0xffff)
86
87 u32 physel;
88 } user[0];
89 };
90
91 static const struct mdio_platform_data default_pdata = {
92 .bus_freq = DEF_OUT_FREQ,
93 };
94
95 struct davinci_mdio_data {
96 struct mdio_platform_data pdata;
97 struct davinci_mdio_regs __iomem *regs;
98 struct clk *clk;
99 struct device *dev;
100 struct mii_bus *bus;
101 bool active_in_suspend;
102 unsigned long access_time; /* jiffies */
103 /* Indicates that driver shouldn't modify phy_mask in case
104 * if MDIO bus is registered from DT.
105 */
106 bool skip_scan;
107 u32 clk_div;
108 };
109
davinci_mdio_init_clk(struct davinci_mdio_data * data)110 static void davinci_mdio_init_clk(struct davinci_mdio_data *data)
111 {
112 u32 mdio_in, div, mdio_out_khz, access_time;
113
114 mdio_in = clk_get_rate(data->clk);
115 div = (mdio_in / data->pdata.bus_freq) - 1;
116 if (div > CONTROL_MAX_DIV)
117 div = CONTROL_MAX_DIV;
118
119 data->clk_div = div;
120 /*
121 * One mdio transaction consists of:
122 * 32 bits of preamble
123 * 32 bits of transferred data
124 * 24 bits of bus yield (not needed unless shared?)
125 */
126 mdio_out_khz = mdio_in / (1000 * (div + 1));
127 access_time = (88 * 1000) / mdio_out_khz;
128
129 /*
130 * In the worst case, we could be kicking off a user-access immediately
131 * after the mdio bus scan state-machine triggered its own read. If
132 * so, our request could get deferred by one access cycle. We
133 * defensively allow for 4 access cycles.
134 */
135 data->access_time = usecs_to_jiffies(access_time * 4);
136 if (!data->access_time)
137 data->access_time = 1;
138 }
139
davinci_mdio_enable(struct davinci_mdio_data * data)140 static void davinci_mdio_enable(struct davinci_mdio_data *data)
141 {
142 /* set enable and clock divider */
143 __raw_writel(data->clk_div | CONTROL_ENABLE, &data->regs->control);
144 }
145
davinci_mdio_reset(struct mii_bus * bus)146 static int davinci_mdio_reset(struct mii_bus *bus)
147 {
148 struct davinci_mdio_data *data = bus->priv;
149 u32 phy_mask, ver;
150 int ret;
151
152 ret = pm_runtime_get_sync(data->dev);
153 if (ret < 0) {
154 pm_runtime_put_noidle(data->dev);
155 return ret;
156 }
157
158 /* wait for scan logic to settle */
159 msleep(PHY_MAX_ADDR * data->access_time);
160
161 /* dump hardware version info */
162 ver = __raw_readl(&data->regs->version);
163 dev_info(data->dev,
164 "davinci mdio revision %d.%d, bus freq %ld\n",
165 (ver >> 8) & 0xff, ver & 0xff,
166 data->pdata.bus_freq);
167
168 if (data->skip_scan)
169 goto done;
170
171 /* get phy mask from the alive register */
172 phy_mask = __raw_readl(&data->regs->alive);
173 if (phy_mask) {
174 /* restrict mdio bus to live phys only */
175 dev_info(data->dev, "detected phy mask %x\n", ~phy_mask);
176 phy_mask = ~phy_mask;
177 } else {
178 /* desperately scan all phys */
179 dev_warn(data->dev, "no live phy, scanning all\n");
180 phy_mask = 0;
181 }
182 data->bus->phy_mask = phy_mask;
183
184 done:
185 pm_runtime_mark_last_busy(data->dev);
186 pm_runtime_put_autosuspend(data->dev);
187
188 return 0;
189 }
190
191 /* wait until hardware is ready for another user access */
wait_for_user_access(struct davinci_mdio_data * data)192 static inline int wait_for_user_access(struct davinci_mdio_data *data)
193 {
194 struct davinci_mdio_regs __iomem *regs = data->regs;
195 unsigned long timeout = jiffies + msecs_to_jiffies(MDIO_TIMEOUT);
196 u32 reg;
197
198 while (time_after(timeout, jiffies)) {
199 reg = __raw_readl(®s->user[0].access);
200 if ((reg & USERACCESS_GO) == 0)
201 return 0;
202
203 reg = __raw_readl(®s->control);
204 if ((reg & CONTROL_IDLE) == 0) {
205 usleep_range(100, 200);
206 continue;
207 }
208
209 /*
210 * An emac soft_reset may have clobbered the mdio controller's
211 * state machine. We need to reset and retry the current
212 * operation
213 */
214 dev_warn(data->dev, "resetting idled controller\n");
215 davinci_mdio_enable(data);
216 return -EAGAIN;
217 }
218
219 reg = __raw_readl(®s->user[0].access);
220 if ((reg & USERACCESS_GO) == 0)
221 return 0;
222
223 dev_err(data->dev, "timed out waiting for user access\n");
224 return -ETIMEDOUT;
225 }
226
227 /* wait until hardware state machine is idle */
wait_for_idle(struct davinci_mdio_data * data)228 static inline int wait_for_idle(struct davinci_mdio_data *data)
229 {
230 struct davinci_mdio_regs __iomem *regs = data->regs;
231 u32 val, ret;
232
233 ret = readl_poll_timeout(®s->control, val, val & CONTROL_IDLE,
234 0, MDIO_TIMEOUT * 1000);
235 if (ret)
236 dev_err(data->dev, "timed out waiting for idle\n");
237
238 return ret;
239 }
240
davinci_mdio_read(struct mii_bus * bus,int phy_id,int phy_reg)241 static int davinci_mdio_read(struct mii_bus *bus, int phy_id, int phy_reg)
242 {
243 struct davinci_mdio_data *data = bus->priv;
244 u32 reg;
245 int ret;
246
247 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
248 return -EINVAL;
249
250 ret = pm_runtime_get_sync(data->dev);
251 if (ret < 0) {
252 pm_runtime_put_noidle(data->dev);
253 return ret;
254 }
255
256 reg = (USERACCESS_GO | USERACCESS_READ | (phy_reg << 21) |
257 (phy_id << 16));
258
259 while (1) {
260 ret = wait_for_user_access(data);
261 if (ret == -EAGAIN)
262 continue;
263 if (ret < 0)
264 break;
265
266 __raw_writel(reg, &data->regs->user[0].access);
267
268 ret = wait_for_user_access(data);
269 if (ret == -EAGAIN)
270 continue;
271 if (ret < 0)
272 break;
273
274 reg = __raw_readl(&data->regs->user[0].access);
275 ret = (reg & USERACCESS_ACK) ? (reg & USERACCESS_DATA) : -EIO;
276 break;
277 }
278
279 pm_runtime_mark_last_busy(data->dev);
280 pm_runtime_put_autosuspend(data->dev);
281 return ret;
282 }
283
davinci_mdio_write(struct mii_bus * bus,int phy_id,int phy_reg,u16 phy_data)284 static int davinci_mdio_write(struct mii_bus *bus, int phy_id,
285 int phy_reg, u16 phy_data)
286 {
287 struct davinci_mdio_data *data = bus->priv;
288 u32 reg;
289 int ret;
290
291 if (phy_reg & ~PHY_REG_MASK || phy_id & ~PHY_ID_MASK)
292 return -EINVAL;
293
294 ret = pm_runtime_get_sync(data->dev);
295 if (ret < 0) {
296 pm_runtime_put_noidle(data->dev);
297 return ret;
298 }
299
300 reg = (USERACCESS_GO | USERACCESS_WRITE | (phy_reg << 21) |
301 (phy_id << 16) | (phy_data & USERACCESS_DATA));
302
303 while (1) {
304 ret = wait_for_user_access(data);
305 if (ret == -EAGAIN)
306 continue;
307 if (ret < 0)
308 break;
309
310 __raw_writel(reg, &data->regs->user[0].access);
311
312 ret = wait_for_user_access(data);
313 if (ret == -EAGAIN)
314 continue;
315 break;
316 }
317
318 pm_runtime_mark_last_busy(data->dev);
319 pm_runtime_put_autosuspend(data->dev);
320
321 return ret;
322 }
323
davinci_mdio_probe_dt(struct mdio_platform_data * data,struct platform_device * pdev)324 static int davinci_mdio_probe_dt(struct mdio_platform_data *data,
325 struct platform_device *pdev)
326 {
327 struct device_node *node = pdev->dev.of_node;
328 u32 prop;
329
330 if (!node)
331 return -EINVAL;
332
333 if (of_property_read_u32(node, "bus_freq", &prop)) {
334 dev_err(&pdev->dev, "Missing bus_freq property in the DT.\n");
335 return -EINVAL;
336 }
337 data->bus_freq = prop;
338
339 return 0;
340 }
341
342 #if IS_ENABLED(CONFIG_OF)
343 static const struct davinci_mdio_of_param of_cpsw_mdio_data = {
344 .autosuspend_delay_ms = 100,
345 };
346
347 static const struct of_device_id davinci_mdio_of_mtable[] = {
348 { .compatible = "ti,davinci_mdio", },
349 { .compatible = "ti,cpsw-mdio", .data = &of_cpsw_mdio_data},
350 { /* sentinel */ },
351 };
352 MODULE_DEVICE_TABLE(of, davinci_mdio_of_mtable);
353 #endif
354
davinci_mdio_probe(struct platform_device * pdev)355 static int davinci_mdio_probe(struct platform_device *pdev)
356 {
357 struct mdio_platform_data *pdata = dev_get_platdata(&pdev->dev);
358 struct device *dev = &pdev->dev;
359 struct davinci_mdio_data *data;
360 struct resource *res;
361 struct phy_device *phy;
362 int ret, addr;
363 int autosuspend_delay_ms = -1;
364
365 data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
366 if (!data)
367 return -ENOMEM;
368
369 data->bus = devm_mdiobus_alloc(dev);
370 if (!data->bus) {
371 dev_err(dev, "failed to alloc mii bus\n");
372 return -ENOMEM;
373 }
374
375 if (IS_ENABLED(CONFIG_OF) && dev->of_node) {
376 const struct of_device_id *of_id;
377
378 ret = davinci_mdio_probe_dt(&data->pdata, pdev);
379 if (ret)
380 return ret;
381 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
382
383 of_id = of_match_device(davinci_mdio_of_mtable, &pdev->dev);
384 if (of_id) {
385 const struct davinci_mdio_of_param *of_mdio_data;
386
387 of_mdio_data = of_id->data;
388 if (of_mdio_data)
389 autosuspend_delay_ms =
390 of_mdio_data->autosuspend_delay_ms;
391 }
392 } else {
393 data->pdata = pdata ? (*pdata) : default_pdata;
394 snprintf(data->bus->id, MII_BUS_ID_SIZE, "%s-%x",
395 pdev->name, pdev->id);
396 }
397
398 data->bus->name = dev_name(dev);
399 data->bus->read = davinci_mdio_read,
400 data->bus->write = davinci_mdio_write,
401 data->bus->reset = davinci_mdio_reset,
402 data->bus->parent = dev;
403 data->bus->priv = data;
404
405 data->clk = devm_clk_get(dev, "fck");
406 if (IS_ERR(data->clk)) {
407 dev_err(dev, "failed to get device clock\n");
408 return PTR_ERR(data->clk);
409 }
410
411 dev_set_drvdata(dev, data);
412 data->dev = dev;
413
414 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
415 data->regs = devm_ioremap_resource(dev, res);
416 if (IS_ERR(data->regs))
417 return PTR_ERR(data->regs);
418
419 davinci_mdio_init_clk(data);
420
421 pm_runtime_set_autosuspend_delay(&pdev->dev, autosuspend_delay_ms);
422 pm_runtime_use_autosuspend(&pdev->dev);
423 pm_runtime_enable(&pdev->dev);
424
425 /* register the mii bus
426 * Create PHYs from DT only in case if PHY child nodes are explicitly
427 * defined to support backward compatibility with DTs which assume that
428 * Davinci MDIO will always scan the bus for PHYs detection.
429 */
430 if (dev->of_node && of_get_child_count(dev->of_node))
431 data->skip_scan = true;
432
433 ret = of_mdiobus_register(data->bus, dev->of_node);
434 if (ret)
435 goto bail_out;
436
437 /* scan and dump the bus */
438 for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
439 phy = mdiobus_get_phy(data->bus, addr);
440 if (phy) {
441 dev_info(dev, "phy[%d]: device %s, driver %s\n",
442 phy->mdio.addr, phydev_name(phy),
443 phy->drv ? phy->drv->name : "unknown");
444 }
445 }
446
447 return 0;
448
449 bail_out:
450 pm_runtime_dont_use_autosuspend(&pdev->dev);
451 pm_runtime_disable(&pdev->dev);
452 return ret;
453 }
454
davinci_mdio_remove(struct platform_device * pdev)455 static int davinci_mdio_remove(struct platform_device *pdev)
456 {
457 struct davinci_mdio_data *data = platform_get_drvdata(pdev);
458
459 if (data->bus)
460 mdiobus_unregister(data->bus);
461
462 pm_runtime_dont_use_autosuspend(&pdev->dev);
463 pm_runtime_disable(&pdev->dev);
464
465 return 0;
466 }
467
468 #ifdef CONFIG_PM
davinci_mdio_runtime_suspend(struct device * dev)469 static int davinci_mdio_runtime_suspend(struct device *dev)
470 {
471 struct davinci_mdio_data *data = dev_get_drvdata(dev);
472 u32 ctrl;
473
474 /* shutdown the scan state machine */
475 ctrl = __raw_readl(&data->regs->control);
476 ctrl &= ~CONTROL_ENABLE;
477 __raw_writel(ctrl, &data->regs->control);
478 wait_for_idle(data);
479
480 return 0;
481 }
482
davinci_mdio_runtime_resume(struct device * dev)483 static int davinci_mdio_runtime_resume(struct device *dev)
484 {
485 struct davinci_mdio_data *data = dev_get_drvdata(dev);
486
487 davinci_mdio_enable(data);
488 return 0;
489 }
490 #endif
491
492 #ifdef CONFIG_PM_SLEEP
davinci_mdio_suspend(struct device * dev)493 static int davinci_mdio_suspend(struct device *dev)
494 {
495 struct davinci_mdio_data *data = dev_get_drvdata(dev);
496 int ret = 0;
497
498 data->active_in_suspend = !pm_runtime_status_suspended(dev);
499 if (data->active_in_suspend)
500 ret = pm_runtime_force_suspend(dev);
501 if (ret < 0)
502 return ret;
503
504 /* Select sleep pin state */
505 pinctrl_pm_select_sleep_state(dev);
506
507 return 0;
508 }
509
davinci_mdio_resume(struct device * dev)510 static int davinci_mdio_resume(struct device *dev)
511 {
512 struct davinci_mdio_data *data = dev_get_drvdata(dev);
513
514 /* Select default pin state */
515 pinctrl_pm_select_default_state(dev);
516
517 if (data->active_in_suspend)
518 pm_runtime_force_resume(dev);
519
520 return 0;
521 }
522 #endif
523
524 static const struct dev_pm_ops davinci_mdio_pm_ops = {
525 SET_RUNTIME_PM_OPS(davinci_mdio_runtime_suspend,
526 davinci_mdio_runtime_resume, NULL)
527 SET_LATE_SYSTEM_SLEEP_PM_OPS(davinci_mdio_suspend, davinci_mdio_resume)
528 };
529
530 static struct platform_driver davinci_mdio_driver = {
531 .driver = {
532 .name = "davinci_mdio",
533 .pm = &davinci_mdio_pm_ops,
534 .of_match_table = of_match_ptr(davinci_mdio_of_mtable),
535 },
536 .probe = davinci_mdio_probe,
537 .remove = davinci_mdio_remove,
538 };
539
davinci_mdio_init(void)540 static int __init davinci_mdio_init(void)
541 {
542 return platform_driver_register(&davinci_mdio_driver);
543 }
544 device_initcall(davinci_mdio_init);
545
davinci_mdio_exit(void)546 static void __exit davinci_mdio_exit(void)
547 {
548 platform_driver_unregister(&davinci_mdio_driver);
549 }
550 module_exit(davinci_mdio_exit);
551
552 MODULE_LICENSE("GPL");
553 MODULE_DESCRIPTION("DaVinci MDIO driver");
554