1 /******************************************************************************
2 *
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
5 *
6 * GPL LICENSE SUMMARY
7 *
8 * Copyright(c) 2008 - 2014 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
11 * Copyright(c) 2018 Intel Corporation
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of version 2 of the GNU General Public License as
15 * published by the Free Software Foundation.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
25 * USA
26 *
27 * The full GNU General Public License is included in this distribution
28 * in the file called COPYING.
29 *
30 * Contact Information:
31 * Intel Linux Wireless <linuxwifi@intel.com>
32 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
33 *
34 * BSD LICENSE
35 *
36 * Copyright(c) 2005 - 2014 Intel Corporation. All rights reserved.
37 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
38 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
39 * Copyright(c) 2018 Intel Corporation
40 * All rights reserved.
41 *
42 * Redistribution and use in source and binary forms, with or without
43 * modification, are permitted provided that the following conditions
44 * are met:
45 *
46 * * Redistributions of source code must retain the above copyright
47 * notice, this list of conditions and the following disclaimer.
48 * * Redistributions in binary form must reproduce the above copyright
49 * notice, this list of conditions and the following disclaimer in
50 * the documentation and/or other materials provided with the
51 * distribution.
52 * * Neither the name Intel Corporation nor the names of its
53 * contributors may be used to endorse or promote products derived
54 * from this software without specific prior written permission.
55 *
56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
57 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
58 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
59 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
60 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
61 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
62 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
63 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
64 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
65 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
66 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
67 *****************************************************************************/
68 #include <linux/types.h>
69 #include <linux/slab.h>
70 #include <linux/export.h>
71 #include <linux/etherdevice.h>
72 #include <linux/pci.h>
73 #include <linux/firmware.h>
74
75 #include "iwl-drv.h"
76 #include "iwl-modparams.h"
77 #include "iwl-nvm-parse.h"
78 #include "iwl-prph.h"
79 #include "iwl-io.h"
80 #include "iwl-csr.h"
81 #include "fw/acpi.h"
82 #include "fw/api/nvm-reg.h"
83 #include "fw/api/commands.h"
84 #include "fw/api/cmdhdr.h"
85 #include "fw/img.h"
86
87 /* NVM offsets (in words) definitions */
88 enum nvm_offsets {
89 /* NVM HW-Section offset (in words) definitions */
90 SUBSYSTEM_ID = 0x0A,
91 HW_ADDR = 0x15,
92
93 /* NVM SW-Section offset (in words) definitions */
94 NVM_SW_SECTION = 0x1C0,
95 NVM_VERSION = 0,
96 RADIO_CFG = 1,
97 SKU = 2,
98 N_HW_ADDRS = 3,
99 NVM_CHANNELS = 0x1E0 - NVM_SW_SECTION,
100
101 /* NVM calibration section offset (in words) definitions */
102 NVM_CALIB_SECTION = 0x2B8,
103 XTAL_CALIB = 0x316 - NVM_CALIB_SECTION,
104
105 /* NVM REGULATORY -Section offset (in words) definitions */
106 NVM_CHANNELS_SDP = 0,
107 };
108
109 enum ext_nvm_offsets {
110 /* NVM HW-Section offset (in words) definitions */
111 MAC_ADDRESS_OVERRIDE_EXT_NVM = 1,
112
113 /* NVM SW-Section offset (in words) definitions */
114 NVM_VERSION_EXT_NVM = 0,
115 RADIO_CFG_FAMILY_EXT_NVM = 0,
116 SKU_FAMILY_8000 = 2,
117 N_HW_ADDRS_FAMILY_8000 = 3,
118
119 /* NVM REGULATORY -Section offset (in words) definitions */
120 NVM_CHANNELS_EXTENDED = 0,
121 NVM_LAR_OFFSET_OLD = 0x4C7,
122 NVM_LAR_OFFSET = 0x507,
123 NVM_LAR_ENABLED = 0x7,
124 };
125
126 /* SKU Capabilities (actual values from NVM definition) */
127 enum nvm_sku_bits {
128 NVM_SKU_CAP_BAND_24GHZ = BIT(0),
129 NVM_SKU_CAP_BAND_52GHZ = BIT(1),
130 NVM_SKU_CAP_11N_ENABLE = BIT(2),
131 NVM_SKU_CAP_11AC_ENABLE = BIT(3),
132 NVM_SKU_CAP_MIMO_DISABLE = BIT(5),
133 };
134
135 /*
136 * These are the channel numbers in the order that they are stored in the NVM
137 */
138 static const u8 iwl_nvm_channels[] = {
139 /* 2.4 GHz */
140 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
141 /* 5 GHz */
142 36, 40, 44 , 48, 52, 56, 60, 64,
143 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
144 149, 153, 157, 161, 165
145 };
146
147 static const u8 iwl_ext_nvm_channels[] = {
148 /* 2.4 GHz */
149 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14,
150 /* 5 GHz */
151 36, 40, 44, 48, 52, 56, 60, 64, 68, 72, 76, 80, 84, 88, 92,
152 96, 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140, 144,
153 149, 153, 157, 161, 165, 169, 173, 177, 181
154 };
155
156 #define IWL_NVM_NUM_CHANNELS ARRAY_SIZE(iwl_nvm_channels)
157 #define IWL_NVM_NUM_CHANNELS_EXT ARRAY_SIZE(iwl_ext_nvm_channels)
158 #define NUM_2GHZ_CHANNELS 14
159 #define NUM_2GHZ_CHANNELS_EXT 14
160 #define FIRST_2GHZ_HT_MINUS 5
161 #define LAST_2GHZ_HT_PLUS 9
162 #define LAST_5GHZ_HT 165
163 #define LAST_5GHZ_HT_FAMILY_8000 181
164 #define N_HW_ADDR_MASK 0xF
165
166 /* rate data (static) */
167 static struct ieee80211_rate iwl_cfg80211_rates[] = {
168 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, },
169 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1,
170 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
171 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2,
172 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
173 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3,
174 .flags = IEEE80211_RATE_SHORT_PREAMBLE, },
175 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, },
176 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, },
177 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, },
178 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, },
179 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, },
180 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, },
181 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, },
182 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, },
183 };
184 #define RATES_24_OFFS 0
185 #define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates)
186 #define RATES_52_OFFS 4
187 #define N_RATES_52 (N_RATES_24 - RATES_52_OFFS)
188
189 /**
190 * enum iwl_nvm_channel_flags - channel flags in NVM
191 * @NVM_CHANNEL_VALID: channel is usable for this SKU/geo
192 * @NVM_CHANNEL_IBSS: usable as an IBSS channel
193 * @NVM_CHANNEL_ACTIVE: active scanning allowed
194 * @NVM_CHANNEL_RADAR: radar detection required
195 * @NVM_CHANNEL_INDOOR_ONLY: only indoor use is allowed
196 * @NVM_CHANNEL_GO_CONCURRENT: GO operation is allowed when connected to BSS
197 * on same channel on 2.4 or same UNII band on 5.2
198 * @NVM_CHANNEL_UNIFORM: uniform spreading required
199 * @NVM_CHANNEL_20MHZ: 20 MHz channel okay
200 * @NVM_CHANNEL_40MHZ: 40 MHz channel okay
201 * @NVM_CHANNEL_80MHZ: 80 MHz channel okay
202 * @NVM_CHANNEL_160MHZ: 160 MHz channel okay
203 * @NVM_CHANNEL_DC_HIGH: DC HIGH required/allowed (?)
204 */
205 enum iwl_nvm_channel_flags {
206 NVM_CHANNEL_VALID = BIT(0),
207 NVM_CHANNEL_IBSS = BIT(1),
208 NVM_CHANNEL_ACTIVE = BIT(3),
209 NVM_CHANNEL_RADAR = BIT(4),
210 NVM_CHANNEL_INDOOR_ONLY = BIT(5),
211 NVM_CHANNEL_GO_CONCURRENT = BIT(6),
212 NVM_CHANNEL_UNIFORM = BIT(7),
213 NVM_CHANNEL_20MHZ = BIT(8),
214 NVM_CHANNEL_40MHZ = BIT(9),
215 NVM_CHANNEL_80MHZ = BIT(10),
216 NVM_CHANNEL_160MHZ = BIT(11),
217 NVM_CHANNEL_DC_HIGH = BIT(12),
218 };
219
220 /**
221 * enum iwl_reg_capa_flags - global flags applied for the whole regulatory
222 * domain.
223 * @REG_CAPA_BF_CCD_LOW_BAND: Beam-forming or Cyclic Delay Diversity in the
224 * 2.4Ghz band is allowed.
225 * @REG_CAPA_BF_CCD_HIGH_BAND: Beam-forming or Cyclic Delay Diversity in the
226 * 5Ghz band is allowed.
227 * @REG_CAPA_160MHZ_ALLOWED: 11ac channel with a width of 160Mhz is allowed
228 * for this regulatory domain (valid only in 5Ghz).
229 * @REG_CAPA_80MHZ_ALLOWED: 11ac channel with a width of 80Mhz is allowed
230 * for this regulatory domain (valid only in 5Ghz).
231 * @REG_CAPA_MCS_8_ALLOWED: 11ac with MCS 8 is allowed.
232 * @REG_CAPA_MCS_9_ALLOWED: 11ac with MCS 9 is allowed.
233 * @REG_CAPA_40MHZ_FORBIDDEN: 11n channel with a width of 40Mhz is forbidden
234 * for this regulatory domain (valid only in 5Ghz).
235 * @REG_CAPA_DC_HIGH_ENABLED: DC HIGH allowed.
236 */
237 enum iwl_reg_capa_flags {
238 REG_CAPA_BF_CCD_LOW_BAND = BIT(0),
239 REG_CAPA_BF_CCD_HIGH_BAND = BIT(1),
240 REG_CAPA_160MHZ_ALLOWED = BIT(2),
241 REG_CAPA_80MHZ_ALLOWED = BIT(3),
242 REG_CAPA_MCS_8_ALLOWED = BIT(4),
243 REG_CAPA_MCS_9_ALLOWED = BIT(5),
244 REG_CAPA_40MHZ_FORBIDDEN = BIT(7),
245 REG_CAPA_DC_HIGH_ENABLED = BIT(9),
246 };
247
iwl_nvm_print_channel_flags(struct device * dev,u32 level,int chan,u16 flags)248 static inline void iwl_nvm_print_channel_flags(struct device *dev, u32 level,
249 int chan, u16 flags)
250 {
251 #define CHECK_AND_PRINT_I(x) \
252 ((flags & NVM_CHANNEL_##x) ? " " #x : "")
253
254 if (!(flags & NVM_CHANNEL_VALID)) {
255 IWL_DEBUG_DEV(dev, level, "Ch. %d: 0x%x: No traffic\n",
256 chan, flags);
257 return;
258 }
259
260 /* Note: already can print up to 101 characters, 110 is the limit! */
261 IWL_DEBUG_DEV(dev, level,
262 "Ch. %d: 0x%x:%s%s%s%s%s%s%s%s%s%s%s%s\n",
263 chan, flags,
264 CHECK_AND_PRINT_I(VALID),
265 CHECK_AND_PRINT_I(IBSS),
266 CHECK_AND_PRINT_I(ACTIVE),
267 CHECK_AND_PRINT_I(RADAR),
268 CHECK_AND_PRINT_I(INDOOR_ONLY),
269 CHECK_AND_PRINT_I(GO_CONCURRENT),
270 CHECK_AND_PRINT_I(UNIFORM),
271 CHECK_AND_PRINT_I(20MHZ),
272 CHECK_AND_PRINT_I(40MHZ),
273 CHECK_AND_PRINT_I(80MHZ),
274 CHECK_AND_PRINT_I(160MHZ),
275 CHECK_AND_PRINT_I(DC_HIGH));
276 #undef CHECK_AND_PRINT_I
277 }
278
iwl_get_channel_flags(u8 ch_num,int ch_idx,bool is_5ghz,u16 nvm_flags,const struct iwl_cfg * cfg)279 static u32 iwl_get_channel_flags(u8 ch_num, int ch_idx, bool is_5ghz,
280 u16 nvm_flags, const struct iwl_cfg *cfg)
281 {
282 u32 flags = IEEE80211_CHAN_NO_HT40;
283 u32 last_5ghz_ht = LAST_5GHZ_HT;
284
285 if (cfg->nvm_type == IWL_NVM_EXT)
286 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
287
288 if (!is_5ghz && (nvm_flags & NVM_CHANNEL_40MHZ)) {
289 if (ch_num <= LAST_2GHZ_HT_PLUS)
290 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
291 if (ch_num >= FIRST_2GHZ_HT_MINUS)
292 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
293 } else if (ch_num <= last_5ghz_ht && (nvm_flags & NVM_CHANNEL_40MHZ)) {
294 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
295 flags &= ~IEEE80211_CHAN_NO_HT40PLUS;
296 else
297 flags &= ~IEEE80211_CHAN_NO_HT40MINUS;
298 }
299 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
300 flags |= IEEE80211_CHAN_NO_80MHZ;
301 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
302 flags |= IEEE80211_CHAN_NO_160MHZ;
303
304 if (!(nvm_flags & NVM_CHANNEL_IBSS))
305 flags |= IEEE80211_CHAN_NO_IR;
306
307 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
308 flags |= IEEE80211_CHAN_NO_IR;
309
310 if (nvm_flags & NVM_CHANNEL_RADAR)
311 flags |= IEEE80211_CHAN_RADAR;
312
313 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
314 flags |= IEEE80211_CHAN_INDOOR_ONLY;
315
316 /* Set the GO concurrent flag only in case that NO_IR is set.
317 * Otherwise it is meaningless
318 */
319 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
320 (flags & IEEE80211_CHAN_NO_IR))
321 flags |= IEEE80211_CHAN_IR_CONCURRENT;
322
323 return flags;
324 }
325
iwl_init_channel_map(struct device * dev,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * const nvm_ch_flags,u32 sbands_flags)326 static int iwl_init_channel_map(struct device *dev, const struct iwl_cfg *cfg,
327 struct iwl_nvm_data *data,
328 const __le16 * const nvm_ch_flags,
329 u32 sbands_flags)
330 {
331 int ch_idx;
332 int n_channels = 0;
333 struct ieee80211_channel *channel;
334 u16 ch_flags;
335 int num_of_ch, num_2ghz_channels;
336 const u8 *nvm_chan;
337
338 if (cfg->nvm_type != IWL_NVM_EXT) {
339 num_of_ch = IWL_NVM_NUM_CHANNELS;
340 nvm_chan = &iwl_nvm_channels[0];
341 num_2ghz_channels = NUM_2GHZ_CHANNELS;
342 } else {
343 num_of_ch = IWL_NVM_NUM_CHANNELS_EXT;
344 nvm_chan = &iwl_ext_nvm_channels[0];
345 num_2ghz_channels = NUM_2GHZ_CHANNELS_EXT;
346 }
347
348 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
349 bool is_5ghz = (ch_idx >= num_2ghz_channels);
350
351 ch_flags = __le16_to_cpup(nvm_ch_flags + ch_idx);
352
353 if (is_5ghz && !data->sku_cap_band_52ghz_enable)
354 continue;
355
356 /* workaround to disable wide channels in 5GHz */
357 if ((sbands_flags & IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ) &&
358 is_5ghz) {
359 ch_flags &= ~(NVM_CHANNEL_40MHZ |
360 NVM_CHANNEL_80MHZ |
361 NVM_CHANNEL_160MHZ);
362 }
363
364 if (ch_flags & NVM_CHANNEL_160MHZ)
365 data->vht160_supported = true;
366
367 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR) &&
368 !(ch_flags & NVM_CHANNEL_VALID)) {
369 /*
370 * Channels might become valid later if lar is
371 * supported, hence we still want to add them to
372 * the list of supported channels to cfg80211.
373 */
374 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
375 nvm_chan[ch_idx], ch_flags);
376 continue;
377 }
378
379 channel = &data->channels[n_channels];
380 n_channels++;
381
382 channel->hw_value = nvm_chan[ch_idx];
383 channel->band = is_5ghz ?
384 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ;
385 channel->center_freq =
386 ieee80211_channel_to_frequency(
387 channel->hw_value, channel->band);
388
389 /* Initialize regulatory-based run-time data */
390
391 /*
392 * Default value - highest tx power value. max_power
393 * is not used in mvm, and is used for backwards compatibility
394 */
395 channel->max_power = IWL_DEFAULT_MAX_TX_POWER;
396
397 /* don't put limitations in case we're using LAR */
398 if (!(sbands_flags & IWL_NVM_SBANDS_FLAGS_LAR))
399 channel->flags = iwl_get_channel_flags(nvm_chan[ch_idx],
400 ch_idx, is_5ghz,
401 ch_flags, cfg);
402 else
403 channel->flags = 0;
404
405 iwl_nvm_print_channel_flags(dev, IWL_DL_EEPROM,
406 channel->hw_value, ch_flags);
407 IWL_DEBUG_EEPROM(dev, "Ch. %d: %ddBm\n",
408 channel->hw_value, channel->max_power);
409 }
410
411 return n_channels;
412 }
413
iwl_init_vht_hw_capab(const struct iwl_cfg * cfg,struct iwl_nvm_data * data,struct ieee80211_sta_vht_cap * vht_cap,u8 tx_chains,u8 rx_chains)414 static void iwl_init_vht_hw_capab(const struct iwl_cfg *cfg,
415 struct iwl_nvm_data *data,
416 struct ieee80211_sta_vht_cap *vht_cap,
417 u8 tx_chains, u8 rx_chains)
418 {
419 int num_rx_ants = num_of_ant(rx_chains);
420 int num_tx_ants = num_of_ant(tx_chains);
421 unsigned int max_ampdu_exponent = (cfg->max_vht_ampdu_exponent ?:
422 IEEE80211_VHT_MAX_AMPDU_1024K);
423
424 vht_cap->vht_supported = true;
425
426 vht_cap->cap = IEEE80211_VHT_CAP_SHORT_GI_80 |
427 IEEE80211_VHT_CAP_RXSTBC_1 |
428 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE |
429 3 << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT |
430 max_ampdu_exponent <<
431 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_SHIFT;
432
433 if (data->vht160_supported)
434 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
435 IEEE80211_VHT_CAP_SHORT_GI_160;
436
437 if (cfg->vht_mu_mimo_supported)
438 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE;
439
440 if (cfg->ht_params->ldpc)
441 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
442
443 if (data->sku_cap_mimo_disabled) {
444 num_rx_ants = 1;
445 num_tx_ants = 1;
446 }
447
448 if (num_tx_ants > 1)
449 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
450 else
451 vht_cap->cap |= IEEE80211_VHT_CAP_TX_ANTENNA_PATTERN;
452
453 switch (iwlwifi_mod_params.amsdu_size) {
454 case IWL_AMSDU_DEF:
455 if (cfg->mq_rx_supported)
456 vht_cap->cap |=
457 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
458 else
459 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
460 break;
461 case IWL_AMSDU_2K:
462 if (cfg->mq_rx_supported)
463 vht_cap->cap |=
464 IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
465 else
466 WARN(1, "RB size of 2K is not supported by this device\n");
467 break;
468 case IWL_AMSDU_4K:
469 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_3895;
470 break;
471 case IWL_AMSDU_8K:
472 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_7991;
473 break;
474 case IWL_AMSDU_12K:
475 vht_cap->cap |= IEEE80211_VHT_CAP_MAX_MPDU_LENGTH_11454;
476 break;
477 default:
478 break;
479 }
480
481 vht_cap->vht_mcs.rx_mcs_map =
482 cpu_to_le16(IEEE80211_VHT_MCS_SUPPORT_0_9 << 0 |
483 IEEE80211_VHT_MCS_SUPPORT_0_9 << 2 |
484 IEEE80211_VHT_MCS_NOT_SUPPORTED << 4 |
485 IEEE80211_VHT_MCS_NOT_SUPPORTED << 6 |
486 IEEE80211_VHT_MCS_NOT_SUPPORTED << 8 |
487 IEEE80211_VHT_MCS_NOT_SUPPORTED << 10 |
488 IEEE80211_VHT_MCS_NOT_SUPPORTED << 12 |
489 IEEE80211_VHT_MCS_NOT_SUPPORTED << 14);
490
491 if (num_rx_ants == 1 || cfg->rx_with_siso_diversity) {
492 vht_cap->cap |= IEEE80211_VHT_CAP_RX_ANTENNA_PATTERN;
493 /* this works because NOT_SUPPORTED == 3 */
494 vht_cap->vht_mcs.rx_mcs_map |=
495 cpu_to_le16(IEEE80211_VHT_MCS_NOT_SUPPORTED << 2);
496 }
497
498 vht_cap->vht_mcs.tx_mcs_map = vht_cap->vht_mcs.rx_mcs_map;
499 }
500
501 static struct ieee80211_sband_iftype_data iwl_he_capa = {
502 .types_mask = BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP),
503 .he_cap = {
504 .has_he = true,
505 .he_cap_elem = {
506 .mac_cap_info[0] =
507 IEEE80211_HE_MAC_CAP0_HTC_HE,
508 .mac_cap_info[1] =
509 IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US |
510 IEEE80211_HE_MAC_CAP1_MULTI_TID_AGG_QOS_8,
511 .mac_cap_info[2] =
512 IEEE80211_HE_MAC_CAP2_32BIT_BA_BITMAP |
513 IEEE80211_HE_MAC_CAP2_ACK_EN,
514 .mac_cap_info[3] =
515 IEEE80211_HE_MAC_CAP3_GRP_ADDR_MULTI_STA_BA_DL_MU |
516 IEEE80211_HE_MAC_CAP3_MAX_A_AMPDU_LEN_EXP_VHT_2,
517 .mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_AMDSU_IN_AMPDU,
518 .phy_cap_info[0] =
519 IEEE80211_HE_PHY_CAP0_DUAL_BAND |
520 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G |
521 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G |
522 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G,
523 .phy_cap_info[1] =
524 IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
525 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
526 IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_MAX_NSTS,
527 .phy_cap_info[2] =
528 IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
529 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
530 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ,
531 .phy_cap_info[3] =
532 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_BPSK |
533 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_1 |
534 IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_BPSK |
535 IEEE80211_HE_PHY_CAP3_DCM_MAX_RX_NSS_1,
536 .phy_cap_info[4] =
537 IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
538 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_8 |
539 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_8,
540 .phy_cap_info[5] =
541 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_UNDER_80MHZ_2 |
542 IEEE80211_HE_PHY_CAP5_BEAMFORMEE_NUM_SND_DIM_ABOVE_80MHZ_2,
543 .phy_cap_info[6] =
544 IEEE80211_HE_PHY_CAP6_PPE_THRESHOLD_PRESENT,
545 .phy_cap_info[7] =
546 IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_AR |
547 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
548 IEEE80211_HE_PHY_CAP7_MAX_NC_7,
549 .phy_cap_info[8] =
550 IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
551 IEEE80211_HE_PHY_CAP8_20MHZ_IN_40MHZ_HE_PPDU_IN_2G |
552 IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
553 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU,
554 },
555 /*
556 * Set default Tx/Rx HE MCS NSS Support field. Indicate support
557 * for up to 2 spatial streams and all MCS, without any special
558 * cases
559 */
560 .he_mcs_nss_supp = {
561 .rx_mcs_80 = cpu_to_le16(0xfffa),
562 .tx_mcs_80 = cpu_to_le16(0xfffa),
563 .rx_mcs_160 = cpu_to_le16(0xfffa),
564 .tx_mcs_160 = cpu_to_le16(0xfffa),
565 .rx_mcs_80p80 = cpu_to_le16(0xffff),
566 .tx_mcs_80p80 = cpu_to_le16(0xffff),
567 },
568 /*
569 * Set default PPE thresholds, with PPET16 set to 0, PPET8 set
570 * to 7
571 */
572 .ppe_thres = {0x61, 0x1c, 0xc7, 0x71},
573 },
574 };
575
iwl_init_he_hw_capab(struct ieee80211_supported_band * sband,u8 tx_chains,u8 rx_chains)576 static void iwl_init_he_hw_capab(struct ieee80211_supported_band *sband,
577 u8 tx_chains, u8 rx_chains)
578 {
579 if (sband->band == NL80211_BAND_2GHZ ||
580 sband->band == NL80211_BAND_5GHZ)
581 sband->iftype_data = &iwl_he_capa;
582 else
583 return;
584
585 sband->n_iftype_data = 1;
586
587 /* If not 2x2, we need to indicate 1x1 in the Midamble RX Max NSTS */
588 if ((tx_chains & rx_chains) != ANT_AB) {
589 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[1] &=
590 ~IEEE80211_HE_PHY_CAP1_MIDAMBLE_RX_MAX_NSTS;
591 iwl_he_capa.he_cap.he_cap_elem.phy_cap_info[2] &=
592 ~IEEE80211_HE_PHY_CAP2_MIDAMBLE_RX_MAX_NSTS;
593 }
594 }
595
iwl_init_sbands(struct device * dev,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * nvm_ch_flags,u8 tx_chains,u8 rx_chains,u32 sbands_flags)596 static void iwl_init_sbands(struct device *dev, const struct iwl_cfg *cfg,
597 struct iwl_nvm_data *data,
598 const __le16 *nvm_ch_flags, u8 tx_chains,
599 u8 rx_chains, u32 sbands_flags)
600 {
601 int n_channels;
602 int n_used = 0;
603 struct ieee80211_supported_band *sband;
604
605 n_channels = iwl_init_channel_map(dev, cfg, data, nvm_ch_flags,
606 sbands_flags);
607 sband = &data->bands[NL80211_BAND_2GHZ];
608 sband->band = NL80211_BAND_2GHZ;
609 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS];
610 sband->n_bitrates = N_RATES_24;
611 n_used += iwl_init_sband_channels(data, sband, n_channels,
612 NL80211_BAND_2GHZ);
613 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_2GHZ,
614 tx_chains, rx_chains);
615
616 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
617 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
618
619 sband = &data->bands[NL80211_BAND_5GHZ];
620 sband->band = NL80211_BAND_5GHZ;
621 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS];
622 sband->n_bitrates = N_RATES_52;
623 n_used += iwl_init_sband_channels(data, sband, n_channels,
624 NL80211_BAND_5GHZ);
625 iwl_init_ht_hw_capab(cfg, data, &sband->ht_cap, NL80211_BAND_5GHZ,
626 tx_chains, rx_chains);
627 if (data->sku_cap_11ac_enable && !iwlwifi_mod_params.disable_11ac)
628 iwl_init_vht_hw_capab(cfg, data, &sband->vht_cap,
629 tx_chains, rx_chains);
630
631 if (data->sku_cap_11ax_enable && !iwlwifi_mod_params.disable_11ax)
632 iwl_init_he_hw_capab(sband, tx_chains, rx_chains);
633
634 if (n_channels != n_used)
635 IWL_ERR_DEV(dev, "NVM: used only %d of %d channels\n",
636 n_used, n_channels);
637 }
638
iwl_get_sku(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)639 static int iwl_get_sku(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
640 const __le16 *phy_sku)
641 {
642 if (cfg->nvm_type != IWL_NVM_EXT)
643 return le16_to_cpup(nvm_sw + SKU);
644
645 return le32_to_cpup((__le32 *)(phy_sku + SKU_FAMILY_8000));
646 }
647
iwl_get_nvm_version(const struct iwl_cfg * cfg,const __le16 * nvm_sw)648 static int iwl_get_nvm_version(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
649 {
650 if (cfg->nvm_type != IWL_NVM_EXT)
651 return le16_to_cpup(nvm_sw + NVM_VERSION);
652 else
653 return le32_to_cpup((__le32 *)(nvm_sw +
654 NVM_VERSION_EXT_NVM));
655 }
656
iwl_get_radio_cfg(const struct iwl_cfg * cfg,const __le16 * nvm_sw,const __le16 * phy_sku)657 static int iwl_get_radio_cfg(const struct iwl_cfg *cfg, const __le16 *nvm_sw,
658 const __le16 *phy_sku)
659 {
660 if (cfg->nvm_type != IWL_NVM_EXT)
661 return le16_to_cpup(nvm_sw + RADIO_CFG);
662
663 return le32_to_cpup((__le32 *)(phy_sku + RADIO_CFG_FAMILY_EXT_NVM));
664
665 }
666
iwl_get_n_hw_addrs(const struct iwl_cfg * cfg,const __le16 * nvm_sw)667 static int iwl_get_n_hw_addrs(const struct iwl_cfg *cfg, const __le16 *nvm_sw)
668 {
669 int n_hw_addr;
670
671 if (cfg->nvm_type != IWL_NVM_EXT)
672 return le16_to_cpup(nvm_sw + N_HW_ADDRS);
673
674 n_hw_addr = le32_to_cpup((__le32 *)(nvm_sw + N_HW_ADDRS_FAMILY_8000));
675
676 return n_hw_addr & N_HW_ADDR_MASK;
677 }
678
iwl_set_radio_cfg(const struct iwl_cfg * cfg,struct iwl_nvm_data * data,u32 radio_cfg)679 static void iwl_set_radio_cfg(const struct iwl_cfg *cfg,
680 struct iwl_nvm_data *data,
681 u32 radio_cfg)
682 {
683 if (cfg->nvm_type != IWL_NVM_EXT) {
684 data->radio_cfg_type = NVM_RF_CFG_TYPE_MSK(radio_cfg);
685 data->radio_cfg_step = NVM_RF_CFG_STEP_MSK(radio_cfg);
686 data->radio_cfg_dash = NVM_RF_CFG_DASH_MSK(radio_cfg);
687 data->radio_cfg_pnum = NVM_RF_CFG_PNUM_MSK(radio_cfg);
688 return;
689 }
690
691 /* set the radio configuration for family 8000 */
692 data->radio_cfg_type = EXT_NVM_RF_CFG_TYPE_MSK(radio_cfg);
693 data->radio_cfg_step = EXT_NVM_RF_CFG_STEP_MSK(radio_cfg);
694 data->radio_cfg_dash = EXT_NVM_RF_CFG_DASH_MSK(radio_cfg);
695 data->radio_cfg_pnum = EXT_NVM_RF_CFG_FLAVOR_MSK(radio_cfg);
696 data->valid_tx_ant = EXT_NVM_RF_CFG_TX_ANT_MSK(radio_cfg);
697 data->valid_rx_ant = EXT_NVM_RF_CFG_RX_ANT_MSK(radio_cfg);
698 }
699
iwl_flip_hw_address(__le32 mac_addr0,__le32 mac_addr1,u8 * dest)700 static void iwl_flip_hw_address(__le32 mac_addr0, __le32 mac_addr1, u8 *dest)
701 {
702 const u8 *hw_addr;
703
704 hw_addr = (const u8 *)&mac_addr0;
705 dest[0] = hw_addr[3];
706 dest[1] = hw_addr[2];
707 dest[2] = hw_addr[1];
708 dest[3] = hw_addr[0];
709
710 hw_addr = (const u8 *)&mac_addr1;
711 dest[4] = hw_addr[1];
712 dest[5] = hw_addr[0];
713 }
714
iwl_set_hw_address_from_csr(struct iwl_trans * trans,struct iwl_nvm_data * data)715 static void iwl_set_hw_address_from_csr(struct iwl_trans *trans,
716 struct iwl_nvm_data *data)
717 {
718 __le32 mac_addr0 =
719 cpu_to_le32(iwl_read32(trans,
720 trans->cfg->csr->mac_addr0_strap));
721 __le32 mac_addr1 =
722 cpu_to_le32(iwl_read32(trans,
723 trans->cfg->csr->mac_addr1_strap));
724
725 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
726 /*
727 * If the OEM fused a valid address, use it instead of the one in the
728 * OTP
729 */
730 if (is_valid_ether_addr(data->hw_addr))
731 return;
732
733 mac_addr0 = cpu_to_le32(iwl_read32(trans,
734 trans->cfg->csr->mac_addr0_otp));
735 mac_addr1 = cpu_to_le32(iwl_read32(trans,
736 trans->cfg->csr->mac_addr1_otp));
737
738 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
739 }
740
iwl_set_hw_address_family_8000(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __le16 * mac_override,const __be16 * nvm_hw)741 static void iwl_set_hw_address_family_8000(struct iwl_trans *trans,
742 const struct iwl_cfg *cfg,
743 struct iwl_nvm_data *data,
744 const __le16 *mac_override,
745 const __be16 *nvm_hw)
746 {
747 const u8 *hw_addr;
748
749 if (mac_override) {
750 static const u8 reserved_mac[] = {
751 0x02, 0xcc, 0xaa, 0xff, 0xee, 0x00
752 };
753
754 hw_addr = (const u8 *)(mac_override +
755 MAC_ADDRESS_OVERRIDE_EXT_NVM);
756
757 /*
758 * Store the MAC address from MAO section.
759 * No byte swapping is required in MAO section
760 */
761 memcpy(data->hw_addr, hw_addr, ETH_ALEN);
762
763 /*
764 * Force the use of the OTP MAC address in case of reserved MAC
765 * address in the NVM, or if address is given but invalid.
766 */
767 if (is_valid_ether_addr(data->hw_addr) &&
768 memcmp(reserved_mac, hw_addr, ETH_ALEN) != 0)
769 return;
770
771 IWL_ERR(trans,
772 "mac address from nvm override section is not valid\n");
773 }
774
775 if (nvm_hw) {
776 /* read the mac address from WFMP registers */
777 __le32 mac_addr0 = cpu_to_le32(iwl_trans_read_prph(trans,
778 WFMP_MAC_ADDR_0));
779 __le32 mac_addr1 = cpu_to_le32(iwl_trans_read_prph(trans,
780 WFMP_MAC_ADDR_1));
781
782 iwl_flip_hw_address(mac_addr0, mac_addr1, data->hw_addr);
783
784 return;
785 }
786
787 IWL_ERR(trans, "mac address is not found\n");
788 }
789
iwl_set_hw_address(struct iwl_trans * trans,const struct iwl_cfg * cfg,struct iwl_nvm_data * data,const __be16 * nvm_hw,const __le16 * mac_override)790 static int iwl_set_hw_address(struct iwl_trans *trans,
791 const struct iwl_cfg *cfg,
792 struct iwl_nvm_data *data, const __be16 *nvm_hw,
793 const __le16 *mac_override)
794 {
795 if (cfg->mac_addr_from_csr) {
796 iwl_set_hw_address_from_csr(trans, data);
797 } else if (cfg->nvm_type != IWL_NVM_EXT) {
798 const u8 *hw_addr = (const u8 *)(nvm_hw + HW_ADDR);
799
800 /* The byte order is little endian 16 bit, meaning 214365 */
801 data->hw_addr[0] = hw_addr[1];
802 data->hw_addr[1] = hw_addr[0];
803 data->hw_addr[2] = hw_addr[3];
804 data->hw_addr[3] = hw_addr[2];
805 data->hw_addr[4] = hw_addr[5];
806 data->hw_addr[5] = hw_addr[4];
807 } else {
808 iwl_set_hw_address_family_8000(trans, cfg, data,
809 mac_override, nvm_hw);
810 }
811
812 if (!is_valid_ether_addr(data->hw_addr)) {
813 IWL_ERR(trans, "no valid mac address was found\n");
814 return -EINVAL;
815 }
816
817 IWL_INFO(trans, "base HW address: %pM\n", data->hw_addr);
818
819 return 0;
820 }
821
822 static bool
iwl_nvm_no_wide_in_5ghz(struct device * dev,const struct iwl_cfg * cfg,const __be16 * nvm_hw)823 iwl_nvm_no_wide_in_5ghz(struct device *dev, const struct iwl_cfg *cfg,
824 const __be16 *nvm_hw)
825 {
826 /*
827 * Workaround a bug in Indonesia SKUs where the regulatory in
828 * some 7000-family OTPs erroneously allow wide channels in
829 * 5GHz. To check for Indonesia, we take the SKU value from
830 * bits 1-4 in the subsystem ID and check if it is either 5 or
831 * 9. In those cases, we need to force-disable wide channels
832 * in 5GHz otherwise the FW will throw a sysassert when we try
833 * to use them.
834 */
835 if (cfg->device_family == IWL_DEVICE_FAMILY_7000) {
836 /*
837 * Unlike the other sections in the NVM, the hw
838 * section uses big-endian.
839 */
840 u16 subsystem_id = be16_to_cpup(nvm_hw + SUBSYSTEM_ID);
841 u8 sku = (subsystem_id & 0x1e) >> 1;
842
843 if (sku == 5 || sku == 9) {
844 IWL_DEBUG_EEPROM(dev,
845 "disabling wide channels in 5GHz (0x%0x %d)\n",
846 subsystem_id, sku);
847 return true;
848 }
849 }
850
851 return false;
852 }
853
854 struct iwl_nvm_data *
iwl_parse_nvm_data(struct iwl_trans * trans,const struct iwl_cfg * cfg,const __be16 * nvm_hw,const __le16 * nvm_sw,const __le16 * nvm_calib,const __le16 * regulatory,const __le16 * mac_override,const __le16 * phy_sku,u8 tx_chains,u8 rx_chains,bool lar_fw_supported)855 iwl_parse_nvm_data(struct iwl_trans *trans, const struct iwl_cfg *cfg,
856 const __be16 *nvm_hw, const __le16 *nvm_sw,
857 const __le16 *nvm_calib, const __le16 *regulatory,
858 const __le16 *mac_override, const __le16 *phy_sku,
859 u8 tx_chains, u8 rx_chains, bool lar_fw_supported)
860 {
861 struct device *dev = trans->dev;
862 struct iwl_nvm_data *data;
863 bool lar_enabled;
864 u32 sku, radio_cfg;
865 u32 sbands_flags = 0;
866 u16 lar_config;
867 const __le16 *ch_section;
868
869 if (cfg->nvm_type != IWL_NVM_EXT)
870 data = kzalloc(sizeof(*data) +
871 sizeof(struct ieee80211_channel) *
872 IWL_NVM_NUM_CHANNELS,
873 GFP_KERNEL);
874 else
875 data = kzalloc(sizeof(*data) +
876 sizeof(struct ieee80211_channel) *
877 IWL_NVM_NUM_CHANNELS_EXT,
878 GFP_KERNEL);
879 if (!data)
880 return NULL;
881
882 data->nvm_version = iwl_get_nvm_version(cfg, nvm_sw);
883
884 radio_cfg = iwl_get_radio_cfg(cfg, nvm_sw, phy_sku);
885 iwl_set_radio_cfg(cfg, data, radio_cfg);
886 if (data->valid_tx_ant)
887 tx_chains &= data->valid_tx_ant;
888 if (data->valid_rx_ant)
889 rx_chains &= data->valid_rx_ant;
890
891 sku = iwl_get_sku(cfg, nvm_sw, phy_sku);
892 data->sku_cap_band_24ghz_enable = sku & NVM_SKU_CAP_BAND_24GHZ;
893 data->sku_cap_band_52ghz_enable = sku & NVM_SKU_CAP_BAND_52GHZ;
894 data->sku_cap_11n_enable = sku & NVM_SKU_CAP_11N_ENABLE;
895 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL)
896 data->sku_cap_11n_enable = false;
897 data->sku_cap_11ac_enable = data->sku_cap_11n_enable &&
898 (sku & NVM_SKU_CAP_11AC_ENABLE);
899 data->sku_cap_mimo_disabled = sku & NVM_SKU_CAP_MIMO_DISABLE;
900
901 data->n_hw_addrs = iwl_get_n_hw_addrs(cfg, nvm_sw);
902
903 if (cfg->nvm_type != IWL_NVM_EXT) {
904 /* Checking for required sections */
905 if (!nvm_calib) {
906 IWL_ERR(trans,
907 "Can't parse empty Calib NVM sections\n");
908 kfree(data);
909 return NULL;
910 }
911
912 ch_section = cfg->nvm_type == IWL_NVM_SDP ?
913 ®ulatory[NVM_CHANNELS_SDP] :
914 &nvm_sw[NVM_CHANNELS];
915
916 /* in family 8000 Xtal calibration values moved to OTP */
917 data->xtal_calib[0] = *(nvm_calib + XTAL_CALIB);
918 data->xtal_calib[1] = *(nvm_calib + XTAL_CALIB + 1);
919 lar_enabled = true;
920 } else {
921 u16 lar_offset = data->nvm_version < 0xE39 ?
922 NVM_LAR_OFFSET_OLD :
923 NVM_LAR_OFFSET;
924
925 lar_config = le16_to_cpup(regulatory + lar_offset);
926 data->lar_enabled = !!(lar_config &
927 NVM_LAR_ENABLED);
928 lar_enabled = data->lar_enabled;
929 ch_section = ®ulatory[NVM_CHANNELS_EXTENDED];
930 }
931
932 /* If no valid mac address was found - bail out */
933 if (iwl_set_hw_address(trans, cfg, data, nvm_hw, mac_override)) {
934 kfree(data);
935 return NULL;
936 }
937
938 if (lar_fw_supported && lar_enabled)
939 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
940
941 if (iwl_nvm_no_wide_in_5ghz(dev, cfg, nvm_hw))
942 sbands_flags |= IWL_NVM_SBANDS_FLAGS_NO_WIDE_IN_5GHZ;
943
944 iwl_init_sbands(dev, cfg, data, ch_section, tx_chains, rx_chains,
945 sbands_flags);
946 data->calib_version = 255;
947
948 return data;
949 }
950 IWL_EXPORT_SYMBOL(iwl_parse_nvm_data);
951
iwl_nvm_get_regdom_bw_flags(const u8 * nvm_chan,int ch_idx,u16 nvm_flags,u16 cap_flags,const struct iwl_cfg * cfg)952 static u32 iwl_nvm_get_regdom_bw_flags(const u8 *nvm_chan,
953 int ch_idx, u16 nvm_flags,
954 u16 cap_flags,
955 const struct iwl_cfg *cfg)
956 {
957 u32 flags = NL80211_RRF_NO_HT40;
958 u32 last_5ghz_ht = LAST_5GHZ_HT;
959
960 if (cfg->nvm_type == IWL_NVM_EXT)
961 last_5ghz_ht = LAST_5GHZ_HT_FAMILY_8000;
962
963 if (ch_idx < NUM_2GHZ_CHANNELS &&
964 (nvm_flags & NVM_CHANNEL_40MHZ)) {
965 if (nvm_chan[ch_idx] <= LAST_2GHZ_HT_PLUS)
966 flags &= ~NL80211_RRF_NO_HT40PLUS;
967 if (nvm_chan[ch_idx] >= FIRST_2GHZ_HT_MINUS)
968 flags &= ~NL80211_RRF_NO_HT40MINUS;
969 } else if (nvm_chan[ch_idx] <= last_5ghz_ht &&
970 (nvm_flags & NVM_CHANNEL_40MHZ)) {
971 if ((ch_idx - NUM_2GHZ_CHANNELS) % 2 == 0)
972 flags &= ~NL80211_RRF_NO_HT40PLUS;
973 else
974 flags &= ~NL80211_RRF_NO_HT40MINUS;
975 }
976
977 if (!(nvm_flags & NVM_CHANNEL_80MHZ))
978 flags |= NL80211_RRF_NO_80MHZ;
979 if (!(nvm_flags & NVM_CHANNEL_160MHZ))
980 flags |= NL80211_RRF_NO_160MHZ;
981
982 if (!(nvm_flags & NVM_CHANNEL_ACTIVE))
983 flags |= NL80211_RRF_NO_IR;
984
985 if (nvm_flags & NVM_CHANNEL_RADAR)
986 flags |= NL80211_RRF_DFS;
987
988 if (nvm_flags & NVM_CHANNEL_INDOOR_ONLY)
989 flags |= NL80211_RRF_NO_OUTDOOR;
990
991 /* Set the GO concurrent flag only in case that NO_IR is set.
992 * Otherwise it is meaningless
993 */
994 if ((nvm_flags & NVM_CHANNEL_GO_CONCURRENT) &&
995 (flags & NL80211_RRF_NO_IR))
996 flags |= NL80211_RRF_GO_CONCURRENT;
997
998 /*
999 * cap_flags is per regulatory domain so apply it for every channel
1000 */
1001 if (ch_idx >= NUM_2GHZ_CHANNELS) {
1002 if (cap_flags & REG_CAPA_40MHZ_FORBIDDEN)
1003 flags |= NL80211_RRF_NO_HT40;
1004
1005 if (!(cap_flags & REG_CAPA_80MHZ_ALLOWED))
1006 flags |= NL80211_RRF_NO_80MHZ;
1007
1008 if (!(cap_flags & REG_CAPA_160MHZ_ALLOWED))
1009 flags |= NL80211_RRF_NO_160MHZ;
1010 }
1011
1012 return flags;
1013 }
1014
1015 struct regdb_ptrs {
1016 struct ieee80211_wmm_rule *rule;
1017 u32 token;
1018 };
1019
1020 struct ieee80211_regdomain *
iwl_parse_nvm_mcc_info(struct device * dev,const struct iwl_cfg * cfg,int num_of_ch,__le32 * channels,u16 fw_mcc,u16 geo_info,u16 cap)1021 iwl_parse_nvm_mcc_info(struct device *dev, const struct iwl_cfg *cfg,
1022 int num_of_ch, __le32 *channels, u16 fw_mcc,
1023 u16 geo_info, u16 cap)
1024 {
1025 int ch_idx;
1026 u16 ch_flags;
1027 u32 reg_rule_flags, prev_reg_rule_flags = 0;
1028 const u8 *nvm_chan = cfg->nvm_type == IWL_NVM_EXT ?
1029 iwl_ext_nvm_channels : iwl_nvm_channels;
1030 struct ieee80211_regdomain *regd, *copy_rd;
1031 int size_of_regd, regd_to_copy;
1032 struct ieee80211_reg_rule *rule;
1033 struct regdb_ptrs *regdb_ptrs;
1034 enum nl80211_band band;
1035 int center_freq, prev_center_freq = 0;
1036 int valid_rules = 0;
1037 bool new_rule;
1038 int max_num_ch = cfg->nvm_type == IWL_NVM_EXT ?
1039 IWL_NVM_NUM_CHANNELS_EXT : IWL_NVM_NUM_CHANNELS;
1040
1041 if (WARN_ON_ONCE(num_of_ch > NL80211_MAX_SUPP_REG_RULES))
1042 return ERR_PTR(-EINVAL);
1043
1044 if (WARN_ON(num_of_ch > max_num_ch))
1045 num_of_ch = max_num_ch;
1046
1047 IWL_DEBUG_DEV(dev, IWL_DL_LAR, "building regdom for %d channels\n",
1048 num_of_ch);
1049
1050 /* build a regdomain rule for every valid channel */
1051 size_of_regd =
1052 sizeof(struct ieee80211_regdomain) +
1053 num_of_ch * sizeof(struct ieee80211_reg_rule);
1054
1055 regd = kzalloc(size_of_regd, GFP_KERNEL);
1056 if (!regd)
1057 return ERR_PTR(-ENOMEM);
1058
1059 regdb_ptrs = kcalloc(num_of_ch, sizeof(*regdb_ptrs), GFP_KERNEL);
1060 if (!regdb_ptrs) {
1061 copy_rd = ERR_PTR(-ENOMEM);
1062 goto out;
1063 }
1064
1065 /* set alpha2 from FW. */
1066 regd->alpha2[0] = fw_mcc >> 8;
1067 regd->alpha2[1] = fw_mcc & 0xff;
1068
1069 for (ch_idx = 0; ch_idx < num_of_ch; ch_idx++) {
1070 ch_flags = (u16)__le32_to_cpup(channels + ch_idx);
1071 band = (ch_idx < NUM_2GHZ_CHANNELS) ?
1072 NL80211_BAND_2GHZ : NL80211_BAND_5GHZ;
1073 center_freq = ieee80211_channel_to_frequency(nvm_chan[ch_idx],
1074 band);
1075 new_rule = false;
1076
1077 if (!(ch_flags & NVM_CHANNEL_VALID)) {
1078 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1079 nvm_chan[ch_idx], ch_flags);
1080 continue;
1081 }
1082
1083 reg_rule_flags = iwl_nvm_get_regdom_bw_flags(nvm_chan, ch_idx,
1084 ch_flags, cap,
1085 cfg);
1086
1087 /* we can't continue the same rule */
1088 if (ch_idx == 0 || prev_reg_rule_flags != reg_rule_flags ||
1089 center_freq - prev_center_freq > 20) {
1090 valid_rules++;
1091 new_rule = true;
1092 }
1093
1094 rule = ®d->reg_rules[valid_rules - 1];
1095
1096 if (new_rule)
1097 rule->freq_range.start_freq_khz =
1098 MHZ_TO_KHZ(center_freq - 10);
1099
1100 rule->freq_range.end_freq_khz = MHZ_TO_KHZ(center_freq + 10);
1101
1102 /* this doesn't matter - not used by FW */
1103 rule->power_rule.max_antenna_gain = DBI_TO_MBI(6);
1104 rule->power_rule.max_eirp =
1105 DBM_TO_MBM(IWL_DEFAULT_MAX_TX_POWER);
1106
1107 rule->flags = reg_rule_flags;
1108
1109 /* rely on auto-calculation to merge BW of contiguous chans */
1110 rule->flags |= NL80211_RRF_AUTO_BW;
1111 rule->freq_range.max_bandwidth_khz = 0;
1112
1113 prev_center_freq = center_freq;
1114 prev_reg_rule_flags = reg_rule_flags;
1115
1116 iwl_nvm_print_channel_flags(dev, IWL_DL_LAR,
1117 nvm_chan[ch_idx], ch_flags);
1118
1119 if (!(geo_info & GEO_WMM_ETSI_5GHZ_INFO) ||
1120 band == NL80211_BAND_2GHZ)
1121 continue;
1122
1123 reg_query_regdb_wmm(regd->alpha2, center_freq, rule);
1124 }
1125
1126 regd->n_reg_rules = valid_rules;
1127
1128 /*
1129 * Narrow down regdom for unused regulatory rules to prevent hole
1130 * between reg rules to wmm rules.
1131 */
1132 regd_to_copy = sizeof(struct ieee80211_regdomain) +
1133 valid_rules * sizeof(struct ieee80211_reg_rule);
1134
1135 copy_rd = kzalloc(regd_to_copy, GFP_KERNEL);
1136 if (!copy_rd) {
1137 copy_rd = ERR_PTR(-ENOMEM);
1138 goto out;
1139 }
1140
1141 memcpy(copy_rd, regd, regd_to_copy);
1142
1143 out:
1144 kfree(regdb_ptrs);
1145 kfree(regd);
1146 return copy_rd;
1147 }
1148 IWL_EXPORT_SYMBOL(iwl_parse_nvm_mcc_info);
1149
1150 #define IWL_MAX_NVM_SECTION_SIZE 0x1b58
1151 #define IWL_MAX_EXT_NVM_SECTION_SIZE 0x1ffc
1152 #define MAX_NVM_FILE_LEN 16384
1153
iwl_nvm_fixups(u32 hw_id,unsigned int section,u8 * data,unsigned int len)1154 void iwl_nvm_fixups(u32 hw_id, unsigned int section, u8 *data,
1155 unsigned int len)
1156 {
1157 #define IWL_4165_DEVICE_ID 0x5501
1158 #define NVM_SKU_CAP_MIMO_DISABLE BIT(5)
1159
1160 if (section == NVM_SECTION_TYPE_PHY_SKU &&
1161 hw_id == IWL_4165_DEVICE_ID && data && len >= 5 &&
1162 (data[4] & NVM_SKU_CAP_MIMO_DISABLE))
1163 /* OTP 0x52 bug work around: it's a 1x1 device */
1164 data[3] = ANT_B | (ANT_B << 4);
1165 }
1166 IWL_EXPORT_SYMBOL(iwl_nvm_fixups);
1167
1168 /*
1169 * Reads external NVM from a file into mvm->nvm_sections
1170 *
1171 * HOW TO CREATE THE NVM FILE FORMAT:
1172 * ------------------------------
1173 * 1. create hex file, format:
1174 * 3800 -> header
1175 * 0000 -> header
1176 * 5a40 -> data
1177 *
1178 * rev - 6 bit (word1)
1179 * len - 10 bit (word1)
1180 * id - 4 bit (word2)
1181 * rsv - 12 bit (word2)
1182 *
1183 * 2. flip 8bits with 8 bits per line to get the right NVM file format
1184 *
1185 * 3. create binary file from the hex file
1186 *
1187 * 4. save as "iNVM_xxx.bin" under /lib/firmware
1188 */
iwl_read_external_nvm(struct iwl_trans * trans,const char * nvm_file_name,struct iwl_nvm_section * nvm_sections)1189 int iwl_read_external_nvm(struct iwl_trans *trans,
1190 const char *nvm_file_name,
1191 struct iwl_nvm_section *nvm_sections)
1192 {
1193 int ret, section_size;
1194 u16 section_id;
1195 const struct firmware *fw_entry;
1196 const struct {
1197 __le16 word1;
1198 __le16 word2;
1199 u8 data[];
1200 } *file_sec;
1201 const u8 *eof;
1202 u8 *temp;
1203 int max_section_size;
1204 const __le32 *dword_buff;
1205
1206 #define NVM_WORD1_LEN(x) (8 * (x & 0x03FF))
1207 #define NVM_WORD2_ID(x) (x >> 12)
1208 #define EXT_NVM_WORD2_LEN(x) (2 * (((x) & 0xFF) << 8 | (x) >> 8))
1209 #define EXT_NVM_WORD1_ID(x) ((x) >> 4)
1210 #define NVM_HEADER_0 (0x2A504C54)
1211 #define NVM_HEADER_1 (0x4E564D2A)
1212 #define NVM_HEADER_SIZE (4 * sizeof(u32))
1213
1214 IWL_DEBUG_EEPROM(trans->dev, "Read from external NVM\n");
1215
1216 /* Maximal size depends on NVM version */
1217 if (trans->cfg->nvm_type != IWL_NVM_EXT)
1218 max_section_size = IWL_MAX_NVM_SECTION_SIZE;
1219 else
1220 max_section_size = IWL_MAX_EXT_NVM_SECTION_SIZE;
1221
1222 /*
1223 * Obtain NVM image via request_firmware. Since we already used
1224 * request_firmware_nowait() for the firmware binary load and only
1225 * get here after that we assume the NVM request can be satisfied
1226 * synchronously.
1227 */
1228 ret = request_firmware(&fw_entry, nvm_file_name, trans->dev);
1229 if (ret) {
1230 IWL_ERR(trans, "ERROR: %s isn't available %d\n",
1231 nvm_file_name, ret);
1232 return ret;
1233 }
1234
1235 IWL_INFO(trans, "Loaded NVM file %s (%zu bytes)\n",
1236 nvm_file_name, fw_entry->size);
1237
1238 if (fw_entry->size > MAX_NVM_FILE_LEN) {
1239 IWL_ERR(trans, "NVM file too large\n");
1240 ret = -EINVAL;
1241 goto out;
1242 }
1243
1244 eof = fw_entry->data + fw_entry->size;
1245 dword_buff = (__le32 *)fw_entry->data;
1246
1247 /* some NVM file will contain a header.
1248 * The header is identified by 2 dwords header as follow:
1249 * dword[0] = 0x2A504C54
1250 * dword[1] = 0x4E564D2A
1251 *
1252 * This header must be skipped when providing the NVM data to the FW.
1253 */
1254 if (fw_entry->size > NVM_HEADER_SIZE &&
1255 dword_buff[0] == cpu_to_le32(NVM_HEADER_0) &&
1256 dword_buff[1] == cpu_to_le32(NVM_HEADER_1)) {
1257 file_sec = (void *)(fw_entry->data + NVM_HEADER_SIZE);
1258 IWL_INFO(trans, "NVM Version %08X\n", le32_to_cpu(dword_buff[2]));
1259 IWL_INFO(trans, "NVM Manufacturing date %08X\n",
1260 le32_to_cpu(dword_buff[3]));
1261
1262 /* nvm file validation, dword_buff[2] holds the file version */
1263 if (trans->cfg->device_family == IWL_DEVICE_FAMILY_8000 &&
1264 CSR_HW_REV_STEP(trans->hw_rev) == SILICON_C_STEP &&
1265 le32_to_cpu(dword_buff[2]) < 0xE4A) {
1266 ret = -EFAULT;
1267 goto out;
1268 }
1269 } else {
1270 file_sec = (void *)fw_entry->data;
1271 }
1272
1273 while (true) {
1274 if (file_sec->data > eof) {
1275 IWL_ERR(trans,
1276 "ERROR - NVM file too short for section header\n");
1277 ret = -EINVAL;
1278 break;
1279 }
1280
1281 /* check for EOF marker */
1282 if (!file_sec->word1 && !file_sec->word2) {
1283 ret = 0;
1284 break;
1285 }
1286
1287 if (trans->cfg->nvm_type != IWL_NVM_EXT) {
1288 section_size =
1289 2 * NVM_WORD1_LEN(le16_to_cpu(file_sec->word1));
1290 section_id = NVM_WORD2_ID(le16_to_cpu(file_sec->word2));
1291 } else {
1292 section_size = 2 * EXT_NVM_WORD2_LEN(
1293 le16_to_cpu(file_sec->word2));
1294 section_id = EXT_NVM_WORD1_ID(
1295 le16_to_cpu(file_sec->word1));
1296 }
1297
1298 if (section_size > max_section_size) {
1299 IWL_ERR(trans, "ERROR - section too large (%d)\n",
1300 section_size);
1301 ret = -EINVAL;
1302 break;
1303 }
1304
1305 if (!section_size) {
1306 IWL_ERR(trans, "ERROR - section empty\n");
1307 ret = -EINVAL;
1308 break;
1309 }
1310
1311 if (file_sec->data + section_size > eof) {
1312 IWL_ERR(trans,
1313 "ERROR - NVM file too short for section (%d bytes)\n",
1314 section_size);
1315 ret = -EINVAL;
1316 break;
1317 }
1318
1319 if (WARN(section_id >= NVM_MAX_NUM_SECTIONS,
1320 "Invalid NVM section ID %d\n", section_id)) {
1321 ret = -EINVAL;
1322 break;
1323 }
1324
1325 temp = kmemdup(file_sec->data, section_size, GFP_KERNEL);
1326 if (!temp) {
1327 ret = -ENOMEM;
1328 break;
1329 }
1330
1331 iwl_nvm_fixups(trans->hw_id, section_id, temp, section_size);
1332
1333 kfree(nvm_sections[section_id].data);
1334 nvm_sections[section_id].data = temp;
1335 nvm_sections[section_id].length = section_size;
1336
1337 /* advance to the next section */
1338 file_sec = (void *)(file_sec->data + section_size);
1339 }
1340 out:
1341 release_firmware(fw_entry);
1342 return ret;
1343 }
1344 IWL_EXPORT_SYMBOL(iwl_read_external_nvm);
1345
iwl_get_nvm(struct iwl_trans * trans,const struct iwl_fw * fw)1346 struct iwl_nvm_data *iwl_get_nvm(struct iwl_trans *trans,
1347 const struct iwl_fw *fw)
1348 {
1349 struct iwl_nvm_get_info cmd = {};
1350 struct iwl_nvm_get_info_rsp *rsp;
1351 struct iwl_nvm_data *nvm;
1352 struct iwl_host_cmd hcmd = {
1353 .flags = CMD_WANT_SKB | CMD_SEND_IN_RFKILL,
1354 .data = { &cmd, },
1355 .len = { sizeof(cmd) },
1356 .id = WIDE_ID(REGULATORY_AND_NVM_GROUP, NVM_GET_INFO)
1357 };
1358 int ret;
1359 bool lar_fw_supported = !iwlwifi_mod_params.lar_disable &&
1360 fw_has_capa(&fw->ucode_capa,
1361 IWL_UCODE_TLV_CAPA_LAR_SUPPORT);
1362 bool empty_otp;
1363 u32 mac_flags;
1364 u32 sbands_flags = 0;
1365
1366 ret = iwl_trans_send_cmd(trans, &hcmd);
1367 if (ret)
1368 return ERR_PTR(ret);
1369
1370 if (WARN(iwl_rx_packet_payload_len(hcmd.resp_pkt) != sizeof(*rsp),
1371 "Invalid payload len in NVM response from FW %d",
1372 iwl_rx_packet_payload_len(hcmd.resp_pkt))) {
1373 ret = -EINVAL;
1374 goto out;
1375 }
1376
1377 rsp = (void *)hcmd.resp_pkt->data;
1378 empty_otp = !!(le32_to_cpu(rsp->general.flags) &
1379 NVM_GENERAL_FLAGS_EMPTY_OTP);
1380 if (empty_otp)
1381 IWL_INFO(trans, "OTP is empty\n");
1382
1383 nvm = kzalloc(sizeof(*nvm) +
1384 sizeof(struct ieee80211_channel) * IWL_NUM_CHANNELS,
1385 GFP_KERNEL);
1386 if (!nvm) {
1387 ret = -ENOMEM;
1388 goto out;
1389 }
1390
1391 iwl_set_hw_address_from_csr(trans, nvm);
1392 /* TODO: if platform NVM has MAC address - override it here */
1393
1394 if (!is_valid_ether_addr(nvm->hw_addr)) {
1395 IWL_ERR(trans, "no valid mac address was found\n");
1396 ret = -EINVAL;
1397 goto err_free;
1398 }
1399
1400 IWL_INFO(trans, "base HW address: %pM\n", nvm->hw_addr);
1401
1402 /* Initialize general data */
1403 nvm->nvm_version = le16_to_cpu(rsp->general.nvm_version);
1404 nvm->n_hw_addrs = rsp->general.n_hw_addrs;
1405 if (nvm->n_hw_addrs == 0)
1406 IWL_WARN(trans,
1407 "Firmware declares no reserved mac addresses. OTP is empty: %d\n",
1408 empty_otp);
1409
1410 /* Initialize MAC sku data */
1411 mac_flags = le32_to_cpu(rsp->mac_sku.mac_sku_flags);
1412 nvm->sku_cap_11ac_enable =
1413 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AC_ENABLED);
1414 nvm->sku_cap_11n_enable =
1415 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11N_ENABLED);
1416 nvm->sku_cap_11ax_enable =
1417 !!(mac_flags & NVM_MAC_SKU_FLAGS_802_11AX_ENABLED);
1418 nvm->sku_cap_band_24ghz_enable =
1419 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_2_4_ENABLED);
1420 nvm->sku_cap_band_52ghz_enable =
1421 !!(mac_flags & NVM_MAC_SKU_FLAGS_BAND_5_2_ENABLED);
1422 nvm->sku_cap_mimo_disabled =
1423 !!(mac_flags & NVM_MAC_SKU_FLAGS_MIMO_DISABLED);
1424
1425 /* Initialize PHY sku data */
1426 nvm->valid_tx_ant = (u8)le32_to_cpu(rsp->phy_sku.tx_chains);
1427 nvm->valid_rx_ant = (u8)le32_to_cpu(rsp->phy_sku.rx_chains);
1428
1429 if (le32_to_cpu(rsp->regulatory.lar_enabled) && lar_fw_supported) {
1430 nvm->lar_enabled = true;
1431 sbands_flags |= IWL_NVM_SBANDS_FLAGS_LAR;
1432 }
1433
1434 iwl_init_sbands(trans->dev, trans->cfg, nvm,
1435 rsp->regulatory.channel_profile,
1436 nvm->valid_tx_ant & fw->valid_tx_ant,
1437 nvm->valid_rx_ant & fw->valid_rx_ant,
1438 sbands_flags);
1439
1440 iwl_free_resp(&hcmd);
1441 return nvm;
1442
1443 err_free:
1444 kfree(nvm);
1445 out:
1446 iwl_free_resp(&hcmd);
1447 return ERR_PTR(ret);
1448 }
1449 IWL_EXPORT_SYMBOL(iwl_get_nvm);
1450