1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #include "wifi.h"
27 #include "core.h"
28 #include "pci.h"
29 #include "base.h"
30 #include "ps.h"
31 #include "efuse.h"
32 #include <linux/interrupt.h>
33 #include <linux/export.h>
34 #include <linux/module.h>
35
36 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
37 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
38 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
39 MODULE_LICENSE("GPL");
40 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
41
42 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
43 INTEL_VENDOR_ID,
44 ATI_VENDOR_ID,
45 AMD_VENDOR_ID,
46 SIS_VENDOR_ID
47 };
48
49 static const u8 ac_to_hwq[] = {
50 VO_QUEUE,
51 VI_QUEUE,
52 BE_QUEUE,
53 BK_QUEUE
54 };
55
_rtl_mac_to_hwqueue(struct ieee80211_hw * hw,struct sk_buff * skb)56 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw, struct sk_buff *skb)
57 {
58 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
59 __le16 fc = rtl_get_fc(skb);
60 u8 queue_index = skb_get_queue_mapping(skb);
61 struct ieee80211_hdr *hdr;
62
63 if (unlikely(ieee80211_is_beacon(fc)))
64 return BEACON_QUEUE;
65 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
66 return MGNT_QUEUE;
67 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
68 if (ieee80211_is_nullfunc(fc))
69 return HIGH_QUEUE;
70 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
71 hdr = rtl_get_hdr(skb);
72
73 if (is_multicast_ether_addr(hdr->addr1) ||
74 is_broadcast_ether_addr(hdr->addr1))
75 return HIGH_QUEUE;
76 }
77
78 return ac_to_hwq[queue_index];
79 }
80
81 /* Update PCI dependent default settings*/
_rtl_pci_update_default_setting(struct ieee80211_hw * hw)82 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
83 {
84 struct rtl_priv *rtlpriv = rtl_priv(hw);
85 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
86 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
87 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
88 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
89 u8 init_aspm;
90
91 ppsc->reg_rfps_level = 0;
92 ppsc->support_aspm = false;
93
94 /*Update PCI ASPM setting */
95 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
96 switch (rtlpci->const_pci_aspm) {
97 case 0:
98 /*No ASPM */
99 break;
100
101 case 1:
102 /*ASPM dynamically enabled/disable. */
103 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
104 break;
105
106 case 2:
107 /*ASPM with Clock Req dynamically enabled/disable. */
108 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
109 RT_RF_OFF_LEVL_CLK_REQ);
110 break;
111
112 case 3:
113 /* Always enable ASPM and Clock Req
114 * from initialization to halt.
115 */
116 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
117 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
118 RT_RF_OFF_LEVL_CLK_REQ);
119 break;
120
121 case 4:
122 /* Always enable ASPM without Clock Req
123 * from initialization to halt.
124 */
125 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
126 RT_RF_OFF_LEVL_CLK_REQ);
127 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
128 break;
129 }
130
131 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
132
133 /*Update Radio OFF setting */
134 switch (rtlpci->const_hwsw_rfoff_d3) {
135 case 1:
136 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
137 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
138 break;
139
140 case 2:
141 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
143 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
144 break;
145
146 case 3:
147 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
148 break;
149 }
150
151 /*Set HW definition to determine if it supports ASPM. */
152 switch (rtlpci->const_support_pciaspm) {
153 case 0:
154 /*Not support ASPM. */
155 ppsc->support_aspm = false;
156 break;
157 case 1:
158 /*Support ASPM. */
159 ppsc->support_aspm = true;
160 ppsc->support_backdoor = true;
161 break;
162 case 2:
163 /*ASPM value set by chipset. */
164 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
165 ppsc->support_aspm = true;
166 break;
167 default:
168 pr_err("switch case %#x not processed\n",
169 rtlpci->const_support_pciaspm);
170 break;
171 }
172
173 /* toshiba aspm issue, toshiba will set aspm selfly
174 * so we should not set aspm in driver
175 */
176 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
177 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
178 init_aspm == 0x43)
179 ppsc->support_aspm = false;
180 }
181
_rtl_pci_platform_switch_device_pci_aspm(struct ieee80211_hw * hw,u8 value)182 static bool _rtl_pci_platform_switch_device_pci_aspm(
183 struct ieee80211_hw *hw,
184 u8 value)
185 {
186 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
187 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
188
189 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
190 value |= 0x40;
191
192 pci_write_config_byte(rtlpci->pdev, 0x80, value);
193
194 return false;
195 }
196
197 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
_rtl_pci_switch_clk_req(struct ieee80211_hw * hw,u8 value)198 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
199 {
200 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
201 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
202
203 pci_write_config_byte(rtlpci->pdev, 0x81, value);
204
205 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
206 udelay(100);
207 }
208
209 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
rtl_pci_disable_aspm(struct ieee80211_hw * hw)210 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
211 {
212 struct rtl_priv *rtlpriv = rtl_priv(hw);
213 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
214 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
215 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
216 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
217 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
218 /*Retrieve original configuration settings. */
219 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
220 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
221 pcibridge_linkctrlreg;
222 u16 aspmlevel = 0;
223 u8 tmp_u1b = 0;
224
225 if (!ppsc->support_aspm)
226 return;
227
228 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
229 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
230 "PCI(Bridge) UNKNOWN\n");
231
232 return;
233 }
234
235 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
236 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
237 _rtl_pci_switch_clk_req(hw, 0x0);
238 }
239
240 /*for promising device will in L0 state after an I/O. */
241 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
242
243 /*Set corresponding value. */
244 aspmlevel |= BIT(0) | BIT(1);
245 linkctrl_reg &= ~aspmlevel;
246 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
247
248 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
249 udelay(50);
250
251 /*4 Disable Pci Bridge ASPM */
252 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
253 pcibridge_linkctrlreg);
254
255 udelay(50);
256 }
257
258 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
259 *power saving We should follow the sequence to enable
260 *RTL8192SE first then enable Pci Bridge ASPM
261 *or the system will show bluescreen.
262 */
rtl_pci_enable_aspm(struct ieee80211_hw * hw)263 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
264 {
265 struct rtl_priv *rtlpriv = rtl_priv(hw);
266 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
267 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
268 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
269 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
270 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
271 u16 aspmlevel;
272 u8 u_pcibridge_aspmsetting;
273 u8 u_device_aspmsetting;
274
275 if (!ppsc->support_aspm)
276 return;
277
278 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
279 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
280 "PCI(Bridge) UNKNOWN\n");
281 return;
282 }
283
284 /*4 Enable Pci Bridge ASPM */
285
286 u_pcibridge_aspmsetting =
287 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
288 rtlpci->const_hostpci_aspm_setting;
289
290 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
291 u_pcibridge_aspmsetting &= ~BIT(0);
292
293 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
294 u_pcibridge_aspmsetting);
295
296 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
297 "PlatformEnableASPM(): Write reg[%x] = %x\n",
298 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
299 u_pcibridge_aspmsetting);
300
301 udelay(50);
302
303 /*Get ASPM level (with/without Clock Req) */
304 aspmlevel = rtlpci->const_devicepci_aspm_setting;
305 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
306
307 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
308 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
309
310 u_device_aspmsetting |= aspmlevel;
311
312 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
313
314 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
315 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
316 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
317 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
318 }
319 udelay(100);
320 }
321
rtl_pci_get_amd_l1_patch(struct ieee80211_hw * hw)322 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
323 {
324 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
325
326 bool status = false;
327 u8 offset_e0;
328 unsigned int offset_e4;
329
330 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
331
332 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
333
334 if (offset_e0 == 0xA0) {
335 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
336 if (offset_e4 & BIT(23))
337 status = true;
338 }
339
340 return status;
341 }
342
rtl_pci_check_buddy_priv(struct ieee80211_hw * hw,struct rtl_priv ** buddy_priv)343 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
344 struct rtl_priv **buddy_priv)
345 {
346 struct rtl_priv *rtlpriv = rtl_priv(hw);
347 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
348 bool find_buddy_priv = false;
349 struct rtl_priv *tpriv;
350 struct rtl_pci_priv *tpcipriv = NULL;
351
352 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
353 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
354 list) {
355 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
356 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
357 "pcipriv->ndis_adapter.funcnumber %x\n",
358 pcipriv->ndis_adapter.funcnumber);
359 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
360 "tpcipriv->ndis_adapter.funcnumber %x\n",
361 tpcipriv->ndis_adapter.funcnumber);
362
363 if (pcipriv->ndis_adapter.busnumber ==
364 tpcipriv->ndis_adapter.busnumber &&
365 pcipriv->ndis_adapter.devnumber ==
366 tpcipriv->ndis_adapter.devnumber &&
367 pcipriv->ndis_adapter.funcnumber !=
368 tpcipriv->ndis_adapter.funcnumber) {
369 find_buddy_priv = true;
370 break;
371 }
372 }
373 }
374
375 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
376 "find_buddy_priv %d\n", find_buddy_priv);
377
378 if (find_buddy_priv)
379 *buddy_priv = tpriv;
380
381 return find_buddy_priv;
382 }
383
rtl_pci_get_linkcontrol_field(struct ieee80211_hw * hw)384 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
385 {
386 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
387 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
388 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
389 u8 linkctrl_reg;
390 u8 num4bbytes;
391
392 num4bbytes = (capabilityoffset + 0x10) / 4;
393
394 /*Read Link Control Register */
395 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
396
397 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
398 }
399
rtl_pci_parse_configuration(struct pci_dev * pdev,struct ieee80211_hw * hw)400 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
401 struct ieee80211_hw *hw)
402 {
403 struct rtl_priv *rtlpriv = rtl_priv(hw);
404 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
405
406 u8 tmp;
407 u16 linkctrl_reg;
408
409 /*Link Control Register */
410 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
411 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
412
413 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
414 pcipriv->ndis_adapter.linkctrl_reg);
415
416 pci_read_config_byte(pdev, 0x98, &tmp);
417 tmp |= BIT(4);
418 pci_write_config_byte(pdev, 0x98, tmp);
419
420 tmp = 0x17;
421 pci_write_config_byte(pdev, 0x70f, tmp);
422 }
423
rtl_pci_init_aspm(struct ieee80211_hw * hw)424 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
425 {
426 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
427
428 _rtl_pci_update_default_setting(hw);
429
430 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
431 /*Always enable ASPM & Clock Req. */
432 rtl_pci_enable_aspm(hw);
433 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
434 }
435 }
436
_rtl_pci_io_handler_init(struct device * dev,struct ieee80211_hw * hw)437 static void _rtl_pci_io_handler_init(struct device *dev,
438 struct ieee80211_hw *hw)
439 {
440 struct rtl_priv *rtlpriv = rtl_priv(hw);
441
442 rtlpriv->io.dev = dev;
443
444 rtlpriv->io.write8_async = pci_write8_async;
445 rtlpriv->io.write16_async = pci_write16_async;
446 rtlpriv->io.write32_async = pci_write32_async;
447
448 rtlpriv->io.read8_sync = pci_read8_sync;
449 rtlpriv->io.read16_sync = pci_read16_sync;
450 rtlpriv->io.read32_sync = pci_read32_sync;
451 }
452
_rtl_update_earlymode_info(struct ieee80211_hw * hw,struct sk_buff * skb,struct rtl_tcb_desc * tcb_desc,u8 tid)453 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
454 struct sk_buff *skb,
455 struct rtl_tcb_desc *tcb_desc, u8 tid)
456 {
457 struct rtl_priv *rtlpriv = rtl_priv(hw);
458 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
459 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
460 struct sk_buff *next_skb;
461 u8 additionlen = FCS_LEN;
462
463 /* here open is 4, wep/tkip is 8, aes is 12*/
464 if (info->control.hw_key)
465 additionlen += info->control.hw_key->icv_len;
466
467 /* The most skb num is 6 */
468 tcb_desc->empkt_num = 0;
469 spin_lock_bh(&rtlpriv->locks.waitq_lock);
470 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
471 struct ieee80211_tx_info *next_info;
472
473 next_info = IEEE80211_SKB_CB(next_skb);
474 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
475 tcb_desc->empkt_len[tcb_desc->empkt_num] =
476 next_skb->len + additionlen;
477 tcb_desc->empkt_num++;
478 } else {
479 break;
480 }
481
482 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
483 next_skb))
484 break;
485
486 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
487 break;
488 }
489 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
490
491 return true;
492 }
493
494 /* just for early mode now */
_rtl_pci_tx_chk_waitq(struct ieee80211_hw * hw)495 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
496 {
497 struct rtl_priv *rtlpriv = rtl_priv(hw);
498 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
499 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
500 struct sk_buff *skb = NULL;
501 struct ieee80211_tx_info *info = NULL;
502 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
503 int tid;
504
505 if (!rtlpriv->rtlhal.earlymode_enable)
506 return;
507
508 if (rtlpriv->dm.supp_phymode_switch &&
509 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
510 (rtlpriv->buddy_priv &&
511 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
512 return;
513 /* we just use em for BE/BK/VI/VO */
514 for (tid = 7; tid >= 0; tid--) {
515 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
516 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
517
518 while (!mac->act_scanning &&
519 rtlpriv->psc.rfpwr_state == ERFON) {
520 struct rtl_tcb_desc tcb_desc;
521
522 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
523
524 spin_lock_bh(&rtlpriv->locks.waitq_lock);
525 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
526 (ring->entries - skb_queue_len(&ring->queue) >
527 rtlhal->max_earlymode_num)) {
528 skb = skb_dequeue(&mac->skb_waitq[tid]);
529 } else {
530 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
531 break;
532 }
533 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
534
535 /* Some macaddr can't do early mode. like
536 * multicast/broadcast/no_qos data
537 */
538 info = IEEE80211_SKB_CB(skb);
539 if (info->flags & IEEE80211_TX_CTL_AMPDU)
540 _rtl_update_earlymode_info(hw, skb,
541 &tcb_desc, tid);
542
543 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
544 }
545 }
546 }
547
_rtl_pci_tx_isr(struct ieee80211_hw * hw,int prio)548 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
549 {
550 struct rtl_priv *rtlpriv = rtl_priv(hw);
551 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
552
553 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
554
555 while (skb_queue_len(&ring->queue)) {
556 struct sk_buff *skb;
557 struct ieee80211_tx_info *info;
558 __le16 fc;
559 u8 tid;
560 u8 *entry;
561
562 if (rtlpriv->use_new_trx_flow)
563 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
564 else
565 entry = (u8 *)(&ring->desc[ring->idx]);
566
567 if (!rtlpriv->cfg->ops->is_tx_desc_closed(hw, prio, ring->idx))
568 return;
569 ring->idx = (ring->idx + 1) % ring->entries;
570
571 skb = __skb_dequeue(&ring->queue);
572 pci_unmap_single(rtlpci->pdev,
573 rtlpriv->cfg->ops->
574 get_desc(hw, (u8 *)entry, true,
575 HW_DESC_TXBUFF_ADDR),
576 skb->len, PCI_DMA_TODEVICE);
577
578 /* remove early mode header */
579 if (rtlpriv->rtlhal.earlymode_enable)
580 skb_pull(skb, EM_HDR_LEN);
581
582 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
583 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
584 ring->idx,
585 skb_queue_len(&ring->queue),
586 *(u16 *)(skb->data + 22));
587
588 if (prio == TXCMD_QUEUE) {
589 dev_kfree_skb(skb);
590 goto tx_status_ok;
591 }
592
593 /* for sw LPS, just after NULL skb send out, we can
594 * sure AP knows we are sleeping, we should not let
595 * rf sleep
596 */
597 fc = rtl_get_fc(skb);
598 if (ieee80211_is_nullfunc(fc)) {
599 if (ieee80211_has_pm(fc)) {
600 rtlpriv->mac80211.offchan_delay = true;
601 rtlpriv->psc.state_inap = true;
602 } else {
603 rtlpriv->psc.state_inap = false;
604 }
605 }
606 if (ieee80211_is_action(fc)) {
607 struct ieee80211_mgmt *action_frame =
608 (struct ieee80211_mgmt *)skb->data;
609 if (action_frame->u.action.u.ht_smps.action ==
610 WLAN_HT_ACTION_SMPS) {
611 dev_kfree_skb(skb);
612 goto tx_status_ok;
613 }
614 }
615
616 /* update tid tx pkt num */
617 tid = rtl_get_tid(skb);
618 if (tid <= 7)
619 rtlpriv->link_info.tidtx_inperiod[tid]++;
620
621 info = IEEE80211_SKB_CB(skb);
622
623 if (likely(!ieee80211_is_nullfunc(fc))) {
624 ieee80211_tx_info_clear_status(info);
625 info->flags |= IEEE80211_TX_STAT_ACK;
626 /*info->status.rates[0].count = 1; */
627 ieee80211_tx_status_irqsafe(hw, skb);
628 } else {
629 rtl_tx_ackqueue(hw, skb);
630 }
631
632 if ((ring->entries - skb_queue_len(&ring->queue)) <= 4) {
633 RT_TRACE(rtlpriv, COMP_ERR, DBG_DMESG,
634 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%x\n",
635 prio, ring->idx,
636 skb_queue_len(&ring->queue));
637
638 ieee80211_wake_queue(hw, skb_get_queue_mapping(skb));
639 }
640 tx_status_ok:
641 skb = NULL;
642 }
643
644 if (((rtlpriv->link_info.num_rx_inperiod +
645 rtlpriv->link_info.num_tx_inperiod) > 8) ||
646 rtlpriv->link_info.num_rx_inperiod > 2)
647 rtl_lps_leave(hw);
648 }
649
_rtl_pci_init_one_rxdesc(struct ieee80211_hw * hw,struct sk_buff * new_skb,u8 * entry,int rxring_idx,int desc_idx)650 static int _rtl_pci_init_one_rxdesc(struct ieee80211_hw *hw,
651 struct sk_buff *new_skb, u8 *entry,
652 int rxring_idx, int desc_idx)
653 {
654 struct rtl_priv *rtlpriv = rtl_priv(hw);
655 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
656 u32 bufferaddress;
657 u8 tmp_one = 1;
658 struct sk_buff *skb;
659
660 if (likely(new_skb)) {
661 skb = new_skb;
662 goto remap;
663 }
664 skb = dev_alloc_skb(rtlpci->rxbuffersize);
665 if (!skb)
666 return 0;
667
668 remap:
669 /* just set skb->cb to mapping addr for pci_unmap_single use */
670 *((dma_addr_t *)skb->cb) =
671 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
672 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
673 bufferaddress = *((dma_addr_t *)skb->cb);
674 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
675 return 0;
676 rtlpci->rx_ring[rxring_idx].rx_buf[desc_idx] = skb;
677 if (rtlpriv->use_new_trx_flow) {
678 /* skb->cb may be 64 bit address */
679 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
680 HW_DESC_RX_PREPARE,
681 (u8 *)(dma_addr_t *)skb->cb);
682 } else {
683 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
684 HW_DESC_RXBUFF_ADDR,
685 (u8 *)&bufferaddress);
686 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
687 HW_DESC_RXPKT_LEN,
688 (u8 *)&rtlpci->rxbuffersize);
689 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
690 HW_DESC_RXOWN,
691 (u8 *)&tmp_one);
692 }
693 return 1;
694 }
695
696 /* inorder to receive 8K AMSDU we have set skb to
697 * 9100bytes in init rx ring, but if this packet is
698 * not a AMSDU, this large packet will be sent to
699 * TCP/IP directly, this cause big packet ping fail
700 * like: "ping -s 65507", so here we will realloc skb
701 * based on the true size of packet, Mac80211
702 * Probably will do it better, but does not yet.
703 *
704 * Some platform will fail when alloc skb sometimes.
705 * in this condition, we will send the old skb to
706 * mac80211 directly, this will not cause any other
707 * issues, but only this packet will be lost by TCP/IP
708 */
_rtl_pci_rx_to_mac80211(struct ieee80211_hw * hw,struct sk_buff * skb,struct ieee80211_rx_status rx_status)709 static void _rtl_pci_rx_to_mac80211(struct ieee80211_hw *hw,
710 struct sk_buff *skb,
711 struct ieee80211_rx_status rx_status)
712 {
713 if (unlikely(!rtl_action_proc(hw, skb, false))) {
714 dev_kfree_skb_any(skb);
715 } else {
716 struct sk_buff *uskb = NULL;
717
718 uskb = dev_alloc_skb(skb->len + 128);
719 if (likely(uskb)) {
720 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status,
721 sizeof(rx_status));
722 skb_put_data(uskb, skb->data, skb->len);
723 dev_kfree_skb_any(skb);
724 ieee80211_rx_irqsafe(hw, uskb);
725 } else {
726 ieee80211_rx_irqsafe(hw, skb);
727 }
728 }
729 }
730
731 /*hsisr interrupt handler*/
_rtl_pci_hs_interrupt(struct ieee80211_hw * hw)732 static void _rtl_pci_hs_interrupt(struct ieee80211_hw *hw)
733 {
734 struct rtl_priv *rtlpriv = rtl_priv(hw);
735 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
736
737 rtl_write_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR],
738 rtl_read_byte(rtlpriv, rtlpriv->cfg->maps[MAC_HSISR]) |
739 rtlpci->sys_irq_mask);
740 }
741
_rtl_pci_rx_interrupt(struct ieee80211_hw * hw)742 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
743 {
744 struct rtl_priv *rtlpriv = rtl_priv(hw);
745 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
746 int rxring_idx = RTL_PCI_RX_MPDU_QUEUE;
747 struct ieee80211_rx_status rx_status = { 0 };
748 unsigned int count = rtlpci->rxringcount;
749 u8 own;
750 u8 tmp_one;
751 bool unicast = false;
752 u8 hw_queue = 0;
753 unsigned int rx_remained_cnt = 0;
754 struct rtl_stats stats = {
755 .signal = 0,
756 .rate = 0,
757 };
758
759 /*RX NORMAL PKT */
760 while (count--) {
761 struct ieee80211_hdr *hdr;
762 __le16 fc;
763 u16 len;
764 /*rx buffer descriptor */
765 struct rtl_rx_buffer_desc *buffer_desc = NULL;
766 /*if use new trx flow, it means wifi info */
767 struct rtl_rx_desc *pdesc = NULL;
768 /*rx pkt */
769 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[
770 rtlpci->rx_ring[rxring_idx].idx];
771 struct sk_buff *new_skb;
772
773 if (rtlpriv->use_new_trx_flow) {
774 if (rx_remained_cnt == 0)
775 rx_remained_cnt =
776 rtlpriv->cfg->ops->rx_desc_buff_remained_cnt(hw,
777 hw_queue);
778 if (rx_remained_cnt == 0)
779 return;
780 buffer_desc = &rtlpci->rx_ring[rxring_idx].buffer_desc[
781 rtlpci->rx_ring[rxring_idx].idx];
782 pdesc = (struct rtl_rx_desc *)skb->data;
783 } else { /* rx descriptor */
784 pdesc = &rtlpci->rx_ring[rxring_idx].desc[
785 rtlpci->rx_ring[rxring_idx].idx];
786
787 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
788 false,
789 HW_DESC_OWN);
790 if (own) /* wait data to be filled by hardware */
791 return;
792 }
793
794 /* Reaching this point means: data is filled already
795 * AAAAAAttention !!!
796 * We can NOT access 'skb' before 'pci_unmap_single'
797 */
798 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
799 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
800
801 /* get a new skb - if fail, old one will be reused */
802 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
803 if (unlikely(!new_skb))
804 goto no_new;
805 memset(&rx_status, 0, sizeof(rx_status));
806 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
807 &rx_status, (u8 *)pdesc, skb);
808
809 if (rtlpriv->use_new_trx_flow)
810 rtlpriv->cfg->ops->rx_check_dma_ok(hw,
811 (u8 *)buffer_desc,
812 hw_queue);
813
814 len = rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc, false,
815 HW_DESC_RXPKT_LEN);
816
817 if (skb->end - skb->tail > len) {
818 skb_put(skb, len);
819 if (rtlpriv->use_new_trx_flow)
820 skb_reserve(skb, stats.rx_drvinfo_size +
821 stats.rx_bufshift + 24);
822 else
823 skb_reserve(skb, stats.rx_drvinfo_size +
824 stats.rx_bufshift);
825 } else {
826 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
827 "skb->end - skb->tail = %d, len is %d\n",
828 skb->end - skb->tail, len);
829 dev_kfree_skb_any(skb);
830 goto new_trx_end;
831 }
832 /* handle command packet here */
833 if (stats.packet_report_type == C2H_PACKET) {
834 rtl_c2hcmd_enqueue(hw, skb);
835 goto new_trx_end;
836 }
837
838 /* NOTICE This can not be use for mac80211,
839 * this is done in mac80211 code,
840 * if done here sec DHCP will fail
841 * skb_trim(skb, skb->len - 4);
842 */
843
844 hdr = rtl_get_hdr(skb);
845 fc = rtl_get_fc(skb);
846
847 if (!stats.crc && !stats.hwerror) {
848 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status,
849 sizeof(rx_status));
850
851 if (is_broadcast_ether_addr(hdr->addr1)) {
852 ;/*TODO*/
853 } else if (is_multicast_ether_addr(hdr->addr1)) {
854 ;/*TODO*/
855 } else {
856 unicast = true;
857 rtlpriv->stats.rxbytesunicast += skb->len;
858 }
859 rtl_is_special_data(hw, skb, false, true);
860
861 if (ieee80211_is_data(fc)) {
862 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
863 if (unicast)
864 rtlpriv->link_info.num_rx_inperiod++;
865 }
866
867 rtl_collect_scan_list(hw, skb);
868
869 /* static bcn for roaming */
870 rtl_beacon_statistic(hw, skb);
871 rtl_p2p_info(hw, (void *)skb->data, skb->len);
872 /* for sw lps */
873 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
874 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
875 if (rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP &&
876 rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G &&
877 (ieee80211_is_beacon(fc) ||
878 ieee80211_is_probe_resp(fc))) {
879 dev_kfree_skb_any(skb);
880 } else {
881 _rtl_pci_rx_to_mac80211(hw, skb, rx_status);
882 }
883 } else {
884 dev_kfree_skb_any(skb);
885 }
886 new_trx_end:
887 if (rtlpriv->use_new_trx_flow) {
888 rtlpci->rx_ring[hw_queue].next_rx_rp += 1;
889 rtlpci->rx_ring[hw_queue].next_rx_rp %=
890 RTL_PCI_MAX_RX_COUNT;
891
892 rx_remained_cnt--;
893 rtl_write_word(rtlpriv, 0x3B4,
894 rtlpci->rx_ring[hw_queue].next_rx_rp);
895 }
896 if (((rtlpriv->link_info.num_rx_inperiod +
897 rtlpriv->link_info.num_tx_inperiod) > 8) ||
898 rtlpriv->link_info.num_rx_inperiod > 2)
899 rtl_lps_leave(hw);
900 skb = new_skb;
901 no_new:
902 if (rtlpriv->use_new_trx_flow) {
903 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)buffer_desc,
904 rxring_idx,
905 rtlpci->rx_ring[rxring_idx].idx);
906 } else {
907 _rtl_pci_init_one_rxdesc(hw, skb, (u8 *)pdesc,
908 rxring_idx,
909 rtlpci->rx_ring[rxring_idx].idx);
910 if (rtlpci->rx_ring[rxring_idx].idx ==
911 rtlpci->rxringcount - 1)
912 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc,
913 false,
914 HW_DESC_RXERO,
915 (u8 *)&tmp_one);
916 }
917 rtlpci->rx_ring[rxring_idx].idx =
918 (rtlpci->rx_ring[rxring_idx].idx + 1) %
919 rtlpci->rxringcount;
920 }
921 }
922
_rtl_pci_interrupt(int irq,void * dev_id)923 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
924 {
925 struct ieee80211_hw *hw = dev_id;
926 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
927 struct rtl_priv *rtlpriv = rtl_priv(hw);
928 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
929 unsigned long flags;
930 struct rtl_int intvec = {0};
931
932 irqreturn_t ret = IRQ_HANDLED;
933
934 if (rtlpci->irq_enabled == 0)
935 return ret;
936
937 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
938 rtlpriv->cfg->ops->disable_interrupt(hw);
939
940 /*read ISR: 4/8bytes */
941 rtlpriv->cfg->ops->interrupt_recognized(hw, &intvec);
942
943 /*Shared IRQ or HW disappeared */
944 if (!intvec.inta || intvec.inta == 0xffff)
945 goto done;
946
947 /*<1> beacon related */
948 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK])
949 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
950 "beacon ok interrupt!\n");
951
952 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_TBDER]))
953 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
954 "beacon err interrupt!\n");
955
956 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BDOK])
957 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
958
959 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
960 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
961 "prepare beacon for interrupt!\n");
962 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
963 }
964
965 /*<2> Tx related */
966 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
967 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
968
969 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
970 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
971 "Manage ok interrupt!\n");
972 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
973 }
974
975 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
976 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
977 "HIGH_QUEUE ok interrupt!\n");
978 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
979 }
980
981 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
982 rtlpriv->link_info.num_tx_inperiod++;
983
984 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
985 "BK Tx OK interrupt!\n");
986 _rtl_pci_tx_isr(hw, BK_QUEUE);
987 }
988
989 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
990 rtlpriv->link_info.num_tx_inperiod++;
991
992 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
993 "BE TX OK interrupt!\n");
994 _rtl_pci_tx_isr(hw, BE_QUEUE);
995 }
996
997 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
998 rtlpriv->link_info.num_tx_inperiod++;
999
1000 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1001 "VI TX OK interrupt!\n");
1002 _rtl_pci_tx_isr(hw, VI_QUEUE);
1003 }
1004
1005 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
1006 rtlpriv->link_info.num_tx_inperiod++;
1007
1008 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1009 "Vo TX OK interrupt!\n");
1010 _rtl_pci_tx_isr(hw, VO_QUEUE);
1011 }
1012
1013 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE) {
1014 if (intvec.intd & rtlpriv->cfg->maps[RTL_IMR_H2CDOK]) {
1015 rtlpriv->link_info.num_tx_inperiod++;
1016
1017 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1018 "H2C TX OK interrupt!\n");
1019 _rtl_pci_tx_isr(hw, H2C_QUEUE);
1020 }
1021 }
1022
1023 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
1024 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
1025 rtlpriv->link_info.num_tx_inperiod++;
1026
1027 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1028 "CMD TX OK interrupt!\n");
1029 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
1030 }
1031 }
1032
1033 /*<3> Rx related */
1034 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
1035 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
1036 _rtl_pci_rx_interrupt(hw);
1037 }
1038
1039 if (unlikely(intvec.inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
1040 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1041 "rx descriptor unavailable!\n");
1042 _rtl_pci_rx_interrupt(hw);
1043 }
1044
1045 if (unlikely(intvec.intb & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
1046 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
1047 _rtl_pci_rx_interrupt(hw);
1048 }
1049
1050 /*<4> fw related*/
1051 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
1052 if (intvec.inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
1053 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1054 "firmware interrupt!\n");
1055 queue_delayed_work(rtlpriv->works.rtl_wq,
1056 &rtlpriv->works.fwevt_wq, 0);
1057 }
1058 }
1059
1060 /*<5> hsisr related*/
1061 /* Only 8188EE & 8723BE Supported.
1062 * If Other ICs Come in, System will corrupt,
1063 * because maps[RTL_IMR_HSISR_IND] & maps[MAC_HSISR]
1064 * are not initialized
1065 */
1066 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8188EE ||
1067 rtlhal->hw_type == HARDWARE_TYPE_RTL8723BE) {
1068 if (unlikely(intvec.inta &
1069 rtlpriv->cfg->maps[RTL_IMR_HSISR_IND])) {
1070 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
1071 "hsisr interrupt!\n");
1072 _rtl_pci_hs_interrupt(hw);
1073 }
1074 }
1075
1076 if (rtlpriv->rtlhal.earlymode_enable)
1077 tasklet_schedule(&rtlpriv->works.irq_tasklet);
1078
1079 done:
1080 rtlpriv->cfg->ops->enable_interrupt(hw);
1081 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1082 return ret;
1083 }
1084
_rtl_pci_irq_tasklet(unsigned long data)1085 static void _rtl_pci_irq_tasklet(unsigned long data)
1086 {
1087 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1088 _rtl_pci_tx_chk_waitq(hw);
1089 }
1090
_rtl_pci_prepare_bcn_tasklet(unsigned long data)1091 static void _rtl_pci_prepare_bcn_tasklet(unsigned long data)
1092 {
1093 struct ieee80211_hw *hw = (struct ieee80211_hw *)data;
1094 struct rtl_priv *rtlpriv = rtl_priv(hw);
1095 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1096 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1097 struct rtl8192_tx_ring *ring = NULL;
1098 struct ieee80211_hdr *hdr = NULL;
1099 struct ieee80211_tx_info *info = NULL;
1100 struct sk_buff *pskb = NULL;
1101 struct rtl_tx_desc *pdesc = NULL;
1102 struct rtl_tcb_desc tcb_desc;
1103 /*This is for new trx flow*/
1104 struct rtl_tx_buffer_desc *pbuffer_desc = NULL;
1105 u8 temp_one = 1;
1106 u8 *entry;
1107
1108 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
1109 ring = &rtlpci->tx_ring[BEACON_QUEUE];
1110 pskb = __skb_dequeue(&ring->queue);
1111 if (rtlpriv->use_new_trx_flow)
1112 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1113 else
1114 entry = (u8 *)(&ring->desc[ring->idx]);
1115 if (pskb) {
1116 pci_unmap_single(rtlpci->pdev,
1117 rtlpriv->cfg->ops->get_desc(
1118 hw, (u8 *)entry, true, HW_DESC_TXBUFF_ADDR),
1119 pskb->len, PCI_DMA_TODEVICE);
1120 kfree_skb(pskb);
1121 }
1122
1123 /*NB: the beacon data buffer must be 32-bit aligned. */
1124 pskb = ieee80211_beacon_get(hw, mac->vif);
1125 if (!pskb)
1126 return;
1127 hdr = rtl_get_hdr(pskb);
1128 info = IEEE80211_SKB_CB(pskb);
1129 pdesc = &ring->desc[0];
1130 if (rtlpriv->use_new_trx_flow)
1131 pbuffer_desc = &ring->buffer_desc[0];
1132
1133 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1134 (u8 *)pbuffer_desc, info, NULL, pskb,
1135 BEACON_QUEUE, &tcb_desc);
1136
1137 __skb_queue_tail(&ring->queue, pskb);
1138
1139 if (rtlpriv->use_new_trx_flow) {
1140 temp_one = 4;
1141 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pbuffer_desc, true,
1142 HW_DESC_OWN, (u8 *)&temp_one);
1143 } else {
1144 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true, HW_DESC_OWN,
1145 &temp_one);
1146 }
1147 }
1148
_rtl_pci_init_trx_var(struct ieee80211_hw * hw)1149 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1150 {
1151 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1152 struct rtl_priv *rtlpriv = rtl_priv(hw);
1153 struct rtl_hal *rtlhal = rtl_hal(rtlpriv);
1154 u8 i;
1155 u16 desc_num;
1156
1157 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192EE)
1158 desc_num = TX_DESC_NUM_92E;
1159 else if (rtlhal->hw_type == HARDWARE_TYPE_RTL8822BE)
1160 desc_num = TX_DESC_NUM_8822B;
1161 else
1162 desc_num = RT_TXDESC_NUM;
1163
1164 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1165 rtlpci->txringcount[i] = desc_num;
1166
1167 /*we just alloc 2 desc for beacon queue,
1168 *because we just need first desc in hw beacon.
1169 */
1170 rtlpci->txringcount[BEACON_QUEUE] = 2;
1171
1172 /*BE queue need more descriptor for performance
1173 *consideration or, No more tx desc will happen,
1174 *and may cause mac80211 mem leakage.
1175 */
1176 if (!rtl_priv(hw)->use_new_trx_flow)
1177 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1178
1179 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1180 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1181 }
1182
_rtl_pci_init_struct(struct ieee80211_hw * hw,struct pci_dev * pdev)1183 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1184 struct pci_dev *pdev)
1185 {
1186 struct rtl_priv *rtlpriv = rtl_priv(hw);
1187 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1188 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1189 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1190
1191 rtlpci->up_first_time = true;
1192 rtlpci->being_init_adapter = false;
1193
1194 rtlhal->hw = hw;
1195 rtlpci->pdev = pdev;
1196
1197 /*Tx/Rx related var */
1198 _rtl_pci_init_trx_var(hw);
1199
1200 /*IBSS*/
1201 mac->beacon_interval = 100;
1202
1203 /*AMPDU*/
1204 mac->min_space_cfg = 0;
1205 mac->max_mss_density = 0;
1206 /*set sane AMPDU defaults */
1207 mac->current_ampdu_density = 7;
1208 mac->current_ampdu_factor = 3;
1209
1210 /*Retry Limit*/
1211 mac->retry_short = 7;
1212 mac->retry_long = 7;
1213
1214 /*QOS*/
1215 rtlpci->acm_method = EACMWAY2_SW;
1216
1217 /*task */
1218 tasklet_init(&rtlpriv->works.irq_tasklet,
1219 _rtl_pci_irq_tasklet,
1220 (unsigned long)hw);
1221 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1222 _rtl_pci_prepare_bcn_tasklet,
1223 (unsigned long)hw);
1224 INIT_WORK(&rtlpriv->works.lps_change_work,
1225 rtl_lps_change_work_callback);
1226 }
1227
_rtl_pci_init_tx_ring(struct ieee80211_hw * hw,unsigned int prio,unsigned int entries)1228 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1229 unsigned int prio, unsigned int entries)
1230 {
1231 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1232 struct rtl_priv *rtlpriv = rtl_priv(hw);
1233 struct rtl_tx_buffer_desc *buffer_desc;
1234 struct rtl_tx_desc *desc;
1235 dma_addr_t buffer_desc_dma, desc_dma;
1236 u32 nextdescaddress;
1237 int i;
1238
1239 /* alloc tx buffer desc for new trx flow*/
1240 if (rtlpriv->use_new_trx_flow) {
1241 buffer_desc =
1242 pci_zalloc_consistent(rtlpci->pdev,
1243 sizeof(*buffer_desc) * entries,
1244 &buffer_desc_dma);
1245
1246 if (!buffer_desc || (unsigned long)buffer_desc & 0xFF) {
1247 pr_err("Cannot allocate TX ring (prio = %d)\n",
1248 prio);
1249 return -ENOMEM;
1250 }
1251
1252 rtlpci->tx_ring[prio].buffer_desc = buffer_desc;
1253 rtlpci->tx_ring[prio].buffer_desc_dma = buffer_desc_dma;
1254
1255 rtlpci->tx_ring[prio].cur_tx_rp = 0;
1256 rtlpci->tx_ring[prio].cur_tx_wp = 0;
1257 }
1258
1259 /* alloc dma for this ring */
1260 desc = pci_zalloc_consistent(rtlpci->pdev,
1261 sizeof(*desc) * entries, &desc_dma);
1262
1263 if (!desc || (unsigned long)desc & 0xFF) {
1264 pr_err("Cannot allocate TX ring (prio = %d)\n", prio);
1265 return -ENOMEM;
1266 }
1267
1268 rtlpci->tx_ring[prio].desc = desc;
1269 rtlpci->tx_ring[prio].dma = desc_dma;
1270
1271 rtlpci->tx_ring[prio].idx = 0;
1272 rtlpci->tx_ring[prio].entries = entries;
1273 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1274
1275 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1276 prio, desc);
1277
1278 /* init every desc in this ring */
1279 if (!rtlpriv->use_new_trx_flow) {
1280 for (i = 0; i < entries; i++) {
1281 nextdescaddress = (u32)desc_dma +
1282 ((i + 1) % entries) *
1283 sizeof(*desc);
1284
1285 rtlpriv->cfg->ops->set_desc(hw, (u8 *)&desc[i],
1286 true,
1287 HW_DESC_TX_NEXTDESC_ADDR,
1288 (u8 *)&nextdescaddress);
1289 }
1290 }
1291 return 0;
1292 }
1293
_rtl_pci_init_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1294 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1295 {
1296 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1297 struct rtl_priv *rtlpriv = rtl_priv(hw);
1298 int i;
1299
1300 if (rtlpriv->use_new_trx_flow) {
1301 struct rtl_rx_buffer_desc *entry = NULL;
1302 /* alloc dma for this ring */
1303 rtlpci->rx_ring[rxring_idx].buffer_desc =
1304 pci_zalloc_consistent(rtlpci->pdev,
1305 sizeof(*rtlpci->rx_ring[rxring_idx].
1306 buffer_desc) *
1307 rtlpci->rxringcount,
1308 &rtlpci->rx_ring[rxring_idx].dma);
1309 if (!rtlpci->rx_ring[rxring_idx].buffer_desc ||
1310 (ulong)rtlpci->rx_ring[rxring_idx].buffer_desc & 0xFF) {
1311 pr_err("Cannot allocate RX ring\n");
1312 return -ENOMEM;
1313 }
1314
1315 /* init every desc in this ring */
1316 rtlpci->rx_ring[rxring_idx].idx = 0;
1317 for (i = 0; i < rtlpci->rxringcount; i++) {
1318 entry = &rtlpci->rx_ring[rxring_idx].buffer_desc[i];
1319 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1320 rxring_idx, i))
1321 return -ENOMEM;
1322 }
1323 } else {
1324 struct rtl_rx_desc *entry = NULL;
1325 u8 tmp_one = 1;
1326 /* alloc dma for this ring */
1327 rtlpci->rx_ring[rxring_idx].desc =
1328 pci_zalloc_consistent(rtlpci->pdev,
1329 sizeof(*rtlpci->rx_ring[rxring_idx].
1330 desc) * rtlpci->rxringcount,
1331 &rtlpci->rx_ring[rxring_idx].dma);
1332 if (!rtlpci->rx_ring[rxring_idx].desc ||
1333 (unsigned long)rtlpci->rx_ring[rxring_idx].desc & 0xFF) {
1334 pr_err("Cannot allocate RX ring\n");
1335 return -ENOMEM;
1336 }
1337
1338 /* init every desc in this ring */
1339 rtlpci->rx_ring[rxring_idx].idx = 0;
1340
1341 for (i = 0; i < rtlpci->rxringcount; i++) {
1342 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1343 if (!_rtl_pci_init_one_rxdesc(hw, NULL, (u8 *)entry,
1344 rxring_idx, i))
1345 return -ENOMEM;
1346 }
1347
1348 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1349 HW_DESC_RXERO, &tmp_one);
1350 }
1351 return 0;
1352 }
1353
_rtl_pci_free_tx_ring(struct ieee80211_hw * hw,unsigned int prio)1354 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1355 unsigned int prio)
1356 {
1357 struct rtl_priv *rtlpriv = rtl_priv(hw);
1358 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1359 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1360
1361 /* free every desc in this ring */
1362 while (skb_queue_len(&ring->queue)) {
1363 u8 *entry;
1364 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1365
1366 if (rtlpriv->use_new_trx_flow)
1367 entry = (u8 *)(&ring->buffer_desc[ring->idx]);
1368 else
1369 entry = (u8 *)(&ring->desc[ring->idx]);
1370
1371 pci_unmap_single(rtlpci->pdev,
1372 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1373 true,
1374 HW_DESC_TXBUFF_ADDR),
1375 skb->len, PCI_DMA_TODEVICE);
1376 kfree_skb(skb);
1377 ring->idx = (ring->idx + 1) % ring->entries;
1378 }
1379
1380 /* free dma of this ring */
1381 pci_free_consistent(rtlpci->pdev,
1382 sizeof(*ring->desc) * ring->entries,
1383 ring->desc, ring->dma);
1384 ring->desc = NULL;
1385 if (rtlpriv->use_new_trx_flow) {
1386 pci_free_consistent(rtlpci->pdev,
1387 sizeof(*ring->buffer_desc) * ring->entries,
1388 ring->buffer_desc, ring->buffer_desc_dma);
1389 ring->buffer_desc = NULL;
1390 }
1391 }
1392
_rtl_pci_free_rx_ring(struct ieee80211_hw * hw,int rxring_idx)1393 static void _rtl_pci_free_rx_ring(struct ieee80211_hw *hw, int rxring_idx)
1394 {
1395 struct rtl_priv *rtlpriv = rtl_priv(hw);
1396 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1397 int i;
1398
1399 /* free every desc in this ring */
1400 for (i = 0; i < rtlpci->rxringcount; i++) {
1401 struct sk_buff *skb = rtlpci->rx_ring[rxring_idx].rx_buf[i];
1402
1403 if (!skb)
1404 continue;
1405 pci_unmap_single(rtlpci->pdev, *((dma_addr_t *)skb->cb),
1406 rtlpci->rxbuffersize, PCI_DMA_FROMDEVICE);
1407 kfree_skb(skb);
1408 }
1409
1410 /* free dma of this ring */
1411 if (rtlpriv->use_new_trx_flow) {
1412 pci_free_consistent(rtlpci->pdev,
1413 sizeof(*rtlpci->rx_ring[rxring_idx].
1414 buffer_desc) * rtlpci->rxringcount,
1415 rtlpci->rx_ring[rxring_idx].buffer_desc,
1416 rtlpci->rx_ring[rxring_idx].dma);
1417 rtlpci->rx_ring[rxring_idx].buffer_desc = NULL;
1418 } else {
1419 pci_free_consistent(rtlpci->pdev,
1420 sizeof(*rtlpci->rx_ring[rxring_idx].desc) *
1421 rtlpci->rxringcount,
1422 rtlpci->rx_ring[rxring_idx].desc,
1423 rtlpci->rx_ring[rxring_idx].dma);
1424 rtlpci->rx_ring[rxring_idx].desc = NULL;
1425 }
1426 }
1427
_rtl_pci_init_trx_ring(struct ieee80211_hw * hw)1428 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1429 {
1430 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1431 int ret;
1432 int i, rxring_idx;
1433
1434 /* rxring_idx 0:RX_MPDU_QUEUE
1435 * rxring_idx 1:RX_CMD_QUEUE
1436 */
1437 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1438 ret = _rtl_pci_init_rx_ring(hw, rxring_idx);
1439 if (ret)
1440 return ret;
1441 }
1442
1443 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1444 ret = _rtl_pci_init_tx_ring(hw, i, rtlpci->txringcount[i]);
1445 if (ret)
1446 goto err_free_rings;
1447 }
1448
1449 return 0;
1450
1451 err_free_rings:
1452 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1453 _rtl_pci_free_rx_ring(hw, rxring_idx);
1454
1455 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1456 if (rtlpci->tx_ring[i].desc ||
1457 rtlpci->tx_ring[i].buffer_desc)
1458 _rtl_pci_free_tx_ring(hw, i);
1459
1460 return 1;
1461 }
1462
_rtl_pci_deinit_trx_ring(struct ieee80211_hw * hw)1463 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1464 {
1465 u32 i, rxring_idx;
1466
1467 /*free rx rings */
1468 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++)
1469 _rtl_pci_free_rx_ring(hw, rxring_idx);
1470
1471 /*free tx rings */
1472 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1473 _rtl_pci_free_tx_ring(hw, i);
1474
1475 return 0;
1476 }
1477
rtl_pci_reset_trx_ring(struct ieee80211_hw * hw)1478 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1479 {
1480 struct rtl_priv *rtlpriv = rtl_priv(hw);
1481 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1482 int i, rxring_idx;
1483 unsigned long flags;
1484 u8 tmp_one = 1;
1485 u32 bufferaddress;
1486 /* rxring_idx 0:RX_MPDU_QUEUE */
1487 /* rxring_idx 1:RX_CMD_QUEUE */
1488 for (rxring_idx = 0; rxring_idx < RTL_PCI_MAX_RX_QUEUE; rxring_idx++) {
1489 /* force the rx_ring[RX_MPDU_QUEUE/
1490 * RX_CMD_QUEUE].idx to the first one
1491 *new trx flow, do nothing
1492 */
1493 if (!rtlpriv->use_new_trx_flow &&
1494 rtlpci->rx_ring[rxring_idx].desc) {
1495 struct rtl_rx_desc *entry = NULL;
1496
1497 rtlpci->rx_ring[rxring_idx].idx = 0;
1498 for (i = 0; i < rtlpci->rxringcount; i++) {
1499 entry = &rtlpci->rx_ring[rxring_idx].desc[i];
1500 bufferaddress =
1501 rtlpriv->cfg->ops->get_desc(hw, (u8 *)entry,
1502 false, HW_DESC_RXBUFF_ADDR);
1503 memset((u8 *)entry, 0,
1504 sizeof(*rtlpci->rx_ring
1505 [rxring_idx].desc));/*clear one entry*/
1506 if (rtlpriv->use_new_trx_flow) {
1507 rtlpriv->cfg->ops->set_desc(hw,
1508 (u8 *)entry, false,
1509 HW_DESC_RX_PREPARE,
1510 (u8 *)&bufferaddress);
1511 } else {
1512 rtlpriv->cfg->ops->set_desc(hw,
1513 (u8 *)entry, false,
1514 HW_DESC_RXBUFF_ADDR,
1515 (u8 *)&bufferaddress);
1516 rtlpriv->cfg->ops->set_desc(hw,
1517 (u8 *)entry, false,
1518 HW_DESC_RXPKT_LEN,
1519 (u8 *)&rtlpci->rxbuffersize);
1520 rtlpriv->cfg->ops->set_desc(hw,
1521 (u8 *)entry, false,
1522 HW_DESC_RXOWN,
1523 (u8 *)&tmp_one);
1524 }
1525 }
1526 rtlpriv->cfg->ops->set_desc(hw, (u8 *)entry, false,
1527 HW_DESC_RXERO, (u8 *)&tmp_one);
1528 }
1529 rtlpci->rx_ring[rxring_idx].idx = 0;
1530 }
1531
1532 /*after reset, release previous pending packet,
1533 *and force the tx idx to the first one
1534 */
1535 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1536 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1537 if (rtlpci->tx_ring[i].desc ||
1538 rtlpci->tx_ring[i].buffer_desc) {
1539 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1540
1541 while (skb_queue_len(&ring->queue)) {
1542 u8 *entry;
1543 struct sk_buff *skb =
1544 __skb_dequeue(&ring->queue);
1545 if (rtlpriv->use_new_trx_flow)
1546 entry = (u8 *)(&ring->buffer_desc
1547 [ring->idx]);
1548 else
1549 entry = (u8 *)(&ring->desc[ring->idx]);
1550
1551 pci_unmap_single(rtlpci->pdev,
1552 rtlpriv->cfg->ops->
1553 get_desc(hw, (u8 *)
1554 entry,
1555 true,
1556 HW_DESC_TXBUFF_ADDR),
1557 skb->len, PCI_DMA_TODEVICE);
1558 dev_kfree_skb_irq(skb);
1559 ring->idx = (ring->idx + 1) % ring->entries;
1560 }
1561
1562 if (rtlpriv->use_new_trx_flow) {
1563 rtlpci->tx_ring[i].cur_tx_rp = 0;
1564 rtlpci->tx_ring[i].cur_tx_wp = 0;
1565 }
1566
1567 ring->idx = 0;
1568 ring->entries = rtlpci->txringcount[i];
1569 }
1570 }
1571 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1572
1573 return 0;
1574 }
1575
rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb)1576 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1577 struct ieee80211_sta *sta,
1578 struct sk_buff *skb)
1579 {
1580 struct rtl_priv *rtlpriv = rtl_priv(hw);
1581 struct rtl_sta_info *sta_entry = NULL;
1582 u8 tid = rtl_get_tid(skb);
1583 __le16 fc = rtl_get_fc(skb);
1584
1585 if (!sta)
1586 return false;
1587 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1588
1589 if (!rtlpriv->rtlhal.earlymode_enable)
1590 return false;
1591 if (ieee80211_is_nullfunc(fc))
1592 return false;
1593 if (ieee80211_is_qos_nullfunc(fc))
1594 return false;
1595 if (ieee80211_is_pspoll(fc))
1596 return false;
1597 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1598 return false;
1599 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1600 return false;
1601 if (tid > 7)
1602 return false;
1603
1604 /* maybe every tid should be checked */
1605 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1606 return false;
1607
1608 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1609 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1610 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1611
1612 return true;
1613 }
1614
rtl_pci_tx(struct ieee80211_hw * hw,struct ieee80211_sta * sta,struct sk_buff * skb,struct rtl_tcb_desc * ptcb_desc)1615 static int rtl_pci_tx(struct ieee80211_hw *hw,
1616 struct ieee80211_sta *sta,
1617 struct sk_buff *skb,
1618 struct rtl_tcb_desc *ptcb_desc)
1619 {
1620 struct rtl_priv *rtlpriv = rtl_priv(hw);
1621 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1622 struct rtl8192_tx_ring *ring;
1623 struct rtl_tx_desc *pdesc;
1624 struct rtl_tx_buffer_desc *ptx_bd_desc = NULL;
1625 u16 idx;
1626 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1627 unsigned long flags;
1628 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1629 __le16 fc = rtl_get_fc(skb);
1630 u8 *pda_addr = hdr->addr1;
1631 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1632 u8 own;
1633 u8 temp_one = 1;
1634
1635 if (ieee80211_is_mgmt(fc))
1636 rtl_tx_mgmt_proc(hw, skb);
1637
1638 if (rtlpriv->psc.sw_ps_enabled) {
1639 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1640 !ieee80211_has_pm(fc))
1641 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1642 }
1643
1644 rtl_action_proc(hw, skb, true);
1645
1646 if (is_multicast_ether_addr(pda_addr))
1647 rtlpriv->stats.txbytesmulticast += skb->len;
1648 else if (is_broadcast_ether_addr(pda_addr))
1649 rtlpriv->stats.txbytesbroadcast += skb->len;
1650 else
1651 rtlpriv->stats.txbytesunicast += skb->len;
1652
1653 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1654 ring = &rtlpci->tx_ring[hw_queue];
1655 if (hw_queue != BEACON_QUEUE) {
1656 if (rtlpriv->use_new_trx_flow)
1657 idx = ring->cur_tx_wp;
1658 else
1659 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1660 ring->entries;
1661 } else {
1662 idx = 0;
1663 }
1664
1665 pdesc = &ring->desc[idx];
1666 if (rtlpriv->use_new_trx_flow) {
1667 ptx_bd_desc = &ring->buffer_desc[idx];
1668 } else {
1669 own = (u8)rtlpriv->cfg->ops->get_desc(hw, (u8 *)pdesc,
1670 true, HW_DESC_OWN);
1671
1672 if (own == 1 && hw_queue != BEACON_QUEUE) {
1673 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1674 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1675 hw_queue, ring->idx, idx,
1676 skb_queue_len(&ring->queue));
1677
1678 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1679 flags);
1680 return skb->len;
1681 }
1682 }
1683
1684 if (rtlpriv->cfg->ops->get_available_desc &&
1685 rtlpriv->cfg->ops->get_available_desc(hw, hw_queue) == 0) {
1686 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1687 "get_available_desc fail\n");
1688 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1689 return skb->len;
1690 }
1691
1692 if (ieee80211_is_data(fc))
1693 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1694
1695 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1696 (u8 *)ptx_bd_desc, info, sta, skb, hw_queue, ptcb_desc);
1697
1698 __skb_queue_tail(&ring->queue, skb);
1699
1700 if (rtlpriv->use_new_trx_flow) {
1701 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1702 HW_DESC_OWN, &hw_queue);
1703 } else {
1704 rtlpriv->cfg->ops->set_desc(hw, (u8 *)pdesc, true,
1705 HW_DESC_OWN, &temp_one);
1706 }
1707
1708 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1709 hw_queue != BEACON_QUEUE) {
1710 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1711 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%x\n",
1712 hw_queue, ring->idx, idx,
1713 skb_queue_len(&ring->queue));
1714
1715 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1716 }
1717
1718 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1719
1720 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1721
1722 return 0;
1723 }
1724
rtl_pci_flush(struct ieee80211_hw * hw,u32 queues,bool drop)1725 static void rtl_pci_flush(struct ieee80211_hw *hw, u32 queues, bool drop)
1726 {
1727 struct rtl_priv *rtlpriv = rtl_priv(hw);
1728 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1729 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1730 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1731 u16 i = 0;
1732 int queue_id;
1733 struct rtl8192_tx_ring *ring;
1734
1735 if (mac->skip_scan)
1736 return;
1737
1738 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1739 u32 queue_len;
1740
1741 if (((queues >> queue_id) & 0x1) == 0) {
1742 queue_id--;
1743 continue;
1744 }
1745 ring = &pcipriv->dev.tx_ring[queue_id];
1746 queue_len = skb_queue_len(&ring->queue);
1747 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1748 queue_id == TXCMD_QUEUE) {
1749 queue_id--;
1750 continue;
1751 } else {
1752 msleep(20);
1753 i++;
1754 }
1755
1756 /* we just wait 1s for all queues */
1757 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1758 is_hal_stop(rtlhal) || i >= 200)
1759 return;
1760 }
1761 }
1762
rtl_pci_deinit(struct ieee80211_hw * hw)1763 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1764 {
1765 struct rtl_priv *rtlpriv = rtl_priv(hw);
1766 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1767
1768 _rtl_pci_deinit_trx_ring(hw);
1769
1770 synchronize_irq(rtlpci->pdev->irq);
1771 tasklet_kill(&rtlpriv->works.irq_tasklet);
1772 cancel_work_sync(&rtlpriv->works.lps_change_work);
1773
1774 flush_workqueue(rtlpriv->works.rtl_wq);
1775 destroy_workqueue(rtlpriv->works.rtl_wq);
1776 }
1777
rtl_pci_init(struct ieee80211_hw * hw,struct pci_dev * pdev)1778 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1779 {
1780 int err;
1781
1782 _rtl_pci_init_struct(hw, pdev);
1783
1784 err = _rtl_pci_init_trx_ring(hw);
1785 if (err) {
1786 pr_err("tx ring initialization failed\n");
1787 return err;
1788 }
1789
1790 return 0;
1791 }
1792
rtl_pci_start(struct ieee80211_hw * hw)1793 static int rtl_pci_start(struct ieee80211_hw *hw)
1794 {
1795 struct rtl_priv *rtlpriv = rtl_priv(hw);
1796 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1797 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1798 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1799 struct rtl_mac *rtlmac = rtl_mac(rtl_priv(hw));
1800 struct rtl_btc_ops *btc_ops = rtlpriv->btcoexist.btc_ops;
1801
1802 int err;
1803
1804 rtl_pci_reset_trx_ring(hw);
1805
1806 rtlpci->driver_is_goingto_unload = false;
1807 if (rtlpriv->cfg->ops->get_btc_status &&
1808 rtlpriv->cfg->ops->get_btc_status()) {
1809 rtlpriv->btcoexist.btc_info.ap_num = 36;
1810 btc_ops->btc_init_variables(rtlpriv);
1811 btc_ops->btc_init_hal_vars(rtlpriv);
1812 } else if (btc_ops) {
1813 btc_ops->btc_init_variables_wifi_only(rtlpriv);
1814 }
1815
1816 err = rtlpriv->cfg->ops->hw_init(hw);
1817 if (err) {
1818 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1819 "Failed to config hardware!\n");
1820 return err;
1821 }
1822 rtlpriv->cfg->ops->set_hw_reg(hw, HW_VAR_RETRY_LIMIT,
1823 &rtlmac->retry_long);
1824
1825 rtlpriv->cfg->ops->enable_interrupt(hw);
1826 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1827
1828 rtl_init_rx_config(hw);
1829
1830 /*should be after adapter start and interrupt enable. */
1831 set_hal_start(rtlhal);
1832
1833 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1834
1835 rtlpci->up_first_time = false;
1836
1837 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "%s OK\n", __func__);
1838 return 0;
1839 }
1840
rtl_pci_stop(struct ieee80211_hw * hw)1841 static void rtl_pci_stop(struct ieee80211_hw *hw)
1842 {
1843 struct rtl_priv *rtlpriv = rtl_priv(hw);
1844 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1845 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1846 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1847 unsigned long flags;
1848 u8 rf_timeout = 0;
1849
1850 if (rtlpriv->cfg->ops->get_btc_status())
1851 rtlpriv->btcoexist.btc_ops->btc_halt_notify(rtlpriv);
1852
1853 if (rtlpriv->btcoexist.btc_ops)
1854 rtlpriv->btcoexist.btc_ops->btc_deinit_variables(rtlpriv);
1855
1856 /*should be before disable interrupt&adapter
1857 *and will do it immediately.
1858 */
1859 set_hal_stop(rtlhal);
1860
1861 rtlpci->driver_is_goingto_unload = true;
1862 rtlpriv->cfg->ops->disable_interrupt(hw);
1863 cancel_work_sync(&rtlpriv->works.lps_change_work);
1864
1865 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1866 while (ppsc->rfchange_inprogress) {
1867 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1868 if (rf_timeout > 100) {
1869 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1870 break;
1871 }
1872 mdelay(1);
1873 rf_timeout++;
1874 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1875 }
1876 ppsc->rfchange_inprogress = true;
1877 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1878
1879 rtlpriv->cfg->ops->hw_disable(hw);
1880 /* some things are not needed if firmware not available */
1881 if (!rtlpriv->max_fw_size)
1882 return;
1883 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1884
1885 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1886 ppsc->rfchange_inprogress = false;
1887 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1888
1889 rtl_pci_enable_aspm(hw);
1890 }
1891
_rtl_pci_find_adapter(struct pci_dev * pdev,struct ieee80211_hw * hw)1892 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1893 struct ieee80211_hw *hw)
1894 {
1895 struct rtl_priv *rtlpriv = rtl_priv(hw);
1896 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1897 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1898 struct pci_dev *bridge_pdev = pdev->bus->self;
1899 u16 venderid;
1900 u16 deviceid;
1901 u8 revisionid;
1902 u16 irqline;
1903 u8 tmp;
1904
1905 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1906 venderid = pdev->vendor;
1907 deviceid = pdev->device;
1908 pci_read_config_byte(pdev, 0x8, &revisionid);
1909 pci_read_config_word(pdev, 0x3C, &irqline);
1910
1911 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1912 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1913 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1914 * the correct driver is r8192e_pci, thus this routine should
1915 * return false.
1916 */
1917 if (deviceid == RTL_PCI_8192SE_DID &&
1918 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1919 return false;
1920
1921 if (deviceid == RTL_PCI_8192_DID ||
1922 deviceid == RTL_PCI_0044_DID ||
1923 deviceid == RTL_PCI_0047_DID ||
1924 deviceid == RTL_PCI_8192SE_DID ||
1925 deviceid == RTL_PCI_8174_DID ||
1926 deviceid == RTL_PCI_8173_DID ||
1927 deviceid == RTL_PCI_8172_DID ||
1928 deviceid == RTL_PCI_8171_DID) {
1929 switch (revisionid) {
1930 case RTL_PCI_REVISION_ID_8192PCIE:
1931 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1932 "8192 PCI-E is found - vid/did=%x/%x\n",
1933 venderid, deviceid);
1934 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1935 return false;
1936 case RTL_PCI_REVISION_ID_8192SE:
1937 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1938 "8192SE is found - vid/did=%x/%x\n",
1939 venderid, deviceid);
1940 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1941 break;
1942 default:
1943 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1944 "Err: Unknown device - vid/did=%x/%x\n",
1945 venderid, deviceid);
1946 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1947 break;
1948 }
1949 } else if (deviceid == RTL_PCI_8723AE_DID) {
1950 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1951 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1952 "8723AE PCI-E is found - vid/did=%x/%x\n",
1953 venderid, deviceid);
1954 } else if (deviceid == RTL_PCI_8192CET_DID ||
1955 deviceid == RTL_PCI_8192CE_DID ||
1956 deviceid == RTL_PCI_8191CE_DID ||
1957 deviceid == RTL_PCI_8188CE_DID) {
1958 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1959 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1960 "8192C PCI-E is found - vid/did=%x/%x\n",
1961 venderid, deviceid);
1962 } else if (deviceid == RTL_PCI_8192DE_DID ||
1963 deviceid == RTL_PCI_8192DE_DID2) {
1964 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1965 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1966 "8192D PCI-E is found - vid/did=%x/%x\n",
1967 venderid, deviceid);
1968 } else if (deviceid == RTL_PCI_8188EE_DID) {
1969 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1970 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1971 "Find adapter, Hardware type is 8188EE\n");
1972 } else if (deviceid == RTL_PCI_8723BE_DID) {
1973 rtlhal->hw_type = HARDWARE_TYPE_RTL8723BE;
1974 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1975 "Find adapter, Hardware type is 8723BE\n");
1976 } else if (deviceid == RTL_PCI_8192EE_DID) {
1977 rtlhal->hw_type = HARDWARE_TYPE_RTL8192EE;
1978 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1979 "Find adapter, Hardware type is 8192EE\n");
1980 } else if (deviceid == RTL_PCI_8821AE_DID) {
1981 rtlhal->hw_type = HARDWARE_TYPE_RTL8821AE;
1982 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1983 "Find adapter, Hardware type is 8821AE\n");
1984 } else if (deviceid == RTL_PCI_8812AE_DID) {
1985 rtlhal->hw_type = HARDWARE_TYPE_RTL8812AE;
1986 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1987 "Find adapter, Hardware type is 8812AE\n");
1988 } else if (deviceid == RTL_PCI_8822BE_DID) {
1989 rtlhal->hw_type = HARDWARE_TYPE_RTL8822BE;
1990 rtlhal->bandset = BAND_ON_BOTH;
1991 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1992 "Find adapter, Hardware type is 8822BE\n");
1993 } else {
1994 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1995 "Err: Unknown device - vid/did=%x/%x\n",
1996 venderid, deviceid);
1997
1998 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1999 }
2000
2001 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
2002 if (revisionid == 0 || revisionid == 1) {
2003 if (revisionid == 0) {
2004 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2005 "Find 92DE MAC0\n");
2006 rtlhal->interfaceindex = 0;
2007 } else if (revisionid == 1) {
2008 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2009 "Find 92DE MAC1\n");
2010 rtlhal->interfaceindex = 1;
2011 }
2012 } else {
2013 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
2014 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
2015 venderid, deviceid, revisionid);
2016 rtlhal->interfaceindex = 0;
2017 }
2018 }
2019
2020 switch (rtlhal->hw_type) {
2021 case HARDWARE_TYPE_RTL8192EE:
2022 case HARDWARE_TYPE_RTL8822BE:
2023 /* use new trx flow */
2024 rtlpriv->use_new_trx_flow = true;
2025 break;
2026
2027 default:
2028 rtlpriv->use_new_trx_flow = false;
2029 break;
2030 }
2031
2032 /*find bus info */
2033 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
2034 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
2035 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
2036
2037 /*find bridge info */
2038 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
2039 /* some ARM have no bridge_pdev and will crash here
2040 * so we should check if bridge_pdev is NULL
2041 */
2042 if (bridge_pdev) {
2043 /*find bridge info if available */
2044 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
2045 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
2046 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
2047 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
2048 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2049 "Pci Bridge Vendor is found index: %d\n",
2050 tmp);
2051 break;
2052 }
2053 }
2054 }
2055
2056 if (pcipriv->ndis_adapter.pcibridge_vendor !=
2057 PCI_BRIDGE_VENDOR_UNKNOWN) {
2058 pcipriv->ndis_adapter.pcibridge_busnum =
2059 bridge_pdev->bus->number;
2060 pcipriv->ndis_adapter.pcibridge_devnum =
2061 PCI_SLOT(bridge_pdev->devfn);
2062 pcipriv->ndis_adapter.pcibridge_funcnum =
2063 PCI_FUNC(bridge_pdev->devfn);
2064 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
2065 pci_pcie_cap(bridge_pdev);
2066 pcipriv->ndis_adapter.num4bytes =
2067 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
2068
2069 rtl_pci_get_linkcontrol_field(hw);
2070
2071 if (pcipriv->ndis_adapter.pcibridge_vendor ==
2072 PCI_BRIDGE_VENDOR_AMD) {
2073 pcipriv->ndis_adapter.amd_l1_patch =
2074 rtl_pci_get_amd_l1_patch(hw);
2075 }
2076 }
2077
2078 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2079 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
2080 pcipriv->ndis_adapter.busnumber,
2081 pcipriv->ndis_adapter.devnumber,
2082 pcipriv->ndis_adapter.funcnumber,
2083 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
2084
2085 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2086 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
2087 pcipriv->ndis_adapter.pcibridge_busnum,
2088 pcipriv->ndis_adapter.pcibridge_devnum,
2089 pcipriv->ndis_adapter.pcibridge_funcnum,
2090 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
2091 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
2092 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
2093 pcipriv->ndis_adapter.amd_l1_patch);
2094
2095 rtl_pci_parse_configuration(pdev, hw);
2096 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
2097
2098 return true;
2099 }
2100
rtl_pci_intr_mode_msi(struct ieee80211_hw * hw)2101 static int rtl_pci_intr_mode_msi(struct ieee80211_hw *hw)
2102 {
2103 struct rtl_priv *rtlpriv = rtl_priv(hw);
2104 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2105 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2106 int ret;
2107
2108 ret = pci_enable_msi(rtlpci->pdev);
2109 if (ret < 0)
2110 return ret;
2111
2112 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2113 IRQF_SHARED, KBUILD_MODNAME, hw);
2114 if (ret < 0) {
2115 pci_disable_msi(rtlpci->pdev);
2116 return ret;
2117 }
2118
2119 rtlpci->using_msi = true;
2120
2121 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2122 "MSI Interrupt Mode!\n");
2123 return 0;
2124 }
2125
rtl_pci_intr_mode_legacy(struct ieee80211_hw * hw)2126 static int rtl_pci_intr_mode_legacy(struct ieee80211_hw *hw)
2127 {
2128 struct rtl_priv *rtlpriv = rtl_priv(hw);
2129 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2130 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2131 int ret;
2132
2133 ret = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
2134 IRQF_SHARED, KBUILD_MODNAME, hw);
2135 if (ret < 0)
2136 return ret;
2137
2138 rtlpci->using_msi = false;
2139 RT_TRACE(rtlpriv, COMP_INIT | COMP_INTR, DBG_DMESG,
2140 "Pin-based Interrupt Mode!\n");
2141 return 0;
2142 }
2143
rtl_pci_intr_mode_decide(struct ieee80211_hw * hw)2144 static int rtl_pci_intr_mode_decide(struct ieee80211_hw *hw)
2145 {
2146 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2147 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2148 int ret;
2149
2150 if (rtlpci->msi_support) {
2151 ret = rtl_pci_intr_mode_msi(hw);
2152 if (ret < 0)
2153 ret = rtl_pci_intr_mode_legacy(hw);
2154 } else {
2155 ret = rtl_pci_intr_mode_legacy(hw);
2156 }
2157 return ret;
2158 }
2159
platform_enable_dma64(struct pci_dev * pdev,bool dma64)2160 static void platform_enable_dma64(struct pci_dev *pdev, bool dma64)
2161 {
2162 u8 value;
2163
2164 pci_read_config_byte(pdev, 0x719, &value);
2165
2166 /* 0x719 Bit5 is DMA64 bit fetch. */
2167 if (dma64)
2168 value |= BIT(5);
2169 else
2170 value &= ~BIT(5);
2171
2172 pci_write_config_byte(pdev, 0x719, value);
2173 }
2174
rtl_pci_probe(struct pci_dev * pdev,const struct pci_device_id * id)2175 int rtl_pci_probe(struct pci_dev *pdev,
2176 const struct pci_device_id *id)
2177 {
2178 struct ieee80211_hw *hw = NULL;
2179
2180 struct rtl_priv *rtlpriv = NULL;
2181 struct rtl_pci_priv *pcipriv = NULL;
2182 struct rtl_pci *rtlpci;
2183 unsigned long pmem_start, pmem_len, pmem_flags;
2184 int err;
2185
2186 err = pci_enable_device(pdev);
2187 if (err) {
2188 WARN_ONCE(true, "%s : Cannot enable new PCI device\n",
2189 pci_name(pdev));
2190 return err;
2191 }
2192
2193 if (((struct rtl_hal_cfg *)id->driver_data)->mod_params->dma64 &&
2194 !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
2195 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) {
2196 WARN_ONCE(true,
2197 "Unable to obtain 64bit DMA for consistent allocations\n");
2198 err = -ENOMEM;
2199 goto fail1;
2200 }
2201
2202 platform_enable_dma64(pdev, true);
2203 } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
2204 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
2205 WARN_ONCE(true,
2206 "rtlwifi: Unable to obtain 32bit DMA for consistent allocations\n");
2207 err = -ENOMEM;
2208 goto fail1;
2209 }
2210
2211 platform_enable_dma64(pdev, false);
2212 }
2213
2214 pci_set_master(pdev);
2215
2216 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
2217 sizeof(struct rtl_priv), &rtl_ops);
2218 if (!hw) {
2219 WARN_ONCE(true,
2220 "%s : ieee80211 alloc failed\n", pci_name(pdev));
2221 err = -ENOMEM;
2222 goto fail1;
2223 }
2224
2225 SET_IEEE80211_DEV(hw, &pdev->dev);
2226 pci_set_drvdata(pdev, hw);
2227
2228 rtlpriv = hw->priv;
2229 rtlpriv->hw = hw;
2230 pcipriv = (void *)rtlpriv->priv;
2231 pcipriv->dev.pdev = pdev;
2232 init_completion(&rtlpriv->firmware_loading_complete);
2233 /*proximity init here*/
2234 rtlpriv->proximity.proxim_on = false;
2235
2236 pcipriv = (void *)rtlpriv->priv;
2237 pcipriv->dev.pdev = pdev;
2238
2239 /* init cfg & intf_ops */
2240 rtlpriv->rtlhal.interface = INTF_PCI;
2241 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
2242 rtlpriv->intf_ops = &rtl_pci_ops;
2243 rtlpriv->glb_var = &rtl_global_var;
2244 rtl_efuse_ops_init(hw);
2245
2246 /* MEM map */
2247 err = pci_request_regions(pdev, KBUILD_MODNAME);
2248 if (err) {
2249 WARN_ONCE(true, "rtlwifi: Can't obtain PCI resources\n");
2250 goto fail1;
2251 }
2252
2253 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
2254 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
2255 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
2256
2257 /*shared mem start */
2258 rtlpriv->io.pci_mem_start =
2259 (unsigned long)pci_iomap(pdev,
2260 rtlpriv->cfg->bar_id, pmem_len);
2261 if (rtlpriv->io.pci_mem_start == 0) {
2262 WARN_ONCE(true, "rtlwifi: Can't map PCI mem\n");
2263 err = -ENOMEM;
2264 goto fail2;
2265 }
2266
2267 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2268 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
2269 pmem_start, pmem_len, pmem_flags,
2270 rtlpriv->io.pci_mem_start);
2271
2272 /* Disable Clk Request */
2273 pci_write_config_byte(pdev, 0x81, 0);
2274 /* leave D3 mode */
2275 pci_write_config_byte(pdev, 0x44, 0);
2276 pci_write_config_byte(pdev, 0x04, 0x06);
2277 pci_write_config_byte(pdev, 0x04, 0x07);
2278
2279 /* find adapter */
2280 if (!_rtl_pci_find_adapter(pdev, hw)) {
2281 err = -ENODEV;
2282 goto fail2;
2283 }
2284
2285 /* Init IO handler */
2286 _rtl_pci_io_handler_init(&pdev->dev, hw);
2287
2288 /*like read eeprom and so on */
2289 rtlpriv->cfg->ops->read_eeprom_info(hw);
2290
2291 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
2292 pr_err("Can't init_sw_vars\n");
2293 err = -ENODEV;
2294 goto fail3;
2295 }
2296 rtlpriv->cfg->ops->init_sw_leds(hw);
2297
2298 /*aspm */
2299 rtl_pci_init_aspm(hw);
2300
2301 /* Init mac80211 sw */
2302 err = rtl_init_core(hw);
2303 if (err) {
2304 pr_err("Can't allocate sw for mac80211\n");
2305 goto fail3;
2306 }
2307
2308 /* Init PCI sw */
2309 err = rtl_pci_init(hw, pdev);
2310 if (err) {
2311 pr_err("Failed to init PCI\n");
2312 goto fail3;
2313 }
2314
2315 err = ieee80211_register_hw(hw);
2316 if (err) {
2317 pr_err("Can't register mac80211 hw.\n");
2318 err = -ENODEV;
2319 goto fail3;
2320 }
2321 rtlpriv->mac80211.mac80211_registered = 1;
2322
2323 /* add for debug */
2324 rtl_debug_add_one(hw);
2325
2326 /*init rfkill */
2327 rtl_init_rfkill(hw); /* Init PCI sw */
2328
2329 rtlpci = rtl_pcidev(pcipriv);
2330 err = rtl_pci_intr_mode_decide(hw);
2331 if (err) {
2332 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
2333 "%s: failed to register IRQ handler\n",
2334 wiphy_name(hw->wiphy));
2335 goto fail3;
2336 }
2337 rtlpci->irq_alloc = 1;
2338
2339 set_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2340 return 0;
2341
2342 fail3:
2343 pci_set_drvdata(pdev, NULL);
2344 rtl_deinit_core(hw);
2345
2346 fail2:
2347 if (rtlpriv->io.pci_mem_start != 0)
2348 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2349
2350 pci_release_regions(pdev);
2351 complete(&rtlpriv->firmware_loading_complete);
2352
2353 fail1:
2354 if (hw)
2355 ieee80211_free_hw(hw);
2356 pci_disable_device(pdev);
2357
2358 return err;
2359 }
2360 EXPORT_SYMBOL(rtl_pci_probe);
2361
rtl_pci_disconnect(struct pci_dev * pdev)2362 void rtl_pci_disconnect(struct pci_dev *pdev)
2363 {
2364 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2365 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2366 struct rtl_priv *rtlpriv = rtl_priv(hw);
2367 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2368 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2369
2370 /* just in case driver is removed before firmware callback */
2371 wait_for_completion(&rtlpriv->firmware_loading_complete);
2372 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2373
2374 /* remove form debug */
2375 rtl_debug_remove_one(hw);
2376
2377 /*ieee80211_unregister_hw will call ops_stop */
2378 if (rtlmac->mac80211_registered == 1) {
2379 ieee80211_unregister_hw(hw);
2380 rtlmac->mac80211_registered = 0;
2381 } else {
2382 rtl_deinit_deferred_work(hw, false);
2383 rtlpriv->intf_ops->adapter_stop(hw);
2384 }
2385 rtlpriv->cfg->ops->disable_interrupt(hw);
2386
2387 /*deinit rfkill */
2388 rtl_deinit_rfkill(hw);
2389
2390 rtl_pci_deinit(hw);
2391 rtl_deinit_core(hw);
2392 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2393
2394 if (rtlpci->irq_alloc) {
2395 free_irq(rtlpci->pdev->irq, hw);
2396 rtlpci->irq_alloc = 0;
2397 }
2398
2399 if (rtlpci->using_msi)
2400 pci_disable_msi(rtlpci->pdev);
2401
2402 list_del(&rtlpriv->list);
2403 if (rtlpriv->io.pci_mem_start != 0) {
2404 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2405 pci_release_regions(pdev);
2406 }
2407
2408 pci_disable_device(pdev);
2409
2410 rtl_pci_disable_aspm(hw);
2411
2412 pci_set_drvdata(pdev, NULL);
2413
2414 ieee80211_free_hw(hw);
2415 }
2416 EXPORT_SYMBOL(rtl_pci_disconnect);
2417
2418 #ifdef CONFIG_PM_SLEEP
2419 /***************************************
2420 * kernel pci power state define:
2421 * PCI_D0 ((pci_power_t __force) 0)
2422 * PCI_D1 ((pci_power_t __force) 1)
2423 * PCI_D2 ((pci_power_t __force) 2)
2424 * PCI_D3hot ((pci_power_t __force) 3)
2425 * PCI_D3cold ((pci_power_t __force) 4)
2426 * PCI_UNKNOWN ((pci_power_t __force) 5)
2427
2428 * This function is called when system
2429 * goes into suspend state mac80211 will
2430 * call rtl_mac_stop() from the mac80211
2431 * suspend function first, So there is
2432 * no need to call hw_disable here.
2433 ****************************************/
rtl_pci_suspend(struct device * dev)2434 int rtl_pci_suspend(struct device *dev)
2435 {
2436 struct pci_dev *pdev = to_pci_dev(dev);
2437 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2438 struct rtl_priv *rtlpriv = rtl_priv(hw);
2439
2440 rtlpriv->cfg->ops->hw_suspend(hw);
2441 rtl_deinit_rfkill(hw);
2442
2443 return 0;
2444 }
2445 EXPORT_SYMBOL(rtl_pci_suspend);
2446
rtl_pci_resume(struct device * dev)2447 int rtl_pci_resume(struct device *dev)
2448 {
2449 struct pci_dev *pdev = to_pci_dev(dev);
2450 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2451 struct rtl_priv *rtlpriv = rtl_priv(hw);
2452
2453 rtlpriv->cfg->ops->hw_resume(hw);
2454 rtl_init_rfkill(hw);
2455 return 0;
2456 }
2457 EXPORT_SYMBOL(rtl_pci_resume);
2458 #endif /* CONFIG_PM_SLEEP */
2459
2460 const struct rtl_intf_ops rtl_pci_ops = {
2461 .read_efuse_byte = read_efuse_byte,
2462 .adapter_start = rtl_pci_start,
2463 .adapter_stop = rtl_pci_stop,
2464 .check_buddy_priv = rtl_pci_check_buddy_priv,
2465 .adapter_tx = rtl_pci_tx,
2466 .flush = rtl_pci_flush,
2467 .reset_trx_ring = rtl_pci_reset_trx_ring,
2468 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2469
2470 .disable_aspm = rtl_pci_disable_aspm,
2471 .enable_aspm = rtl_pci_enable_aspm,
2472 };
2473