1 /*
2 * I2C Link Layer for PN544 HCI based Driver
3 *
4 * Copyright (C) 2012 Intel Corporation. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
20
21 #include <linux/crc-ccitt.h>
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/acpi.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/nfc.h>
28 #include <linux/firmware.h>
29 #include <linux/gpio/consumer.h>
30
31 #include <asm/unaligned.h>
32
33 #include <net/nfc/hci.h>
34 #include <net/nfc/llc.h>
35 #include <net/nfc/nfc.h>
36
37 #include "pn544.h"
38
39 #define PN544_I2C_FRAME_HEADROOM 1
40 #define PN544_I2C_FRAME_TAILROOM 2
41
42 /* GPIO names */
43 #define PN544_GPIO_NAME_IRQ "pn544_irq"
44 #define PN544_GPIO_NAME_FW "pn544_fw"
45 #define PN544_GPIO_NAME_EN "pn544_en"
46
47 /* framing in HCI mode */
48 #define PN544_HCI_I2C_LLC_LEN 1
49 #define PN544_HCI_I2C_LLC_CRC 2
50 #define PN544_HCI_I2C_LLC_LEN_CRC (PN544_HCI_I2C_LLC_LEN + \
51 PN544_HCI_I2C_LLC_CRC)
52 #define PN544_HCI_I2C_LLC_MIN_SIZE (1 + PN544_HCI_I2C_LLC_LEN_CRC)
53 #define PN544_HCI_I2C_LLC_MAX_PAYLOAD 29
54 #define PN544_HCI_I2C_LLC_MAX_SIZE (PN544_HCI_I2C_LLC_LEN_CRC + 1 + \
55 PN544_HCI_I2C_LLC_MAX_PAYLOAD)
56
57 static const struct i2c_device_id pn544_hci_i2c_id_table[] = {
58 {"pn544", 0},
59 {}
60 };
61
62 MODULE_DEVICE_TABLE(i2c, pn544_hci_i2c_id_table);
63
64 static const struct acpi_device_id pn544_hci_i2c_acpi_match[] = {
65 {"NXP5440", 0},
66 {}
67 };
68
69 MODULE_DEVICE_TABLE(acpi, pn544_hci_i2c_acpi_match);
70
71 #define PN544_HCI_I2C_DRIVER_NAME "pn544_hci_i2c"
72
73 /*
74 * Exposed through the 4 most significant bytes
75 * from the HCI SW_VERSION first byte, a.k.a.
76 * SW RomLib.
77 */
78 #define PN544_HW_VARIANT_C2 0xa
79 #define PN544_HW_VARIANT_C3 0xb
80
81 #define PN544_FW_CMD_RESET 0x01
82 #define PN544_FW_CMD_WRITE 0x08
83 #define PN544_FW_CMD_CHECK 0x06
84 #define PN544_FW_CMD_SECURE_WRITE 0x0C
85 #define PN544_FW_CMD_SECURE_CHUNK_WRITE 0x0D
86
87 struct pn544_i2c_fw_frame_write {
88 u8 cmd;
89 u16 be_length;
90 u8 be_dest_addr[3];
91 u16 be_datalen;
92 u8 data[];
93 } __packed;
94
95 struct pn544_i2c_fw_frame_check {
96 u8 cmd;
97 u16 be_length;
98 u8 be_start_addr[3];
99 u16 be_datalen;
100 u16 be_crc;
101 } __packed;
102
103 struct pn544_i2c_fw_frame_response {
104 u8 status;
105 u16 be_length;
106 } __packed;
107
108 struct pn544_i2c_fw_blob {
109 u32 be_size;
110 u32 be_destaddr;
111 u8 data[];
112 };
113
114 struct pn544_i2c_fw_secure_frame {
115 u8 cmd;
116 u16 be_datalen;
117 u8 data[];
118 } __packed;
119
120 struct pn544_i2c_fw_secure_blob {
121 u64 header;
122 u8 data[];
123 };
124
125 #define PN544_FW_CMD_RESULT_TIMEOUT 0x01
126 #define PN544_FW_CMD_RESULT_BAD_CRC 0x02
127 #define PN544_FW_CMD_RESULT_ACCESS_DENIED 0x08
128 #define PN544_FW_CMD_RESULT_PROTOCOL_ERROR 0x0B
129 #define PN544_FW_CMD_RESULT_INVALID_PARAMETER 0x11
130 #define PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND 0x13
131 #define PN544_FW_CMD_RESULT_INVALID_LENGTH 0x18
132 #define PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR 0x19
133 #define PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR 0x1D
134 #define PN544_FW_CMD_RESULT_MEMORY_ERROR 0x20
135 #define PN544_FW_CMD_RESULT_CHUNK_OK 0x21
136 #define PN544_FW_CMD_RESULT_WRITE_FAILED 0x74
137 #define PN544_FW_CMD_RESULT_COMMAND_REJECTED 0xE0
138 #define PN544_FW_CMD_RESULT_CHUNK_ERROR 0xE6
139
140 #define MIN(X, Y) ((X) < (Y) ? (X) : (Y))
141
142 #define PN544_FW_WRITE_BUFFER_MAX_LEN 0x9f7
143 #define PN544_FW_I2C_MAX_PAYLOAD PN544_HCI_I2C_LLC_MAX_SIZE
144 #define PN544_FW_I2C_WRITE_FRAME_HEADER_LEN 8
145 #define PN544_FW_I2C_WRITE_DATA_MAX_LEN MIN((PN544_FW_I2C_MAX_PAYLOAD -\
146 PN544_FW_I2C_WRITE_FRAME_HEADER_LEN),\
147 PN544_FW_WRITE_BUFFER_MAX_LEN)
148 #define PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN 3
149 #define PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN (PN544_FW_I2C_MAX_PAYLOAD -\
150 PN544_FW_SECURE_CHUNK_WRITE_HEADER_LEN)
151 #define PN544_FW_SECURE_FRAME_HEADER_LEN 3
152 #define PN544_FW_SECURE_BLOB_HEADER_LEN 8
153
154 #define FW_WORK_STATE_IDLE 1
155 #define FW_WORK_STATE_START 2
156 #define FW_WORK_STATE_WAIT_WRITE_ANSWER 3
157 #define FW_WORK_STATE_WAIT_CHECK_ANSWER 4
158 #define FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER 5
159
160 struct pn544_i2c_phy {
161 struct i2c_client *i2c_dev;
162 struct nfc_hci_dev *hdev;
163
164 struct gpio_desc *gpiod_en;
165 struct gpio_desc *gpiod_fw;
166
167 unsigned int en_polarity;
168
169 u8 hw_variant;
170
171 struct work_struct fw_work;
172 int fw_work_state;
173 char firmware_name[NFC_FIRMWARE_NAME_MAXSIZE + 1];
174 const struct firmware *fw;
175 u32 fw_blob_dest_addr;
176 size_t fw_blob_size;
177 const u8 *fw_blob_data;
178 size_t fw_written;
179 size_t fw_size;
180
181 int fw_cmd_result;
182
183 int powered;
184 int run_mode;
185
186 int hard_fault; /*
187 * < 0 if hardware error occured (e.g. i2c err)
188 * and prevents normal operation.
189 */
190 };
191
192 #define I2C_DUMP_SKB(info, skb) \
193 do { \
194 pr_debug("%s:\n", info); \
195 print_hex_dump(KERN_DEBUG, "i2c: ", DUMP_PREFIX_OFFSET, \
196 16, 1, (skb)->data, (skb)->len, 0); \
197 } while (0)
198
pn544_hci_i2c_platform_init(struct pn544_i2c_phy * phy)199 static void pn544_hci_i2c_platform_init(struct pn544_i2c_phy *phy)
200 {
201 int polarity, retry, ret;
202 char rset_cmd[] = { 0x05, 0xF9, 0x04, 0x00, 0xC3, 0xE5 };
203 int count = sizeof(rset_cmd);
204
205 nfc_info(&phy->i2c_dev->dev, "Detecting nfc_en polarity\n");
206
207 /* Disable fw download */
208 gpiod_set_value_cansleep(phy->gpiod_fw, 0);
209
210 for (polarity = 0; polarity < 2; polarity++) {
211 phy->en_polarity = polarity;
212 retry = 3;
213 while (retry--) {
214 /* power off */
215 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
216 usleep_range(10000, 15000);
217
218 /* power on */
219 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
220 usleep_range(10000, 15000);
221
222 /* send reset */
223 dev_dbg(&phy->i2c_dev->dev, "Sending reset cmd\n");
224 ret = i2c_master_send(phy->i2c_dev, rset_cmd, count);
225 if (ret == count) {
226 nfc_info(&phy->i2c_dev->dev,
227 "nfc_en polarity : active %s\n",
228 (polarity == 0 ? "low" : "high"));
229 goto out;
230 }
231 }
232 }
233
234 nfc_err(&phy->i2c_dev->dev,
235 "Could not detect nfc_en polarity, fallback to active high\n");
236
237 out:
238 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
239 usleep_range(10000, 15000);
240 }
241
pn544_hci_i2c_enable_mode(struct pn544_i2c_phy * phy,int run_mode)242 static void pn544_hci_i2c_enable_mode(struct pn544_i2c_phy *phy, int run_mode)
243 {
244 gpiod_set_value_cansleep(phy->gpiod_fw, run_mode == PN544_FW_MODE ? 1 : 0);
245 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
246 usleep_range(10000, 15000);
247
248 phy->run_mode = run_mode;
249 }
250
pn544_hci_i2c_enable(void * phy_id)251 static int pn544_hci_i2c_enable(void *phy_id)
252 {
253 struct pn544_i2c_phy *phy = phy_id;
254
255 pr_info("%s\n", __func__);
256
257 pn544_hci_i2c_enable_mode(phy, PN544_HCI_MODE);
258
259 phy->powered = 1;
260
261 return 0;
262 }
263
pn544_hci_i2c_disable(void * phy_id)264 static void pn544_hci_i2c_disable(void *phy_id)
265 {
266 struct pn544_i2c_phy *phy = phy_id;
267
268 gpiod_set_value_cansleep(phy->gpiod_fw, 0);
269 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
270 usleep_range(10000, 15000);
271
272 gpiod_set_value_cansleep(phy->gpiod_en, phy->en_polarity);
273 usleep_range(10000, 15000);
274
275 gpiod_set_value_cansleep(phy->gpiod_en, !phy->en_polarity);
276 usleep_range(10000, 15000);
277
278 phy->powered = 0;
279 }
280
pn544_hci_i2c_add_len_crc(struct sk_buff * skb)281 static void pn544_hci_i2c_add_len_crc(struct sk_buff *skb)
282 {
283 u16 crc;
284 int len;
285
286 len = skb->len + 2;
287 *(u8 *)skb_push(skb, 1) = len;
288
289 crc = crc_ccitt(0xffff, skb->data, skb->len);
290 crc = ~crc;
291 skb_put_u8(skb, crc & 0xff);
292 skb_put_u8(skb, crc >> 8);
293 }
294
pn544_hci_i2c_remove_len_crc(struct sk_buff * skb)295 static void pn544_hci_i2c_remove_len_crc(struct sk_buff *skb)
296 {
297 skb_pull(skb, PN544_I2C_FRAME_HEADROOM);
298 skb_trim(skb, PN544_I2C_FRAME_TAILROOM);
299 }
300
301 /*
302 * Writing a frame must not return the number of written bytes.
303 * It must return either zero for success, or <0 for error.
304 * In addition, it must not alter the skb
305 */
pn544_hci_i2c_write(void * phy_id,struct sk_buff * skb)306 static int pn544_hci_i2c_write(void *phy_id, struct sk_buff *skb)
307 {
308 int r;
309 struct pn544_i2c_phy *phy = phy_id;
310 struct i2c_client *client = phy->i2c_dev;
311
312 if (phy->hard_fault != 0)
313 return phy->hard_fault;
314
315 usleep_range(3000, 6000);
316
317 pn544_hci_i2c_add_len_crc(skb);
318
319 I2C_DUMP_SKB("i2c frame written", skb);
320
321 r = i2c_master_send(client, skb->data, skb->len);
322
323 if (r == -EREMOTEIO) { /* Retry, chip was in standby */
324 usleep_range(6000, 10000);
325 r = i2c_master_send(client, skb->data, skb->len);
326 }
327
328 if (r >= 0) {
329 if (r != skb->len)
330 r = -EREMOTEIO;
331 else
332 r = 0;
333 }
334
335 pn544_hci_i2c_remove_len_crc(skb);
336
337 return r;
338 }
339
check_crc(u8 * buf,int buflen)340 static int check_crc(u8 *buf, int buflen)
341 {
342 int len;
343 u16 crc;
344
345 len = buf[0] + 1;
346 crc = crc_ccitt(0xffff, buf, len - 2);
347 crc = ~crc;
348
349 if (buf[len - 2] != (crc & 0xff) || buf[len - 1] != (crc >> 8)) {
350 pr_err("CRC error 0x%x != 0x%x 0x%x\n",
351 crc, buf[len - 1], buf[len - 2]);
352 pr_info("%s: BAD CRC\n", __func__);
353 print_hex_dump(KERN_DEBUG, "crc: ", DUMP_PREFIX_NONE,
354 16, 2, buf, buflen, false);
355 return -EPERM;
356 }
357 return 0;
358 }
359
360 /*
361 * Reads an shdlc frame and returns it in a newly allocated sk_buff. Guarantees
362 * that i2c bus will be flushed and that next read will start on a new frame.
363 * returned skb contains only LLC header and payload.
364 * returns:
365 * -EREMOTEIO : i2c read error (fatal)
366 * -EBADMSG : frame was incorrect and discarded
367 * -ENOMEM : cannot allocate skb, frame dropped
368 */
pn544_hci_i2c_read(struct pn544_i2c_phy * phy,struct sk_buff ** skb)369 static int pn544_hci_i2c_read(struct pn544_i2c_phy *phy, struct sk_buff **skb)
370 {
371 int r;
372 u8 len;
373 u8 tmp[PN544_HCI_I2C_LLC_MAX_SIZE - 1];
374 struct i2c_client *client = phy->i2c_dev;
375
376 r = i2c_master_recv(client, &len, 1);
377 if (r != 1) {
378 nfc_err(&client->dev, "cannot read len byte\n");
379 return -EREMOTEIO;
380 }
381
382 if ((len < (PN544_HCI_I2C_LLC_MIN_SIZE - 1)) ||
383 (len > (PN544_HCI_I2C_LLC_MAX_SIZE - 1))) {
384 nfc_err(&client->dev, "invalid len byte\n");
385 r = -EBADMSG;
386 goto flush;
387 }
388
389 *skb = alloc_skb(1 + len, GFP_KERNEL);
390 if (*skb == NULL) {
391 r = -ENOMEM;
392 goto flush;
393 }
394
395 skb_put_u8(*skb, len);
396
397 r = i2c_master_recv(client, skb_put(*skb, len), len);
398 if (r != len) {
399 kfree_skb(*skb);
400 return -EREMOTEIO;
401 }
402
403 I2C_DUMP_SKB("i2c frame read", *skb);
404
405 r = check_crc((*skb)->data, (*skb)->len);
406 if (r != 0) {
407 kfree_skb(*skb);
408 r = -EBADMSG;
409 goto flush;
410 }
411
412 skb_pull(*skb, 1);
413 skb_trim(*skb, (*skb)->len - 2);
414
415 usleep_range(3000, 6000);
416
417 return 0;
418
419 flush:
420 if (i2c_master_recv(client, tmp, sizeof(tmp)) < 0)
421 r = -EREMOTEIO;
422
423 usleep_range(3000, 6000);
424
425 return r;
426 }
427
pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy * phy)428 static int pn544_hci_i2c_fw_read_status(struct pn544_i2c_phy *phy)
429 {
430 int r;
431 struct pn544_i2c_fw_frame_response response;
432 struct i2c_client *client = phy->i2c_dev;
433
434 r = i2c_master_recv(client, (char *) &response, sizeof(response));
435 if (r != sizeof(response)) {
436 nfc_err(&client->dev, "cannot read fw status\n");
437 return -EIO;
438 }
439
440 usleep_range(3000, 6000);
441
442 switch (response.status) {
443 case 0:
444 return 0;
445 case PN544_FW_CMD_RESULT_CHUNK_OK:
446 return response.status;
447 case PN544_FW_CMD_RESULT_TIMEOUT:
448 return -ETIMEDOUT;
449 case PN544_FW_CMD_RESULT_BAD_CRC:
450 return -ENODATA;
451 case PN544_FW_CMD_RESULT_ACCESS_DENIED:
452 return -EACCES;
453 case PN544_FW_CMD_RESULT_PROTOCOL_ERROR:
454 return -EPROTO;
455 case PN544_FW_CMD_RESULT_INVALID_PARAMETER:
456 return -EINVAL;
457 case PN544_FW_CMD_RESULT_UNSUPPORTED_COMMAND:
458 return -ENOTSUPP;
459 case PN544_FW_CMD_RESULT_INVALID_LENGTH:
460 return -EBADMSG;
461 case PN544_FW_CMD_RESULT_CRYPTOGRAPHIC_ERROR:
462 return -ENOKEY;
463 case PN544_FW_CMD_RESULT_VERSION_CONDITIONS_ERROR:
464 return -EINVAL;
465 case PN544_FW_CMD_RESULT_MEMORY_ERROR:
466 return -ENOMEM;
467 case PN544_FW_CMD_RESULT_COMMAND_REJECTED:
468 return -EACCES;
469 case PN544_FW_CMD_RESULT_WRITE_FAILED:
470 case PN544_FW_CMD_RESULT_CHUNK_ERROR:
471 return -EIO;
472 default:
473 return -EIO;
474 }
475 }
476
477 /*
478 * Reads an shdlc frame from the chip. This is not as straightforward as it
479 * seems. There are cases where we could loose the frame start synchronization.
480 * The frame format is len-data-crc, and corruption can occur anywhere while
481 * transiting on i2c bus, such that we could read an invalid len.
482 * In order to recover synchronization with the next frame, we must be sure
483 * to read the real amount of data without using the len byte. We do this by
484 * assuming the following:
485 * - the chip will always present only one single complete frame on the bus
486 * before triggering the interrupt
487 * - the chip will not present a new frame until we have completely read
488 * the previous one (or until we have handled the interrupt).
489 * The tricky case is when we read a corrupted len that is less than the real
490 * len. We must detect this here in order to determine that we need to flush
491 * the bus. This is the reason why we check the crc here.
492 */
pn544_hci_i2c_irq_thread_fn(int irq,void * phy_id)493 static irqreturn_t pn544_hci_i2c_irq_thread_fn(int irq, void *phy_id)
494 {
495 struct pn544_i2c_phy *phy = phy_id;
496 struct i2c_client *client;
497 struct sk_buff *skb = NULL;
498 int r;
499
500 if (!phy || irq != phy->i2c_dev->irq) {
501 WARN_ON_ONCE(1);
502 return IRQ_NONE;
503 }
504
505 client = phy->i2c_dev;
506 dev_dbg(&client->dev, "IRQ\n");
507
508 if (phy->hard_fault != 0)
509 return IRQ_HANDLED;
510
511 if (phy->run_mode == PN544_FW_MODE) {
512 phy->fw_cmd_result = pn544_hci_i2c_fw_read_status(phy);
513 schedule_work(&phy->fw_work);
514 } else {
515 r = pn544_hci_i2c_read(phy, &skb);
516 if (r == -EREMOTEIO) {
517 phy->hard_fault = r;
518
519 nfc_hci_recv_frame(phy->hdev, NULL);
520
521 return IRQ_HANDLED;
522 } else if ((r == -ENOMEM) || (r == -EBADMSG)) {
523 return IRQ_HANDLED;
524 }
525
526 nfc_hci_recv_frame(phy->hdev, skb);
527 }
528 return IRQ_HANDLED;
529 }
530
531 static struct nfc_phy_ops i2c_phy_ops = {
532 .write = pn544_hci_i2c_write,
533 .enable = pn544_hci_i2c_enable,
534 .disable = pn544_hci_i2c_disable,
535 };
536
pn544_hci_i2c_fw_download(void * phy_id,const char * firmware_name,u8 hw_variant)537 static int pn544_hci_i2c_fw_download(void *phy_id, const char *firmware_name,
538 u8 hw_variant)
539 {
540 struct pn544_i2c_phy *phy = phy_id;
541
542 pr_info("Starting Firmware Download (%s)\n", firmware_name);
543
544 strcpy(phy->firmware_name, firmware_name);
545
546 phy->hw_variant = hw_variant;
547 phy->fw_work_state = FW_WORK_STATE_START;
548
549 schedule_work(&phy->fw_work);
550
551 return 0;
552 }
553
pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy * phy,int result)554 static void pn544_hci_i2c_fw_work_complete(struct pn544_i2c_phy *phy,
555 int result)
556 {
557 pr_info("Firmware Download Complete, result=%d\n", result);
558
559 pn544_hci_i2c_disable(phy);
560
561 phy->fw_work_state = FW_WORK_STATE_IDLE;
562
563 if (phy->fw) {
564 release_firmware(phy->fw);
565 phy->fw = NULL;
566 }
567
568 nfc_fw_download_done(phy->hdev->ndev, phy->firmware_name, (u32) -result);
569 }
570
pn544_hci_i2c_fw_write_cmd(struct i2c_client * client,u32 dest_addr,const u8 * data,u16 datalen)571 static int pn544_hci_i2c_fw_write_cmd(struct i2c_client *client, u32 dest_addr,
572 const u8 *data, u16 datalen)
573 {
574 u8 frame[PN544_FW_I2C_MAX_PAYLOAD];
575 struct pn544_i2c_fw_frame_write *framep;
576 u16 params_len;
577 int framelen;
578 int r;
579
580 if (datalen > PN544_FW_I2C_WRITE_DATA_MAX_LEN)
581 datalen = PN544_FW_I2C_WRITE_DATA_MAX_LEN;
582
583 framep = (struct pn544_i2c_fw_frame_write *) frame;
584
585 params_len = sizeof(framep->be_dest_addr) +
586 sizeof(framep->be_datalen) + datalen;
587 framelen = params_len + sizeof(framep->cmd) +
588 sizeof(framep->be_length);
589
590 framep->cmd = PN544_FW_CMD_WRITE;
591
592 put_unaligned_be16(params_len, &framep->be_length);
593
594 framep->be_dest_addr[0] = (dest_addr & 0xff0000) >> 16;
595 framep->be_dest_addr[1] = (dest_addr & 0xff00) >> 8;
596 framep->be_dest_addr[2] = dest_addr & 0xff;
597
598 put_unaligned_be16(datalen, &framep->be_datalen);
599
600 memcpy(framep->data, data, datalen);
601
602 r = i2c_master_send(client, frame, framelen);
603
604 if (r == framelen)
605 return datalen;
606 else if (r < 0)
607 return r;
608 else
609 return -EIO;
610 }
611
pn544_hci_i2c_fw_check_cmd(struct i2c_client * client,u32 start_addr,const u8 * data,u16 datalen)612 static int pn544_hci_i2c_fw_check_cmd(struct i2c_client *client, u32 start_addr,
613 const u8 *data, u16 datalen)
614 {
615 struct pn544_i2c_fw_frame_check frame;
616 int r;
617 u16 crc;
618
619 /* calculate local crc for the data we want to check */
620 crc = crc_ccitt(0xffff, data, datalen);
621
622 frame.cmd = PN544_FW_CMD_CHECK;
623
624 put_unaligned_be16(sizeof(frame.be_start_addr) +
625 sizeof(frame.be_datalen) + sizeof(frame.be_crc),
626 &frame.be_length);
627
628 /* tell the chip the memory region to which our crc applies */
629 frame.be_start_addr[0] = (start_addr & 0xff0000) >> 16;
630 frame.be_start_addr[1] = (start_addr & 0xff00) >> 8;
631 frame.be_start_addr[2] = start_addr & 0xff;
632
633 put_unaligned_be16(datalen, &frame.be_datalen);
634
635 /*
636 * and give our local crc. Chip will calculate its own crc for the
637 * region and compare with ours.
638 */
639 put_unaligned_be16(crc, &frame.be_crc);
640
641 r = i2c_master_send(client, (const char *) &frame, sizeof(frame));
642
643 if (r == sizeof(frame))
644 return 0;
645 else if (r < 0)
646 return r;
647 else
648 return -EIO;
649 }
650
pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy * phy)651 static int pn544_hci_i2c_fw_write_chunk(struct pn544_i2c_phy *phy)
652 {
653 int r;
654
655 r = pn544_hci_i2c_fw_write_cmd(phy->i2c_dev,
656 phy->fw_blob_dest_addr + phy->fw_written,
657 phy->fw_blob_data + phy->fw_written,
658 phy->fw_blob_size - phy->fw_written);
659 if (r < 0)
660 return r;
661
662 phy->fw_written += r;
663 phy->fw_work_state = FW_WORK_STATE_WAIT_WRITE_ANSWER;
664
665 return 0;
666 }
667
pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy * phy,const u8 * data,u16 datalen)668 static int pn544_hci_i2c_fw_secure_write_frame_cmd(struct pn544_i2c_phy *phy,
669 const u8 *data, u16 datalen)
670 {
671 u8 buf[PN544_FW_I2C_MAX_PAYLOAD];
672 struct pn544_i2c_fw_secure_frame *chunk;
673 int chunklen;
674 int r;
675
676 if (datalen > PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN)
677 datalen = PN544_FW_SECURE_CHUNK_WRITE_DATA_MAX_LEN;
678
679 chunk = (struct pn544_i2c_fw_secure_frame *) buf;
680
681 chunk->cmd = PN544_FW_CMD_SECURE_CHUNK_WRITE;
682
683 put_unaligned_be16(datalen, &chunk->be_datalen);
684
685 memcpy(chunk->data, data, datalen);
686
687 chunklen = sizeof(chunk->cmd) + sizeof(chunk->be_datalen) + datalen;
688
689 r = i2c_master_send(phy->i2c_dev, buf, chunklen);
690
691 if (r == chunklen)
692 return datalen;
693 else if (r < 0)
694 return r;
695 else
696 return -EIO;
697
698 }
699
pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy * phy)700 static int pn544_hci_i2c_fw_secure_write_frame(struct pn544_i2c_phy *phy)
701 {
702 struct pn544_i2c_fw_secure_frame *framep;
703 int r;
704
705 framep = (struct pn544_i2c_fw_secure_frame *) phy->fw_blob_data;
706 if (phy->fw_written == 0)
707 phy->fw_blob_size = get_unaligned_be16(&framep->be_datalen)
708 + PN544_FW_SECURE_FRAME_HEADER_LEN;
709
710 /* Only secure write command can be chunked*/
711 if (phy->fw_blob_size > PN544_FW_I2C_MAX_PAYLOAD &&
712 framep->cmd != PN544_FW_CMD_SECURE_WRITE)
713 return -EINVAL;
714
715 /* The firmware also have other commands, we just send them directly */
716 if (phy->fw_blob_size < PN544_FW_I2C_MAX_PAYLOAD) {
717 r = i2c_master_send(phy->i2c_dev,
718 (const char *) phy->fw_blob_data, phy->fw_blob_size);
719
720 if (r == phy->fw_blob_size)
721 goto exit;
722 else if (r < 0)
723 return r;
724 else
725 return -EIO;
726 }
727
728 r = pn544_hci_i2c_fw_secure_write_frame_cmd(phy,
729 phy->fw_blob_data + phy->fw_written,
730 phy->fw_blob_size - phy->fw_written);
731 if (r < 0)
732 return r;
733
734 exit:
735 phy->fw_written += r;
736 phy->fw_work_state = FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER;
737
738 /* SW reset command will not trig any response from PN544 */
739 if (framep->cmd == PN544_FW_CMD_RESET) {
740 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
741 phy->fw_cmd_result = 0;
742 schedule_work(&phy->fw_work);
743 }
744
745 return 0;
746 }
747
pn544_hci_i2c_fw_work(struct work_struct * work)748 static void pn544_hci_i2c_fw_work(struct work_struct *work)
749 {
750 struct pn544_i2c_phy *phy = container_of(work, struct pn544_i2c_phy,
751 fw_work);
752 int r;
753 struct pn544_i2c_fw_blob *blob;
754 struct pn544_i2c_fw_secure_blob *secure_blob;
755
756 switch (phy->fw_work_state) {
757 case FW_WORK_STATE_START:
758 pn544_hci_i2c_enable_mode(phy, PN544_FW_MODE);
759
760 r = request_firmware(&phy->fw, phy->firmware_name,
761 &phy->i2c_dev->dev);
762 if (r < 0)
763 goto exit_state_start;
764
765 phy->fw_written = 0;
766
767 switch (phy->hw_variant) {
768 case PN544_HW_VARIANT_C2:
769 blob = (struct pn544_i2c_fw_blob *) phy->fw->data;
770 phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
771 phy->fw_blob_dest_addr = get_unaligned_be32(
772 &blob->be_destaddr);
773 phy->fw_blob_data = blob->data;
774
775 r = pn544_hci_i2c_fw_write_chunk(phy);
776 break;
777 case PN544_HW_VARIANT_C3:
778 secure_blob = (struct pn544_i2c_fw_secure_blob *)
779 phy->fw->data;
780 phy->fw_blob_data = secure_blob->data;
781 phy->fw_size = phy->fw->size;
782 r = pn544_hci_i2c_fw_secure_write_frame(phy);
783 break;
784 default:
785 r = -ENOTSUPP;
786 break;
787 }
788
789 exit_state_start:
790 if (r < 0)
791 pn544_hci_i2c_fw_work_complete(phy, r);
792 break;
793
794 case FW_WORK_STATE_WAIT_WRITE_ANSWER:
795 r = phy->fw_cmd_result;
796 if (r < 0)
797 goto exit_state_wait_write_answer;
798
799 if (phy->fw_written == phy->fw_blob_size) {
800 r = pn544_hci_i2c_fw_check_cmd(phy->i2c_dev,
801 phy->fw_blob_dest_addr,
802 phy->fw_blob_data,
803 phy->fw_blob_size);
804 if (r < 0)
805 goto exit_state_wait_write_answer;
806 phy->fw_work_state = FW_WORK_STATE_WAIT_CHECK_ANSWER;
807 break;
808 }
809
810 r = pn544_hci_i2c_fw_write_chunk(phy);
811
812 exit_state_wait_write_answer:
813 if (r < 0)
814 pn544_hci_i2c_fw_work_complete(phy, r);
815 break;
816
817 case FW_WORK_STATE_WAIT_CHECK_ANSWER:
818 r = phy->fw_cmd_result;
819 if (r < 0)
820 goto exit_state_wait_check_answer;
821
822 blob = (struct pn544_i2c_fw_blob *) (phy->fw_blob_data +
823 phy->fw_blob_size);
824 phy->fw_blob_size = get_unaligned_be32(&blob->be_size);
825 if (phy->fw_blob_size != 0) {
826 phy->fw_blob_dest_addr =
827 get_unaligned_be32(&blob->be_destaddr);
828 phy->fw_blob_data = blob->data;
829
830 phy->fw_written = 0;
831 r = pn544_hci_i2c_fw_write_chunk(phy);
832 }
833
834 exit_state_wait_check_answer:
835 if (r < 0 || phy->fw_blob_size == 0)
836 pn544_hci_i2c_fw_work_complete(phy, r);
837 break;
838
839 case FW_WORK_STATE_WAIT_SECURE_WRITE_ANSWER:
840 r = phy->fw_cmd_result;
841 if (r < 0)
842 goto exit_state_wait_secure_write_answer;
843
844 if (r == PN544_FW_CMD_RESULT_CHUNK_OK) {
845 r = pn544_hci_i2c_fw_secure_write_frame(phy);
846 goto exit_state_wait_secure_write_answer;
847 }
848
849 if (phy->fw_written == phy->fw_blob_size) {
850 secure_blob = (struct pn544_i2c_fw_secure_blob *)
851 (phy->fw_blob_data + phy->fw_blob_size);
852 phy->fw_size -= phy->fw_blob_size +
853 PN544_FW_SECURE_BLOB_HEADER_LEN;
854 if (phy->fw_size >= PN544_FW_SECURE_BLOB_HEADER_LEN
855 + PN544_FW_SECURE_FRAME_HEADER_LEN) {
856 phy->fw_blob_data = secure_blob->data;
857
858 phy->fw_written = 0;
859 r = pn544_hci_i2c_fw_secure_write_frame(phy);
860 }
861 }
862
863 exit_state_wait_secure_write_answer:
864 if (r < 0 || phy->fw_size == 0)
865 pn544_hci_i2c_fw_work_complete(phy, r);
866 break;
867
868 default:
869 break;
870 }
871 }
872
873 static const struct acpi_gpio_params enable_gpios = { 1, 0, false };
874 static const struct acpi_gpio_params firmware_gpios = { 2, 0, false };
875
876 static const struct acpi_gpio_mapping acpi_pn544_gpios[] = {
877 { "enable-gpios", &enable_gpios, 1 },
878 { "firmware-gpios", &firmware_gpios, 1 },
879 { },
880 };
881
pn544_hci_i2c_probe(struct i2c_client * client,const struct i2c_device_id * id)882 static int pn544_hci_i2c_probe(struct i2c_client *client,
883 const struct i2c_device_id *id)
884 {
885 struct device *dev = &client->dev;
886 struct pn544_i2c_phy *phy;
887 int r = 0;
888
889 dev_dbg(&client->dev, "%s\n", __func__);
890 dev_dbg(&client->dev, "IRQ: %d\n", client->irq);
891
892 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
893 nfc_err(&client->dev, "Need I2C_FUNC_I2C\n");
894 return -ENODEV;
895 }
896
897 phy = devm_kzalloc(&client->dev, sizeof(struct pn544_i2c_phy),
898 GFP_KERNEL);
899 if (!phy)
900 return -ENOMEM;
901
902 INIT_WORK(&phy->fw_work, pn544_hci_i2c_fw_work);
903 phy->fw_work_state = FW_WORK_STATE_IDLE;
904
905 phy->i2c_dev = client;
906 i2c_set_clientdata(client, phy);
907
908 r = devm_acpi_dev_add_driver_gpios(dev, acpi_pn544_gpios);
909 if (r)
910 dev_dbg(dev, "Unable to add GPIO mapping table\n");
911
912 /* Get EN GPIO */
913 phy->gpiod_en = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW);
914 if (IS_ERR(phy->gpiod_en)) {
915 nfc_err(dev, "Unable to get EN GPIO\n");
916 return PTR_ERR(phy->gpiod_en);
917 }
918
919 /* Get FW GPIO */
920 phy->gpiod_fw = devm_gpiod_get(dev, "firmware", GPIOD_OUT_LOW);
921 if (IS_ERR(phy->gpiod_fw)) {
922 nfc_err(dev, "Unable to get FW GPIO\n");
923 return PTR_ERR(phy->gpiod_fw);
924 }
925
926 pn544_hci_i2c_platform_init(phy);
927
928 r = devm_request_threaded_irq(&client->dev, client->irq, NULL,
929 pn544_hci_i2c_irq_thread_fn,
930 IRQF_TRIGGER_RISING | IRQF_ONESHOT,
931 PN544_HCI_I2C_DRIVER_NAME, phy);
932 if (r < 0) {
933 nfc_err(&client->dev, "Unable to register IRQ handler\n");
934 return r;
935 }
936
937 r = pn544_hci_probe(phy, &i2c_phy_ops, LLC_SHDLC_NAME,
938 PN544_I2C_FRAME_HEADROOM, PN544_I2C_FRAME_TAILROOM,
939 PN544_HCI_I2C_LLC_MAX_PAYLOAD,
940 pn544_hci_i2c_fw_download, &phy->hdev);
941 if (r < 0)
942 return r;
943
944 return 0;
945 }
946
pn544_hci_i2c_remove(struct i2c_client * client)947 static int pn544_hci_i2c_remove(struct i2c_client *client)
948 {
949 struct pn544_i2c_phy *phy = i2c_get_clientdata(client);
950
951 dev_dbg(&client->dev, "%s\n", __func__);
952
953 cancel_work_sync(&phy->fw_work);
954 if (phy->fw_work_state != FW_WORK_STATE_IDLE)
955 pn544_hci_i2c_fw_work_complete(phy, -ENODEV);
956
957 pn544_hci_remove(phy->hdev);
958
959 if (phy->powered)
960 pn544_hci_i2c_disable(phy);
961
962 return 0;
963 }
964
965 static const struct of_device_id of_pn544_i2c_match[] = {
966 { .compatible = "nxp,pn544-i2c", },
967 {},
968 };
969 MODULE_DEVICE_TABLE(of, of_pn544_i2c_match);
970
971 static struct i2c_driver pn544_hci_i2c_driver = {
972 .driver = {
973 .name = PN544_HCI_I2C_DRIVER_NAME,
974 .of_match_table = of_match_ptr(of_pn544_i2c_match),
975 .acpi_match_table = ACPI_PTR(pn544_hci_i2c_acpi_match),
976 },
977 .probe = pn544_hci_i2c_probe,
978 .id_table = pn544_hci_i2c_id_table,
979 .remove = pn544_hci_i2c_remove,
980 };
981
982 module_i2c_driver(pn544_hci_i2c_driver);
983
984 MODULE_LICENSE("GPL");
985 MODULE_DESCRIPTION(DRIVER_DESC);
986