1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * PCIe host controller driver for Freescale i.MX6 SoCs
4 *
5 * Copyright (C) 2013 Kosagi
6 * http://www.kosagi.com
7 *
8 * Author: Sean Cross <xobs@kosagi.com>
9 */
10
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/gpio.h>
14 #include <linux/kernel.h>
15 #include <linux/mfd/syscon.h>
16 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
17 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
18 #include <linux/module.h>
19 #include <linux/of_gpio.h>
20 #include <linux/of_device.h>
21 #include <linux/pci.h>
22 #include <linux/platform_device.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
25 #include <linux/resource.h>
26 #include <linux/signal.h>
27 #include <linux/types.h>
28 #include <linux/interrupt.h>
29 #include <linux/reset.h>
30
31 #include "pcie-designware.h"
32
33 #define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
34
35 enum imx6_pcie_variants {
36 IMX6Q,
37 IMX6SX,
38 IMX6QP,
39 IMX7D,
40 };
41
42 struct imx6_pcie {
43 struct dw_pcie *pci;
44 int reset_gpio;
45 bool gpio_active_high;
46 struct clk *pcie_bus;
47 struct clk *pcie_phy;
48 struct clk *pcie_inbound_axi;
49 struct clk *pcie;
50 struct regmap *iomuxc_gpr;
51 struct reset_control *pciephy_reset;
52 struct reset_control *apps_reset;
53 enum imx6_pcie_variants variant;
54 u32 tx_deemph_gen1;
55 u32 tx_deemph_gen2_3p5db;
56 u32 tx_deemph_gen2_6db;
57 u32 tx_swing_full;
58 u32 tx_swing_low;
59 int link_gen;
60 struct regulator *vpcie;
61 };
62
63 /* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
64 #define PHY_PLL_LOCK_WAIT_MAX_RETRIES 2000
65 #define PHY_PLL_LOCK_WAIT_USLEEP_MIN 50
66 #define PHY_PLL_LOCK_WAIT_USLEEP_MAX 200
67
68 /* PCIe Root Complex registers (memory-mapped) */
69 #define PCIE_RC_IMX6_MSI_CAP 0x50
70 #define PCIE_RC_LCR 0x7c
71 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1 0x1
72 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2 0x2
73 #define PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK 0xf
74
75 #define PCIE_RC_LCSR 0x80
76
77 /* PCIe Port Logic registers (memory-mapped) */
78 #define PL_OFFSET 0x700
79 #define PCIE_PL_PFLR (PL_OFFSET + 0x08)
80 #define PCIE_PL_PFLR_LINK_STATE_MASK (0x3f << 16)
81 #define PCIE_PL_PFLR_FORCE_LINK (1 << 15)
82 #define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28)
83 #define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c)
84
85 #define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
86 #define PCIE_PHY_CTRL_DATA_LOC 0
87 #define PCIE_PHY_CTRL_CAP_ADR_LOC 16
88 #define PCIE_PHY_CTRL_CAP_DAT_LOC 17
89 #define PCIE_PHY_CTRL_WR_LOC 18
90 #define PCIE_PHY_CTRL_RD_LOC 19
91
92 #define PCIE_PHY_STAT (PL_OFFSET + 0x110)
93 #define PCIE_PHY_STAT_ACK_LOC 16
94
95 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
96 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
97
98 /* PHY registers (not memory-mapped) */
99 #define PCIE_PHY_RX_ASIC_OUT 0x100D
100 #define PCIE_PHY_RX_ASIC_OUT_VALID (1 << 0)
101
102 #define PHY_RX_OVRD_IN_LO 0x1005
103 #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5)
104 #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3)
105
pcie_phy_poll_ack(struct imx6_pcie * imx6_pcie,int exp_val)106 static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, int exp_val)
107 {
108 struct dw_pcie *pci = imx6_pcie->pci;
109 u32 val;
110 u32 max_iterations = 10;
111 u32 wait_counter = 0;
112
113 do {
114 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
115 val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1;
116 wait_counter++;
117
118 if (val == exp_val)
119 return 0;
120
121 udelay(1);
122 } while (wait_counter < max_iterations);
123
124 return -ETIMEDOUT;
125 }
126
pcie_phy_wait_ack(struct imx6_pcie * imx6_pcie,int addr)127 static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
128 {
129 struct dw_pcie *pci = imx6_pcie->pci;
130 u32 val;
131 int ret;
132
133 val = addr << PCIE_PHY_CTRL_DATA_LOC;
134 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
135
136 val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC);
137 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
138
139 ret = pcie_phy_poll_ack(imx6_pcie, 1);
140 if (ret)
141 return ret;
142
143 val = addr << PCIE_PHY_CTRL_DATA_LOC;
144 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
145
146 return pcie_phy_poll_ack(imx6_pcie, 0);
147 }
148
149 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
pcie_phy_read(struct imx6_pcie * imx6_pcie,int addr,int * data)150 static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, int *data)
151 {
152 struct dw_pcie *pci = imx6_pcie->pci;
153 u32 val, phy_ctl;
154 int ret;
155
156 ret = pcie_phy_wait_ack(imx6_pcie, addr);
157 if (ret)
158 return ret;
159
160 /* assert Read signal */
161 phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC;
162 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
163
164 ret = pcie_phy_poll_ack(imx6_pcie, 1);
165 if (ret)
166 return ret;
167
168 val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
169 *data = val & 0xffff;
170
171 /* deassert Read signal */
172 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
173
174 return pcie_phy_poll_ack(imx6_pcie, 0);
175 }
176
pcie_phy_write(struct imx6_pcie * imx6_pcie,int addr,int data)177 static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, int data)
178 {
179 struct dw_pcie *pci = imx6_pcie->pci;
180 u32 var;
181 int ret;
182
183 /* write addr */
184 /* cap addr */
185 ret = pcie_phy_wait_ack(imx6_pcie, addr);
186 if (ret)
187 return ret;
188
189 var = data << PCIE_PHY_CTRL_DATA_LOC;
190 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
191
192 /* capture data */
193 var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC);
194 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
195
196 ret = pcie_phy_poll_ack(imx6_pcie, 1);
197 if (ret)
198 return ret;
199
200 /* deassert cap data */
201 var = data << PCIE_PHY_CTRL_DATA_LOC;
202 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
203
204 /* wait for ack de-assertion */
205 ret = pcie_phy_poll_ack(imx6_pcie, 0);
206 if (ret)
207 return ret;
208
209 /* assert wr signal */
210 var = 0x1 << PCIE_PHY_CTRL_WR_LOC;
211 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
212
213 /* wait for ack */
214 ret = pcie_phy_poll_ack(imx6_pcie, 1);
215 if (ret)
216 return ret;
217
218 /* deassert wr signal */
219 var = data << PCIE_PHY_CTRL_DATA_LOC;
220 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
221
222 /* wait for ack de-assertion */
223 ret = pcie_phy_poll_ack(imx6_pcie, 0);
224 if (ret)
225 return ret;
226
227 dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
228
229 return 0;
230 }
231
imx6_pcie_reset_phy(struct imx6_pcie * imx6_pcie)232 static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
233 {
234 u32 tmp;
235
236 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
237 tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
238 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
239 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
240
241 usleep_range(2000, 3000);
242
243 pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
244 tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
245 PHY_RX_OVRD_IN_LO_RX_PLL_EN);
246 pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
247 }
248
249 /* Added for PCI abort handling */
imx6q_pcie_abort_handler(unsigned long addr,unsigned int fsr,struct pt_regs * regs)250 static int imx6q_pcie_abort_handler(unsigned long addr,
251 unsigned int fsr, struct pt_regs *regs)
252 {
253 unsigned long pc = instruction_pointer(regs);
254 unsigned long instr = *(unsigned long *)pc;
255 int reg = (instr >> 12) & 15;
256
257 /*
258 * If the instruction being executed was a read,
259 * make it look like it read all-ones.
260 */
261 if ((instr & 0x0c100000) == 0x04100000) {
262 unsigned long val;
263
264 if (instr & 0x00400000)
265 val = 255;
266 else
267 val = -1;
268
269 regs->uregs[reg] = val;
270 regs->ARM_pc += 4;
271 return 0;
272 }
273
274 if ((instr & 0x0e100090) == 0x00100090) {
275 regs->uregs[reg] = -1;
276 regs->ARM_pc += 4;
277 return 0;
278 }
279
280 return 1;
281 }
282
imx6_pcie_assert_core_reset(struct imx6_pcie * imx6_pcie)283 static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
284 {
285 struct device *dev = imx6_pcie->pci->dev;
286
287 switch (imx6_pcie->variant) {
288 case IMX7D:
289 reset_control_assert(imx6_pcie->pciephy_reset);
290 reset_control_assert(imx6_pcie->apps_reset);
291 break;
292 case IMX6SX:
293 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
294 IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
295 IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
296 /* Force PCIe PHY reset */
297 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
298 IMX6SX_GPR5_PCIE_BTNRST_RESET,
299 IMX6SX_GPR5_PCIE_BTNRST_RESET);
300 break;
301 case IMX6QP:
302 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
303 IMX6Q_GPR1_PCIE_SW_RST,
304 IMX6Q_GPR1_PCIE_SW_RST);
305 break;
306 case IMX6Q:
307 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
308 IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
309 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
310 IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
311 break;
312 }
313
314 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
315 int ret = regulator_disable(imx6_pcie->vpcie);
316
317 if (ret)
318 dev_err(dev, "failed to disable vpcie regulator: %d\n",
319 ret);
320 }
321 }
322
imx6_pcie_enable_ref_clk(struct imx6_pcie * imx6_pcie)323 static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
324 {
325 struct dw_pcie *pci = imx6_pcie->pci;
326 struct device *dev = pci->dev;
327 int ret = 0;
328
329 switch (imx6_pcie->variant) {
330 case IMX6SX:
331 ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
332 if (ret) {
333 dev_err(dev, "unable to enable pcie_axi clock\n");
334 break;
335 }
336
337 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
338 IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
339 break;
340 case IMX6QP: /* FALLTHROUGH */
341 case IMX6Q:
342 /* power up core phy and enable ref clock */
343 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
344 IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
345 /*
346 * the async reset input need ref clock to sync internally,
347 * when the ref clock comes after reset, internal synced
348 * reset time is too short, cannot meet the requirement.
349 * add one ~10us delay here.
350 */
351 udelay(10);
352 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
353 IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
354 break;
355 case IMX7D:
356 break;
357 }
358
359 return ret;
360 }
361
imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie * imx6_pcie)362 static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
363 {
364 u32 val;
365 unsigned int retries;
366 struct device *dev = imx6_pcie->pci->dev;
367
368 for (retries = 0; retries < PHY_PLL_LOCK_WAIT_MAX_RETRIES; retries++) {
369 regmap_read(imx6_pcie->iomuxc_gpr, IOMUXC_GPR22, &val);
370
371 if (val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED)
372 return;
373
374 usleep_range(PHY_PLL_LOCK_WAIT_USLEEP_MIN,
375 PHY_PLL_LOCK_WAIT_USLEEP_MAX);
376 }
377
378 dev_err(dev, "PCIe PLL lock timeout\n");
379 }
380
imx6_pcie_deassert_core_reset(struct imx6_pcie * imx6_pcie)381 static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
382 {
383 struct dw_pcie *pci = imx6_pcie->pci;
384 struct device *dev = pci->dev;
385 int ret;
386
387 if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
388 ret = regulator_enable(imx6_pcie->vpcie);
389 if (ret) {
390 dev_err(dev, "failed to enable vpcie regulator: %d\n",
391 ret);
392 return;
393 }
394 }
395
396 ret = clk_prepare_enable(imx6_pcie->pcie_phy);
397 if (ret) {
398 dev_err(dev, "unable to enable pcie_phy clock\n");
399 goto err_pcie_phy;
400 }
401
402 ret = clk_prepare_enable(imx6_pcie->pcie_bus);
403 if (ret) {
404 dev_err(dev, "unable to enable pcie_bus clock\n");
405 goto err_pcie_bus;
406 }
407
408 ret = clk_prepare_enable(imx6_pcie->pcie);
409 if (ret) {
410 dev_err(dev, "unable to enable pcie clock\n");
411 goto err_pcie;
412 }
413
414 ret = imx6_pcie_enable_ref_clk(imx6_pcie);
415 if (ret) {
416 dev_err(dev, "unable to enable pcie ref clock\n");
417 goto err_ref_clk;
418 }
419
420 /* allow the clocks to stabilize */
421 usleep_range(200, 500);
422
423 /* Some boards don't have PCIe reset GPIO. */
424 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
425 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
426 imx6_pcie->gpio_active_high);
427 msleep(100);
428 gpio_set_value_cansleep(imx6_pcie->reset_gpio,
429 !imx6_pcie->gpio_active_high);
430 }
431
432 switch (imx6_pcie->variant) {
433 case IMX7D:
434 reset_control_deassert(imx6_pcie->pciephy_reset);
435 imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
436 break;
437 case IMX6SX:
438 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
439 IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
440 break;
441 case IMX6QP:
442 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
443 IMX6Q_GPR1_PCIE_SW_RST, 0);
444
445 usleep_range(200, 500);
446 break;
447 case IMX6Q: /* Nothing to do */
448 break;
449 }
450
451 return;
452
453 err_ref_clk:
454 clk_disable_unprepare(imx6_pcie->pcie);
455 err_pcie:
456 clk_disable_unprepare(imx6_pcie->pcie_bus);
457 err_pcie_bus:
458 clk_disable_unprepare(imx6_pcie->pcie_phy);
459 err_pcie_phy:
460 if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
461 ret = regulator_disable(imx6_pcie->vpcie);
462 if (ret)
463 dev_err(dev, "failed to disable vpcie regulator: %d\n",
464 ret);
465 }
466 }
467
imx6_pcie_init_phy(struct imx6_pcie * imx6_pcie)468 static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
469 {
470 switch (imx6_pcie->variant) {
471 case IMX7D:
472 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
473 IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
474 break;
475 case IMX6SX:
476 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
477 IMX6SX_GPR12_PCIE_RX_EQ_MASK,
478 IMX6SX_GPR12_PCIE_RX_EQ_2);
479 /* FALLTHROUGH */
480 default:
481 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
482 IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
483
484 /* configure constant input signal to the pcie ctrl and phy */
485 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
486 IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
487
488 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
489 IMX6Q_GPR8_TX_DEEMPH_GEN1,
490 imx6_pcie->tx_deemph_gen1 << 0);
491 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
492 IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
493 imx6_pcie->tx_deemph_gen2_3p5db << 6);
494 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
495 IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
496 imx6_pcie->tx_deemph_gen2_6db << 12);
497 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
498 IMX6Q_GPR8_TX_SWING_FULL,
499 imx6_pcie->tx_swing_full << 18);
500 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
501 IMX6Q_GPR8_TX_SWING_LOW,
502 imx6_pcie->tx_swing_low << 25);
503 break;
504 }
505
506 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
507 IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12);
508 }
509
imx6_pcie_wait_for_link(struct imx6_pcie * imx6_pcie)510 static int imx6_pcie_wait_for_link(struct imx6_pcie *imx6_pcie)
511 {
512 struct dw_pcie *pci = imx6_pcie->pci;
513 struct device *dev = pci->dev;
514
515 /* check if the link is up or not */
516 if (!dw_pcie_wait_for_link(pci))
517 return 0;
518
519 dev_dbg(dev, "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n",
520 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
521 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
522 return -ETIMEDOUT;
523 }
524
imx6_pcie_wait_for_speed_change(struct imx6_pcie * imx6_pcie)525 static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
526 {
527 struct dw_pcie *pci = imx6_pcie->pci;
528 struct device *dev = pci->dev;
529 u32 tmp;
530 unsigned int retries;
531
532 for (retries = 0; retries < 200; retries++) {
533 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
534 /* Test if the speed change finished. */
535 if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
536 return 0;
537 usleep_range(100, 1000);
538 }
539
540 dev_err(dev, "Speed change timeout\n");
541 return -EINVAL;
542 }
543
imx6_pcie_establish_link(struct imx6_pcie * imx6_pcie)544 static int imx6_pcie_establish_link(struct imx6_pcie *imx6_pcie)
545 {
546 struct dw_pcie *pci = imx6_pcie->pci;
547 struct device *dev = pci->dev;
548 u32 tmp;
549 int ret;
550
551 /*
552 * Force Gen1 operation when starting the link. In case the link is
553 * started in Gen2 mode, there is a possibility the devices on the
554 * bus will not be detected at all. This happens with PCIe switches.
555 */
556 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
557 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
558 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN1;
559 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
560
561 /* Start LTSSM. */
562 if (imx6_pcie->variant == IMX7D)
563 reset_control_deassert(imx6_pcie->apps_reset);
564 else
565 regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
566 IMX6Q_GPR12_PCIE_CTL_2, 1 << 10);
567
568 ret = imx6_pcie_wait_for_link(imx6_pcie);
569 if (ret)
570 goto err_reset_phy;
571
572 if (imx6_pcie->link_gen == 2) {
573 /* Allow Gen2 mode after the link is up. */
574 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCR);
575 tmp &= ~PCIE_RC_LCR_MAX_LINK_SPEEDS_MASK;
576 tmp |= PCIE_RC_LCR_MAX_LINK_SPEEDS_GEN2;
577 dw_pcie_writel_dbi(pci, PCIE_RC_LCR, tmp);
578
579 /*
580 * Start Directed Speed Change so the best possible
581 * speed both link partners support can be negotiated.
582 */
583 tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
584 tmp |= PORT_LOGIC_SPEED_CHANGE;
585 dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
586
587 if (imx6_pcie->variant != IMX7D) {
588 /*
589 * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
590 * from i.MX6 family when no link speed transition
591 * occurs and we go Gen1 -> yep, Gen1. The difference
592 * is that, in such case, it will not be cleared by HW
593 * which will cause the following code to report false
594 * failure.
595 */
596
597 ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
598 if (ret) {
599 dev_err(dev, "Failed to bring link up!\n");
600 goto err_reset_phy;
601 }
602 }
603
604 /* Make sure link training is finished as well! */
605 ret = imx6_pcie_wait_for_link(imx6_pcie);
606 if (ret) {
607 dev_err(dev, "Failed to bring link up!\n");
608 goto err_reset_phy;
609 }
610 } else {
611 dev_info(dev, "Link: Gen2 disabled\n");
612 }
613
614 tmp = dw_pcie_readl_dbi(pci, PCIE_RC_LCSR);
615 dev_info(dev, "Link up, Gen%i\n", (tmp >> 16) & 0xf);
616 return 0;
617
618 err_reset_phy:
619 dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
620 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R0),
621 dw_pcie_readl_dbi(pci, PCIE_PHY_DEBUG_R1));
622 imx6_pcie_reset_phy(imx6_pcie);
623 return ret;
624 }
625
imx6_pcie_host_init(struct pcie_port * pp)626 static int imx6_pcie_host_init(struct pcie_port *pp)
627 {
628 struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
629 struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
630
631 imx6_pcie_assert_core_reset(imx6_pcie);
632 imx6_pcie_init_phy(imx6_pcie);
633 imx6_pcie_deassert_core_reset(imx6_pcie);
634 dw_pcie_setup_rc(pp);
635 imx6_pcie_establish_link(imx6_pcie);
636
637 if (IS_ENABLED(CONFIG_PCI_MSI))
638 dw_pcie_msi_init(pp);
639
640 return 0;
641 }
642
643 static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
644 .host_init = imx6_pcie_host_init,
645 };
646
imx6_add_pcie_port(struct imx6_pcie * imx6_pcie,struct platform_device * pdev)647 static int imx6_add_pcie_port(struct imx6_pcie *imx6_pcie,
648 struct platform_device *pdev)
649 {
650 struct dw_pcie *pci = imx6_pcie->pci;
651 struct pcie_port *pp = &pci->pp;
652 struct device *dev = &pdev->dev;
653 int ret;
654
655 if (IS_ENABLED(CONFIG_PCI_MSI)) {
656 pp->msi_irq = platform_get_irq_byname(pdev, "msi");
657 if (pp->msi_irq <= 0) {
658 dev_err(dev, "failed to get MSI irq\n");
659 return -ENODEV;
660 }
661 }
662
663 pp->ops = &imx6_pcie_host_ops;
664
665 ret = dw_pcie_host_init(pp);
666 if (ret) {
667 dev_err(dev, "failed to initialize host\n");
668 return ret;
669 }
670
671 return 0;
672 }
673
674 static const struct dw_pcie_ops dw_pcie_ops = {
675 /* No special ops needed, but pcie-designware still expects this struct */
676 };
677
imx6_pcie_probe(struct platform_device * pdev)678 static int imx6_pcie_probe(struct platform_device *pdev)
679 {
680 struct device *dev = &pdev->dev;
681 struct dw_pcie *pci;
682 struct imx6_pcie *imx6_pcie;
683 struct resource *dbi_base;
684 struct device_node *node = dev->of_node;
685 int ret;
686 u16 val;
687
688 imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
689 if (!imx6_pcie)
690 return -ENOMEM;
691
692 pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
693 if (!pci)
694 return -ENOMEM;
695
696 pci->dev = dev;
697 pci->ops = &dw_pcie_ops;
698
699 imx6_pcie->pci = pci;
700 imx6_pcie->variant =
701 (enum imx6_pcie_variants)of_device_get_match_data(dev);
702
703 dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
704 pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
705 if (IS_ERR(pci->dbi_base))
706 return PTR_ERR(pci->dbi_base);
707
708 /* Fetch GPIOs */
709 imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
710 imx6_pcie->gpio_active_high = of_property_read_bool(node,
711 "reset-gpio-active-high");
712 if (gpio_is_valid(imx6_pcie->reset_gpio)) {
713 ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
714 imx6_pcie->gpio_active_high ?
715 GPIOF_OUT_INIT_HIGH :
716 GPIOF_OUT_INIT_LOW,
717 "PCIe reset");
718 if (ret) {
719 dev_err(dev, "unable to get reset gpio\n");
720 return ret;
721 }
722 } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
723 return imx6_pcie->reset_gpio;
724 }
725
726 /* Fetch clocks */
727 imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
728 if (IS_ERR(imx6_pcie->pcie_phy)) {
729 dev_err(dev, "pcie_phy clock source missing or invalid\n");
730 return PTR_ERR(imx6_pcie->pcie_phy);
731 }
732
733 imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
734 if (IS_ERR(imx6_pcie->pcie_bus)) {
735 dev_err(dev, "pcie_bus clock source missing or invalid\n");
736 return PTR_ERR(imx6_pcie->pcie_bus);
737 }
738
739 imx6_pcie->pcie = devm_clk_get(dev, "pcie");
740 if (IS_ERR(imx6_pcie->pcie)) {
741 dev_err(dev, "pcie clock source missing or invalid\n");
742 return PTR_ERR(imx6_pcie->pcie);
743 }
744
745 switch (imx6_pcie->variant) {
746 case IMX6SX:
747 imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
748 "pcie_inbound_axi");
749 if (IS_ERR(imx6_pcie->pcie_inbound_axi)) {
750 dev_err(dev, "pcie_inbound_axi clock missing or invalid\n");
751 return PTR_ERR(imx6_pcie->pcie_inbound_axi);
752 }
753 break;
754 case IMX7D:
755 imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
756 "pciephy");
757 if (IS_ERR(imx6_pcie->pciephy_reset)) {
758 dev_err(dev, "Failed to get PCIEPHY reset control\n");
759 return PTR_ERR(imx6_pcie->pciephy_reset);
760 }
761
762 imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
763 "apps");
764 if (IS_ERR(imx6_pcie->apps_reset)) {
765 dev_err(dev, "Failed to get PCIE APPS reset control\n");
766 return PTR_ERR(imx6_pcie->apps_reset);
767 }
768 break;
769 default:
770 break;
771 }
772
773 /* Grab GPR config register range */
774 imx6_pcie->iomuxc_gpr =
775 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
776 if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
777 dev_err(dev, "unable to find iomuxc registers\n");
778 return PTR_ERR(imx6_pcie->iomuxc_gpr);
779 }
780
781 /* Grab PCIe PHY Tx Settings */
782 if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
783 &imx6_pcie->tx_deemph_gen1))
784 imx6_pcie->tx_deemph_gen1 = 0;
785
786 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
787 &imx6_pcie->tx_deemph_gen2_3p5db))
788 imx6_pcie->tx_deemph_gen2_3p5db = 0;
789
790 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
791 &imx6_pcie->tx_deemph_gen2_6db))
792 imx6_pcie->tx_deemph_gen2_6db = 20;
793
794 if (of_property_read_u32(node, "fsl,tx-swing-full",
795 &imx6_pcie->tx_swing_full))
796 imx6_pcie->tx_swing_full = 127;
797
798 if (of_property_read_u32(node, "fsl,tx-swing-low",
799 &imx6_pcie->tx_swing_low))
800 imx6_pcie->tx_swing_low = 127;
801
802 /* Limit link speed */
803 ret = of_property_read_u32(node, "fsl,max-link-speed",
804 &imx6_pcie->link_gen);
805 if (ret)
806 imx6_pcie->link_gen = 1;
807
808 imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
809 if (IS_ERR(imx6_pcie->vpcie)) {
810 if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
811 return PTR_ERR(imx6_pcie->vpcie);
812 imx6_pcie->vpcie = NULL;
813 }
814
815 platform_set_drvdata(pdev, imx6_pcie);
816
817 ret = imx6_add_pcie_port(imx6_pcie, pdev);
818 if (ret < 0)
819 return ret;
820
821 if (pci_msi_enabled()) {
822 val = dw_pcie_readw_dbi(pci, PCIE_RC_IMX6_MSI_CAP +
823 PCI_MSI_FLAGS);
824 val |= PCI_MSI_FLAGS_ENABLE;
825 dw_pcie_writew_dbi(pci, PCIE_RC_IMX6_MSI_CAP + PCI_MSI_FLAGS,
826 val);
827 }
828
829 return 0;
830 }
831
imx6_pcie_shutdown(struct platform_device * pdev)832 static void imx6_pcie_shutdown(struct platform_device *pdev)
833 {
834 struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
835
836 /* bring down link, so bootloader gets clean state in case of reboot */
837 imx6_pcie_assert_core_reset(imx6_pcie);
838 }
839
840 static const struct of_device_id imx6_pcie_of_match[] = {
841 { .compatible = "fsl,imx6q-pcie", .data = (void *)IMX6Q, },
842 { .compatible = "fsl,imx6sx-pcie", .data = (void *)IMX6SX, },
843 { .compatible = "fsl,imx6qp-pcie", .data = (void *)IMX6QP, },
844 { .compatible = "fsl,imx7d-pcie", .data = (void *)IMX7D, },
845 {},
846 };
847
848 static struct platform_driver imx6_pcie_driver = {
849 .driver = {
850 .name = "imx6q-pcie",
851 .of_match_table = imx6_pcie_of_match,
852 .suppress_bind_attrs = true,
853 },
854 .probe = imx6_pcie_probe,
855 .shutdown = imx6_pcie_shutdown,
856 };
857
imx6_pcie_init(void)858 static int __init imx6_pcie_init(void)
859 {
860 /*
861 * Since probe() can be deferred we need to make sure that
862 * hook_fault_code is not called after __init memory is freed
863 * by kernel and since imx6q_pcie_abort_handler() is a no-op,
864 * we can install the handler here without risking it
865 * accessing some uninitialized driver state.
866 */
867 hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
868 "external abort on non-linefetch");
869
870 return platform_driver_register(&imx6_pcie_driver);
871 }
872 device_initcall(imx6_pcie_init);
873