1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/bitops.h>
13 #include <linux/interrupt.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/acpi.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
19 #include <linux/io.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25
26 /* memory mapped register offsets */
27 #define BYT_CONF0_REG 0x000
28 #define BYT_CONF1_REG 0x004
29 #define BYT_VAL_REG 0x008
30 #define BYT_DFT_REG 0x00c
31 #define BYT_INT_STAT_REG 0x800
32 #define BYT_DEBOUNCE_REG 0x9d0
33
34 /* BYT_CONF0_REG register bits */
35 #define BYT_IODEN BIT(31)
36 #define BYT_DIRECT_IRQ_EN BIT(27)
37 #define BYT_TRIG_NEG BIT(26)
38 #define BYT_TRIG_POS BIT(25)
39 #define BYT_TRIG_LVL BIT(24)
40 #define BYT_DEBOUNCE_EN BIT(20)
41 #define BYT_GLITCH_FILTER_EN BIT(19)
42 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
43 #define BYT_GLITCH_F_FAST_CLK BIT(16)
44 #define BYT_PULL_STR_SHIFT 9
45 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
46 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
47 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
48 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
49 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
50 #define BYT_PULL_ASSIGN_SHIFT 7
51 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
52 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
53 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
54 #define BYT_PIN_MUX 0x07
55
56 /* BYT_VAL_REG register bits */
57 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
58 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
59 #define BYT_LEVEL BIT(0)
60
61 #define BYT_DIR_MASK (BIT(1) | BIT(2))
62 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
63
64 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
65 BYT_PIN_MUX)
66 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
67
68 /* BYT_DEBOUNCE_REG bits */
69 #define BYT_DEBOUNCE_PULSE_MASK 0x7
70 #define BYT_DEBOUNCE_PULSE_375US 1
71 #define BYT_DEBOUNCE_PULSE_750US 2
72 #define BYT_DEBOUNCE_PULSE_1500US 3
73 #define BYT_DEBOUNCE_PULSE_3MS 4
74 #define BYT_DEBOUNCE_PULSE_6MS 5
75 #define BYT_DEBOUNCE_PULSE_12MS 6
76 #define BYT_DEBOUNCE_PULSE_24MS 7
77
78 #define BYT_NGPIO_SCORE 102
79 #define BYT_NGPIO_NCORE 28
80 #define BYT_NGPIO_SUS 44
81
82 #define BYT_SCORE_ACPI_UID "1"
83 #define BYT_NCORE_ACPI_UID "2"
84 #define BYT_SUS_ACPI_UID "3"
85
86 /*
87 * This is the function value most pins have for GPIO muxing. If the value
88 * differs from the default one, it must be explicitly mentioned. Otherwise, the
89 * pin control implementation will set the muxing value to default GPIO if it
90 * does not find a match for the requested function.
91 */
92 #define BYT_DEFAULT_GPIO_MUX 0
93
94 struct byt_gpio_pin_context {
95 u32 conf0;
96 u32 val;
97 };
98
99 struct byt_simple_func_mux {
100 const char *name;
101 unsigned short func;
102 };
103
104 struct byt_mixed_func_mux {
105 const char *name;
106 const unsigned short *func_values;
107 };
108
109 struct byt_pingroup {
110 const char *name;
111 const unsigned int *pins;
112 size_t npins;
113 unsigned short has_simple_funcs;
114 union {
115 const struct byt_simple_func_mux *simple_funcs;
116 const struct byt_mixed_func_mux *mixed_funcs;
117 };
118 size_t nfuncs;
119 };
120
121 struct byt_function {
122 const char *name;
123 const char * const *groups;
124 size_t ngroups;
125 };
126
127 struct byt_community {
128 unsigned int pin_base;
129 size_t npins;
130 const unsigned int *pad_map;
131 void __iomem *reg_base;
132 };
133
134 #define SIMPLE_FUNC(n, f) \
135 { \
136 .name = (n), \
137 .func = (f), \
138 }
139 #define MIXED_FUNC(n, f) \
140 { \
141 .name = (n), \
142 .func_values = (f), \
143 }
144
145 #define PIN_GROUP_SIMPLE(n, p, f) \
146 { \
147 .name = (n), \
148 .pins = (p), \
149 .npins = ARRAY_SIZE((p)), \
150 .has_simple_funcs = 1, \
151 { \
152 .simple_funcs = (f), \
153 }, \
154 .nfuncs = ARRAY_SIZE((f)), \
155 }
156 #define PIN_GROUP_MIXED(n, p, f) \
157 { \
158 .name = (n), \
159 .pins = (p), \
160 .npins = ARRAY_SIZE((p)), \
161 .has_simple_funcs = 0, \
162 { \
163 .mixed_funcs = (f), \
164 }, \
165 .nfuncs = ARRAY_SIZE((f)), \
166 }
167
168 #define FUNCTION(n, g) \
169 { \
170 .name = (n), \
171 .groups = (g), \
172 .ngroups = ARRAY_SIZE((g)), \
173 }
174
175 #define COMMUNITY(p, n, map) \
176 { \
177 .pin_base = (p), \
178 .npins = (n), \
179 .pad_map = (map),\
180 }
181
182 struct byt_pinctrl_soc_data {
183 const char *uid;
184 const struct pinctrl_pin_desc *pins;
185 size_t npins;
186 const struct byt_pingroup *groups;
187 size_t ngroups;
188 const struct byt_function *functions;
189 size_t nfunctions;
190 const struct byt_community *communities;
191 size_t ncommunities;
192 };
193
194 struct byt_gpio {
195 struct gpio_chip chip;
196 struct platform_device *pdev;
197 struct pinctrl_dev *pctl_dev;
198 struct pinctrl_desc pctl_desc;
199 const struct byt_pinctrl_soc_data *soc_data;
200 struct byt_community *communities_copy;
201 struct byt_gpio_pin_context *saved_context;
202 };
203
204 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
205 static const struct pinctrl_pin_desc byt_score_pins[] = {
206 PINCTRL_PIN(0, "SATA_GP0"),
207 PINCTRL_PIN(1, "SATA_GP1"),
208 PINCTRL_PIN(2, "SATA_LED#"),
209 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
210 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
211 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
212 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
213 PINCTRL_PIN(7, "SD3_WP"),
214 PINCTRL_PIN(8, "HDA_RST"),
215 PINCTRL_PIN(9, "HDA_SYNC"),
216 PINCTRL_PIN(10, "HDA_CLK"),
217 PINCTRL_PIN(11, "HDA_SDO"),
218 PINCTRL_PIN(12, "HDA_SDI0"),
219 PINCTRL_PIN(13, "HDA_SDI1"),
220 PINCTRL_PIN(14, "GPIO_S0_SC14"),
221 PINCTRL_PIN(15, "GPIO_S0_SC15"),
222 PINCTRL_PIN(16, "MMC1_CLK"),
223 PINCTRL_PIN(17, "MMC1_D0"),
224 PINCTRL_PIN(18, "MMC1_D1"),
225 PINCTRL_PIN(19, "MMC1_D2"),
226 PINCTRL_PIN(20, "MMC1_D3"),
227 PINCTRL_PIN(21, "MMC1_D4"),
228 PINCTRL_PIN(22, "MMC1_D5"),
229 PINCTRL_PIN(23, "MMC1_D6"),
230 PINCTRL_PIN(24, "MMC1_D7"),
231 PINCTRL_PIN(25, "MMC1_CMD"),
232 PINCTRL_PIN(26, "MMC1_RST"),
233 PINCTRL_PIN(27, "SD2_CLK"),
234 PINCTRL_PIN(28, "SD2_D0"),
235 PINCTRL_PIN(29, "SD2_D1"),
236 PINCTRL_PIN(30, "SD2_D2"),
237 PINCTRL_PIN(31, "SD2_D3_CD"),
238 PINCTRL_PIN(32, "SD2_CMD"),
239 PINCTRL_PIN(33, "SD3_CLK"),
240 PINCTRL_PIN(34, "SD3_D0"),
241 PINCTRL_PIN(35, "SD3_D1"),
242 PINCTRL_PIN(36, "SD3_D2"),
243 PINCTRL_PIN(37, "SD3_D3"),
244 PINCTRL_PIN(38, "SD3_CD"),
245 PINCTRL_PIN(39, "SD3_CMD"),
246 PINCTRL_PIN(40, "SD3_1P8EN"),
247 PINCTRL_PIN(41, "SD3_PWREN#"),
248 PINCTRL_PIN(42, "ILB_LPC_AD0"),
249 PINCTRL_PIN(43, "ILB_LPC_AD1"),
250 PINCTRL_PIN(44, "ILB_LPC_AD2"),
251 PINCTRL_PIN(45, "ILB_LPC_AD3"),
252 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
253 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
254 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
255 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
256 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
257 PINCTRL_PIN(51, "PCU_SMB_DATA"),
258 PINCTRL_PIN(52, "PCU_SMB_CLK"),
259 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
260 PINCTRL_PIN(54, "ILB_8254_SPKR"),
261 PINCTRL_PIN(55, "GPIO_S0_SC55"),
262 PINCTRL_PIN(56, "GPIO_S0_SC56"),
263 PINCTRL_PIN(57, "GPIO_S0_SC57"),
264 PINCTRL_PIN(58, "GPIO_S0_SC58"),
265 PINCTRL_PIN(59, "GPIO_S0_SC59"),
266 PINCTRL_PIN(60, "GPIO_S0_SC60"),
267 PINCTRL_PIN(61, "GPIO_S0_SC61"),
268 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
269 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
270 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
271 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
272 PINCTRL_PIN(66, "SIO_SPI_CS"),
273 PINCTRL_PIN(67, "SIO_SPI_MISO"),
274 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
275 PINCTRL_PIN(69, "SIO_SPI_CLK"),
276 PINCTRL_PIN(70, "SIO_UART1_RXD"),
277 PINCTRL_PIN(71, "SIO_UART1_TXD"),
278 PINCTRL_PIN(72, "SIO_UART1_RTS"),
279 PINCTRL_PIN(73, "SIO_UART1_CTS"),
280 PINCTRL_PIN(74, "SIO_UART2_RXD"),
281 PINCTRL_PIN(75, "SIO_UART2_TXD"),
282 PINCTRL_PIN(76, "SIO_UART2_RTS"),
283 PINCTRL_PIN(77, "SIO_UART2_CTS"),
284 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
285 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
286 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
287 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
288 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
289 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
290 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
291 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
292 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
293 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
294 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
295 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
296 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
297 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
298 PINCTRL_PIN(92, "GPIO_S0_SC92"),
299 PINCTRL_PIN(93, "GPIO_S0_SC93"),
300 PINCTRL_PIN(94, "SIO_PWM0"),
301 PINCTRL_PIN(95, "SIO_PWM1"),
302 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
303 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
304 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
305 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
306 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
307 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
308 };
309
310 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
311 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
312 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
313 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
314 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
315 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
316 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
317 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
318 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
319 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
320 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
321 97, 100,
322 };
323
324 /* SCORE groups */
325 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
326 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
327 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
328 SIMPLE_FUNC("uart", 1),
329 };
330
331 static const unsigned int byt_score_pwm0_pins[] = { 94 };
332 static const unsigned int byt_score_pwm1_pins[] = { 95 };
333 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
334 SIMPLE_FUNC("pwm", 1),
335 };
336
337 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
338 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
339 SIMPLE_FUNC("spi", 1),
340 };
341
342 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
343 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
344 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
345 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
346 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
347 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
348 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
349 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
350 SIMPLE_FUNC("i2c", 1),
351 };
352
353 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
354 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
355 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
356 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
357 SIMPLE_FUNC("ssp", 1),
358 };
359
360 static const unsigned int byt_score_sdcard_pins[] = {
361 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
362 };
363 static const unsigned short byt_score_sdcard_mux_values[] = {
364 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
365 };
366 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
367 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
368 };
369
370 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
371 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
372 SIMPLE_FUNC("sdio", 1),
373 };
374
375 static const unsigned int byt_score_emmc_pins[] = {
376 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
377 };
378 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
379 SIMPLE_FUNC("emmc", 1),
380 };
381
382 static const unsigned int byt_score_ilb_lpc_pins[] = {
383 42, 43, 44, 45, 46, 47, 48, 49, 50,
384 };
385 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
386 SIMPLE_FUNC("lpc", 1),
387 };
388
389 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
390 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
391 SIMPLE_FUNC("sata", 1),
392 };
393
394 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
395 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
396 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
397 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
398 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
399 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
400 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
401 SIMPLE_FUNC("plt_clk", 1),
402 };
403
404 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
405 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
406 SIMPLE_FUNC("smbus", 1),
407 };
408
409 static const struct byt_pingroup byt_score_groups[] = {
410 PIN_GROUP_SIMPLE("uart1_grp",
411 byt_score_uart1_pins, byt_score_uart_mux),
412 PIN_GROUP_SIMPLE("uart2_grp",
413 byt_score_uart2_pins, byt_score_uart_mux),
414 PIN_GROUP_SIMPLE("pwm0_grp",
415 byt_score_pwm0_pins, byt_score_pwm_mux),
416 PIN_GROUP_SIMPLE("pwm1_grp",
417 byt_score_pwm1_pins, byt_score_pwm_mux),
418 PIN_GROUP_SIMPLE("ssp2_grp",
419 byt_score_ssp2_pins, byt_score_pwm_mux),
420 PIN_GROUP_SIMPLE("sio_spi_grp",
421 byt_score_sio_spi_pins, byt_score_spi_mux),
422 PIN_GROUP_SIMPLE("i2c5_grp",
423 byt_score_i2c5_pins, byt_score_i2c_mux),
424 PIN_GROUP_SIMPLE("i2c6_grp",
425 byt_score_i2c6_pins, byt_score_i2c_mux),
426 PIN_GROUP_SIMPLE("i2c4_grp",
427 byt_score_i2c4_pins, byt_score_i2c_mux),
428 PIN_GROUP_SIMPLE("i2c3_grp",
429 byt_score_i2c3_pins, byt_score_i2c_mux),
430 PIN_GROUP_SIMPLE("i2c2_grp",
431 byt_score_i2c2_pins, byt_score_i2c_mux),
432 PIN_GROUP_SIMPLE("i2c1_grp",
433 byt_score_i2c1_pins, byt_score_i2c_mux),
434 PIN_GROUP_SIMPLE("i2c0_grp",
435 byt_score_i2c0_pins, byt_score_i2c_mux),
436 PIN_GROUP_SIMPLE("ssp0_grp",
437 byt_score_ssp0_pins, byt_score_ssp_mux),
438 PIN_GROUP_SIMPLE("ssp1_grp",
439 byt_score_ssp1_pins, byt_score_ssp_mux),
440 PIN_GROUP_MIXED("sdcard_grp",
441 byt_score_sdcard_pins, byt_score_sdcard_mux),
442 PIN_GROUP_SIMPLE("sdio_grp",
443 byt_score_sdio_pins, byt_score_sdio_mux),
444 PIN_GROUP_SIMPLE("emmc_grp",
445 byt_score_emmc_pins, byt_score_emmc_mux),
446 PIN_GROUP_SIMPLE("lpc_grp",
447 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
448 PIN_GROUP_SIMPLE("sata_grp",
449 byt_score_sata_pins, byt_score_sata_mux),
450 PIN_GROUP_SIMPLE("plt_clk0_grp",
451 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
452 PIN_GROUP_SIMPLE("plt_clk1_grp",
453 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
454 PIN_GROUP_SIMPLE("plt_clk2_grp",
455 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
456 PIN_GROUP_SIMPLE("plt_clk3_grp",
457 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
458 PIN_GROUP_SIMPLE("plt_clk4_grp",
459 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
460 PIN_GROUP_SIMPLE("plt_clk5_grp",
461 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
462 PIN_GROUP_SIMPLE("smbus_grp",
463 byt_score_smbus_pins, byt_score_smbus_mux),
464 };
465
466 static const char * const byt_score_uart_groups[] = {
467 "uart1_grp", "uart2_grp",
468 };
469 static const char * const byt_score_pwm_groups[] = {
470 "pwm0_grp", "pwm1_grp",
471 };
472 static const char * const byt_score_ssp_groups[] = {
473 "ssp0_grp", "ssp1_grp", "ssp2_grp",
474 };
475 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
476 static const char * const byt_score_i2c_groups[] = {
477 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
478 "i2c6_grp",
479 };
480 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
481 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
482 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
483 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
484 static const char * const byt_score_sata_groups[] = { "sata_grp" };
485 static const char * const byt_score_plt_clk_groups[] = {
486 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
487 "plt_clk4_grp", "plt_clk5_grp",
488 };
489 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
490 static const char * const byt_score_gpio_groups[] = {
491 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
492 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
493 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
494 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
495 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
496 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
497
498 };
499
500 static const struct byt_function byt_score_functions[] = {
501 FUNCTION("uart", byt_score_uart_groups),
502 FUNCTION("pwm", byt_score_pwm_groups),
503 FUNCTION("ssp", byt_score_ssp_groups),
504 FUNCTION("spi", byt_score_spi_groups),
505 FUNCTION("i2c", byt_score_i2c_groups),
506 FUNCTION("sdcard", byt_score_sdcard_groups),
507 FUNCTION("sdio", byt_score_sdio_groups),
508 FUNCTION("emmc", byt_score_emmc_groups),
509 FUNCTION("lpc", byt_score_lpc_groups),
510 FUNCTION("sata", byt_score_sata_groups),
511 FUNCTION("plt_clk", byt_score_plt_clk_groups),
512 FUNCTION("smbus", byt_score_smbus_groups),
513 FUNCTION("gpio", byt_score_gpio_groups),
514 };
515
516 static const struct byt_community byt_score_communities[] = {
517 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
518 };
519
520 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
521 .uid = BYT_SCORE_ACPI_UID,
522 .pins = byt_score_pins,
523 .npins = ARRAY_SIZE(byt_score_pins),
524 .groups = byt_score_groups,
525 .ngroups = ARRAY_SIZE(byt_score_groups),
526 .functions = byt_score_functions,
527 .nfunctions = ARRAY_SIZE(byt_score_functions),
528 .communities = byt_score_communities,
529 .ncommunities = ARRAY_SIZE(byt_score_communities),
530 };
531
532 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
533 static const struct pinctrl_pin_desc byt_sus_pins[] = {
534 PINCTRL_PIN(0, "GPIO_S50"),
535 PINCTRL_PIN(1, "GPIO_S51"),
536 PINCTRL_PIN(2, "GPIO_S52"),
537 PINCTRL_PIN(3, "GPIO_S53"),
538 PINCTRL_PIN(4, "GPIO_S54"),
539 PINCTRL_PIN(5, "GPIO_S55"),
540 PINCTRL_PIN(6, "GPIO_S56"),
541 PINCTRL_PIN(7, "GPIO_S57"),
542 PINCTRL_PIN(8, "GPIO_S58"),
543 PINCTRL_PIN(9, "GPIO_S59"),
544 PINCTRL_PIN(10, "GPIO_S510"),
545 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
546 PINCTRL_PIN(12, "PMC_SUSCLK0"),
547 PINCTRL_PIN(13, "GPIO_S513"),
548 PINCTRL_PIN(14, "USB_ULPI_RST"),
549 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
550 PINCTRL_PIN(16, "PMC_PWRBTN"),
551 PINCTRL_PIN(17, "GPIO_S517"),
552 PINCTRL_PIN(18, "PMC_SUS_STAT"),
553 PINCTRL_PIN(19, "USB_OC0"),
554 PINCTRL_PIN(20, "USB_OC1"),
555 PINCTRL_PIN(21, "PCU_SPI_CS1"),
556 PINCTRL_PIN(22, "GPIO_S522"),
557 PINCTRL_PIN(23, "GPIO_S523"),
558 PINCTRL_PIN(24, "GPIO_S524"),
559 PINCTRL_PIN(25, "GPIO_S525"),
560 PINCTRL_PIN(26, "GPIO_S526"),
561 PINCTRL_PIN(27, "GPIO_S527"),
562 PINCTRL_PIN(28, "GPIO_S528"),
563 PINCTRL_PIN(29, "GPIO_S529"),
564 PINCTRL_PIN(30, "GPIO_S530"),
565 PINCTRL_PIN(31, "USB_ULPI_CLK"),
566 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
567 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
568 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
569 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
570 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
571 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
572 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
573 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
574 PINCTRL_PIN(40, "USB_ULPI_DIR"),
575 PINCTRL_PIN(41, "USB_ULPI_NXT"),
576 PINCTRL_PIN(42, "USB_ULPI_STP"),
577 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
578 };
579
580 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
581 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
582 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
583 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
584 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
585 52, 53, 59, 40,
586 };
587
588 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
589 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
590 SIMPLE_FUNC("usb", 0),
591 SIMPLE_FUNC("gpio", 1),
592 };
593
594 static const unsigned int byt_sus_usb_ulpi_pins[] = {
595 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
596 };
597 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
598 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
599 };
600 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
601 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
602 };
603 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
604 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
605 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
606 };
607
608 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
609 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
610 SIMPLE_FUNC("spi", 0),
611 SIMPLE_FUNC("gpio", 1),
612 };
613
614 static const struct byt_pingroup byt_sus_groups[] = {
615 PIN_GROUP_SIMPLE("usb_oc_grp",
616 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
617 PIN_GROUP_MIXED("usb_ulpi_grp",
618 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
619 PIN_GROUP_SIMPLE("pcu_spi_grp",
620 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
621 };
622
623 static const char * const byt_sus_usb_groups[] = {
624 "usb_oc_grp", "usb_ulpi_grp",
625 };
626 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
627 static const char * const byt_sus_gpio_groups[] = {
628 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
629 };
630
631 static const struct byt_function byt_sus_functions[] = {
632 FUNCTION("usb", byt_sus_usb_groups),
633 FUNCTION("spi", byt_sus_spi_groups),
634 FUNCTION("gpio", byt_sus_gpio_groups),
635 };
636
637 static const struct byt_community byt_sus_communities[] = {
638 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
639 };
640
641 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
642 .uid = BYT_SUS_ACPI_UID,
643 .pins = byt_sus_pins,
644 .npins = ARRAY_SIZE(byt_sus_pins),
645 .groups = byt_sus_groups,
646 .ngroups = ARRAY_SIZE(byt_sus_groups),
647 .functions = byt_sus_functions,
648 .nfunctions = ARRAY_SIZE(byt_sus_functions),
649 .communities = byt_sus_communities,
650 .ncommunities = ARRAY_SIZE(byt_sus_communities),
651 };
652
653 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
654 PINCTRL_PIN(0, "GPIO_NCORE0"),
655 PINCTRL_PIN(1, "GPIO_NCORE1"),
656 PINCTRL_PIN(2, "GPIO_NCORE2"),
657 PINCTRL_PIN(3, "GPIO_NCORE3"),
658 PINCTRL_PIN(4, "GPIO_NCORE4"),
659 PINCTRL_PIN(5, "GPIO_NCORE5"),
660 PINCTRL_PIN(6, "GPIO_NCORE6"),
661 PINCTRL_PIN(7, "GPIO_NCORE7"),
662 PINCTRL_PIN(8, "GPIO_NCORE8"),
663 PINCTRL_PIN(9, "GPIO_NCORE9"),
664 PINCTRL_PIN(10, "GPIO_NCORE10"),
665 PINCTRL_PIN(11, "GPIO_NCORE11"),
666 PINCTRL_PIN(12, "GPIO_NCORE12"),
667 PINCTRL_PIN(13, "GPIO_NCORE13"),
668 PINCTRL_PIN(14, "GPIO_NCORE14"),
669 PINCTRL_PIN(15, "GPIO_NCORE15"),
670 PINCTRL_PIN(16, "GPIO_NCORE16"),
671 PINCTRL_PIN(17, "GPIO_NCORE17"),
672 PINCTRL_PIN(18, "GPIO_NCORE18"),
673 PINCTRL_PIN(19, "GPIO_NCORE19"),
674 PINCTRL_PIN(20, "GPIO_NCORE20"),
675 PINCTRL_PIN(21, "GPIO_NCORE21"),
676 PINCTRL_PIN(22, "GPIO_NCORE22"),
677 PINCTRL_PIN(23, "GPIO_NCORE23"),
678 PINCTRL_PIN(24, "GPIO_NCORE24"),
679 PINCTRL_PIN(25, "GPIO_NCORE25"),
680 PINCTRL_PIN(26, "GPIO_NCORE26"),
681 PINCTRL_PIN(27, "GPIO_NCORE27"),
682 };
683
684 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
685 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
686 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
687 3, 6, 10, 13, 2, 5, 9, 7,
688 };
689
690 static const struct byt_community byt_ncore_communities[] = {
691 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
692 };
693
694 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
695 .uid = BYT_NCORE_ACPI_UID,
696 .pins = byt_ncore_pins,
697 .npins = ARRAY_SIZE(byt_ncore_pins),
698 .communities = byt_ncore_communities,
699 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
700 };
701
702 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
703 &byt_score_soc_data,
704 &byt_sus_soc_data,
705 &byt_ncore_soc_data,
706 NULL,
707 };
708
709 static DEFINE_RAW_SPINLOCK(byt_lock);
710
byt_get_community(struct byt_gpio * vg,unsigned int pin)711 static struct byt_community *byt_get_community(struct byt_gpio *vg,
712 unsigned int pin)
713 {
714 struct byt_community *comm;
715 int i;
716
717 for (i = 0; i < vg->soc_data->ncommunities; i++) {
718 comm = vg->communities_copy + i;
719 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
720 return comm;
721 }
722
723 return NULL;
724 }
725
byt_gpio_reg(struct byt_gpio * vg,unsigned int offset,int reg)726 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
727 int reg)
728 {
729 struct byt_community *comm = byt_get_community(vg, offset);
730 u32 reg_offset;
731
732 if (!comm)
733 return NULL;
734
735 offset -= comm->pin_base;
736 switch (reg) {
737 case BYT_INT_STAT_REG:
738 reg_offset = (offset / 32) * 4;
739 break;
740 case BYT_DEBOUNCE_REG:
741 reg_offset = 0;
742 break;
743 default:
744 reg_offset = comm->pad_map[offset] * 16;
745 break;
746 }
747
748 return comm->reg_base + reg_offset + reg;
749 }
750
byt_get_groups_count(struct pinctrl_dev * pctldev)751 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
752 {
753 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
754
755 return vg->soc_data->ngroups;
756 }
757
byt_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)758 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
759 unsigned int selector)
760 {
761 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
762
763 return vg->soc_data->groups[selector].name;
764 }
765
byt_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)766 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
767 unsigned int selector,
768 const unsigned int **pins,
769 unsigned int *num_pins)
770 {
771 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
772
773 *pins = vg->soc_data->groups[selector].pins;
774 *num_pins = vg->soc_data->groups[selector].npins;
775
776 return 0;
777 }
778
779 static const struct pinctrl_ops byt_pinctrl_ops = {
780 .get_groups_count = byt_get_groups_count,
781 .get_group_name = byt_get_group_name,
782 .get_group_pins = byt_get_group_pins,
783 };
784
byt_get_functions_count(struct pinctrl_dev * pctldev)785 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
786 {
787 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
788
789 return vg->soc_data->nfunctions;
790 }
791
byt_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)792 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
793 unsigned int selector)
794 {
795 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
796
797 return vg->soc_data->functions[selector].name;
798 }
799
byt_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)800 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
801 unsigned int selector,
802 const char * const **groups,
803 unsigned int *num_groups)
804 {
805 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
806
807 *groups = vg->soc_data->functions[selector].groups;
808 *num_groups = vg->soc_data->functions[selector].ngroups;
809
810 return 0;
811 }
812
byt_get_group_simple_mux(const struct byt_pingroup group,const char * func_name,unsigned short * func)813 static int byt_get_group_simple_mux(const struct byt_pingroup group,
814 const char *func_name,
815 unsigned short *func)
816 {
817 int i;
818
819 for (i = 0; i < group.nfuncs; i++) {
820 if (!strcmp(group.simple_funcs[i].name, func_name)) {
821 *func = group.simple_funcs[i].func;
822 return 0;
823 }
824 }
825
826 return 1;
827 }
828
byt_get_group_mixed_mux(const struct byt_pingroup group,const char * func_name,const unsigned short ** func)829 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
830 const char *func_name,
831 const unsigned short **func)
832 {
833 int i;
834
835 for (i = 0; i < group.nfuncs; i++) {
836 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
837 *func = group.mixed_funcs[i].func_values;
838 return 0;
839 }
840 }
841
842 return 1;
843 }
844
byt_set_group_simple_mux(struct byt_gpio * vg,const struct byt_pingroup group,unsigned short func)845 static void byt_set_group_simple_mux(struct byt_gpio *vg,
846 const struct byt_pingroup group,
847 unsigned short func)
848 {
849 unsigned long flags;
850 int i;
851
852 raw_spin_lock_irqsave(&byt_lock, flags);
853
854 for (i = 0; i < group.npins; i++) {
855 void __iomem *padcfg0;
856 u32 value;
857
858 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
859 if (!padcfg0) {
860 dev_warn(&vg->pdev->dev,
861 "Group %s, pin %i not muxed (no padcfg0)\n",
862 group.name, i);
863 continue;
864 }
865
866 value = readl(padcfg0);
867 value &= ~BYT_PIN_MUX;
868 value |= func;
869 writel(value, padcfg0);
870 }
871
872 raw_spin_unlock_irqrestore(&byt_lock, flags);
873 }
874
byt_set_group_mixed_mux(struct byt_gpio * vg,const struct byt_pingroup group,const unsigned short * func)875 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
876 const struct byt_pingroup group,
877 const unsigned short *func)
878 {
879 unsigned long flags;
880 int i;
881
882 raw_spin_lock_irqsave(&byt_lock, flags);
883
884 for (i = 0; i < group.npins; i++) {
885 void __iomem *padcfg0;
886 u32 value;
887
888 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
889 if (!padcfg0) {
890 dev_warn(&vg->pdev->dev,
891 "Group %s, pin %i not muxed (no padcfg0)\n",
892 group.name, i);
893 continue;
894 }
895
896 value = readl(padcfg0);
897 value &= ~BYT_PIN_MUX;
898 value |= func[i];
899 writel(value, padcfg0);
900 }
901
902 raw_spin_unlock_irqrestore(&byt_lock, flags);
903 }
904
byt_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)905 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
906 unsigned int group_selector)
907 {
908 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
909 const struct byt_function func = vg->soc_data->functions[func_selector];
910 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
911 const unsigned short *mixed_func;
912 unsigned short simple_func;
913 int ret = 1;
914
915 if (group.has_simple_funcs)
916 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
917 else
918 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
919
920 if (ret)
921 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
922 else if (group.has_simple_funcs)
923 byt_set_group_simple_mux(vg, group, simple_func);
924 else
925 byt_set_group_mixed_mux(vg, group, mixed_func);
926
927 return 0;
928 }
929
byt_get_gpio_mux(struct byt_gpio * vg,unsigned offset)930 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
931 {
932 /* SCORE pin 92-93 */
933 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
934 offset >= 92 && offset <= 93)
935 return 1;
936
937 /* SUS pin 11-21 */
938 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
939 offset >= 11 && offset <= 21)
940 return 1;
941
942 return 0;
943 }
944
byt_gpio_clear_triggering(struct byt_gpio * vg,unsigned int offset)945 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
946 {
947 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
948 unsigned long flags;
949 u32 value;
950
951 raw_spin_lock_irqsave(&byt_lock, flags);
952 value = readl(reg);
953
954 /* Do not clear direct-irq enabled IRQs (from gpio_disable_free) */
955 if (value & BYT_DIRECT_IRQ_EN)
956 /* nothing to do */ ;
957 else
958 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
959
960 writel(value, reg);
961 raw_spin_unlock_irqrestore(&byt_lock, flags);
962 }
963
byt_gpio_request_enable(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)964 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
965 struct pinctrl_gpio_range *range,
966 unsigned int offset)
967 {
968 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
969 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
970 u32 value, gpio_mux;
971 unsigned long flags;
972
973 raw_spin_lock_irqsave(&byt_lock, flags);
974
975 /*
976 * In most cases, func pin mux 000 means GPIO function.
977 * But, some pins may have func pin mux 001 represents
978 * GPIO function.
979 *
980 * Because there are devices out there where some pins were not
981 * configured correctly we allow changing the mux value from
982 * request (but print out warning about that).
983 */
984 value = readl(reg) & BYT_PIN_MUX;
985 gpio_mux = byt_get_gpio_mux(vg, offset);
986 if (gpio_mux != value) {
987 value = readl(reg) & ~BYT_PIN_MUX;
988 value |= gpio_mux;
989 writel(value, reg);
990
991 dev_warn(&vg->pdev->dev, FW_BUG
992 "pin %u forcibly re-configured as GPIO\n", offset);
993 }
994
995 raw_spin_unlock_irqrestore(&byt_lock, flags);
996
997 pm_runtime_get(&vg->pdev->dev);
998
999 return 0;
1000 }
1001
byt_gpio_disable_free(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)1002 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
1003 struct pinctrl_gpio_range *range,
1004 unsigned int offset)
1005 {
1006 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1007
1008 byt_gpio_clear_triggering(vg, offset);
1009 pm_runtime_put(&vg->pdev->dev);
1010 }
1011
byt_gpio_set_direction(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)1012 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1013 struct pinctrl_gpio_range *range,
1014 unsigned int offset,
1015 bool input)
1016 {
1017 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1018 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1019 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1020 unsigned long flags;
1021 u32 value;
1022
1023 raw_spin_lock_irqsave(&byt_lock, flags);
1024
1025 value = readl(val_reg);
1026 value &= ~BYT_DIR_MASK;
1027 if (input)
1028 value |= BYT_OUTPUT_EN;
1029 else
1030 /*
1031 * Before making any direction modifications, do a check if gpio
1032 * is set for direct IRQ. On baytrail, setting GPIO to output
1033 * does not make sense, so let's at least warn the caller before
1034 * they shoot themselves in the foot.
1035 */
1036 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1037 "Potential Error: Setting GPIO with direct_irq_en to output");
1038 writel(value, val_reg);
1039
1040 raw_spin_unlock_irqrestore(&byt_lock, flags);
1041
1042 return 0;
1043 }
1044
1045 static const struct pinmux_ops byt_pinmux_ops = {
1046 .get_functions_count = byt_get_functions_count,
1047 .get_function_name = byt_get_function_name,
1048 .get_function_groups = byt_get_function_groups,
1049 .set_mux = byt_set_mux,
1050 .gpio_request_enable = byt_gpio_request_enable,
1051 .gpio_disable_free = byt_gpio_disable_free,
1052 .gpio_set_direction = byt_gpio_set_direction,
1053 };
1054
byt_get_pull_strength(u32 reg,u16 * strength)1055 static void byt_get_pull_strength(u32 reg, u16 *strength)
1056 {
1057 switch (reg & BYT_PULL_STR_MASK) {
1058 case BYT_PULL_STR_2K:
1059 *strength = 2000;
1060 break;
1061 case BYT_PULL_STR_10K:
1062 *strength = 10000;
1063 break;
1064 case BYT_PULL_STR_20K:
1065 *strength = 20000;
1066 break;
1067 case BYT_PULL_STR_40K:
1068 *strength = 40000;
1069 break;
1070 }
1071 }
1072
byt_set_pull_strength(u32 * reg,u16 strength)1073 static int byt_set_pull_strength(u32 *reg, u16 strength)
1074 {
1075 *reg &= ~BYT_PULL_STR_MASK;
1076
1077 switch (strength) {
1078 case 2000:
1079 *reg |= BYT_PULL_STR_2K;
1080 break;
1081 case 10000:
1082 *reg |= BYT_PULL_STR_10K;
1083 break;
1084 case 20000:
1085 *reg |= BYT_PULL_STR_20K;
1086 break;
1087 case 40000:
1088 *reg |= BYT_PULL_STR_40K;
1089 break;
1090 default:
1091 return -EINVAL;
1092 }
1093
1094 return 0;
1095 }
1096
byt_pin_config_get(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * config)1097 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1098 unsigned long *config)
1099 {
1100 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1101 enum pin_config_param param = pinconf_to_config_param(*config);
1102 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1103 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1104 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1105 unsigned long flags;
1106 u32 conf, pull, val, debounce;
1107 u16 arg = 0;
1108
1109 raw_spin_lock_irqsave(&byt_lock, flags);
1110 conf = readl(conf_reg);
1111 pull = conf & BYT_PULL_ASSIGN_MASK;
1112 val = readl(val_reg);
1113 raw_spin_unlock_irqrestore(&byt_lock, flags);
1114
1115 switch (param) {
1116 case PIN_CONFIG_BIAS_DISABLE:
1117 if (pull)
1118 return -EINVAL;
1119 break;
1120 case PIN_CONFIG_BIAS_PULL_DOWN:
1121 /* Pull assignment is only applicable in input mode */
1122 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1123 return -EINVAL;
1124
1125 byt_get_pull_strength(conf, &arg);
1126
1127 break;
1128 case PIN_CONFIG_BIAS_PULL_UP:
1129 /* Pull assignment is only applicable in input mode */
1130 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1131 return -EINVAL;
1132
1133 byt_get_pull_strength(conf, &arg);
1134
1135 break;
1136 case PIN_CONFIG_INPUT_DEBOUNCE:
1137 if (!(conf & BYT_DEBOUNCE_EN))
1138 return -EINVAL;
1139
1140 raw_spin_lock_irqsave(&byt_lock, flags);
1141 debounce = readl(db_reg);
1142 raw_spin_unlock_irqrestore(&byt_lock, flags);
1143
1144 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1145 case BYT_DEBOUNCE_PULSE_375US:
1146 arg = 375;
1147 break;
1148 case BYT_DEBOUNCE_PULSE_750US:
1149 arg = 750;
1150 break;
1151 case BYT_DEBOUNCE_PULSE_1500US:
1152 arg = 1500;
1153 break;
1154 case BYT_DEBOUNCE_PULSE_3MS:
1155 arg = 3000;
1156 break;
1157 case BYT_DEBOUNCE_PULSE_6MS:
1158 arg = 6000;
1159 break;
1160 case BYT_DEBOUNCE_PULSE_12MS:
1161 arg = 12000;
1162 break;
1163 case BYT_DEBOUNCE_PULSE_24MS:
1164 arg = 24000;
1165 break;
1166 default:
1167 return -EINVAL;
1168 }
1169
1170 break;
1171 default:
1172 return -ENOTSUPP;
1173 }
1174
1175 *config = pinconf_to_config_packed(param, arg);
1176
1177 return 0;
1178 }
1179
byt_pin_config_set(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * configs,unsigned int num_configs)1180 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1181 unsigned int offset,
1182 unsigned long *configs,
1183 unsigned int num_configs)
1184 {
1185 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1186 unsigned int param, arg;
1187 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1188 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1189 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1190 unsigned long flags;
1191 u32 conf, val, debounce;
1192 int i, ret = 0;
1193
1194 raw_spin_lock_irqsave(&byt_lock, flags);
1195
1196 conf = readl(conf_reg);
1197 val = readl(val_reg);
1198
1199 for (i = 0; i < num_configs; i++) {
1200 param = pinconf_to_config_param(configs[i]);
1201 arg = pinconf_to_config_argument(configs[i]);
1202
1203 switch (param) {
1204 case PIN_CONFIG_BIAS_DISABLE:
1205 conf &= ~BYT_PULL_ASSIGN_MASK;
1206 break;
1207 case PIN_CONFIG_BIAS_PULL_DOWN:
1208 /* Set default strength value in case none is given */
1209 if (arg == 1)
1210 arg = 2000;
1211
1212 /*
1213 * Pull assignment is only applicable in input mode. If
1214 * chip is not in input mode, set it and warn about it.
1215 */
1216 if (val & BYT_INPUT_EN) {
1217 val &= ~BYT_INPUT_EN;
1218 writel(val, val_reg);
1219 dev_warn(&vg->pdev->dev,
1220 "pin %u forcibly set to input mode\n",
1221 offset);
1222 }
1223
1224 conf &= ~BYT_PULL_ASSIGN_MASK;
1225 conf |= BYT_PULL_ASSIGN_DOWN;
1226 ret = byt_set_pull_strength(&conf, arg);
1227
1228 break;
1229 case PIN_CONFIG_BIAS_PULL_UP:
1230 /* Set default strength value in case none is given */
1231 if (arg == 1)
1232 arg = 2000;
1233
1234 /*
1235 * Pull assignment is only applicable in input mode. If
1236 * chip is not in input mode, set it and warn about it.
1237 */
1238 if (val & BYT_INPUT_EN) {
1239 val &= ~BYT_INPUT_EN;
1240 writel(val, val_reg);
1241 dev_warn(&vg->pdev->dev,
1242 "pin %u forcibly set to input mode\n",
1243 offset);
1244 }
1245
1246 conf &= ~BYT_PULL_ASSIGN_MASK;
1247 conf |= BYT_PULL_ASSIGN_UP;
1248 ret = byt_set_pull_strength(&conf, arg);
1249
1250 break;
1251 case PIN_CONFIG_INPUT_DEBOUNCE:
1252 debounce = readl(db_reg);
1253 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1254
1255 if (arg)
1256 conf |= BYT_DEBOUNCE_EN;
1257 else
1258 conf &= ~BYT_DEBOUNCE_EN;
1259
1260 switch (arg) {
1261 case 375:
1262 debounce |= BYT_DEBOUNCE_PULSE_375US;
1263 break;
1264 case 750:
1265 debounce |= BYT_DEBOUNCE_PULSE_750US;
1266 break;
1267 case 1500:
1268 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1269 break;
1270 case 3000:
1271 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1272 break;
1273 case 6000:
1274 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1275 break;
1276 case 12000:
1277 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1278 break;
1279 case 24000:
1280 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1281 break;
1282 default:
1283 if (arg)
1284 ret = -EINVAL;
1285 break;
1286 }
1287
1288 if (!ret)
1289 writel(debounce, db_reg);
1290 break;
1291 default:
1292 ret = -ENOTSUPP;
1293 }
1294
1295 if (ret)
1296 break;
1297 }
1298
1299 if (!ret)
1300 writel(conf, conf_reg);
1301
1302 raw_spin_unlock_irqrestore(&byt_lock, flags);
1303
1304 return ret;
1305 }
1306
1307 static const struct pinconf_ops byt_pinconf_ops = {
1308 .is_generic = true,
1309 .pin_config_get = byt_pin_config_get,
1310 .pin_config_set = byt_pin_config_set,
1311 };
1312
1313 static const struct pinctrl_desc byt_pinctrl_desc = {
1314 .pctlops = &byt_pinctrl_ops,
1315 .pmxops = &byt_pinmux_ops,
1316 .confops = &byt_pinconf_ops,
1317 .owner = THIS_MODULE,
1318 };
1319
byt_gpio_get(struct gpio_chip * chip,unsigned offset)1320 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1321 {
1322 struct byt_gpio *vg = gpiochip_get_data(chip);
1323 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1324 unsigned long flags;
1325 u32 val;
1326
1327 raw_spin_lock_irqsave(&byt_lock, flags);
1328 val = readl(reg);
1329 raw_spin_unlock_irqrestore(&byt_lock, flags);
1330
1331 return !!(val & BYT_LEVEL);
1332 }
1333
byt_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1334 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1335 {
1336 struct byt_gpio *vg = gpiochip_get_data(chip);
1337 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1338 unsigned long flags;
1339 u32 old_val;
1340
1341 if (!reg)
1342 return;
1343
1344 raw_spin_lock_irqsave(&byt_lock, flags);
1345 old_val = readl(reg);
1346 if (value)
1347 writel(old_val | BYT_LEVEL, reg);
1348 else
1349 writel(old_val & ~BYT_LEVEL, reg);
1350 raw_spin_unlock_irqrestore(&byt_lock, flags);
1351 }
1352
byt_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1353 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1354 {
1355 struct byt_gpio *vg = gpiochip_get_data(chip);
1356 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1357 unsigned long flags;
1358 u32 value;
1359
1360 if (!reg)
1361 return -EINVAL;
1362
1363 raw_spin_lock_irqsave(&byt_lock, flags);
1364 value = readl(reg);
1365 raw_spin_unlock_irqrestore(&byt_lock, flags);
1366
1367 if (!(value & BYT_OUTPUT_EN))
1368 return GPIOF_DIR_OUT;
1369 if (!(value & BYT_INPUT_EN))
1370 return GPIOF_DIR_IN;
1371
1372 return -EINVAL;
1373 }
1374
byt_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1375 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1376 {
1377 return pinctrl_gpio_direction_input(chip->base + offset);
1378 }
1379
byt_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1380 static int byt_gpio_direction_output(struct gpio_chip *chip,
1381 unsigned int offset, int value)
1382 {
1383 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1384
1385 if (ret)
1386 return ret;
1387
1388 byt_gpio_set(chip, offset, value);
1389
1390 return 0;
1391 }
1392
byt_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1393 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1394 {
1395 struct byt_gpio *vg = gpiochip_get_data(chip);
1396 int i;
1397 u32 conf0, val;
1398
1399 for (i = 0; i < vg->soc_data->npins; i++) {
1400 const struct byt_community *comm;
1401 const char *pull_str = NULL;
1402 const char *pull = NULL;
1403 void __iomem *reg;
1404 unsigned long flags;
1405 const char *label;
1406 unsigned int pin;
1407
1408 raw_spin_lock_irqsave(&byt_lock, flags);
1409 pin = vg->soc_data->pins[i].number;
1410 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1411 if (!reg) {
1412 seq_printf(s,
1413 "Could not retrieve pin %i conf0 reg\n",
1414 pin);
1415 raw_spin_unlock_irqrestore(&byt_lock, flags);
1416 continue;
1417 }
1418 conf0 = readl(reg);
1419
1420 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1421 if (!reg) {
1422 seq_printf(s,
1423 "Could not retrieve pin %i val reg\n", pin);
1424 raw_spin_unlock_irqrestore(&byt_lock, flags);
1425 continue;
1426 }
1427 val = readl(reg);
1428 raw_spin_unlock_irqrestore(&byt_lock, flags);
1429
1430 comm = byt_get_community(vg, pin);
1431 if (!comm) {
1432 seq_printf(s,
1433 "Could not get community for pin %i\n", pin);
1434 continue;
1435 }
1436 label = gpiochip_is_requested(chip, i);
1437 if (!label)
1438 label = "Unrequested";
1439
1440 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1441 case BYT_PULL_ASSIGN_UP:
1442 pull = "up";
1443 break;
1444 case BYT_PULL_ASSIGN_DOWN:
1445 pull = "down";
1446 break;
1447 }
1448
1449 switch (conf0 & BYT_PULL_STR_MASK) {
1450 case BYT_PULL_STR_2K:
1451 pull_str = "2k";
1452 break;
1453 case BYT_PULL_STR_10K:
1454 pull_str = "10k";
1455 break;
1456 case BYT_PULL_STR_20K:
1457 pull_str = "20k";
1458 break;
1459 case BYT_PULL_STR_40K:
1460 pull_str = "40k";
1461 break;
1462 }
1463
1464 seq_printf(s,
1465 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1466 pin,
1467 label,
1468 val & BYT_INPUT_EN ? " " : "in",
1469 val & BYT_OUTPUT_EN ? " " : "out",
1470 val & BYT_LEVEL ? "hi" : "lo",
1471 comm->pad_map[i], comm->pad_map[i] * 16,
1472 conf0 & 0x7,
1473 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1474 conf0 & BYT_TRIG_POS ? " rise" : " ",
1475 conf0 & BYT_TRIG_LVL ? " level" : " ");
1476
1477 if (pull && pull_str)
1478 seq_printf(s, " %-4s %-3s", pull, pull_str);
1479 else
1480 seq_puts(s, " ");
1481
1482 if (conf0 & BYT_IODEN)
1483 seq_puts(s, " open-drain");
1484
1485 seq_puts(s, "\n");
1486 }
1487 }
1488
1489 static const struct gpio_chip byt_gpio_chip = {
1490 .owner = THIS_MODULE,
1491 .request = gpiochip_generic_request,
1492 .free = gpiochip_generic_free,
1493 .get_direction = byt_gpio_get_direction,
1494 .direction_input = byt_gpio_direction_input,
1495 .direction_output = byt_gpio_direction_output,
1496 .get = byt_gpio_get,
1497 .set = byt_gpio_set,
1498 .set_config = gpiochip_generic_config,
1499 .dbg_show = byt_gpio_dbg_show,
1500 };
1501
byt_irq_ack(struct irq_data * d)1502 static void byt_irq_ack(struct irq_data *d)
1503 {
1504 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1505 struct byt_gpio *vg = gpiochip_get_data(gc);
1506 unsigned offset = irqd_to_hwirq(d);
1507 void __iomem *reg;
1508
1509 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1510 if (!reg)
1511 return;
1512
1513 raw_spin_lock(&byt_lock);
1514 writel(BIT(offset % 32), reg);
1515 raw_spin_unlock(&byt_lock);
1516 }
1517
byt_irq_mask(struct irq_data * d)1518 static void byt_irq_mask(struct irq_data *d)
1519 {
1520 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1521 struct byt_gpio *vg = gpiochip_get_data(gc);
1522
1523 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1524 }
1525
byt_irq_unmask(struct irq_data * d)1526 static void byt_irq_unmask(struct irq_data *d)
1527 {
1528 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1529 struct byt_gpio *vg = gpiochip_get_data(gc);
1530 unsigned offset = irqd_to_hwirq(d);
1531 unsigned long flags;
1532 void __iomem *reg;
1533 u32 value;
1534
1535 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1536 if (!reg)
1537 return;
1538
1539 raw_spin_lock_irqsave(&byt_lock, flags);
1540 value = readl(reg);
1541
1542 switch (irqd_get_trigger_type(d)) {
1543 case IRQ_TYPE_LEVEL_HIGH:
1544 value |= BYT_TRIG_LVL;
1545 /* fall through */
1546 case IRQ_TYPE_EDGE_RISING:
1547 value |= BYT_TRIG_POS;
1548 break;
1549 case IRQ_TYPE_LEVEL_LOW:
1550 value |= BYT_TRIG_LVL;
1551 /* fall through */
1552 case IRQ_TYPE_EDGE_FALLING:
1553 value |= BYT_TRIG_NEG;
1554 break;
1555 case IRQ_TYPE_EDGE_BOTH:
1556 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1557 break;
1558 }
1559
1560 writel(value, reg);
1561
1562 raw_spin_unlock_irqrestore(&byt_lock, flags);
1563 }
1564
byt_irq_type(struct irq_data * d,unsigned int type)1565 static int byt_irq_type(struct irq_data *d, unsigned int type)
1566 {
1567 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1568 u32 offset = irqd_to_hwirq(d);
1569 u32 value;
1570 unsigned long flags;
1571 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1572
1573 if (!reg || offset >= vg->chip.ngpio)
1574 return -EINVAL;
1575
1576 raw_spin_lock_irqsave(&byt_lock, flags);
1577 value = readl(reg);
1578
1579 WARN(value & BYT_DIRECT_IRQ_EN,
1580 "Bad pad config for io mode, force direct_irq_en bit clearing");
1581
1582 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1583 * are used to indicate high and low level triggering
1584 */
1585 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1586 BYT_TRIG_LVL);
1587 /* Enable glitch filtering */
1588 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1589 BYT_GLITCH_F_FAST_CLK;
1590
1591 writel(value, reg);
1592
1593 if (type & IRQ_TYPE_EDGE_BOTH)
1594 irq_set_handler_locked(d, handle_edge_irq);
1595 else if (type & IRQ_TYPE_LEVEL_MASK)
1596 irq_set_handler_locked(d, handle_level_irq);
1597
1598 raw_spin_unlock_irqrestore(&byt_lock, flags);
1599
1600 return 0;
1601 }
1602
1603 static struct irq_chip byt_irqchip = {
1604 .name = "BYT-GPIO",
1605 .irq_ack = byt_irq_ack,
1606 .irq_mask = byt_irq_mask,
1607 .irq_unmask = byt_irq_unmask,
1608 .irq_set_type = byt_irq_type,
1609 .flags = IRQCHIP_SKIP_SET_WAKE,
1610 };
1611
byt_gpio_irq_handler(struct irq_desc * desc)1612 static void byt_gpio_irq_handler(struct irq_desc *desc)
1613 {
1614 struct irq_data *data = irq_desc_get_irq_data(desc);
1615 struct byt_gpio *vg = gpiochip_get_data(
1616 irq_desc_get_handler_data(desc));
1617 struct irq_chip *chip = irq_data_get_irq_chip(data);
1618 u32 base, pin;
1619 void __iomem *reg;
1620 unsigned long pending;
1621 unsigned int virq;
1622
1623 /* check from GPIO controller which pin triggered the interrupt */
1624 for (base = 0; base < vg->chip.ngpio; base += 32) {
1625 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1626
1627 if (!reg) {
1628 dev_warn(&vg->pdev->dev,
1629 "Pin %i: could not retrieve interrupt status register\n",
1630 base);
1631 continue;
1632 }
1633
1634 raw_spin_lock(&byt_lock);
1635 pending = readl(reg);
1636 raw_spin_unlock(&byt_lock);
1637 for_each_set_bit(pin, &pending, 32) {
1638 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1639 generic_handle_irq(virq);
1640 }
1641 }
1642 chip->irq_eoi(data);
1643 }
1644
byt_gpio_irq_init_hw(struct byt_gpio * vg)1645 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1646 {
1647 struct gpio_chip *gc = &vg->chip;
1648 struct device *dev = &vg->pdev->dev;
1649 void __iomem *reg;
1650 u32 base, value;
1651 int i;
1652
1653 /*
1654 * Clear interrupt triggers for all pins that are GPIOs and
1655 * do not use direct IRQ mode. This will prevent spurious
1656 * interrupts from misconfigured pins.
1657 */
1658 for (i = 0; i < vg->soc_data->npins; i++) {
1659 unsigned int pin = vg->soc_data->pins[i].number;
1660
1661 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1662 if (!reg) {
1663 dev_warn(&vg->pdev->dev,
1664 "Pin %i: could not retrieve conf0 register\n",
1665 i);
1666 continue;
1667 }
1668
1669 value = readl(reg);
1670 if (value & BYT_DIRECT_IRQ_EN) {
1671 clear_bit(i, gc->irq.valid_mask);
1672 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1673 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1674 byt_gpio_clear_triggering(vg, i);
1675 dev_dbg(dev, "disabling GPIO %d\n", i);
1676 }
1677 }
1678
1679 /* clear interrupt status trigger registers */
1680 for (base = 0; base < vg->soc_data->npins; base += 32) {
1681 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1682
1683 if (!reg) {
1684 dev_warn(&vg->pdev->dev,
1685 "Pin %i: could not retrieve irq status reg\n",
1686 base);
1687 continue;
1688 }
1689
1690 writel(0xffffffff, reg);
1691 /* make sure trigger bits are cleared, if not then a pin
1692 might be misconfigured in bios */
1693 value = readl(reg);
1694 if (value)
1695 dev_err(&vg->pdev->dev,
1696 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1697 base / 32, value);
1698 }
1699 }
1700
byt_gpio_probe(struct byt_gpio * vg)1701 static int byt_gpio_probe(struct byt_gpio *vg)
1702 {
1703 struct gpio_chip *gc;
1704 struct resource *irq_rc;
1705 int ret;
1706
1707 /* Set up gpio chip */
1708 vg->chip = byt_gpio_chip;
1709 gc = &vg->chip;
1710 gc->label = dev_name(&vg->pdev->dev);
1711 gc->base = -1;
1712 gc->can_sleep = false;
1713 gc->parent = &vg->pdev->dev;
1714 gc->ngpio = vg->soc_data->npins;
1715 gc->irq.need_valid_mask = true;
1716
1717 #ifdef CONFIG_PM_SLEEP
1718 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1719 sizeof(*vg->saved_context), GFP_KERNEL);
1720 #endif
1721 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1722 if (ret) {
1723 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1724 return ret;
1725 }
1726
1727 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1728 0, 0, vg->soc_data->npins);
1729 if (ret) {
1730 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1731 return ret;
1732 }
1733
1734 /* set up interrupts */
1735 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1736 if (irq_rc && irq_rc->start) {
1737 byt_gpio_irq_init_hw(vg);
1738 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1739 handle_bad_irq, IRQ_TYPE_NONE);
1740 if (ret) {
1741 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1742 return ret;
1743 }
1744
1745 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1746 (unsigned)irq_rc->start,
1747 byt_gpio_irq_handler);
1748 }
1749
1750 return ret;
1751 }
1752
byt_set_soc_data(struct byt_gpio * vg,const struct byt_pinctrl_soc_data * soc_data)1753 static int byt_set_soc_data(struct byt_gpio *vg,
1754 const struct byt_pinctrl_soc_data *soc_data)
1755 {
1756 int i;
1757
1758 vg->soc_data = soc_data;
1759 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1760 soc_data->ncommunities,
1761 sizeof(*vg->communities_copy),
1762 GFP_KERNEL);
1763 if (!vg->communities_copy)
1764 return -ENOMEM;
1765
1766 for (i = 0; i < soc_data->ncommunities; i++) {
1767 struct byt_community *comm = vg->communities_copy + i;
1768 struct resource *mem_rc;
1769
1770 *comm = vg->soc_data->communities[i];
1771
1772 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1773 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1774 if (IS_ERR(comm->reg_base))
1775 return PTR_ERR(comm->reg_base);
1776 }
1777
1778 return 0;
1779 }
1780
1781 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1782 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1783 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1784 { }
1785 };
1786 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1787
byt_pinctrl_probe(struct platform_device * pdev)1788 static int byt_pinctrl_probe(struct platform_device *pdev)
1789 {
1790 const struct byt_pinctrl_soc_data *soc_data = NULL;
1791 const struct byt_pinctrl_soc_data **soc_table;
1792 const struct acpi_device_id *acpi_id;
1793 struct acpi_device *acpi_dev;
1794 struct byt_gpio *vg;
1795 int i, ret;
1796
1797 acpi_dev = ACPI_COMPANION(&pdev->dev);
1798 if (!acpi_dev)
1799 return -ENODEV;
1800
1801 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1802 if (!acpi_id)
1803 return -ENODEV;
1804
1805 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1806
1807 for (i = 0; soc_table[i]; i++) {
1808 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1809 soc_data = soc_table[i];
1810 break;
1811 }
1812 }
1813
1814 if (!soc_data)
1815 return -ENODEV;
1816
1817 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1818 if (!vg)
1819 return -ENOMEM;
1820
1821 vg->pdev = pdev;
1822 ret = byt_set_soc_data(vg, soc_data);
1823 if (ret) {
1824 dev_err(&pdev->dev, "failed to set soc data\n");
1825 return ret;
1826 }
1827
1828 vg->pctl_desc = byt_pinctrl_desc;
1829 vg->pctl_desc.name = dev_name(&pdev->dev);
1830 vg->pctl_desc.pins = vg->soc_data->pins;
1831 vg->pctl_desc.npins = vg->soc_data->npins;
1832
1833 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1834 if (IS_ERR(vg->pctl_dev)) {
1835 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1836 return PTR_ERR(vg->pctl_dev);
1837 }
1838
1839 ret = byt_gpio_probe(vg);
1840 if (ret)
1841 return ret;
1842
1843 platform_set_drvdata(pdev, vg);
1844 pm_runtime_enable(&pdev->dev);
1845
1846 return 0;
1847 }
1848
1849 #ifdef CONFIG_PM_SLEEP
byt_gpio_suspend(struct device * dev)1850 static int byt_gpio_suspend(struct device *dev)
1851 {
1852 struct platform_device *pdev = to_platform_device(dev);
1853 struct byt_gpio *vg = platform_get_drvdata(pdev);
1854 unsigned long flags;
1855 int i;
1856
1857 raw_spin_lock_irqsave(&byt_lock, flags);
1858
1859 for (i = 0; i < vg->soc_data->npins; i++) {
1860 void __iomem *reg;
1861 u32 value;
1862 unsigned int pin = vg->soc_data->pins[i].number;
1863
1864 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1865 if (!reg) {
1866 dev_warn(&vg->pdev->dev,
1867 "Pin %i: could not retrieve conf0 register\n",
1868 i);
1869 continue;
1870 }
1871 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1872 vg->saved_context[i].conf0 = value;
1873
1874 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1875 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1876 vg->saved_context[i].val = value;
1877 }
1878
1879 raw_spin_unlock_irqrestore(&byt_lock, flags);
1880 return 0;
1881 }
1882
byt_gpio_resume(struct device * dev)1883 static int byt_gpio_resume(struct device *dev)
1884 {
1885 struct platform_device *pdev = to_platform_device(dev);
1886 struct byt_gpio *vg = platform_get_drvdata(pdev);
1887 unsigned long flags;
1888 int i;
1889
1890 raw_spin_lock_irqsave(&byt_lock, flags);
1891
1892 for (i = 0; i < vg->soc_data->npins; i++) {
1893 void __iomem *reg;
1894 u32 value;
1895 unsigned int pin = vg->soc_data->pins[i].number;
1896
1897 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1898 if (!reg) {
1899 dev_warn(&vg->pdev->dev,
1900 "Pin %i: could not retrieve conf0 register\n",
1901 i);
1902 continue;
1903 }
1904 value = readl(reg);
1905 if ((value & BYT_CONF0_RESTORE_MASK) !=
1906 vg->saved_context[i].conf0) {
1907 value &= ~BYT_CONF0_RESTORE_MASK;
1908 value |= vg->saved_context[i].conf0;
1909 writel(value, reg);
1910 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1911 }
1912
1913 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1914 value = readl(reg);
1915 if ((value & BYT_VAL_RESTORE_MASK) !=
1916 vg->saved_context[i].val) {
1917 u32 v;
1918
1919 v = value & ~BYT_VAL_RESTORE_MASK;
1920 v |= vg->saved_context[i].val;
1921 if (v != value) {
1922 writel(v, reg);
1923 dev_dbg(dev, "restored pin %d val %#08x\n",
1924 i, v);
1925 }
1926 }
1927 }
1928
1929 raw_spin_unlock_irqrestore(&byt_lock, flags);
1930 return 0;
1931 }
1932 #endif
1933
1934 #ifdef CONFIG_PM
byt_gpio_runtime_suspend(struct device * dev)1935 static int byt_gpio_runtime_suspend(struct device *dev)
1936 {
1937 return 0;
1938 }
1939
byt_gpio_runtime_resume(struct device * dev)1940 static int byt_gpio_runtime_resume(struct device *dev)
1941 {
1942 return 0;
1943 }
1944 #endif
1945
1946 static const struct dev_pm_ops byt_gpio_pm_ops = {
1947 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1948 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1949 NULL)
1950 };
1951
1952 static struct platform_driver byt_gpio_driver = {
1953 .probe = byt_pinctrl_probe,
1954 .driver = {
1955 .name = "byt_gpio",
1956 .pm = &byt_gpio_pm_ops,
1957 .suppress_bind_attrs = true,
1958
1959 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1960 },
1961 };
1962
byt_gpio_init(void)1963 static int __init byt_gpio_init(void)
1964 {
1965 return platform_driver_register(&byt_gpio_driver);
1966 }
1967 subsys_initcall(byt_gpio_init);
1968