1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8 #include <linux/delay.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
26
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
36
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39 static int qla82xx_crb_table_initialized;
40
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45 const int MD_MIU_TEST_AGT_RDDATA[] = {
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
48 };
49
qla82xx_crb_addr_transform_setup(void)50 static void qla82xx_crb_addr_transform_setup(void)
51 {
52 qla82xx_crb_addr_transform(XDMA);
53 qla82xx_crb_addr_transform(TIMR);
54 qla82xx_crb_addr_transform(SRE);
55 qla82xx_crb_addr_transform(SQN3);
56 qla82xx_crb_addr_transform(SQN2);
57 qla82xx_crb_addr_transform(SQN1);
58 qla82xx_crb_addr_transform(SQN0);
59 qla82xx_crb_addr_transform(SQS3);
60 qla82xx_crb_addr_transform(SQS2);
61 qla82xx_crb_addr_transform(SQS1);
62 qla82xx_crb_addr_transform(SQS0);
63 qla82xx_crb_addr_transform(RPMX7);
64 qla82xx_crb_addr_transform(RPMX6);
65 qla82xx_crb_addr_transform(RPMX5);
66 qla82xx_crb_addr_transform(RPMX4);
67 qla82xx_crb_addr_transform(RPMX3);
68 qla82xx_crb_addr_transform(RPMX2);
69 qla82xx_crb_addr_transform(RPMX1);
70 qla82xx_crb_addr_transform(RPMX0);
71 qla82xx_crb_addr_transform(ROMUSB);
72 qla82xx_crb_addr_transform(SN);
73 qla82xx_crb_addr_transform(QMN);
74 qla82xx_crb_addr_transform(QMS);
75 qla82xx_crb_addr_transform(PGNI);
76 qla82xx_crb_addr_transform(PGND);
77 qla82xx_crb_addr_transform(PGN3);
78 qla82xx_crb_addr_transform(PGN2);
79 qla82xx_crb_addr_transform(PGN1);
80 qla82xx_crb_addr_transform(PGN0);
81 qla82xx_crb_addr_transform(PGSI);
82 qla82xx_crb_addr_transform(PGSD);
83 qla82xx_crb_addr_transform(PGS3);
84 qla82xx_crb_addr_transform(PGS2);
85 qla82xx_crb_addr_transform(PGS1);
86 qla82xx_crb_addr_transform(PGS0);
87 qla82xx_crb_addr_transform(PS);
88 qla82xx_crb_addr_transform(PH);
89 qla82xx_crb_addr_transform(NIU);
90 qla82xx_crb_addr_transform(I2Q);
91 qla82xx_crb_addr_transform(EG);
92 qla82xx_crb_addr_transform(MN);
93 qla82xx_crb_addr_transform(MS);
94 qla82xx_crb_addr_transform(CAS2);
95 qla82xx_crb_addr_transform(CAS1);
96 qla82xx_crb_addr_transform(CAS0);
97 qla82xx_crb_addr_transform(CAM);
98 qla82xx_crb_addr_transform(C2C1);
99 qla82xx_crb_addr_transform(C2C0);
100 qla82xx_crb_addr_transform(SMB);
101 qla82xx_crb_addr_transform(OCM0);
102 /*
103 * Used only in P3 just define it for P2 also.
104 */
105 qla82xx_crb_addr_transform(I2C0);
106
107 qla82xx_crb_table_initialized = 1;
108 }
109
110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
111 {{{0, 0, 0, 0} } },
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
129 {{{0, 0, 0, 0} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
218 {{{0} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{0} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
253 {{{0} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
260 {{{0} } },
261 {{{0} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
265 };
266
267 /*
268 * top 12 bits of crb internal address (hub, agent)
269 */
270 static unsigned qla82xx_crb_hub_agt[64] = {
271 0,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
275 0,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
303 0,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
306 0,
307 0,
308 0,
309 0,
310 0,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
312 0,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
328 0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
332 0,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
334 0,
335 };
336
337 /* Device states */
338 static char *q_dev_state[] = {
339 "Unknown",
340 "Cold",
341 "Initializing",
342 "Ready",
343 "Need Reset",
344 "Need Quiescent",
345 "Failed",
346 "Quiescent",
347 };
348
qdev_state(uint32_t dev_state)349 char *qdev_state(uint32_t dev_state)
350 {
351 return q_dev_state[dev_state];
352 }
353
354 /*
355 * In: 'off_in' is offset from CRB space in 128M pci map
356 * Out: 'off_out' is 2M pci map addr
357 * side effect: lock crb window
358 */
359 static void
qla82xx_pci_set_crbwindow_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
361 void __iomem **off_out)
362 {
363 u32 win_read;
364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
365
366 ha->crb_win = CRB_HI(off_in);
367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
368
369 /* Read back value to make sure write has gone through before trying
370 * to use it.
371 */
372 win_read = RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
373 if (win_read != ha->crb_win) {
374 ql_dbg(ql_dbg_p3p, vha, 0xb000,
375 "%s: Written crbwin (0x%x) "
376 "!= Read crbwin (0x%x), off=0x%lx.\n",
377 __func__, ha->crb_win, win_read, off_in);
378 }
379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
380 }
381
382 static inline unsigned long
qla82xx_pci_set_crbwindow(struct qla_hw_data * ha,u64 off)383 qla82xx_pci_set_crbwindow(struct qla_hw_data *ha, u64 off)
384 {
385 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
386 /* See if we are currently pointing to the region we want to use next */
387 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_DDR_NET)) {
388 /* No need to change window. PCIX and PCIEregs are in both
389 * regs are in both windows.
390 */
391 return off;
392 }
393
394 if ((off >= QLA82XX_CRB_PCIX_HOST) && (off < QLA82XX_CRB_PCIX_HOST2)) {
395 /* We are in first CRB window */
396 if (ha->curr_window != 0)
397 WARN_ON(1);
398 return off;
399 }
400
401 if ((off > QLA82XX_CRB_PCIX_HOST2) && (off < QLA82XX_CRB_MAX)) {
402 /* We are in second CRB window */
403 off = off - QLA82XX_CRB_PCIX_HOST2 + QLA82XX_CRB_PCIX_HOST;
404
405 if (ha->curr_window != 1)
406 return off;
407
408 /* We are in the QM or direct access
409 * register region - do nothing
410 */
411 if ((off >= QLA82XX_PCI_DIRECT_CRB) &&
412 (off < QLA82XX_PCI_CAMQM_MAX))
413 return off;
414 }
415 /* strange address given */
416 ql_dbg(ql_dbg_p3p, vha, 0xb001,
417 "%s: Warning: unm_nic_pci_set_crbwindow "
418 "called with an unknown address(%llx).\n",
419 QLA2XXX_DRIVER_NAME, off);
420 return off;
421 }
422
423 static int
qla82xx_pci_get_crb_addr_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)424 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
425 void __iomem **off_out)
426 {
427 struct crb_128M_2M_sub_block_map *m;
428
429 if (off_in >= QLA82XX_CRB_MAX)
430 return -1;
431
432 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
433 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
434 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
435 return 0;
436 }
437
438 if (off_in < QLA82XX_PCI_CRBSPACE)
439 return -1;
440
441 off_in -= QLA82XX_PCI_CRBSPACE;
442
443 /* Try direct map */
444 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
445
446 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
447 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
448 return 0;
449 }
450 /* Not in direct map, use crb window */
451 *off_out = (void __iomem *)off_in;
452 return 1;
453 }
454
455 #define CRB_WIN_LOCK_TIMEOUT 100000000
qla82xx_crb_win_lock(struct qla_hw_data * ha)456 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
457 {
458 int done = 0, timeout = 0;
459
460 while (!done) {
461 /* acquire semaphore3 from PCI HW block */
462 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
463 if (done == 1)
464 break;
465 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
466 return -1;
467 timeout++;
468 }
469 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
470 return 0;
471 }
472
473 int
qla82xx_wr_32(struct qla_hw_data * ha,ulong off_in,u32 data)474 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
475 {
476 void __iomem *off;
477 unsigned long flags = 0;
478 int rv;
479
480 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
481
482 BUG_ON(rv == -1);
483
484 if (rv == 1) {
485 #ifndef __CHECKER__
486 write_lock_irqsave(&ha->hw_lock, flags);
487 #endif
488 qla82xx_crb_win_lock(ha);
489 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
490 }
491
492 writel(data, (void __iomem *)off);
493
494 if (rv == 1) {
495 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
496 #ifndef __CHECKER__
497 write_unlock_irqrestore(&ha->hw_lock, flags);
498 #endif
499 }
500 return 0;
501 }
502
503 int
qla82xx_rd_32(struct qla_hw_data * ha,ulong off_in)504 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
505 {
506 void __iomem *off;
507 unsigned long flags = 0;
508 int rv;
509 u32 data;
510
511 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
512
513 BUG_ON(rv == -1);
514
515 if (rv == 1) {
516 #ifndef __CHECKER__
517 write_lock_irqsave(&ha->hw_lock, flags);
518 #endif
519 qla82xx_crb_win_lock(ha);
520 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
521 }
522 data = RD_REG_DWORD(off);
523
524 if (rv == 1) {
525 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
526 #ifndef __CHECKER__
527 write_unlock_irqrestore(&ha->hw_lock, flags);
528 #endif
529 }
530 return data;
531 }
532
533 #define IDC_LOCK_TIMEOUT 100000000
qla82xx_idc_lock(struct qla_hw_data * ha)534 int qla82xx_idc_lock(struct qla_hw_data *ha)
535 {
536 int i;
537 int done = 0, timeout = 0;
538
539 while (!done) {
540 /* acquire semaphore5 from PCI HW block */
541 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
542 if (done == 1)
543 break;
544 if (timeout >= IDC_LOCK_TIMEOUT)
545 return -1;
546
547 timeout++;
548
549 /* Yield CPU */
550 if (!in_interrupt())
551 schedule();
552 else {
553 for (i = 0; i < 20; i++)
554 cpu_relax();
555 }
556 }
557
558 return 0;
559 }
560
qla82xx_idc_unlock(struct qla_hw_data * ha)561 void qla82xx_idc_unlock(struct qla_hw_data *ha)
562 {
563 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
564 }
565
566 /*
567 * check memory access boundary.
568 * used by test agent. support ddr access only for now
569 */
570 static unsigned long
qla82xx_pci_mem_bound_check(struct qla_hw_data * ha,unsigned long long addr,int size)571 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
572 unsigned long long addr, int size)
573 {
574 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
575 QLA82XX_ADDR_DDR_NET_MAX) ||
576 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
577 QLA82XX_ADDR_DDR_NET_MAX) ||
578 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
579 return 0;
580 else
581 return 1;
582 }
583
584 static int qla82xx_pci_set_window_warning_count;
585
586 static unsigned long
qla82xx_pci_set_window(struct qla_hw_data * ha,unsigned long long addr)587 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
588 {
589 int window;
590 u32 win_read;
591 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
592
593 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
594 QLA82XX_ADDR_DDR_NET_MAX)) {
595 /* DDR network side */
596 window = MN_WIN(addr);
597 ha->ddr_mn_window = window;
598 qla82xx_wr_32(ha,
599 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
600 win_read = qla82xx_rd_32(ha,
601 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
602 if ((win_read << 17) != window) {
603 ql_dbg(ql_dbg_p3p, vha, 0xb003,
604 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
605 __func__, window, win_read);
606 }
607 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
608 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
609 QLA82XX_ADDR_OCM0_MAX)) {
610 unsigned int temp1;
611 if ((addr & 0x00ff800) == 0xff800) {
612 ql_log(ql_log_warn, vha, 0xb004,
613 "%s: QM access not handled.\n", __func__);
614 addr = -1UL;
615 }
616 window = OCM_WIN(addr);
617 ha->ddr_mn_window = window;
618 qla82xx_wr_32(ha,
619 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
620 win_read = qla82xx_rd_32(ha,
621 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
622 temp1 = ((window & 0x1FF) << 7) |
623 ((window & 0x0FFFE0000) >> 17);
624 if (win_read != temp1) {
625 ql_log(ql_log_warn, vha, 0xb005,
626 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
627 __func__, temp1, win_read);
628 }
629 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
630
631 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
632 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
633 /* QDR network side */
634 window = MS_WIN(addr);
635 ha->qdr_sn_window = window;
636 qla82xx_wr_32(ha,
637 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
638 win_read = qla82xx_rd_32(ha,
639 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
640 if (win_read != window) {
641 ql_log(ql_log_warn, vha, 0xb006,
642 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
643 __func__, window, win_read);
644 }
645 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
646 } else {
647 /*
648 * peg gdb frequently accesses memory that doesn't exist,
649 * this limits the chit chat so debugging isn't slowed down.
650 */
651 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
652 (qla82xx_pci_set_window_warning_count%64 == 0)) {
653 ql_log(ql_log_warn, vha, 0xb007,
654 "%s: Warning:%s Unknown address range!.\n",
655 __func__, QLA2XXX_DRIVER_NAME);
656 }
657 addr = -1UL;
658 }
659 return addr;
660 }
661
662 /* check if address is in the same windows as the previous access */
qla82xx_pci_is_same_window(struct qla_hw_data * ha,unsigned long long addr)663 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
664 unsigned long long addr)
665 {
666 int window;
667 unsigned long long qdr_max;
668
669 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
670
671 /* DDR network side */
672 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
673 QLA82XX_ADDR_DDR_NET_MAX))
674 BUG();
675 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
676 QLA82XX_ADDR_OCM0_MAX))
677 return 1;
678 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
679 QLA82XX_ADDR_OCM1_MAX))
680 return 1;
681 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
682 /* QDR network side */
683 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
684 if (ha->qdr_sn_window == window)
685 return 1;
686 }
687 return 0;
688 }
689
qla82xx_pci_mem_read_direct(struct qla_hw_data * ha,u64 off,void * data,int size)690 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
691 u64 off, void *data, int size)
692 {
693 unsigned long flags;
694 void __iomem *addr = NULL;
695 int ret = 0;
696 u64 start;
697 uint8_t __iomem *mem_ptr = NULL;
698 unsigned long mem_base;
699 unsigned long mem_page;
700 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
701
702 write_lock_irqsave(&ha->hw_lock, flags);
703
704 /*
705 * If attempting to access unknown address or straddle hw windows,
706 * do not access.
707 */
708 start = qla82xx_pci_set_window(ha, off);
709 if ((start == -1UL) ||
710 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
711 write_unlock_irqrestore(&ha->hw_lock, flags);
712 ql_log(ql_log_fatal, vha, 0xb008,
713 "%s out of bound pci memory "
714 "access, offset is 0x%llx.\n",
715 QLA2XXX_DRIVER_NAME, off);
716 return -1;
717 }
718
719 write_unlock_irqrestore(&ha->hw_lock, flags);
720 mem_base = pci_resource_start(ha->pdev, 0);
721 mem_page = start & PAGE_MASK;
722 /* Map two pages whenever user tries to access addresses in two
723 * consecutive pages.
724 */
725 if (mem_page != ((start + size - 1) & PAGE_MASK))
726 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
727 else
728 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
729 if (mem_ptr == NULL) {
730 *(u8 *)data = 0;
731 return -1;
732 }
733 addr = mem_ptr;
734 addr += start & (PAGE_SIZE - 1);
735 write_lock_irqsave(&ha->hw_lock, flags);
736
737 switch (size) {
738 case 1:
739 *(u8 *)data = readb(addr);
740 break;
741 case 2:
742 *(u16 *)data = readw(addr);
743 break;
744 case 4:
745 *(u32 *)data = readl(addr);
746 break;
747 case 8:
748 *(u64 *)data = readq(addr);
749 break;
750 default:
751 ret = -1;
752 break;
753 }
754 write_unlock_irqrestore(&ha->hw_lock, flags);
755
756 if (mem_ptr)
757 iounmap(mem_ptr);
758 return ret;
759 }
760
761 static int
qla82xx_pci_mem_write_direct(struct qla_hw_data * ha,u64 off,void * data,int size)762 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
763 u64 off, void *data, int size)
764 {
765 unsigned long flags;
766 void __iomem *addr = NULL;
767 int ret = 0;
768 u64 start;
769 uint8_t __iomem *mem_ptr = NULL;
770 unsigned long mem_base;
771 unsigned long mem_page;
772 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
773
774 write_lock_irqsave(&ha->hw_lock, flags);
775
776 /*
777 * If attempting to access unknown address or straddle hw windows,
778 * do not access.
779 */
780 start = qla82xx_pci_set_window(ha, off);
781 if ((start == -1UL) ||
782 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
783 write_unlock_irqrestore(&ha->hw_lock, flags);
784 ql_log(ql_log_fatal, vha, 0xb009,
785 "%s out of bound memory "
786 "access, offset is 0x%llx.\n",
787 QLA2XXX_DRIVER_NAME, off);
788 return -1;
789 }
790
791 write_unlock_irqrestore(&ha->hw_lock, flags);
792 mem_base = pci_resource_start(ha->pdev, 0);
793 mem_page = start & PAGE_MASK;
794 /* Map two pages whenever user tries to access addresses in two
795 * consecutive pages.
796 */
797 if (mem_page != ((start + size - 1) & PAGE_MASK))
798 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
799 else
800 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
801 if (mem_ptr == NULL)
802 return -1;
803
804 addr = mem_ptr;
805 addr += start & (PAGE_SIZE - 1);
806 write_lock_irqsave(&ha->hw_lock, flags);
807
808 switch (size) {
809 case 1:
810 writeb(*(u8 *)data, addr);
811 break;
812 case 2:
813 writew(*(u16 *)data, addr);
814 break;
815 case 4:
816 writel(*(u32 *)data, addr);
817 break;
818 case 8:
819 writeq(*(u64 *)data, addr);
820 break;
821 default:
822 ret = -1;
823 break;
824 }
825 write_unlock_irqrestore(&ha->hw_lock, flags);
826 if (mem_ptr)
827 iounmap(mem_ptr);
828 return ret;
829 }
830
831 #define MTU_FUDGE_FACTOR 100
832 static unsigned long
qla82xx_decode_crb_addr(unsigned long addr)833 qla82xx_decode_crb_addr(unsigned long addr)
834 {
835 int i;
836 unsigned long base_addr, offset, pci_base;
837
838 if (!qla82xx_crb_table_initialized)
839 qla82xx_crb_addr_transform_setup();
840
841 pci_base = ADDR_ERROR;
842 base_addr = addr & 0xfff00000;
843 offset = addr & 0x000fffff;
844
845 for (i = 0; i < MAX_CRB_XFORM; i++) {
846 if (crb_addr_xform[i] == base_addr) {
847 pci_base = i << 20;
848 break;
849 }
850 }
851 if (pci_base == ADDR_ERROR)
852 return pci_base;
853 return pci_base + offset;
854 }
855
856 static long rom_max_timeout = 100;
857 static long qla82xx_rom_lock_timeout = 100;
858
859 static int
qla82xx_rom_lock(struct qla_hw_data * ha)860 qla82xx_rom_lock(struct qla_hw_data *ha)
861 {
862 int done = 0, timeout = 0;
863 uint32_t lock_owner = 0;
864 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
865
866 while (!done) {
867 /* acquire semaphore2 from PCI HW block */
868 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
869 if (done == 1)
870 break;
871 if (timeout >= qla82xx_rom_lock_timeout) {
872 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
873 ql_dbg(ql_dbg_p3p, vha, 0xb157,
874 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
875 __func__, ha->portnum, lock_owner);
876 return -1;
877 }
878 timeout++;
879 }
880 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
881 return 0;
882 }
883
884 static void
qla82xx_rom_unlock(struct qla_hw_data * ha)885 qla82xx_rom_unlock(struct qla_hw_data *ha)
886 {
887 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
888 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
889 }
890
891 static int
qla82xx_wait_rom_busy(struct qla_hw_data * ha)892 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
893 {
894 long timeout = 0;
895 long done = 0 ;
896 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
897
898 while (done == 0) {
899 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
900 done &= 4;
901 timeout++;
902 if (timeout >= rom_max_timeout) {
903 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
904 "%s: Timeout reached waiting for rom busy.\n",
905 QLA2XXX_DRIVER_NAME);
906 return -1;
907 }
908 }
909 return 0;
910 }
911
912 static int
qla82xx_wait_rom_done(struct qla_hw_data * ha)913 qla82xx_wait_rom_done(struct qla_hw_data *ha)
914 {
915 long timeout = 0;
916 long done = 0 ;
917 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
918
919 while (done == 0) {
920 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
921 done &= 2;
922 timeout++;
923 if (timeout >= rom_max_timeout) {
924 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
925 "%s: Timeout reached waiting for rom done.\n",
926 QLA2XXX_DRIVER_NAME);
927 return -1;
928 }
929 }
930 return 0;
931 }
932
933 static int
qla82xx_md_rw_32(struct qla_hw_data * ha,uint32_t off,u32 data,uint8_t flag)934 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
935 {
936 uint32_t off_value, rval = 0;
937
938 WRT_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
939
940 /* Read back value to make sure write has gone through */
941 RD_REG_DWORD(CRB_WINDOW_2M + ha->nx_pcibase);
942 off_value = (off & 0x0000FFFF);
943
944 if (flag)
945 WRT_REG_DWORD(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
946 data);
947 else
948 rval = RD_REG_DWORD(off_value + CRB_INDIRECT_2M +
949 ha->nx_pcibase);
950
951 return rval;
952 }
953
954 static int
qla82xx_do_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)955 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
956 {
957 /* Dword reads to flash. */
958 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
959 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
960 (addr & 0x0000FFFF), 0, 0);
961
962 return 0;
963 }
964
965 static int
qla82xx_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)966 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
967 {
968 int ret, loops = 0;
969 uint32_t lock_owner = 0;
970 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
971
972 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
973 udelay(100);
974 schedule();
975 loops++;
976 }
977 if (loops >= 50000) {
978 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
979 ql_log(ql_log_fatal, vha, 0x00b9,
980 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
981 lock_owner);
982 return -1;
983 }
984 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
985 qla82xx_rom_unlock(ha);
986 return ret;
987 }
988
989 static int
qla82xx_read_status_reg(struct qla_hw_data * ha,uint32_t * val)990 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
991 {
992 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
993 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
994 qla82xx_wait_rom_busy(ha);
995 if (qla82xx_wait_rom_done(ha)) {
996 ql_log(ql_log_warn, vha, 0xb00c,
997 "Error waiting for rom done.\n");
998 return -1;
999 }
1000 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
1001 return 0;
1002 }
1003
1004 static int
qla82xx_flash_wait_write_finish(struct qla_hw_data * ha)1005 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
1006 {
1007 long timeout = 0;
1008 uint32_t done = 1 ;
1009 uint32_t val;
1010 int ret = 0;
1011 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1012
1013 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1014 while ((done != 0) && (ret == 0)) {
1015 ret = qla82xx_read_status_reg(ha, &val);
1016 done = val & 1;
1017 timeout++;
1018 udelay(10);
1019 cond_resched();
1020 if (timeout >= 50000) {
1021 ql_log(ql_log_warn, vha, 0xb00d,
1022 "Timeout reached waiting for write finish.\n");
1023 return -1;
1024 }
1025 }
1026 return ret;
1027 }
1028
1029 static int
qla82xx_flash_set_write_enable(struct qla_hw_data * ha)1030 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
1031 {
1032 uint32_t val;
1033 qla82xx_wait_rom_busy(ha);
1034 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
1035 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
1036 qla82xx_wait_rom_busy(ha);
1037 if (qla82xx_wait_rom_done(ha))
1038 return -1;
1039 if (qla82xx_read_status_reg(ha, &val) != 0)
1040 return -1;
1041 if ((val & 2) != 2)
1042 return -1;
1043 return 0;
1044 }
1045
1046 static int
qla82xx_write_status_reg(struct qla_hw_data * ha,uint32_t val)1047 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1048 {
1049 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1050 if (qla82xx_flash_set_write_enable(ha))
1051 return -1;
1052 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1053 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1054 if (qla82xx_wait_rom_done(ha)) {
1055 ql_log(ql_log_warn, vha, 0xb00e,
1056 "Error waiting for rom done.\n");
1057 return -1;
1058 }
1059 return qla82xx_flash_wait_write_finish(ha);
1060 }
1061
1062 static int
qla82xx_write_disable_flash(struct qla_hw_data * ha)1063 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1064 {
1065 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1066 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1067 if (qla82xx_wait_rom_done(ha)) {
1068 ql_log(ql_log_warn, vha, 0xb00f,
1069 "Error waiting for rom done.\n");
1070 return -1;
1071 }
1072 return 0;
1073 }
1074
1075 static int
ql82xx_rom_lock_d(struct qla_hw_data * ha)1076 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1077 {
1078 int loops = 0;
1079 uint32_t lock_owner = 0;
1080 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1081
1082 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1083 udelay(100);
1084 cond_resched();
1085 loops++;
1086 }
1087 if (loops >= 50000) {
1088 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1089 ql_log(ql_log_warn, vha, 0xb010,
1090 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1091 return -1;
1092 }
1093 return 0;
1094 }
1095
1096 static int
qla82xx_write_flash_dword(struct qla_hw_data * ha,uint32_t flashaddr,uint32_t data)1097 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1098 uint32_t data)
1099 {
1100 int ret = 0;
1101 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1102
1103 ret = ql82xx_rom_lock_d(ha);
1104 if (ret < 0) {
1105 ql_log(ql_log_warn, vha, 0xb011,
1106 "ROM lock failed.\n");
1107 return ret;
1108 }
1109
1110 if (qla82xx_flash_set_write_enable(ha))
1111 goto done_write;
1112
1113 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1114 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1115 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1116 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1117 qla82xx_wait_rom_busy(ha);
1118 if (qla82xx_wait_rom_done(ha)) {
1119 ql_log(ql_log_warn, vha, 0xb012,
1120 "Error waiting for rom done.\n");
1121 ret = -1;
1122 goto done_write;
1123 }
1124
1125 ret = qla82xx_flash_wait_write_finish(ha);
1126
1127 done_write:
1128 qla82xx_rom_unlock(ha);
1129 return ret;
1130 }
1131
1132 /* This routine does CRB initialize sequence
1133 * to put the ISP into operational state
1134 */
1135 static int
qla82xx_pinit_from_rom(scsi_qla_host_t * vha)1136 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1137 {
1138 int addr, val;
1139 int i ;
1140 struct crb_addr_pair *buf;
1141 unsigned long off;
1142 unsigned offset, n;
1143 struct qla_hw_data *ha = vha->hw;
1144
1145 struct crb_addr_pair {
1146 long addr;
1147 long data;
1148 };
1149
1150 /* Halt all the individual PEGs and other blocks of the ISP */
1151 qla82xx_rom_lock(ha);
1152
1153 /* disable all I2Q */
1154 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1155 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1156 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1157 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1158 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1159 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1160
1161 /* disable all niu interrupts */
1162 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1163 /* disable xge rx/tx */
1164 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1165 /* disable xg1 rx/tx */
1166 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1167 /* disable sideband mac */
1168 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1169 /* disable ap0 mac */
1170 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1171 /* disable ap1 mac */
1172 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1173
1174 /* halt sre */
1175 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1176 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1177
1178 /* halt epg */
1179 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1180
1181 /* halt timers */
1182 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1183 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1184 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1185 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1186 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1187 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1188
1189 /* halt pegs */
1190 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1191 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1192 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1193 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1194 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1195 msleep(20);
1196
1197 /* big hammer */
1198 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1199 /* don't reset CAM block on reset */
1200 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1201 else
1202 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1203 qla82xx_rom_unlock(ha);
1204
1205 /* Read the signature value from the flash.
1206 * Offset 0: Contain signature (0xcafecafe)
1207 * Offset 4: Offset and number of addr/value pairs
1208 * that present in CRB initialize sequence
1209 */
1210 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1211 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1212 ql_log(ql_log_fatal, vha, 0x006e,
1213 "Error Reading crb_init area: n: %08x.\n", n);
1214 return -1;
1215 }
1216
1217 /* Offset in flash = lower 16 bits
1218 * Number of entries = upper 16 bits
1219 */
1220 offset = n & 0xffffU;
1221 n = (n >> 16) & 0xffffU;
1222
1223 /* number of addr/value pair should not exceed 1024 entries */
1224 if (n >= 1024) {
1225 ql_log(ql_log_fatal, vha, 0x0071,
1226 "Card flash not initialized:n=0x%x.\n", n);
1227 return -1;
1228 }
1229
1230 ql_log(ql_log_info, vha, 0x0072,
1231 "%d CRB init values found in ROM.\n", n);
1232
1233 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1234 if (buf == NULL) {
1235 ql_log(ql_log_fatal, vha, 0x010c,
1236 "Unable to allocate memory.\n");
1237 return -ENOMEM;
1238 }
1239
1240 for (i = 0; i < n; i++) {
1241 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1242 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1243 kfree(buf);
1244 return -1;
1245 }
1246
1247 buf[i].addr = addr;
1248 buf[i].data = val;
1249 }
1250
1251 for (i = 0; i < n; i++) {
1252 /* Translate internal CRB initialization
1253 * address to PCI bus address
1254 */
1255 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1256 QLA82XX_PCI_CRBSPACE;
1257 /* Not all CRB addr/value pair to be written,
1258 * some of them are skipped
1259 */
1260
1261 /* skipping cold reboot MAGIC */
1262 if (off == QLA82XX_CAM_RAM(0x1fc))
1263 continue;
1264
1265 /* do not reset PCI */
1266 if (off == (ROMUSB_GLB + 0xbc))
1267 continue;
1268
1269 /* skip core clock, so that firmware can increase the clock */
1270 if (off == (ROMUSB_GLB + 0xc8))
1271 continue;
1272
1273 /* skip the function enable register */
1274 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1275 continue;
1276
1277 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1278 continue;
1279
1280 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1281 continue;
1282
1283 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1284 continue;
1285
1286 if (off == ADDR_ERROR) {
1287 ql_log(ql_log_fatal, vha, 0x0116,
1288 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1289 continue;
1290 }
1291
1292 qla82xx_wr_32(ha, off, buf[i].data);
1293
1294 /* ISP requires much bigger delay to settle down,
1295 * else crb_window returns 0xffffffff
1296 */
1297 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1298 msleep(1000);
1299
1300 /* ISP requires millisec delay between
1301 * successive CRB register updation
1302 */
1303 msleep(1);
1304 }
1305
1306 kfree(buf);
1307
1308 /* Resetting the data and instruction cache */
1309 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1310 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1311 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1312
1313 /* Clear all protocol processing engines */
1314 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1315 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1316 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1317 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1318 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1319 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1320 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1321 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1322 return 0;
1323 }
1324
1325 static int
qla82xx_pci_mem_write_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1326 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1327 u64 off, void *data, int size)
1328 {
1329 int i, j, ret = 0, loop, sz[2], off0;
1330 int scale, shift_amount, startword;
1331 uint32_t temp;
1332 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1333
1334 /*
1335 * If not MN, go check for MS or invalid.
1336 */
1337 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1338 mem_crb = QLA82XX_CRB_QDR_NET;
1339 else {
1340 mem_crb = QLA82XX_CRB_DDR_NET;
1341 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1342 return qla82xx_pci_mem_write_direct(ha,
1343 off, data, size);
1344 }
1345
1346 off0 = off & 0x7;
1347 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1348 sz[1] = size - sz[0];
1349
1350 off8 = off & 0xfffffff0;
1351 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1352 shift_amount = 4;
1353 scale = 2;
1354 startword = (off & 0xf)/8;
1355
1356 for (i = 0; i < loop; i++) {
1357 if (qla82xx_pci_mem_read_2M(ha, off8 +
1358 (i << shift_amount), &word[i * scale], 8))
1359 return -1;
1360 }
1361
1362 switch (size) {
1363 case 1:
1364 tmpw = *((uint8_t *)data);
1365 break;
1366 case 2:
1367 tmpw = *((uint16_t *)data);
1368 break;
1369 case 4:
1370 tmpw = *((uint32_t *)data);
1371 break;
1372 case 8:
1373 default:
1374 tmpw = *((uint64_t *)data);
1375 break;
1376 }
1377
1378 if (sz[0] == 8) {
1379 word[startword] = tmpw;
1380 } else {
1381 word[startword] &=
1382 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1383 word[startword] |= tmpw << (off0 * 8);
1384 }
1385 if (sz[1] != 0) {
1386 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1387 word[startword+1] |= tmpw >> (sz[0] * 8);
1388 }
1389
1390 for (i = 0; i < loop; i++) {
1391 temp = off8 + (i << shift_amount);
1392 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1393 temp = 0;
1394 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1395 temp = word[i * scale] & 0xffffffff;
1396 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1397 temp = (word[i * scale] >> 32) & 0xffffffff;
1398 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1399 temp = word[i*scale + 1] & 0xffffffff;
1400 qla82xx_wr_32(ha, mem_crb +
1401 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1402 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1403 qla82xx_wr_32(ha, mem_crb +
1404 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1405
1406 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1407 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1408 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1409 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1410
1411 for (j = 0; j < MAX_CTL_CHECK; j++) {
1412 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1413 if ((temp & MIU_TA_CTL_BUSY) == 0)
1414 break;
1415 }
1416
1417 if (j >= MAX_CTL_CHECK) {
1418 if (printk_ratelimit())
1419 dev_err(&ha->pdev->dev,
1420 "failed to write through agent.\n");
1421 ret = -1;
1422 break;
1423 }
1424 }
1425
1426 return ret;
1427 }
1428
1429 static int
qla82xx_fw_load_from_flash(struct qla_hw_data * ha)1430 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1431 {
1432 int i;
1433 long size = 0;
1434 long flashaddr = ha->flt_region_bootload << 2;
1435 long memaddr = BOOTLD_START;
1436 u64 data;
1437 u32 high, low;
1438 size = (IMAGE_START - BOOTLD_START) / 8;
1439
1440 for (i = 0; i < size; i++) {
1441 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1442 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1443 return -1;
1444 }
1445 data = ((u64)high << 32) | low ;
1446 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1447 flashaddr += 8;
1448 memaddr += 8;
1449
1450 if (i % 0x1000 == 0)
1451 msleep(1);
1452 }
1453 udelay(100);
1454 read_lock(&ha->hw_lock);
1455 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1456 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1457 read_unlock(&ha->hw_lock);
1458 return 0;
1459 }
1460
1461 int
qla82xx_pci_mem_read_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1462 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1463 u64 off, void *data, int size)
1464 {
1465 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1466 int shift_amount;
1467 uint32_t temp;
1468 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1469
1470 /*
1471 * If not MN, go check for MS or invalid.
1472 */
1473
1474 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1475 mem_crb = QLA82XX_CRB_QDR_NET;
1476 else {
1477 mem_crb = QLA82XX_CRB_DDR_NET;
1478 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1479 return qla82xx_pci_mem_read_direct(ha,
1480 off, data, size);
1481 }
1482
1483 off8 = off & 0xfffffff0;
1484 off0[0] = off & 0xf;
1485 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1486 shift_amount = 4;
1487 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1488 off0[1] = 0;
1489 sz[1] = size - sz[0];
1490
1491 for (i = 0; i < loop; i++) {
1492 temp = off8 + (i << shift_amount);
1493 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1494 temp = 0;
1495 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1496 temp = MIU_TA_CTL_ENABLE;
1497 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1498 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1499 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1500
1501 for (j = 0; j < MAX_CTL_CHECK; j++) {
1502 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1503 if ((temp & MIU_TA_CTL_BUSY) == 0)
1504 break;
1505 }
1506
1507 if (j >= MAX_CTL_CHECK) {
1508 if (printk_ratelimit())
1509 dev_err(&ha->pdev->dev,
1510 "failed to read through agent.\n");
1511 break;
1512 }
1513
1514 start = off0[i] >> 2;
1515 end = (off0[i] + sz[i] - 1) >> 2;
1516 for (k = start; k <= end; k++) {
1517 temp = qla82xx_rd_32(ha,
1518 mem_crb + MIU_TEST_AGT_RDDATA(k));
1519 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1520 }
1521 }
1522
1523 if (j >= MAX_CTL_CHECK)
1524 return -1;
1525
1526 if ((off0[0] & 7) == 0) {
1527 val = word[0];
1528 } else {
1529 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1530 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1531 }
1532
1533 switch (size) {
1534 case 1:
1535 *(uint8_t *)data = val;
1536 break;
1537 case 2:
1538 *(uint16_t *)data = val;
1539 break;
1540 case 4:
1541 *(uint32_t *)data = val;
1542 break;
1543 case 8:
1544 *(uint64_t *)data = val;
1545 break;
1546 }
1547 return 0;
1548 }
1549
1550
1551 static struct qla82xx_uri_table_desc *
qla82xx_get_table_desc(const u8 * unirom,int section)1552 qla82xx_get_table_desc(const u8 *unirom, int section)
1553 {
1554 uint32_t i;
1555 struct qla82xx_uri_table_desc *directory =
1556 (struct qla82xx_uri_table_desc *)&unirom[0];
1557 __le32 offset;
1558 __le32 tab_type;
1559 __le32 entries = cpu_to_le32(directory->num_entries);
1560
1561 for (i = 0; i < entries; i++) {
1562 offset = cpu_to_le32(directory->findex) +
1563 (i * cpu_to_le32(directory->entry_size));
1564 tab_type = cpu_to_le32(*((u32 *)&unirom[offset] + 8));
1565
1566 if (tab_type == section)
1567 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1568 }
1569
1570 return NULL;
1571 }
1572
1573 static struct qla82xx_uri_data_desc *
qla82xx_get_data_desc(struct qla_hw_data * ha,u32 section,u32 idx_offset)1574 qla82xx_get_data_desc(struct qla_hw_data *ha,
1575 u32 section, u32 idx_offset)
1576 {
1577 const u8 *unirom = ha->hablob->fw->data;
1578 int idx = cpu_to_le32(*((int *)&unirom[ha->file_prd_off] + idx_offset));
1579 struct qla82xx_uri_table_desc *tab_desc = NULL;
1580 __le32 offset;
1581
1582 tab_desc = qla82xx_get_table_desc(unirom, section);
1583 if (!tab_desc)
1584 return NULL;
1585
1586 offset = cpu_to_le32(tab_desc->findex) +
1587 (cpu_to_le32(tab_desc->entry_size) * idx);
1588
1589 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1590 }
1591
1592 static u8 *
qla82xx_get_bootld_offset(struct qla_hw_data * ha)1593 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1594 {
1595 u32 offset = BOOTLD_START;
1596 struct qla82xx_uri_data_desc *uri_desc = NULL;
1597
1598 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1599 uri_desc = qla82xx_get_data_desc(ha,
1600 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1601 if (uri_desc)
1602 offset = cpu_to_le32(uri_desc->findex);
1603 }
1604
1605 return (u8 *)&ha->hablob->fw->data[offset];
1606 }
1607
qla82xx_get_fw_size(struct qla_hw_data * ha)1608 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1609 {
1610 struct qla82xx_uri_data_desc *uri_desc = NULL;
1611
1612 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1613 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1614 QLA82XX_URI_FIRMWARE_IDX_OFF);
1615 if (uri_desc)
1616 return cpu_to_le32(uri_desc->size);
1617 }
1618
1619 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1620 }
1621
1622 static u8 *
qla82xx_get_fw_offs(struct qla_hw_data * ha)1623 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1624 {
1625 u32 offset = IMAGE_START;
1626 struct qla82xx_uri_data_desc *uri_desc = NULL;
1627
1628 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1629 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1630 QLA82XX_URI_FIRMWARE_IDX_OFF);
1631 if (uri_desc)
1632 offset = cpu_to_le32(uri_desc->findex);
1633 }
1634
1635 return (u8 *)&ha->hablob->fw->data[offset];
1636 }
1637
1638 /* PCI related functions */
qla82xx_pci_region_offset(struct pci_dev * pdev,int region)1639 int qla82xx_pci_region_offset(struct pci_dev *pdev, int region)
1640 {
1641 unsigned long val = 0;
1642 u32 control;
1643
1644 switch (region) {
1645 case 0:
1646 val = 0;
1647 break;
1648 case 1:
1649 pci_read_config_dword(pdev, QLA82XX_PCI_REG_MSIX_TBL, &control);
1650 val = control + QLA82XX_MSIX_TBL_SPACE;
1651 break;
1652 }
1653 return val;
1654 }
1655
1656
1657 int
qla82xx_iospace_config(struct qla_hw_data * ha)1658 qla82xx_iospace_config(struct qla_hw_data *ha)
1659 {
1660 uint32_t len = 0;
1661
1662 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1663 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1664 "Failed to reserver selected regions.\n");
1665 goto iospace_error_exit;
1666 }
1667
1668 /* Use MMIO operations for all accesses. */
1669 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1670 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1671 "Region #0 not an MMIO resource, aborting.\n");
1672 goto iospace_error_exit;
1673 }
1674
1675 len = pci_resource_len(ha->pdev, 0);
1676 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1677 if (!ha->nx_pcibase) {
1678 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1679 "Cannot remap pcibase MMIO, aborting.\n");
1680 goto iospace_error_exit;
1681 }
1682
1683 /* Mapping of IO base pointer */
1684 if (IS_QLA8044(ha)) {
1685 ha->iobase = ha->nx_pcibase;
1686 } else if (IS_QLA82XX(ha)) {
1687 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1688 }
1689
1690 if (!ql2xdbwr) {
1691 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1692 (ha->pdev->devfn << 12)), 4);
1693 if (!ha->nxdb_wr_ptr) {
1694 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1695 "Cannot remap MMIO, aborting.\n");
1696 goto iospace_error_exit;
1697 }
1698
1699 /* Mapping of IO base pointer,
1700 * door bell read and write pointer
1701 */
1702 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1703 (ha->pdev->devfn * 8);
1704 } else {
1705 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1706 QLA82XX_CAMRAM_DB1 :
1707 QLA82XX_CAMRAM_DB2);
1708 }
1709
1710 ha->max_req_queues = ha->max_rsp_queues = 1;
1711 ha->msix_count = ha->max_rsp_queues + 1;
1712 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1713 "nx_pci_base=%p iobase=%p "
1714 "max_req_queues=%d msix_count=%d.\n",
1715 ha->nx_pcibase, ha->iobase,
1716 ha->max_req_queues, ha->msix_count);
1717 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1718 "nx_pci_base=%p iobase=%p "
1719 "max_req_queues=%d msix_count=%d.\n",
1720 ha->nx_pcibase, ha->iobase,
1721 ha->max_req_queues, ha->msix_count);
1722 return 0;
1723
1724 iospace_error_exit:
1725 return -ENOMEM;
1726 }
1727
1728 /* GS related functions */
1729
1730 /* Initialization related functions */
1731
1732 /**
1733 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1734 * @vha: HA context
1735 *
1736 * Returns 0 on success.
1737 */
1738 int
qla82xx_pci_config(scsi_qla_host_t * vha)1739 qla82xx_pci_config(scsi_qla_host_t *vha)
1740 {
1741 struct qla_hw_data *ha = vha->hw;
1742 int ret;
1743
1744 pci_set_master(ha->pdev);
1745 ret = pci_set_mwi(ha->pdev);
1746 ha->chip_revision = ha->pdev->revision;
1747 ql_dbg(ql_dbg_init, vha, 0x0043,
1748 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1749 ha->chip_revision, ret);
1750 return 0;
1751 }
1752
1753 /**
1754 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1755 * @vha: HA context
1756 *
1757 * Returns 0 on success.
1758 */
1759 void
qla82xx_reset_chip(scsi_qla_host_t * vha)1760 qla82xx_reset_chip(scsi_qla_host_t *vha)
1761 {
1762 struct qla_hw_data *ha = vha->hw;
1763 ha->isp_ops->disable_intrs(ha);
1764 }
1765
qla82xx_config_rings(struct scsi_qla_host * vha)1766 void qla82xx_config_rings(struct scsi_qla_host *vha)
1767 {
1768 struct qla_hw_data *ha = vha->hw;
1769 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1770 struct init_cb_81xx *icb;
1771 struct req_que *req = ha->req_q_map[0];
1772 struct rsp_que *rsp = ha->rsp_q_map[0];
1773
1774 /* Setup ring parameters in initialization control block. */
1775 icb = (struct init_cb_81xx *)ha->init_cb;
1776 icb->request_q_outpointer = cpu_to_le16(0);
1777 icb->response_q_inpointer = cpu_to_le16(0);
1778 icb->request_q_length = cpu_to_le16(req->length);
1779 icb->response_q_length = cpu_to_le16(rsp->length);
1780 icb->request_q_address[0] = cpu_to_le32(LSD(req->dma));
1781 icb->request_q_address[1] = cpu_to_le32(MSD(req->dma));
1782 icb->response_q_address[0] = cpu_to_le32(LSD(rsp->dma));
1783 icb->response_q_address[1] = cpu_to_le32(MSD(rsp->dma));
1784
1785 WRT_REG_DWORD(®->req_q_out[0], 0);
1786 WRT_REG_DWORD(®->rsp_q_in[0], 0);
1787 WRT_REG_DWORD(®->rsp_q_out[0], 0);
1788 }
1789
1790 static int
qla82xx_fw_load_from_blob(struct qla_hw_data * ha)1791 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1792 {
1793 u64 *ptr64;
1794 u32 i, flashaddr, size;
1795 __le64 data;
1796
1797 size = (IMAGE_START - BOOTLD_START) / 8;
1798
1799 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1800 flashaddr = BOOTLD_START;
1801
1802 for (i = 0; i < size; i++) {
1803 data = cpu_to_le64(ptr64[i]);
1804 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1805 return -EIO;
1806 flashaddr += 8;
1807 }
1808
1809 flashaddr = FLASH_ADDR_START;
1810 size = qla82xx_get_fw_size(ha) / 8;
1811 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1812
1813 for (i = 0; i < size; i++) {
1814 data = cpu_to_le64(ptr64[i]);
1815
1816 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1817 return -EIO;
1818 flashaddr += 8;
1819 }
1820 udelay(100);
1821
1822 /* Write a magic value to CAMRAM register
1823 * at a specified offset to indicate
1824 * that all data is written and
1825 * ready for firmware to initialize.
1826 */
1827 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1828
1829 read_lock(&ha->hw_lock);
1830 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1831 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1832 read_unlock(&ha->hw_lock);
1833 return 0;
1834 }
1835
1836 static int
qla82xx_set_product_offset(struct qla_hw_data * ha)1837 qla82xx_set_product_offset(struct qla_hw_data *ha)
1838 {
1839 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1840 const uint8_t *unirom = ha->hablob->fw->data;
1841 uint32_t i;
1842 __le32 entries;
1843 __le32 flags, file_chiprev, offset;
1844 uint8_t chiprev = ha->chip_revision;
1845 /* Hardcoding mn_present flag for P3P */
1846 int mn_present = 0;
1847 uint32_t flagbit;
1848
1849 ptab_desc = qla82xx_get_table_desc(unirom,
1850 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1851 if (!ptab_desc)
1852 return -1;
1853
1854 entries = cpu_to_le32(ptab_desc->num_entries);
1855
1856 for (i = 0; i < entries; i++) {
1857 offset = cpu_to_le32(ptab_desc->findex) +
1858 (i * cpu_to_le32(ptab_desc->entry_size));
1859 flags = cpu_to_le32(*((int *)&unirom[offset] +
1860 QLA82XX_URI_FLAGS_OFF));
1861 file_chiprev = cpu_to_le32(*((int *)&unirom[offset] +
1862 QLA82XX_URI_CHIP_REV_OFF));
1863
1864 flagbit = mn_present ? 1 : 2;
1865
1866 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1867 ha->file_prd_off = offset;
1868 return 0;
1869 }
1870 }
1871 return -1;
1872 }
1873
1874 static int
qla82xx_validate_firmware_blob(scsi_qla_host_t * vha,uint8_t fw_type)1875 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1876 {
1877 __le32 val;
1878 uint32_t min_size;
1879 struct qla_hw_data *ha = vha->hw;
1880 const struct firmware *fw = ha->hablob->fw;
1881
1882 ha->fw_type = fw_type;
1883
1884 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1885 if (qla82xx_set_product_offset(ha))
1886 return -EINVAL;
1887
1888 min_size = QLA82XX_URI_FW_MIN_SIZE;
1889 } else {
1890 val = cpu_to_le32(*(u32 *)&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1891 if ((__force u32)val != QLA82XX_BDINFO_MAGIC)
1892 return -EINVAL;
1893
1894 min_size = QLA82XX_FW_MIN_SIZE;
1895 }
1896
1897 if (fw->size < min_size)
1898 return -EINVAL;
1899 return 0;
1900 }
1901
1902 static int
qla82xx_check_cmdpeg_state(struct qla_hw_data * ha)1903 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1904 {
1905 u32 val = 0;
1906 int retries = 60;
1907 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1908
1909 do {
1910 read_lock(&ha->hw_lock);
1911 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1912 read_unlock(&ha->hw_lock);
1913
1914 switch (val) {
1915 case PHAN_INITIALIZE_COMPLETE:
1916 case PHAN_INITIALIZE_ACK:
1917 return QLA_SUCCESS;
1918 case PHAN_INITIALIZE_FAILED:
1919 break;
1920 default:
1921 break;
1922 }
1923 ql_log(ql_log_info, vha, 0x00a8,
1924 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1925 val, retries);
1926
1927 msleep(500);
1928
1929 } while (--retries);
1930
1931 ql_log(ql_log_fatal, vha, 0x00a9,
1932 "Cmd Peg initialization failed: 0x%x.\n", val);
1933
1934 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1935 read_lock(&ha->hw_lock);
1936 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1937 read_unlock(&ha->hw_lock);
1938 return QLA_FUNCTION_FAILED;
1939 }
1940
1941 static int
qla82xx_check_rcvpeg_state(struct qla_hw_data * ha)1942 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1943 {
1944 u32 val = 0;
1945 int retries = 60;
1946 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1947
1948 do {
1949 read_lock(&ha->hw_lock);
1950 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1951 read_unlock(&ha->hw_lock);
1952
1953 switch (val) {
1954 case PHAN_INITIALIZE_COMPLETE:
1955 case PHAN_INITIALIZE_ACK:
1956 return QLA_SUCCESS;
1957 case PHAN_INITIALIZE_FAILED:
1958 break;
1959 default:
1960 break;
1961 }
1962 ql_log(ql_log_info, vha, 0x00ab,
1963 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1964 val, retries);
1965
1966 msleep(500);
1967
1968 } while (--retries);
1969
1970 ql_log(ql_log_fatal, vha, 0x00ac,
1971 "Rcv Peg initializatin failed: 0x%x.\n", val);
1972 read_lock(&ha->hw_lock);
1973 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1974 read_unlock(&ha->hw_lock);
1975 return QLA_FUNCTION_FAILED;
1976 }
1977
1978 /* ISR related functions */
1979 static struct qla82xx_legacy_intr_set legacy_intr[] = \
1980 QLA82XX_LEGACY_INTR_CONFIG;
1981
1982 /*
1983 * qla82xx_mbx_completion() - Process mailbox command completions.
1984 * @ha: SCSI driver HA context
1985 * @mb0: Mailbox0 register
1986 */
1987 void
qla82xx_mbx_completion(scsi_qla_host_t * vha,uint16_t mb0)1988 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1989 {
1990 uint16_t cnt;
1991 uint16_t __iomem *wptr;
1992 struct qla_hw_data *ha = vha->hw;
1993 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1994 wptr = (uint16_t __iomem *)®->mailbox_out[1];
1995
1996 /* Load return mailbox registers. */
1997 ha->flags.mbox_int = 1;
1998 ha->mailbox_out[0] = mb0;
1999
2000 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
2001 ha->mailbox_out[cnt] = RD_REG_WORD(wptr);
2002 wptr++;
2003 }
2004
2005 if (!ha->mcp)
2006 ql_dbg(ql_dbg_async, vha, 0x5053,
2007 "MBX pointer ERROR.\n");
2008 }
2009
2010 /**
2011 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
2012 * @irq:
2013 * @dev_id: SCSI driver HA context
2014 *
2015 * Called by system whenever the host adapter generates an interrupt.
2016 *
2017 * Returns handled flag.
2018 */
2019 irqreturn_t
qla82xx_intr_handler(int irq,void * dev_id)2020 qla82xx_intr_handler(int irq, void *dev_id)
2021 {
2022 scsi_qla_host_t *vha;
2023 struct qla_hw_data *ha;
2024 struct rsp_que *rsp;
2025 struct device_reg_82xx __iomem *reg;
2026 int status = 0, status1 = 0;
2027 unsigned long flags;
2028 unsigned long iter;
2029 uint32_t stat = 0;
2030 uint16_t mb[4];
2031
2032 rsp = (struct rsp_que *) dev_id;
2033 if (!rsp) {
2034 ql_log(ql_log_info, NULL, 0xb053,
2035 "%s: NULL response queue pointer.\n", __func__);
2036 return IRQ_NONE;
2037 }
2038 ha = rsp->hw;
2039
2040 if (!ha->flags.msi_enabled) {
2041 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
2042 if (!(status & ha->nx_legacy_intr.int_vec_bit))
2043 return IRQ_NONE;
2044
2045 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
2046 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
2047 return IRQ_NONE;
2048 }
2049
2050 /* clear the interrupt */
2051 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
2052
2053 /* read twice to ensure write is flushed */
2054 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2055 qla82xx_rd_32(ha, ISR_INT_VECTOR);
2056
2057 reg = &ha->iobase->isp82;
2058
2059 spin_lock_irqsave(&ha->hardware_lock, flags);
2060 vha = pci_get_drvdata(ha->pdev);
2061 for (iter = 1; iter--; ) {
2062
2063 if (RD_REG_DWORD(®->host_int)) {
2064 stat = RD_REG_DWORD(®->host_status);
2065
2066 switch (stat & 0xff) {
2067 case 0x1:
2068 case 0x2:
2069 case 0x10:
2070 case 0x11:
2071 qla82xx_mbx_completion(vha, MSW(stat));
2072 status |= MBX_INTERRUPT;
2073 break;
2074 case 0x12:
2075 mb[0] = MSW(stat);
2076 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2077 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2078 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2079 qla2x00_async_event(vha, rsp, mb);
2080 break;
2081 case 0x13:
2082 qla24xx_process_response_queue(vha, rsp);
2083 break;
2084 default:
2085 ql_dbg(ql_dbg_async, vha, 0x5054,
2086 "Unrecognized interrupt type (%d).\n",
2087 stat & 0xff);
2088 break;
2089 }
2090 }
2091 WRT_REG_DWORD(®->host_int, 0);
2092 }
2093
2094 qla2x00_handle_mbx_completion(ha, status);
2095 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2096
2097 if (!ha->flags.msi_enabled)
2098 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2099
2100 return IRQ_HANDLED;
2101 }
2102
2103 irqreturn_t
qla82xx_msix_default(int irq,void * dev_id)2104 qla82xx_msix_default(int irq, void *dev_id)
2105 {
2106 scsi_qla_host_t *vha;
2107 struct qla_hw_data *ha;
2108 struct rsp_que *rsp;
2109 struct device_reg_82xx __iomem *reg;
2110 int status = 0;
2111 unsigned long flags;
2112 uint32_t stat = 0;
2113 uint32_t host_int = 0;
2114 uint16_t mb[4];
2115
2116 rsp = (struct rsp_que *) dev_id;
2117 if (!rsp) {
2118 printk(KERN_INFO
2119 "%s(): NULL response queue pointer.\n", __func__);
2120 return IRQ_NONE;
2121 }
2122 ha = rsp->hw;
2123
2124 reg = &ha->iobase->isp82;
2125
2126 spin_lock_irqsave(&ha->hardware_lock, flags);
2127 vha = pci_get_drvdata(ha->pdev);
2128 do {
2129 host_int = RD_REG_DWORD(®->host_int);
2130 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2131 break;
2132 if (host_int) {
2133 stat = RD_REG_DWORD(®->host_status);
2134
2135 switch (stat & 0xff) {
2136 case 0x1:
2137 case 0x2:
2138 case 0x10:
2139 case 0x11:
2140 qla82xx_mbx_completion(vha, MSW(stat));
2141 status |= MBX_INTERRUPT;
2142 break;
2143 case 0x12:
2144 mb[0] = MSW(stat);
2145 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2146 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2147 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2148 qla2x00_async_event(vha, rsp, mb);
2149 break;
2150 case 0x13:
2151 qla24xx_process_response_queue(vha, rsp);
2152 break;
2153 default:
2154 ql_dbg(ql_dbg_async, vha, 0x5041,
2155 "Unrecognized interrupt type (%d).\n",
2156 stat & 0xff);
2157 break;
2158 }
2159 }
2160 WRT_REG_DWORD(®->host_int, 0);
2161 } while (0);
2162
2163 qla2x00_handle_mbx_completion(ha, status);
2164 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2165
2166 return IRQ_HANDLED;
2167 }
2168
2169 irqreturn_t
qla82xx_msix_rsp_q(int irq,void * dev_id)2170 qla82xx_msix_rsp_q(int irq, void *dev_id)
2171 {
2172 scsi_qla_host_t *vha;
2173 struct qla_hw_data *ha;
2174 struct rsp_que *rsp;
2175 struct device_reg_82xx __iomem *reg;
2176 unsigned long flags;
2177 uint32_t host_int = 0;
2178
2179 rsp = (struct rsp_que *) dev_id;
2180 if (!rsp) {
2181 printk(KERN_INFO
2182 "%s(): NULL response queue pointer.\n", __func__);
2183 return IRQ_NONE;
2184 }
2185
2186 ha = rsp->hw;
2187 reg = &ha->iobase->isp82;
2188 spin_lock_irqsave(&ha->hardware_lock, flags);
2189 vha = pci_get_drvdata(ha->pdev);
2190 host_int = RD_REG_DWORD(®->host_int);
2191 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2192 goto out;
2193 qla24xx_process_response_queue(vha, rsp);
2194 WRT_REG_DWORD(®->host_int, 0);
2195 out:
2196 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2197 return IRQ_HANDLED;
2198 }
2199
2200 void
qla82xx_poll(int irq,void * dev_id)2201 qla82xx_poll(int irq, void *dev_id)
2202 {
2203 scsi_qla_host_t *vha;
2204 struct qla_hw_data *ha;
2205 struct rsp_que *rsp;
2206 struct device_reg_82xx __iomem *reg;
2207 int status = 0;
2208 uint32_t stat;
2209 uint32_t host_int = 0;
2210 uint16_t mb[4];
2211 unsigned long flags;
2212
2213 rsp = (struct rsp_que *) dev_id;
2214 if (!rsp) {
2215 printk(KERN_INFO
2216 "%s(): NULL response queue pointer.\n", __func__);
2217 return;
2218 }
2219 ha = rsp->hw;
2220
2221 reg = &ha->iobase->isp82;
2222 spin_lock_irqsave(&ha->hardware_lock, flags);
2223 vha = pci_get_drvdata(ha->pdev);
2224
2225 host_int = RD_REG_DWORD(®->host_int);
2226 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2227 goto out;
2228 if (host_int) {
2229 stat = RD_REG_DWORD(®->host_status);
2230 switch (stat & 0xff) {
2231 case 0x1:
2232 case 0x2:
2233 case 0x10:
2234 case 0x11:
2235 qla82xx_mbx_completion(vha, MSW(stat));
2236 status |= MBX_INTERRUPT;
2237 break;
2238 case 0x12:
2239 mb[0] = MSW(stat);
2240 mb[1] = RD_REG_WORD(®->mailbox_out[1]);
2241 mb[2] = RD_REG_WORD(®->mailbox_out[2]);
2242 mb[3] = RD_REG_WORD(®->mailbox_out[3]);
2243 qla2x00_async_event(vha, rsp, mb);
2244 break;
2245 case 0x13:
2246 qla24xx_process_response_queue(vha, rsp);
2247 break;
2248 default:
2249 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2250 "Unrecognized interrupt type (%d).\n",
2251 stat * 0xff);
2252 break;
2253 }
2254 WRT_REG_DWORD(®->host_int, 0);
2255 }
2256 out:
2257 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2258 }
2259
2260 void
qla82xx_enable_intrs(struct qla_hw_data * ha)2261 qla82xx_enable_intrs(struct qla_hw_data *ha)
2262 {
2263 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2264 qla82xx_mbx_intr_enable(vha);
2265 spin_lock_irq(&ha->hardware_lock);
2266 if (IS_QLA8044(ha))
2267 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2268 else
2269 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2270 spin_unlock_irq(&ha->hardware_lock);
2271 ha->interrupts_on = 1;
2272 }
2273
2274 void
qla82xx_disable_intrs(struct qla_hw_data * ha)2275 qla82xx_disable_intrs(struct qla_hw_data *ha)
2276 {
2277 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2278 qla82xx_mbx_intr_disable(vha);
2279 spin_lock_irq(&ha->hardware_lock);
2280 if (IS_QLA8044(ha))
2281 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2282 else
2283 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2284 spin_unlock_irq(&ha->hardware_lock);
2285 ha->interrupts_on = 0;
2286 }
2287
qla82xx_init_flags(struct qla_hw_data * ha)2288 void qla82xx_init_flags(struct qla_hw_data *ha)
2289 {
2290 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2291
2292 /* ISP 8021 initializations */
2293 rwlock_init(&ha->hw_lock);
2294 ha->qdr_sn_window = -1;
2295 ha->ddr_mn_window = -1;
2296 ha->curr_window = 255;
2297 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2298 nx_legacy_intr = &legacy_intr[ha->portnum];
2299 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2300 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2301 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2302 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2303 }
2304
2305 static inline void
qla82xx_set_idc_version(scsi_qla_host_t * vha)2306 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2307 {
2308 int idc_ver;
2309 uint32_t drv_active;
2310 struct qla_hw_data *ha = vha->hw;
2311
2312 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2313 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2314 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2315 QLA82XX_IDC_VERSION);
2316 ql_log(ql_log_info, vha, 0xb082,
2317 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2318 } else {
2319 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2320 if (idc_ver != QLA82XX_IDC_VERSION)
2321 ql_log(ql_log_info, vha, 0xb083,
2322 "qla2xxx driver IDC version %d is not compatible "
2323 "with IDC version %d of the other drivers\n",
2324 QLA82XX_IDC_VERSION, idc_ver);
2325 }
2326 }
2327
2328 inline void
qla82xx_set_drv_active(scsi_qla_host_t * vha)2329 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2330 {
2331 uint32_t drv_active;
2332 struct qla_hw_data *ha = vha->hw;
2333
2334 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2335
2336 /* If reset value is all FF's, initialize DRV_ACTIVE */
2337 if (drv_active == 0xffffffff) {
2338 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2339 QLA82XX_DRV_NOT_ACTIVE);
2340 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2341 }
2342 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2343 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2344 }
2345
2346 inline void
qla82xx_clear_drv_active(struct qla_hw_data * ha)2347 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2348 {
2349 uint32_t drv_active;
2350
2351 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2352 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2353 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2354 }
2355
2356 static inline int
qla82xx_need_reset(struct qla_hw_data * ha)2357 qla82xx_need_reset(struct qla_hw_data *ha)
2358 {
2359 uint32_t drv_state;
2360 int rval;
2361
2362 if (ha->flags.nic_core_reset_owner)
2363 return 1;
2364 else {
2365 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2366 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2367 return rval;
2368 }
2369 }
2370
2371 static inline void
qla82xx_set_rst_ready(struct qla_hw_data * ha)2372 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2373 {
2374 uint32_t drv_state;
2375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2376
2377 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2378
2379 /* If reset value is all FF's, initialize DRV_STATE */
2380 if (drv_state == 0xffffffff) {
2381 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2382 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2383 }
2384 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2385 ql_dbg(ql_dbg_init, vha, 0x00bb,
2386 "drv_state = 0x%08x.\n", drv_state);
2387 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2388 }
2389
2390 static inline void
qla82xx_clear_rst_ready(struct qla_hw_data * ha)2391 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2392 {
2393 uint32_t drv_state;
2394
2395 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2396 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2397 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2398 }
2399
2400 static inline void
qla82xx_set_qsnt_ready(struct qla_hw_data * ha)2401 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2402 {
2403 uint32_t qsnt_state;
2404
2405 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2406 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2407 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2408 }
2409
2410 void
qla82xx_clear_qsnt_ready(scsi_qla_host_t * vha)2411 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2412 {
2413 struct qla_hw_data *ha = vha->hw;
2414 uint32_t qsnt_state;
2415
2416 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2417 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2418 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2419 }
2420
2421 static int
qla82xx_load_fw(scsi_qla_host_t * vha)2422 qla82xx_load_fw(scsi_qla_host_t *vha)
2423 {
2424 int rst;
2425 struct fw_blob *blob;
2426 struct qla_hw_data *ha = vha->hw;
2427
2428 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2429 ql_log(ql_log_fatal, vha, 0x009f,
2430 "Error during CRB initialization.\n");
2431 return QLA_FUNCTION_FAILED;
2432 }
2433 udelay(500);
2434
2435 /* Bring QM and CAMRAM out of reset */
2436 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2437 rst &= ~((1 << 28) | (1 << 24));
2438 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2439
2440 /*
2441 * FW Load priority:
2442 * 1) Operational firmware residing in flash.
2443 * 2) Firmware via request-firmware interface (.bin file).
2444 */
2445 if (ql2xfwloadbin == 2)
2446 goto try_blob_fw;
2447
2448 ql_log(ql_log_info, vha, 0x00a0,
2449 "Attempting to load firmware from flash.\n");
2450
2451 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2452 ql_log(ql_log_info, vha, 0x00a1,
2453 "Firmware loaded successfully from flash.\n");
2454 return QLA_SUCCESS;
2455 } else {
2456 ql_log(ql_log_warn, vha, 0x0108,
2457 "Firmware load from flash failed.\n");
2458 }
2459
2460 try_blob_fw:
2461 ql_log(ql_log_info, vha, 0x00a2,
2462 "Attempting to load firmware from blob.\n");
2463
2464 /* Load firmware blob. */
2465 blob = ha->hablob = qla2x00_request_firmware(vha);
2466 if (!blob) {
2467 ql_log(ql_log_fatal, vha, 0x00a3,
2468 "Firmware image not present.\n");
2469 goto fw_load_failed;
2470 }
2471
2472 /* Validating firmware blob */
2473 if (qla82xx_validate_firmware_blob(vha,
2474 QLA82XX_FLASH_ROMIMAGE)) {
2475 /* Fallback to URI format */
2476 if (qla82xx_validate_firmware_blob(vha,
2477 QLA82XX_UNIFIED_ROMIMAGE)) {
2478 ql_log(ql_log_fatal, vha, 0x00a4,
2479 "No valid firmware image found.\n");
2480 return QLA_FUNCTION_FAILED;
2481 }
2482 }
2483
2484 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2485 ql_log(ql_log_info, vha, 0x00a5,
2486 "Firmware loaded successfully from binary blob.\n");
2487 return QLA_SUCCESS;
2488 }
2489
2490 ql_log(ql_log_fatal, vha, 0x00a6,
2491 "Firmware load failed for binary blob.\n");
2492 blob->fw = NULL;
2493 blob = NULL;
2494
2495 fw_load_failed:
2496 return QLA_FUNCTION_FAILED;
2497 }
2498
2499 int
qla82xx_start_firmware(scsi_qla_host_t * vha)2500 qla82xx_start_firmware(scsi_qla_host_t *vha)
2501 {
2502 uint16_t lnk;
2503 struct qla_hw_data *ha = vha->hw;
2504
2505 /* scrub dma mask expansion register */
2506 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2507
2508 /* Put both the PEG CMD and RCV PEG to default state
2509 * of 0 before resetting the hardware
2510 */
2511 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2512 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2513
2514 /* Overwrite stale initialization register values */
2515 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2516 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2517
2518 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2519 ql_log(ql_log_fatal, vha, 0x00a7,
2520 "Error trying to start fw.\n");
2521 return QLA_FUNCTION_FAILED;
2522 }
2523
2524 /* Handshake with the card before we register the devices. */
2525 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2526 ql_log(ql_log_fatal, vha, 0x00aa,
2527 "Error during card handshake.\n");
2528 return QLA_FUNCTION_FAILED;
2529 }
2530
2531 /* Negotiated Link width */
2532 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2533 ha->link_width = (lnk >> 4) & 0x3f;
2534
2535 /* Synchronize with Receive peg */
2536 return qla82xx_check_rcvpeg_state(ha);
2537 }
2538
2539 static uint32_t *
qla82xx_read_flash_data(scsi_qla_host_t * vha,uint32_t * dwptr,uint32_t faddr,uint32_t length)2540 qla82xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr,
2541 uint32_t length)
2542 {
2543 uint32_t i;
2544 uint32_t val;
2545 struct qla_hw_data *ha = vha->hw;
2546
2547 /* Dword reads to flash. */
2548 for (i = 0; i < length/4; i++, faddr += 4) {
2549 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2550 ql_log(ql_log_warn, vha, 0x0106,
2551 "Do ROM fast read failed.\n");
2552 goto done_read;
2553 }
2554 dwptr[i] = cpu_to_le32(val);
2555 }
2556 done_read:
2557 return dwptr;
2558 }
2559
2560 static int
qla82xx_unprotect_flash(struct qla_hw_data * ha)2561 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2562 {
2563 int ret;
2564 uint32_t val;
2565 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2566
2567 ret = ql82xx_rom_lock_d(ha);
2568 if (ret < 0) {
2569 ql_log(ql_log_warn, vha, 0xb014,
2570 "ROM Lock failed.\n");
2571 return ret;
2572 }
2573
2574 ret = qla82xx_read_status_reg(ha, &val);
2575 if (ret < 0)
2576 goto done_unprotect;
2577
2578 val &= ~(BLOCK_PROTECT_BITS << 2);
2579 ret = qla82xx_write_status_reg(ha, val);
2580 if (ret < 0) {
2581 val |= (BLOCK_PROTECT_BITS << 2);
2582 qla82xx_write_status_reg(ha, val);
2583 }
2584
2585 if (qla82xx_write_disable_flash(ha) != 0)
2586 ql_log(ql_log_warn, vha, 0xb015,
2587 "Write disable failed.\n");
2588
2589 done_unprotect:
2590 qla82xx_rom_unlock(ha);
2591 return ret;
2592 }
2593
2594 static int
qla82xx_protect_flash(struct qla_hw_data * ha)2595 qla82xx_protect_flash(struct qla_hw_data *ha)
2596 {
2597 int ret;
2598 uint32_t val;
2599 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2600
2601 ret = ql82xx_rom_lock_d(ha);
2602 if (ret < 0) {
2603 ql_log(ql_log_warn, vha, 0xb016,
2604 "ROM Lock failed.\n");
2605 return ret;
2606 }
2607
2608 ret = qla82xx_read_status_reg(ha, &val);
2609 if (ret < 0)
2610 goto done_protect;
2611
2612 val |= (BLOCK_PROTECT_BITS << 2);
2613 /* LOCK all sectors */
2614 ret = qla82xx_write_status_reg(ha, val);
2615 if (ret < 0)
2616 ql_log(ql_log_warn, vha, 0xb017,
2617 "Write status register failed.\n");
2618
2619 if (qla82xx_write_disable_flash(ha) != 0)
2620 ql_log(ql_log_warn, vha, 0xb018,
2621 "Write disable failed.\n");
2622 done_protect:
2623 qla82xx_rom_unlock(ha);
2624 return ret;
2625 }
2626
2627 static int
qla82xx_erase_sector(struct qla_hw_data * ha,int addr)2628 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2629 {
2630 int ret = 0;
2631 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2632
2633 ret = ql82xx_rom_lock_d(ha);
2634 if (ret < 0) {
2635 ql_log(ql_log_warn, vha, 0xb019,
2636 "ROM Lock failed.\n");
2637 return ret;
2638 }
2639
2640 qla82xx_flash_set_write_enable(ha);
2641 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2642 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2643 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2644
2645 if (qla82xx_wait_rom_done(ha)) {
2646 ql_log(ql_log_warn, vha, 0xb01a,
2647 "Error waiting for rom done.\n");
2648 ret = -1;
2649 goto done;
2650 }
2651 ret = qla82xx_flash_wait_write_finish(ha);
2652 done:
2653 qla82xx_rom_unlock(ha);
2654 return ret;
2655 }
2656
2657 /*
2658 * Address and length are byte address
2659 */
2660 uint8_t *
qla82xx_read_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)2661 qla82xx_read_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2662 uint32_t offset, uint32_t length)
2663 {
2664 scsi_block_requests(vha->host);
2665 qla82xx_read_flash_data(vha, (uint32_t *)buf, offset, length);
2666 scsi_unblock_requests(vha->host);
2667 return buf;
2668 }
2669
2670 static int
qla82xx_write_flash_data(struct scsi_qla_host * vha,uint32_t * dwptr,uint32_t faddr,uint32_t dwords)2671 qla82xx_write_flash_data(struct scsi_qla_host *vha, uint32_t *dwptr,
2672 uint32_t faddr, uint32_t dwords)
2673 {
2674 int ret;
2675 uint32_t liter;
2676 uint32_t rest_addr;
2677 dma_addr_t optrom_dma;
2678 void *optrom = NULL;
2679 int page_mode = 0;
2680 struct qla_hw_data *ha = vha->hw;
2681
2682 ret = -1;
2683
2684 /* Prepare burst-capable write on supported ISPs. */
2685 if (page_mode && !(faddr & 0xfff) &&
2686 dwords > OPTROM_BURST_DWORDS) {
2687 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2688 &optrom_dma, GFP_KERNEL);
2689 if (!optrom) {
2690 ql_log(ql_log_warn, vha, 0xb01b,
2691 "Unable to allocate memory "
2692 "for optrom burst write (%x KB).\n",
2693 OPTROM_BURST_SIZE / 1024);
2694 }
2695 }
2696
2697 rest_addr = ha->fdt_block_size - 1;
2698
2699 ret = qla82xx_unprotect_flash(ha);
2700 if (ret) {
2701 ql_log(ql_log_warn, vha, 0xb01c,
2702 "Unable to unprotect flash for update.\n");
2703 goto write_done;
2704 }
2705
2706 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2707 /* Are we at the beginning of a sector? */
2708 if ((faddr & rest_addr) == 0) {
2709
2710 ret = qla82xx_erase_sector(ha, faddr);
2711 if (ret) {
2712 ql_log(ql_log_warn, vha, 0xb01d,
2713 "Unable to erase sector: address=%x.\n",
2714 faddr);
2715 break;
2716 }
2717 }
2718
2719 /* Go with burst-write. */
2720 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2721 /* Copy data to DMA'ble buffer. */
2722 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2723
2724 ret = qla2x00_load_ram(vha, optrom_dma,
2725 (ha->flash_data_off | faddr),
2726 OPTROM_BURST_DWORDS);
2727 if (ret != QLA_SUCCESS) {
2728 ql_log(ql_log_warn, vha, 0xb01e,
2729 "Unable to burst-write optrom segment "
2730 "(%x/%x/%llx).\n", ret,
2731 (ha->flash_data_off | faddr),
2732 (unsigned long long)optrom_dma);
2733 ql_log(ql_log_warn, vha, 0xb01f,
2734 "Reverting to slow-write.\n");
2735
2736 dma_free_coherent(&ha->pdev->dev,
2737 OPTROM_BURST_SIZE, optrom, optrom_dma);
2738 optrom = NULL;
2739 } else {
2740 liter += OPTROM_BURST_DWORDS - 1;
2741 faddr += OPTROM_BURST_DWORDS - 1;
2742 dwptr += OPTROM_BURST_DWORDS - 1;
2743 continue;
2744 }
2745 }
2746
2747 ret = qla82xx_write_flash_dword(ha, faddr,
2748 cpu_to_le32(*dwptr));
2749 if (ret) {
2750 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2751 "Unable to program flash address=%x data=%x.\n",
2752 faddr, *dwptr);
2753 break;
2754 }
2755 }
2756
2757 ret = qla82xx_protect_flash(ha);
2758 if (ret)
2759 ql_log(ql_log_warn, vha, 0xb021,
2760 "Unable to protect flash after update.\n");
2761 write_done:
2762 if (optrom)
2763 dma_free_coherent(&ha->pdev->dev,
2764 OPTROM_BURST_SIZE, optrom, optrom_dma);
2765 return ret;
2766 }
2767
2768 int
qla82xx_write_optrom_data(struct scsi_qla_host * vha,uint8_t * buf,uint32_t offset,uint32_t length)2769 qla82xx_write_optrom_data(struct scsi_qla_host *vha, uint8_t *buf,
2770 uint32_t offset, uint32_t length)
2771 {
2772 int rval;
2773
2774 /* Suspend HBA. */
2775 scsi_block_requests(vha->host);
2776 rval = qla82xx_write_flash_data(vha, (uint32_t *)buf, offset,
2777 length >> 2);
2778 scsi_unblock_requests(vha->host);
2779
2780 /* Convert return ISP82xx to generic */
2781 if (rval)
2782 rval = QLA_FUNCTION_FAILED;
2783 else
2784 rval = QLA_SUCCESS;
2785 return rval;
2786 }
2787
2788 void
qla82xx_start_iocbs(scsi_qla_host_t * vha)2789 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2790 {
2791 struct qla_hw_data *ha = vha->hw;
2792 struct req_que *req = ha->req_q_map[0];
2793 uint32_t dbval;
2794
2795 /* Adjust ring index. */
2796 req->ring_index++;
2797 if (req->ring_index == req->length) {
2798 req->ring_index = 0;
2799 req->ring_ptr = req->ring;
2800 } else
2801 req->ring_ptr++;
2802
2803 dbval = 0x04 | (ha->portnum << 5);
2804
2805 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2806 if (ql2xdbwr)
2807 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2808 else {
2809 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2810 wmb();
2811 while (RD_REG_DWORD(ha->nxdb_rd_ptr) != dbval) {
2812 WRT_REG_DWORD(ha->nxdb_wr_ptr, dbval);
2813 wmb();
2814 }
2815 }
2816 }
2817
2818 static void
qla82xx_rom_lock_recovery(struct qla_hw_data * ha)2819 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2820 {
2821 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2822 uint32_t lock_owner = 0;
2823
2824 if (qla82xx_rom_lock(ha)) {
2825 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2826 /* Someone else is holding the lock. */
2827 ql_log(ql_log_info, vha, 0xb022,
2828 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2829 }
2830 /*
2831 * Either we got the lock, or someone
2832 * else died while holding it.
2833 * In either case, unlock.
2834 */
2835 qla82xx_rom_unlock(ha);
2836 }
2837
2838 /*
2839 * qla82xx_device_bootstrap
2840 * Initialize device, set DEV_READY, start fw
2841 *
2842 * Note:
2843 * IDC lock must be held upon entry
2844 *
2845 * Return:
2846 * Success : 0
2847 * Failed : 1
2848 */
2849 static int
qla82xx_device_bootstrap(scsi_qla_host_t * vha)2850 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2851 {
2852 int rval = QLA_SUCCESS;
2853 int i;
2854 uint32_t old_count, count;
2855 struct qla_hw_data *ha = vha->hw;
2856 int need_reset = 0;
2857
2858 need_reset = qla82xx_need_reset(ha);
2859
2860 if (need_reset) {
2861 /* We are trying to perform a recovery here. */
2862 if (ha->flags.isp82xx_fw_hung)
2863 qla82xx_rom_lock_recovery(ha);
2864 } else {
2865 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2866 for (i = 0; i < 10; i++) {
2867 msleep(200);
2868 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2869 if (count != old_count) {
2870 rval = QLA_SUCCESS;
2871 goto dev_ready;
2872 }
2873 }
2874 qla82xx_rom_lock_recovery(ha);
2875 }
2876
2877 /* set to DEV_INITIALIZING */
2878 ql_log(ql_log_info, vha, 0x009e,
2879 "HW State: INITIALIZING.\n");
2880 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2881
2882 qla82xx_idc_unlock(ha);
2883 rval = qla82xx_start_firmware(vha);
2884 qla82xx_idc_lock(ha);
2885
2886 if (rval != QLA_SUCCESS) {
2887 ql_log(ql_log_fatal, vha, 0x00ad,
2888 "HW State: FAILED.\n");
2889 qla82xx_clear_drv_active(ha);
2890 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2891 return rval;
2892 }
2893
2894 dev_ready:
2895 ql_log(ql_log_info, vha, 0x00ae,
2896 "HW State: READY.\n");
2897 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2898
2899 return QLA_SUCCESS;
2900 }
2901
2902 /*
2903 * qla82xx_need_qsnt_handler
2904 * Code to start quiescence sequence
2905 *
2906 * Note:
2907 * IDC lock must be held upon entry
2908 *
2909 * Return: void
2910 */
2911
2912 static void
qla82xx_need_qsnt_handler(scsi_qla_host_t * vha)2913 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2914 {
2915 struct qla_hw_data *ha = vha->hw;
2916 uint32_t dev_state, drv_state, drv_active;
2917 unsigned long reset_timeout;
2918
2919 if (vha->flags.online) {
2920 /*Block any further I/O and wait for pending cmnds to complete*/
2921 qla2x00_quiesce_io(vha);
2922 }
2923
2924 /* Set the quiescence ready bit */
2925 qla82xx_set_qsnt_ready(ha);
2926
2927 /*wait for 30 secs for other functions to ack */
2928 reset_timeout = jiffies + (30 * HZ);
2929
2930 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2931 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2932 /* Its 2 that is written when qsnt is acked, moving one bit */
2933 drv_active = drv_active << 0x01;
2934
2935 while (drv_state != drv_active) {
2936
2937 if (time_after_eq(jiffies, reset_timeout)) {
2938 /* quiescence timeout, other functions didn't ack
2939 * changing the state to DEV_READY
2940 */
2941 ql_log(ql_log_info, vha, 0xb023,
2942 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2943 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2944 drv_active, drv_state);
2945 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2946 QLA8XXX_DEV_READY);
2947 ql_log(ql_log_info, vha, 0xb025,
2948 "HW State: DEV_READY.\n");
2949 qla82xx_idc_unlock(ha);
2950 qla2x00_perform_loop_resync(vha);
2951 qla82xx_idc_lock(ha);
2952
2953 qla82xx_clear_qsnt_ready(vha);
2954 return;
2955 }
2956
2957 qla82xx_idc_unlock(ha);
2958 msleep(1000);
2959 qla82xx_idc_lock(ha);
2960
2961 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2962 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2963 drv_active = drv_active << 0x01;
2964 }
2965 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2966 /* everyone acked so set the state to DEV_QUIESCENCE */
2967 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2968 ql_log(ql_log_info, vha, 0xb026,
2969 "HW State: DEV_QUIESCENT.\n");
2970 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2971 }
2972 }
2973
2974 /*
2975 * qla82xx_wait_for_state_change
2976 * Wait for device state to change from given current state
2977 *
2978 * Note:
2979 * IDC lock must not be held upon entry
2980 *
2981 * Return:
2982 * Changed device state.
2983 */
2984 uint32_t
qla82xx_wait_for_state_change(scsi_qla_host_t * vha,uint32_t curr_state)2985 qla82xx_wait_for_state_change(scsi_qla_host_t *vha, uint32_t curr_state)
2986 {
2987 struct qla_hw_data *ha = vha->hw;
2988 uint32_t dev_state;
2989
2990 do {
2991 msleep(1000);
2992 qla82xx_idc_lock(ha);
2993 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2994 qla82xx_idc_unlock(ha);
2995 } while (dev_state == curr_state);
2996
2997 return dev_state;
2998 }
2999
3000 void
qla8xxx_dev_failed_handler(scsi_qla_host_t * vha)3001 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
3002 {
3003 struct qla_hw_data *ha = vha->hw;
3004
3005 /* Disable the board */
3006 ql_log(ql_log_fatal, vha, 0x00b8,
3007 "Disabling the board.\n");
3008
3009 if (IS_QLA82XX(ha)) {
3010 qla82xx_clear_drv_active(ha);
3011 qla82xx_idc_unlock(ha);
3012 } else if (IS_QLA8044(ha)) {
3013 qla8044_clear_drv_active(ha);
3014 qla8044_idc_unlock(ha);
3015 }
3016
3017 /* Set DEV_FAILED flag to disable timer */
3018 vha->device_flags |= DFLG_DEV_FAILED;
3019 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3020 qla2x00_mark_all_devices_lost(vha, 0);
3021 vha->flags.online = 0;
3022 vha->flags.init_done = 0;
3023 }
3024
3025 /*
3026 * qla82xx_need_reset_handler
3027 * Code to start reset sequence
3028 *
3029 * Note:
3030 * IDC lock must be held upon entry
3031 *
3032 * Return:
3033 * Success : 0
3034 * Failed : 1
3035 */
3036 static void
qla82xx_need_reset_handler(scsi_qla_host_t * vha)3037 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
3038 {
3039 uint32_t dev_state, drv_state, drv_active;
3040 uint32_t active_mask = 0;
3041 unsigned long reset_timeout;
3042 struct qla_hw_data *ha = vha->hw;
3043 struct req_que *req = ha->req_q_map[0];
3044
3045 if (vha->flags.online) {
3046 qla82xx_idc_unlock(ha);
3047 qla2x00_abort_isp_cleanup(vha);
3048 ha->isp_ops->get_flash_version(vha, req->ring);
3049 ha->isp_ops->nvram_config(vha);
3050 qla82xx_idc_lock(ha);
3051 }
3052
3053 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3054 if (!ha->flags.nic_core_reset_owner) {
3055 ql_dbg(ql_dbg_p3p, vha, 0xb028,
3056 "reset_acknowledged by 0x%x\n", ha->portnum);
3057 qla82xx_set_rst_ready(ha);
3058 } else {
3059 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
3060 drv_active &= active_mask;
3061 ql_dbg(ql_dbg_p3p, vha, 0xb029,
3062 "active_mask: 0x%08x\n", active_mask);
3063 }
3064
3065 /* wait for 10 seconds for reset ack from all functions */
3066 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
3067
3068 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3069 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3070 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3071
3072 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
3073 "drv_state: 0x%08x, drv_active: 0x%08x, "
3074 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3075 drv_state, drv_active, dev_state, active_mask);
3076
3077 while (drv_state != drv_active &&
3078 dev_state != QLA8XXX_DEV_INITIALIZING) {
3079 if (time_after_eq(jiffies, reset_timeout)) {
3080 ql_log(ql_log_warn, vha, 0x00b5,
3081 "Reset timeout.\n");
3082 break;
3083 }
3084 qla82xx_idc_unlock(ha);
3085 msleep(1000);
3086 qla82xx_idc_lock(ha);
3087 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3088 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3089 if (ha->flags.nic_core_reset_owner)
3090 drv_active &= active_mask;
3091 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3092 }
3093
3094 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3095 "drv_state: 0x%08x, drv_active: 0x%08x, "
3096 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3097 drv_state, drv_active, dev_state, active_mask);
3098
3099 ql_log(ql_log_info, vha, 0x00b6,
3100 "Device state is 0x%x = %s.\n",
3101 dev_state,
3102 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3103
3104 /* Force to DEV_COLD unless someone else is starting a reset */
3105 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3106 dev_state != QLA8XXX_DEV_COLD) {
3107 ql_log(ql_log_info, vha, 0x00b7,
3108 "HW State: COLD/RE-INIT.\n");
3109 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3110 qla82xx_set_rst_ready(ha);
3111 if (ql2xmdenable) {
3112 if (qla82xx_md_collect(vha))
3113 ql_log(ql_log_warn, vha, 0xb02c,
3114 "Minidump not collected.\n");
3115 } else
3116 ql_log(ql_log_warn, vha, 0xb04f,
3117 "Minidump disabled.\n");
3118 }
3119 }
3120
3121 int
qla82xx_check_md_needed(scsi_qla_host_t * vha)3122 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3123 {
3124 struct qla_hw_data *ha = vha->hw;
3125 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3126 int rval = QLA_SUCCESS;
3127
3128 fw_major_version = ha->fw_major_version;
3129 fw_minor_version = ha->fw_minor_version;
3130 fw_subminor_version = ha->fw_subminor_version;
3131
3132 rval = qla2x00_get_fw_version(vha);
3133 if (rval != QLA_SUCCESS)
3134 return rval;
3135
3136 if (ql2xmdenable) {
3137 if (!ha->fw_dumped) {
3138 if ((fw_major_version != ha->fw_major_version ||
3139 fw_minor_version != ha->fw_minor_version ||
3140 fw_subminor_version != ha->fw_subminor_version) ||
3141 (ha->prev_minidump_failed)) {
3142 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3143 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3144 fw_major_version, fw_minor_version,
3145 fw_subminor_version,
3146 ha->fw_major_version,
3147 ha->fw_minor_version,
3148 ha->fw_subminor_version,
3149 ha->prev_minidump_failed);
3150 /* Release MiniDump resources */
3151 qla82xx_md_free(vha);
3152 /* ALlocate MiniDump resources */
3153 qla82xx_md_prep(vha);
3154 }
3155 } else
3156 ql_log(ql_log_info, vha, 0xb02e,
3157 "Firmware dump available to retrieve\n");
3158 }
3159 return rval;
3160 }
3161
3162
3163 static int
qla82xx_check_fw_alive(scsi_qla_host_t * vha)3164 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3165 {
3166 uint32_t fw_heartbeat_counter;
3167 int status = 0;
3168
3169 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3170 QLA82XX_PEG_ALIVE_COUNTER);
3171 /* all 0xff, assume AER/EEH in progress, ignore */
3172 if (fw_heartbeat_counter == 0xffffffff) {
3173 ql_dbg(ql_dbg_timer, vha, 0x6003,
3174 "FW heartbeat counter is 0xffffffff, "
3175 "returning status=%d.\n", status);
3176 return status;
3177 }
3178 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3179 vha->seconds_since_last_heartbeat++;
3180 /* FW not alive after 2 seconds */
3181 if (vha->seconds_since_last_heartbeat == 2) {
3182 vha->seconds_since_last_heartbeat = 0;
3183 status = 1;
3184 }
3185 } else
3186 vha->seconds_since_last_heartbeat = 0;
3187 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3188 if (status)
3189 ql_dbg(ql_dbg_timer, vha, 0x6004,
3190 "Returning status=%d.\n", status);
3191 return status;
3192 }
3193
3194 /*
3195 * qla82xx_device_state_handler
3196 * Main state handler
3197 *
3198 * Note:
3199 * IDC lock must be held upon entry
3200 *
3201 * Return:
3202 * Success : 0
3203 * Failed : 1
3204 */
3205 int
qla82xx_device_state_handler(scsi_qla_host_t * vha)3206 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3207 {
3208 uint32_t dev_state;
3209 uint32_t old_dev_state;
3210 int rval = QLA_SUCCESS;
3211 unsigned long dev_init_timeout;
3212 struct qla_hw_data *ha = vha->hw;
3213 int loopcount = 0;
3214
3215 qla82xx_idc_lock(ha);
3216 if (!vha->flags.init_done) {
3217 qla82xx_set_drv_active(vha);
3218 qla82xx_set_idc_version(vha);
3219 }
3220
3221 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3222 old_dev_state = dev_state;
3223 ql_log(ql_log_info, vha, 0x009b,
3224 "Device state is 0x%x = %s.\n",
3225 dev_state,
3226 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3227
3228 /* wait for 30 seconds for device to go ready */
3229 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3230
3231 while (1) {
3232
3233 if (time_after_eq(jiffies, dev_init_timeout)) {
3234 ql_log(ql_log_fatal, vha, 0x009c,
3235 "Device init failed.\n");
3236 rval = QLA_FUNCTION_FAILED;
3237 break;
3238 }
3239 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3240 if (old_dev_state != dev_state) {
3241 loopcount = 0;
3242 old_dev_state = dev_state;
3243 }
3244 if (loopcount < 5) {
3245 ql_log(ql_log_info, vha, 0x009d,
3246 "Device state is 0x%x = %s.\n",
3247 dev_state,
3248 dev_state < MAX_STATES ? qdev_state(dev_state) :
3249 "Unknown");
3250 }
3251
3252 switch (dev_state) {
3253 case QLA8XXX_DEV_READY:
3254 ha->flags.nic_core_reset_owner = 0;
3255 goto rel_lock;
3256 case QLA8XXX_DEV_COLD:
3257 rval = qla82xx_device_bootstrap(vha);
3258 break;
3259 case QLA8XXX_DEV_INITIALIZING:
3260 qla82xx_idc_unlock(ha);
3261 msleep(1000);
3262 qla82xx_idc_lock(ha);
3263 break;
3264 case QLA8XXX_DEV_NEED_RESET:
3265 if (!ql2xdontresethba)
3266 qla82xx_need_reset_handler(vha);
3267 else {
3268 qla82xx_idc_unlock(ha);
3269 msleep(1000);
3270 qla82xx_idc_lock(ha);
3271 }
3272 dev_init_timeout = jiffies +
3273 (ha->fcoe_dev_init_timeout * HZ);
3274 break;
3275 case QLA8XXX_DEV_NEED_QUIESCENT:
3276 qla82xx_need_qsnt_handler(vha);
3277 /* Reset timeout value after quiescence handler */
3278 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3279 * HZ);
3280 break;
3281 case QLA8XXX_DEV_QUIESCENT:
3282 /* Owner will exit and other will wait for the state
3283 * to get changed
3284 */
3285 if (ha->flags.quiesce_owner)
3286 goto rel_lock;
3287
3288 qla82xx_idc_unlock(ha);
3289 msleep(1000);
3290 qla82xx_idc_lock(ha);
3291
3292 /* Reset timeout value after quiescence handler */
3293 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout\
3294 * HZ);
3295 break;
3296 case QLA8XXX_DEV_FAILED:
3297 qla8xxx_dev_failed_handler(vha);
3298 rval = QLA_FUNCTION_FAILED;
3299 goto exit;
3300 default:
3301 qla82xx_idc_unlock(ha);
3302 msleep(1000);
3303 qla82xx_idc_lock(ha);
3304 }
3305 loopcount++;
3306 }
3307 rel_lock:
3308 qla82xx_idc_unlock(ha);
3309 exit:
3310 return rval;
3311 }
3312
qla82xx_check_temp(scsi_qla_host_t * vha)3313 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3314 {
3315 uint32_t temp, temp_state, temp_val;
3316 struct qla_hw_data *ha = vha->hw;
3317
3318 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3319 temp_state = qla82xx_get_temp_state(temp);
3320 temp_val = qla82xx_get_temp_val(temp);
3321
3322 if (temp_state == QLA82XX_TEMP_PANIC) {
3323 ql_log(ql_log_warn, vha, 0x600e,
3324 "Device temperature %d degrees C exceeds "
3325 " maximum allowed. Hardware has been shut down.\n",
3326 temp_val);
3327 return 1;
3328 } else if (temp_state == QLA82XX_TEMP_WARN) {
3329 ql_log(ql_log_warn, vha, 0x600f,
3330 "Device temperature %d degrees C exceeds "
3331 "operating range. Immediate action needed.\n",
3332 temp_val);
3333 }
3334 return 0;
3335 }
3336
qla82xx_read_temperature(scsi_qla_host_t * vha)3337 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3338 {
3339 uint32_t temp;
3340
3341 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3342 return qla82xx_get_temp_val(temp);
3343 }
3344
qla82xx_clear_pending_mbx(scsi_qla_host_t * vha)3345 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3346 {
3347 struct qla_hw_data *ha = vha->hw;
3348
3349 if (ha->flags.mbox_busy) {
3350 ha->flags.mbox_int = 1;
3351 ha->flags.mbox_busy = 0;
3352 ql_log(ql_log_warn, vha, 0x6010,
3353 "Doing premature completion of mbx command.\n");
3354 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3355 complete(&ha->mbx_intr_comp);
3356 }
3357 }
3358
qla82xx_watchdog(scsi_qla_host_t * vha)3359 void qla82xx_watchdog(scsi_qla_host_t *vha)
3360 {
3361 uint32_t dev_state, halt_status;
3362 struct qla_hw_data *ha = vha->hw;
3363
3364 /* don't poll if reset is going on */
3365 if (!ha->flags.nic_core_reset_hdlr_active) {
3366 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3367 if (qla82xx_check_temp(vha)) {
3368 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3369 ha->flags.isp82xx_fw_hung = 1;
3370 qla82xx_clear_pending_mbx(vha);
3371 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3372 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3373 ql_log(ql_log_warn, vha, 0x6001,
3374 "Adapter reset needed.\n");
3375 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3376 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3377 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3378 ql_log(ql_log_warn, vha, 0x6002,
3379 "Quiescent needed.\n");
3380 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3381 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3382 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3383 vha->flags.online == 1) {
3384 ql_log(ql_log_warn, vha, 0xb055,
3385 "Adapter state is failed. Offlining.\n");
3386 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3387 ha->flags.isp82xx_fw_hung = 1;
3388 qla82xx_clear_pending_mbx(vha);
3389 } else {
3390 if (qla82xx_check_fw_alive(vha)) {
3391 ql_dbg(ql_dbg_timer, vha, 0x6011,
3392 "disabling pause transmit on port 0 & 1.\n");
3393 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3394 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3395 halt_status = qla82xx_rd_32(ha,
3396 QLA82XX_PEG_HALT_STATUS1);
3397 ql_log(ql_log_info, vha, 0x6005,
3398 "dumping hw/fw registers:.\n "
3399 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3400 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3401 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3402 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3403 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3404 qla82xx_rd_32(ha,
3405 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3406 qla82xx_rd_32(ha,
3407 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3408 qla82xx_rd_32(ha,
3409 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3410 qla82xx_rd_32(ha,
3411 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3412 qla82xx_rd_32(ha,
3413 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3414 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3415 ql_log(ql_log_warn, vha, 0xb052,
3416 "Firmware aborted with "
3417 "error code 0x00006700. Device is "
3418 "being reset.\n");
3419 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3420 set_bit(ISP_UNRECOVERABLE,
3421 &vha->dpc_flags);
3422 } else {
3423 ql_log(ql_log_info, vha, 0x6006,
3424 "Detect abort needed.\n");
3425 set_bit(ISP_ABORT_NEEDED,
3426 &vha->dpc_flags);
3427 }
3428 ha->flags.isp82xx_fw_hung = 1;
3429 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3430 qla82xx_clear_pending_mbx(vha);
3431 }
3432 }
3433 }
3434 }
3435
qla82xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)3436 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3437 {
3438 int rval = -1;
3439 struct qla_hw_data *ha = vha->hw;
3440
3441 if (IS_QLA82XX(ha))
3442 rval = qla82xx_device_state_handler(vha);
3443 else if (IS_QLA8044(ha)) {
3444 qla8044_idc_lock(ha);
3445 /* Decide the reset ownership */
3446 qla83xx_reset_ownership(vha);
3447 qla8044_idc_unlock(ha);
3448 rval = qla8044_device_state_handler(vha);
3449 }
3450 return rval;
3451 }
3452
3453 void
qla82xx_set_reset_owner(scsi_qla_host_t * vha)3454 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3455 {
3456 struct qla_hw_data *ha = vha->hw;
3457 uint32_t dev_state = 0;
3458
3459 if (IS_QLA82XX(ha))
3460 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3461 else if (IS_QLA8044(ha))
3462 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3463
3464 if (dev_state == QLA8XXX_DEV_READY) {
3465 ql_log(ql_log_info, vha, 0xb02f,
3466 "HW State: NEED RESET\n");
3467 if (IS_QLA82XX(ha)) {
3468 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3469 QLA8XXX_DEV_NEED_RESET);
3470 ha->flags.nic_core_reset_owner = 1;
3471 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3472 "reset_owner is 0x%x\n", ha->portnum);
3473 } else if (IS_QLA8044(ha))
3474 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3475 QLA8XXX_DEV_NEED_RESET);
3476 } else
3477 ql_log(ql_log_info, vha, 0xb031,
3478 "Device state is 0x%x = %s.\n",
3479 dev_state,
3480 dev_state < MAX_STATES ? qdev_state(dev_state) : "Unknown");
3481 }
3482
3483 /*
3484 * qla82xx_abort_isp
3485 * Resets ISP and aborts all outstanding commands.
3486 *
3487 * Input:
3488 * ha = adapter block pointer.
3489 *
3490 * Returns:
3491 * 0 = success
3492 */
3493 int
qla82xx_abort_isp(scsi_qla_host_t * vha)3494 qla82xx_abort_isp(scsi_qla_host_t *vha)
3495 {
3496 int rval = -1;
3497 struct qla_hw_data *ha = vha->hw;
3498
3499 if (vha->device_flags & DFLG_DEV_FAILED) {
3500 ql_log(ql_log_warn, vha, 0x8024,
3501 "Device in failed state, exiting.\n");
3502 return QLA_SUCCESS;
3503 }
3504 ha->flags.nic_core_reset_hdlr_active = 1;
3505
3506 qla82xx_idc_lock(ha);
3507 qla82xx_set_reset_owner(vha);
3508 qla82xx_idc_unlock(ha);
3509
3510 if (IS_QLA82XX(ha))
3511 rval = qla82xx_device_state_handler(vha);
3512 else if (IS_QLA8044(ha)) {
3513 qla8044_idc_lock(ha);
3514 /* Decide the reset ownership */
3515 qla83xx_reset_ownership(vha);
3516 qla8044_idc_unlock(ha);
3517 rval = qla8044_device_state_handler(vha);
3518 }
3519
3520 qla82xx_idc_lock(ha);
3521 qla82xx_clear_rst_ready(ha);
3522 qla82xx_idc_unlock(ha);
3523
3524 if (rval == QLA_SUCCESS) {
3525 ha->flags.isp82xx_fw_hung = 0;
3526 ha->flags.nic_core_reset_hdlr_active = 0;
3527 qla82xx_restart_isp(vha);
3528 }
3529
3530 if (rval) {
3531 vha->flags.online = 1;
3532 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3533 if (ha->isp_abort_cnt == 0) {
3534 ql_log(ql_log_warn, vha, 0x8027,
3535 "ISP error recover failed - board "
3536 "disabled.\n");
3537 /*
3538 * The next call disables the board
3539 * completely.
3540 */
3541 ha->isp_ops->reset_adapter(vha);
3542 vha->flags.online = 0;
3543 clear_bit(ISP_ABORT_RETRY,
3544 &vha->dpc_flags);
3545 rval = QLA_SUCCESS;
3546 } else { /* schedule another ISP abort */
3547 ha->isp_abort_cnt--;
3548 ql_log(ql_log_warn, vha, 0x8036,
3549 "ISP abort - retry remaining %d.\n",
3550 ha->isp_abort_cnt);
3551 rval = QLA_FUNCTION_FAILED;
3552 }
3553 } else {
3554 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3555 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3556 "ISP error recovery - retrying (%d) more times.\n",
3557 ha->isp_abort_cnt);
3558 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3559 rval = QLA_FUNCTION_FAILED;
3560 }
3561 }
3562 return rval;
3563 }
3564
3565 /*
3566 * qla82xx_fcoe_ctx_reset
3567 * Perform a quick reset and aborts all outstanding commands.
3568 * This will only perform an FCoE context reset and avoids a full blown
3569 * chip reset.
3570 *
3571 * Input:
3572 * ha = adapter block pointer.
3573 * is_reset_path = flag for identifying the reset path.
3574 *
3575 * Returns:
3576 * 0 = success
3577 */
qla82xx_fcoe_ctx_reset(scsi_qla_host_t * vha)3578 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3579 {
3580 int rval = QLA_FUNCTION_FAILED;
3581
3582 if (vha->flags.online) {
3583 /* Abort all outstanding commands, so as to be requeued later */
3584 qla2x00_abort_isp_cleanup(vha);
3585 }
3586
3587 /* Stop currently executing firmware.
3588 * This will destroy existing FCoE context at the F/W end.
3589 */
3590 qla2x00_try_to_stop_firmware(vha);
3591
3592 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3593 rval = qla82xx_restart_isp(vha);
3594
3595 return rval;
3596 }
3597
3598 /*
3599 * qla2x00_wait_for_fcoe_ctx_reset
3600 * Wait till the FCoE context is reset.
3601 *
3602 * Note:
3603 * Does context switching here.
3604 * Release SPIN_LOCK (if any) before calling this routine.
3605 *
3606 * Return:
3607 * Success (fcoe_ctx reset is done) : 0
3608 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3609 */
qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t * vha)3610 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3611 {
3612 int status = QLA_FUNCTION_FAILED;
3613 unsigned long wait_reset;
3614
3615 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3616 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3617 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3618 && time_before(jiffies, wait_reset)) {
3619
3620 set_current_state(TASK_UNINTERRUPTIBLE);
3621 schedule_timeout(HZ);
3622
3623 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3624 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3625 status = QLA_SUCCESS;
3626 break;
3627 }
3628 }
3629 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3630 "%s: status=%d.\n", __func__, status);
3631
3632 return status;
3633 }
3634
3635 void
qla82xx_chip_reset_cleanup(scsi_qla_host_t * vha)3636 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3637 {
3638 int i, fw_state = 0;
3639 unsigned long flags;
3640 struct qla_hw_data *ha = vha->hw;
3641
3642 /* Check if 82XX firmware is alive or not
3643 * We may have arrived here from NEED_RESET
3644 * detection only
3645 */
3646 if (!ha->flags.isp82xx_fw_hung) {
3647 for (i = 0; i < 2; i++) {
3648 msleep(1000);
3649 if (IS_QLA82XX(ha))
3650 fw_state = qla82xx_check_fw_alive(vha);
3651 else if (IS_QLA8044(ha))
3652 fw_state = qla8044_check_fw_alive(vha);
3653 if (fw_state) {
3654 ha->flags.isp82xx_fw_hung = 1;
3655 qla82xx_clear_pending_mbx(vha);
3656 break;
3657 }
3658 }
3659 }
3660 ql_dbg(ql_dbg_init, vha, 0x00b0,
3661 "Entered %s fw_hung=%d.\n",
3662 __func__, ha->flags.isp82xx_fw_hung);
3663
3664 /* Abort all commands gracefully if fw NOT hung */
3665 if (!ha->flags.isp82xx_fw_hung) {
3666 int cnt, que;
3667 srb_t *sp;
3668 struct req_que *req;
3669
3670 spin_lock_irqsave(&ha->hardware_lock, flags);
3671 for (que = 0; que < ha->max_req_queues; que++) {
3672 req = ha->req_q_map[que];
3673 if (!req)
3674 continue;
3675 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3676 sp = req->outstanding_cmds[cnt];
3677 if (sp) {
3678 if ((!sp->u.scmd.ctx ||
3679 (sp->flags &
3680 SRB_FCP_CMND_DMA_VALID)) &&
3681 !ha->flags.isp82xx_fw_hung) {
3682 spin_unlock_irqrestore(
3683 &ha->hardware_lock, flags);
3684 if (ha->isp_ops->abort_command(sp)) {
3685 ql_log(ql_log_info, vha,
3686 0x00b1,
3687 "mbx abort failed.\n");
3688 } else {
3689 ql_log(ql_log_info, vha,
3690 0x00b2,
3691 "mbx abort success.\n");
3692 }
3693 spin_lock_irqsave(&ha->hardware_lock, flags);
3694 }
3695 }
3696 }
3697 }
3698 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3699
3700 /* Wait for pending cmds (physical and virtual) to complete */
3701 if (!qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3702 WAIT_HOST) == QLA_SUCCESS) {
3703 ql_dbg(ql_dbg_init, vha, 0x00b3,
3704 "Done wait for "
3705 "pending commands.\n");
3706 }
3707 }
3708 }
3709
3710 /* Minidump related functions */
3711 static int
qla82xx_minidump_process_control(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3712 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3713 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3714 {
3715 struct qla_hw_data *ha = vha->hw;
3716 struct qla82xx_md_entry_crb *crb_entry;
3717 uint32_t read_value, opcode, poll_time;
3718 uint32_t addr, index, crb_addr;
3719 unsigned long wtime;
3720 struct qla82xx_md_template_hdr *tmplt_hdr;
3721 uint32_t rval = QLA_SUCCESS;
3722 int i;
3723
3724 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3725 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3726 crb_addr = crb_entry->addr;
3727
3728 for (i = 0; i < crb_entry->op_count; i++) {
3729 opcode = crb_entry->crb_ctrl.opcode;
3730 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3731 qla82xx_md_rw_32(ha, crb_addr,
3732 crb_entry->value_1, 1);
3733 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3734 }
3735
3736 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3737 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3738 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3739 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3740 }
3741
3742 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3743 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3744 read_value &= crb_entry->value_2;
3745 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3746 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3747 read_value |= crb_entry->value_3;
3748 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3749 }
3750 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3751 }
3752
3753 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3754 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3755 read_value |= crb_entry->value_3;
3756 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3757 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3758 }
3759
3760 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3761 poll_time = crb_entry->crb_strd.poll_timeout;
3762 wtime = jiffies + poll_time;
3763 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3764
3765 do {
3766 if ((read_value & crb_entry->value_2)
3767 == crb_entry->value_1)
3768 break;
3769 else if (time_after_eq(jiffies, wtime)) {
3770 /* capturing dump failed */
3771 rval = QLA_FUNCTION_FAILED;
3772 break;
3773 } else
3774 read_value = qla82xx_md_rw_32(ha,
3775 crb_addr, 0, 0);
3776 } while (1);
3777 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3778 }
3779
3780 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3781 if (crb_entry->crb_strd.state_index_a) {
3782 index = crb_entry->crb_strd.state_index_a;
3783 addr = tmplt_hdr->saved_state_array[index];
3784 } else
3785 addr = crb_addr;
3786
3787 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3788 index = crb_entry->crb_ctrl.state_index_v;
3789 tmplt_hdr->saved_state_array[index] = read_value;
3790 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3791 }
3792
3793 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3794 if (crb_entry->crb_strd.state_index_a) {
3795 index = crb_entry->crb_strd.state_index_a;
3796 addr = tmplt_hdr->saved_state_array[index];
3797 } else
3798 addr = crb_addr;
3799
3800 if (crb_entry->crb_ctrl.state_index_v) {
3801 index = crb_entry->crb_ctrl.state_index_v;
3802 read_value =
3803 tmplt_hdr->saved_state_array[index];
3804 } else
3805 read_value = crb_entry->value_1;
3806
3807 qla82xx_md_rw_32(ha, addr, read_value, 1);
3808 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3809 }
3810
3811 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3812 index = crb_entry->crb_ctrl.state_index_v;
3813 read_value = tmplt_hdr->saved_state_array[index];
3814 read_value <<= crb_entry->crb_ctrl.shl;
3815 read_value >>= crb_entry->crb_ctrl.shr;
3816 if (crb_entry->value_2)
3817 read_value &= crb_entry->value_2;
3818 read_value |= crb_entry->value_3;
3819 read_value += crb_entry->value_1;
3820 tmplt_hdr->saved_state_array[index] = read_value;
3821 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3822 }
3823 crb_addr += crb_entry->crb_strd.addr_stride;
3824 }
3825 return rval;
3826 }
3827
3828 static void
qla82xx_minidump_process_rdocm(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3829 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3830 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3831 {
3832 struct qla_hw_data *ha = vha->hw;
3833 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3834 struct qla82xx_md_entry_rdocm *ocm_hdr;
3835 uint32_t *data_ptr = *d_ptr;
3836
3837 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3838 r_addr = ocm_hdr->read_addr;
3839 r_stride = ocm_hdr->read_addr_stride;
3840 loop_cnt = ocm_hdr->op_count;
3841
3842 for (i = 0; i < loop_cnt; i++) {
3843 r_value = RD_REG_DWORD(r_addr + ha->nx_pcibase);
3844 *data_ptr++ = cpu_to_le32(r_value);
3845 r_addr += r_stride;
3846 }
3847 *d_ptr = data_ptr;
3848 }
3849
3850 static void
qla82xx_minidump_process_rdmux(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3851 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3852 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3853 {
3854 struct qla_hw_data *ha = vha->hw;
3855 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3856 struct qla82xx_md_entry_mux *mux_hdr;
3857 uint32_t *data_ptr = *d_ptr;
3858
3859 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3860 r_addr = mux_hdr->read_addr;
3861 s_addr = mux_hdr->select_addr;
3862 s_stride = mux_hdr->select_value_stride;
3863 s_value = mux_hdr->select_value;
3864 loop_cnt = mux_hdr->op_count;
3865
3866 for (i = 0; i < loop_cnt; i++) {
3867 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3868 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3869 *data_ptr++ = cpu_to_le32(s_value);
3870 *data_ptr++ = cpu_to_le32(r_value);
3871 s_value += s_stride;
3872 }
3873 *d_ptr = data_ptr;
3874 }
3875
3876 static void
qla82xx_minidump_process_rdcrb(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3877 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3878 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3879 {
3880 struct qla_hw_data *ha = vha->hw;
3881 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3882 struct qla82xx_md_entry_crb *crb_hdr;
3883 uint32_t *data_ptr = *d_ptr;
3884
3885 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3886 r_addr = crb_hdr->addr;
3887 r_stride = crb_hdr->crb_strd.addr_stride;
3888 loop_cnt = crb_hdr->op_count;
3889
3890 for (i = 0; i < loop_cnt; i++) {
3891 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3892 *data_ptr++ = cpu_to_le32(r_addr);
3893 *data_ptr++ = cpu_to_le32(r_value);
3894 r_addr += r_stride;
3895 }
3896 *d_ptr = data_ptr;
3897 }
3898
3899 static int
qla82xx_minidump_process_l2tag(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3900 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3901 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3902 {
3903 struct qla_hw_data *ha = vha->hw;
3904 uint32_t addr, r_addr, c_addr, t_r_addr;
3905 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3906 unsigned long p_wait, w_time, p_mask;
3907 uint32_t c_value_w, c_value_r;
3908 struct qla82xx_md_entry_cache *cache_hdr;
3909 int rval = QLA_FUNCTION_FAILED;
3910 uint32_t *data_ptr = *d_ptr;
3911
3912 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3913 loop_count = cache_hdr->op_count;
3914 r_addr = cache_hdr->read_addr;
3915 c_addr = cache_hdr->control_addr;
3916 c_value_w = cache_hdr->cache_ctrl.write_value;
3917
3918 t_r_addr = cache_hdr->tag_reg_addr;
3919 t_value = cache_hdr->addr_ctrl.init_tag_value;
3920 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3921 p_wait = cache_hdr->cache_ctrl.poll_wait;
3922 p_mask = cache_hdr->cache_ctrl.poll_mask;
3923
3924 for (i = 0; i < loop_count; i++) {
3925 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3926 if (c_value_w)
3927 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3928
3929 if (p_mask) {
3930 w_time = jiffies + p_wait;
3931 do {
3932 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3933 if ((c_value_r & p_mask) == 0)
3934 break;
3935 else if (time_after_eq(jiffies, w_time)) {
3936 /* capturing dump failed */
3937 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3938 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3939 "w_time: 0x%lx\n",
3940 c_value_r, p_mask, w_time);
3941 return rval;
3942 }
3943 } while (1);
3944 }
3945
3946 addr = r_addr;
3947 for (k = 0; k < r_cnt; k++) {
3948 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3949 *data_ptr++ = cpu_to_le32(r_value);
3950 addr += cache_hdr->read_ctrl.read_addr_stride;
3951 }
3952 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3953 }
3954 *d_ptr = data_ptr;
3955 return QLA_SUCCESS;
3956 }
3957
3958 static void
qla82xx_minidump_process_l1cache(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3959 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3960 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3961 {
3962 struct qla_hw_data *ha = vha->hw;
3963 uint32_t addr, r_addr, c_addr, t_r_addr;
3964 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3965 uint32_t c_value_w;
3966 struct qla82xx_md_entry_cache *cache_hdr;
3967 uint32_t *data_ptr = *d_ptr;
3968
3969 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3970 loop_count = cache_hdr->op_count;
3971 r_addr = cache_hdr->read_addr;
3972 c_addr = cache_hdr->control_addr;
3973 c_value_w = cache_hdr->cache_ctrl.write_value;
3974
3975 t_r_addr = cache_hdr->tag_reg_addr;
3976 t_value = cache_hdr->addr_ctrl.init_tag_value;
3977 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3978
3979 for (i = 0; i < loop_count; i++) {
3980 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3981 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3982 addr = r_addr;
3983 for (k = 0; k < r_cnt; k++) {
3984 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3985 *data_ptr++ = cpu_to_le32(r_value);
3986 addr += cache_hdr->read_ctrl.read_addr_stride;
3987 }
3988 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3989 }
3990 *d_ptr = data_ptr;
3991 }
3992
3993 static void
qla82xx_minidump_process_queue(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)3994 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3995 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
3996 {
3997 struct qla_hw_data *ha = vha->hw;
3998 uint32_t s_addr, r_addr;
3999 uint32_t r_stride, r_value, r_cnt, qid = 0;
4000 uint32_t i, k, loop_cnt;
4001 struct qla82xx_md_entry_queue *q_hdr;
4002 uint32_t *data_ptr = *d_ptr;
4003
4004 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
4005 s_addr = q_hdr->select_addr;
4006 r_cnt = q_hdr->rd_strd.read_addr_cnt;
4007 r_stride = q_hdr->rd_strd.read_addr_stride;
4008 loop_cnt = q_hdr->op_count;
4009
4010 for (i = 0; i < loop_cnt; i++) {
4011 qla82xx_md_rw_32(ha, s_addr, qid, 1);
4012 r_addr = q_hdr->read_addr;
4013 for (k = 0; k < r_cnt; k++) {
4014 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
4015 *data_ptr++ = cpu_to_le32(r_value);
4016 r_addr += r_stride;
4017 }
4018 qid += q_hdr->q_strd.queue_id_stride;
4019 }
4020 *d_ptr = data_ptr;
4021 }
4022
4023 static void
qla82xx_minidump_process_rdrom(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)4024 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
4025 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4026 {
4027 struct qla_hw_data *ha = vha->hw;
4028 uint32_t r_addr, r_value;
4029 uint32_t i, loop_cnt;
4030 struct qla82xx_md_entry_rdrom *rom_hdr;
4031 uint32_t *data_ptr = *d_ptr;
4032
4033 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
4034 r_addr = rom_hdr->read_addr;
4035 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
4036
4037 for (i = 0; i < loop_cnt; i++) {
4038 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
4039 (r_addr & 0xFFFF0000), 1);
4040 r_value = qla82xx_md_rw_32(ha,
4041 MD_DIRECT_ROM_READ_BASE +
4042 (r_addr & 0x0000FFFF), 0, 0);
4043 *data_ptr++ = cpu_to_le32(r_value);
4044 r_addr += sizeof(uint32_t);
4045 }
4046 *d_ptr = data_ptr;
4047 }
4048
4049 static int
qla82xx_minidump_process_rdmem(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,uint32_t ** d_ptr)4050 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
4051 qla82xx_md_entry_hdr_t *entry_hdr, uint32_t **d_ptr)
4052 {
4053 struct qla_hw_data *ha = vha->hw;
4054 uint32_t r_addr, r_value, r_data;
4055 uint32_t i, j, loop_cnt;
4056 struct qla82xx_md_entry_rdmem *m_hdr;
4057 unsigned long flags;
4058 int rval = QLA_FUNCTION_FAILED;
4059 uint32_t *data_ptr = *d_ptr;
4060
4061 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
4062 r_addr = m_hdr->read_addr;
4063 loop_cnt = m_hdr->read_data_size/16;
4064
4065 if (r_addr & 0xf) {
4066 ql_log(ql_log_warn, vha, 0xb033,
4067 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
4068 return rval;
4069 }
4070
4071 if (m_hdr->read_data_size % 16) {
4072 ql_log(ql_log_warn, vha, 0xb034,
4073 "Read data[0x%x] not multiple of 16 bytes\n",
4074 m_hdr->read_data_size);
4075 return rval;
4076 }
4077
4078 ql_dbg(ql_dbg_p3p, vha, 0xb035,
4079 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
4080 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
4081
4082 write_lock_irqsave(&ha->hw_lock, flags);
4083 for (i = 0; i < loop_cnt; i++) {
4084 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
4085 r_value = 0;
4086 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
4087 r_value = MIU_TA_CTL_ENABLE;
4088 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4089 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4090 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4091
4092 for (j = 0; j < MAX_CTL_CHECK; j++) {
4093 r_value = qla82xx_md_rw_32(ha,
4094 MD_MIU_TEST_AGT_CTRL, 0, 0);
4095 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4096 break;
4097 }
4098
4099 if (j >= MAX_CTL_CHECK) {
4100 printk_ratelimited(KERN_ERR
4101 "failed to read through agent\n");
4102 write_unlock_irqrestore(&ha->hw_lock, flags);
4103 return rval;
4104 }
4105
4106 for (j = 0; j < 4; j++) {
4107 r_data = qla82xx_md_rw_32(ha,
4108 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4109 *data_ptr++ = cpu_to_le32(r_data);
4110 }
4111 r_addr += 16;
4112 }
4113 write_unlock_irqrestore(&ha->hw_lock, flags);
4114 *d_ptr = data_ptr;
4115 return QLA_SUCCESS;
4116 }
4117
4118 int
qla82xx_validate_template_chksum(scsi_qla_host_t * vha)4119 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4120 {
4121 struct qla_hw_data *ha = vha->hw;
4122 uint64_t chksum = 0;
4123 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4124 int count = ha->md_template_size/sizeof(uint32_t);
4125
4126 while (count-- > 0)
4127 chksum += *d_ptr++;
4128 while (chksum >> 32)
4129 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4130 return ~chksum;
4131 }
4132
4133 static void
qla82xx_mark_entry_skipped(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,int index)4134 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4135 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4136 {
4137 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4138 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4139 "Skipping entry[%d]: "
4140 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4141 index, entry_hdr->entry_type,
4142 entry_hdr->d_ctrl.entry_capture_mask);
4143 }
4144
4145 int
qla82xx_md_collect(scsi_qla_host_t * vha)4146 qla82xx_md_collect(scsi_qla_host_t *vha)
4147 {
4148 struct qla_hw_data *ha = vha->hw;
4149 int no_entry_hdr = 0;
4150 qla82xx_md_entry_hdr_t *entry_hdr;
4151 struct qla82xx_md_template_hdr *tmplt_hdr;
4152 uint32_t *data_ptr;
4153 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4154 int i = 0, rval = QLA_FUNCTION_FAILED;
4155
4156 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4157 data_ptr = (uint32_t *)ha->md_dump;
4158
4159 if (ha->fw_dumped) {
4160 ql_log(ql_log_warn, vha, 0xb037,
4161 "Firmware has been previously dumped (%p) "
4162 "-- ignoring request.\n", ha->fw_dump);
4163 goto md_failed;
4164 }
4165
4166 ha->fw_dumped = 0;
4167
4168 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4169 ql_log(ql_log_warn, vha, 0xb038,
4170 "Memory not allocated for minidump capture\n");
4171 goto md_failed;
4172 }
4173
4174 if (ha->flags.isp82xx_no_md_cap) {
4175 ql_log(ql_log_warn, vha, 0xb054,
4176 "Forced reset from application, "
4177 "ignore minidump capture\n");
4178 ha->flags.isp82xx_no_md_cap = 0;
4179 goto md_failed;
4180 }
4181
4182 if (qla82xx_validate_template_chksum(vha)) {
4183 ql_log(ql_log_info, vha, 0xb039,
4184 "Template checksum validation error\n");
4185 goto md_failed;
4186 }
4187
4188 no_entry_hdr = tmplt_hdr->num_of_entries;
4189 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4190 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4191
4192 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4193 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4194
4195 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4196
4197 /* Validate whether required debug level is set */
4198 if ((f_capture_mask & 0x3) != 0x3) {
4199 ql_log(ql_log_warn, vha, 0xb03c,
4200 "Minimum required capture mask[0x%x] level not set\n",
4201 f_capture_mask);
4202 goto md_failed;
4203 }
4204 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4205
4206 tmplt_hdr->driver_info[0] = vha->host_no;
4207 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4208 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4209 QLA_DRIVER_BETA_VER;
4210
4211 total_data_size = ha->md_dump_size;
4212
4213 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4214 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4215
4216 /* Check whether template obtained is valid */
4217 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4218 ql_log(ql_log_warn, vha, 0xb04e,
4219 "Bad template header entry type: 0x%x obtained\n",
4220 tmplt_hdr->entry_type);
4221 goto md_failed;
4222 }
4223
4224 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4225 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4226
4227 /* Walk through the entry headers */
4228 for (i = 0; i < no_entry_hdr; i++) {
4229
4230 if (data_collected > total_data_size) {
4231 ql_log(ql_log_warn, vha, 0xb03e,
4232 "More MiniDump data collected: [0x%x]\n",
4233 data_collected);
4234 goto md_failed;
4235 }
4236
4237 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4238 ql2xmdcapmask)) {
4239 entry_hdr->d_ctrl.driver_flags |=
4240 QLA82XX_DBG_SKIPPED_FLAG;
4241 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4242 "Skipping entry[%d]: "
4243 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4244 i, entry_hdr->entry_type,
4245 entry_hdr->d_ctrl.entry_capture_mask);
4246 goto skip_nxt_entry;
4247 }
4248
4249 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4250 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4251 "entry_type: 0x%x, capture_mask: 0x%x\n",
4252 __func__, i, data_ptr, entry_hdr,
4253 entry_hdr->entry_type,
4254 entry_hdr->d_ctrl.entry_capture_mask);
4255
4256 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4257 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4258 data_collected, (ha->md_dump_size - data_collected));
4259
4260 /* Decode the entry type and take
4261 * required action to capture debug data */
4262 switch (entry_hdr->entry_type) {
4263 case QLA82XX_RDEND:
4264 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4265 break;
4266 case QLA82XX_CNTRL:
4267 rval = qla82xx_minidump_process_control(vha,
4268 entry_hdr, &data_ptr);
4269 if (rval != QLA_SUCCESS) {
4270 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4271 goto md_failed;
4272 }
4273 break;
4274 case QLA82XX_RDCRB:
4275 qla82xx_minidump_process_rdcrb(vha,
4276 entry_hdr, &data_ptr);
4277 break;
4278 case QLA82XX_RDMEM:
4279 rval = qla82xx_minidump_process_rdmem(vha,
4280 entry_hdr, &data_ptr);
4281 if (rval != QLA_SUCCESS) {
4282 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4283 goto md_failed;
4284 }
4285 break;
4286 case QLA82XX_BOARD:
4287 case QLA82XX_RDROM:
4288 qla82xx_minidump_process_rdrom(vha,
4289 entry_hdr, &data_ptr);
4290 break;
4291 case QLA82XX_L2DTG:
4292 case QLA82XX_L2ITG:
4293 case QLA82XX_L2DAT:
4294 case QLA82XX_L2INS:
4295 rval = qla82xx_minidump_process_l2tag(vha,
4296 entry_hdr, &data_ptr);
4297 if (rval != QLA_SUCCESS) {
4298 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4299 goto md_failed;
4300 }
4301 break;
4302 case QLA82XX_L1DAT:
4303 case QLA82XX_L1INS:
4304 qla82xx_minidump_process_l1cache(vha,
4305 entry_hdr, &data_ptr);
4306 break;
4307 case QLA82XX_RDOCM:
4308 qla82xx_minidump_process_rdocm(vha,
4309 entry_hdr, &data_ptr);
4310 break;
4311 case QLA82XX_RDMUX:
4312 qla82xx_minidump_process_rdmux(vha,
4313 entry_hdr, &data_ptr);
4314 break;
4315 case QLA82XX_QUEUE:
4316 qla82xx_minidump_process_queue(vha,
4317 entry_hdr, &data_ptr);
4318 break;
4319 case QLA82XX_RDNOP:
4320 default:
4321 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4322 break;
4323 }
4324
4325 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4326 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4327
4328 data_collected = (uint8_t *)data_ptr -
4329 (uint8_t *)ha->md_dump;
4330 skip_nxt_entry:
4331 entry_hdr = (qla82xx_md_entry_hdr_t *) \
4332 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4333 }
4334
4335 if (data_collected != total_data_size) {
4336 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4337 "MiniDump data mismatch: Data collected: [0x%x],"
4338 "total_data_size:[0x%x]\n",
4339 data_collected, total_data_size);
4340 goto md_failed;
4341 }
4342
4343 ql_log(ql_log_info, vha, 0xb044,
4344 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4345 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4346 ha->fw_dumped = 1;
4347 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4348
4349 md_failed:
4350 return rval;
4351 }
4352
4353 int
qla82xx_md_alloc(scsi_qla_host_t * vha)4354 qla82xx_md_alloc(scsi_qla_host_t *vha)
4355 {
4356 struct qla_hw_data *ha = vha->hw;
4357 int i, k;
4358 struct qla82xx_md_template_hdr *tmplt_hdr;
4359
4360 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4361
4362 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4363 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4364 ql_log(ql_log_info, vha, 0xb045,
4365 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4366 ql2xmdcapmask);
4367 }
4368
4369 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4370 if (i & ql2xmdcapmask)
4371 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4372 }
4373
4374 if (ha->md_dump) {
4375 ql_log(ql_log_warn, vha, 0xb046,
4376 "Firmware dump previously allocated.\n");
4377 return 1;
4378 }
4379
4380 ha->md_dump = vmalloc(ha->md_dump_size);
4381 if (ha->md_dump == NULL) {
4382 ql_log(ql_log_warn, vha, 0xb047,
4383 "Unable to allocate memory for Minidump size "
4384 "(0x%x).\n", ha->md_dump_size);
4385 return 1;
4386 }
4387 return 0;
4388 }
4389
4390 void
qla82xx_md_free(scsi_qla_host_t * vha)4391 qla82xx_md_free(scsi_qla_host_t *vha)
4392 {
4393 struct qla_hw_data *ha = vha->hw;
4394
4395 /* Release the template header allocated */
4396 if (ha->md_tmplt_hdr) {
4397 ql_log(ql_log_info, vha, 0xb048,
4398 "Free MiniDump template: %p, size (%d KB)\n",
4399 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4400 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4401 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4402 ha->md_tmplt_hdr = NULL;
4403 }
4404
4405 /* Release the template data buffer allocated */
4406 if (ha->md_dump) {
4407 ql_log(ql_log_info, vha, 0xb049,
4408 "Free MiniDump memory: %p, size (%d KB)\n",
4409 ha->md_dump, ha->md_dump_size / 1024);
4410 vfree(ha->md_dump);
4411 ha->md_dump_size = 0;
4412 ha->md_dump = NULL;
4413 }
4414 }
4415
4416 void
qla82xx_md_prep(scsi_qla_host_t * vha)4417 qla82xx_md_prep(scsi_qla_host_t *vha)
4418 {
4419 struct qla_hw_data *ha = vha->hw;
4420 int rval;
4421
4422 /* Get Minidump template size */
4423 rval = qla82xx_md_get_template_size(vha);
4424 if (rval == QLA_SUCCESS) {
4425 ql_log(ql_log_info, vha, 0xb04a,
4426 "MiniDump Template size obtained (%d KB)\n",
4427 ha->md_template_size / 1024);
4428
4429 /* Get Minidump template */
4430 if (IS_QLA8044(ha))
4431 rval = qla8044_md_get_template(vha);
4432 else
4433 rval = qla82xx_md_get_template(vha);
4434
4435 if (rval == QLA_SUCCESS) {
4436 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4437 "MiniDump Template obtained\n");
4438
4439 /* Allocate memory for minidump */
4440 rval = qla82xx_md_alloc(vha);
4441 if (rval == QLA_SUCCESS)
4442 ql_log(ql_log_info, vha, 0xb04c,
4443 "MiniDump memory allocated (%d KB)\n",
4444 ha->md_dump_size / 1024);
4445 else {
4446 ql_log(ql_log_info, vha, 0xb04d,
4447 "Free MiniDump template: %p, size: (%d KB)\n",
4448 ha->md_tmplt_hdr,
4449 ha->md_template_size / 1024);
4450 dma_free_coherent(&ha->pdev->dev,
4451 ha->md_template_size,
4452 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4453 ha->md_tmplt_hdr = NULL;
4454 }
4455
4456 }
4457 }
4458 }
4459
4460 int
qla82xx_beacon_on(struct scsi_qla_host * vha)4461 qla82xx_beacon_on(struct scsi_qla_host *vha)
4462 {
4463
4464 int rval;
4465 struct qla_hw_data *ha = vha->hw;
4466 qla82xx_idc_lock(ha);
4467 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4468
4469 if (rval) {
4470 ql_log(ql_log_warn, vha, 0xb050,
4471 "mbx set led config failed in %s\n", __func__);
4472 goto exit;
4473 }
4474 ha->beacon_blink_led = 1;
4475 exit:
4476 qla82xx_idc_unlock(ha);
4477 return rval;
4478 }
4479
4480 int
qla82xx_beacon_off(struct scsi_qla_host * vha)4481 qla82xx_beacon_off(struct scsi_qla_host *vha)
4482 {
4483
4484 int rval;
4485 struct qla_hw_data *ha = vha->hw;
4486 qla82xx_idc_lock(ha);
4487 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4488
4489 if (rval) {
4490 ql_log(ql_log_warn, vha, 0xb051,
4491 "mbx set led config failed in %s\n", __func__);
4492 goto exit;
4493 }
4494 ha->beacon_blink_led = 0;
4495 exit:
4496 qla82xx_idc_unlock(ha);
4497 return rval;
4498 }
4499
4500 void
qla82xx_fw_dump(scsi_qla_host_t * vha,int hardware_locked)4501 qla82xx_fw_dump(scsi_qla_host_t *vha, int hardware_locked)
4502 {
4503 struct qla_hw_data *ha = vha->hw;
4504
4505 if (!ha->allow_cna_fw_dump)
4506 return;
4507
4508 scsi_block_requests(vha->host);
4509 ha->flags.isp82xx_no_md_cap = 1;
4510 qla82xx_idc_lock(ha);
4511 qla82xx_set_reset_owner(vha);
4512 qla82xx_idc_unlock(ha);
4513 qla2x00_wait_for_chip_reset(vha);
4514 scsi_unblock_requests(vha->host);
4515 }
4516