1 /*
2 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 *
16 */
17
18 #include <linux/device.h>
19 #include <linux/clk.h>
20 #include <linux/err.h>
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/of_device.h>
24 #include <linux/of_address.h>
25 #include <linux/platform_device.h>
26 #include <linux/random.h>
27
28 #include <soc/tegra/fuse.h>
29
30 #include "fuse.h"
31
32 #define FUSE_BEGIN 0x100
33
34 /* Tegra30 and later */
35 #define FUSE_VENDOR_CODE 0x100
36 #define FUSE_FAB_CODE 0x104
37 #define FUSE_LOT_CODE_0 0x108
38 #define FUSE_LOT_CODE_1 0x10c
39 #define FUSE_WAFER_ID 0x110
40 #define FUSE_X_COORDINATE 0x114
41 #define FUSE_Y_COORDINATE 0x118
42
43 #define FUSE_HAS_REVISION_INFO BIT(0)
44
45 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
46 defined(CONFIG_ARCH_TEGRA_114_SOC) || \
47 defined(CONFIG_ARCH_TEGRA_124_SOC) || \
48 defined(CONFIG_ARCH_TEGRA_132_SOC) || \
49 defined(CONFIG_ARCH_TEGRA_210_SOC) || \
50 defined(CONFIG_ARCH_TEGRA_186_SOC) || \
51 defined(CONFIG_ARCH_TEGRA_194_SOC)
tegra30_fuse_read_early(struct tegra_fuse * fuse,unsigned int offset)52 static u32 tegra30_fuse_read_early(struct tegra_fuse *fuse, unsigned int offset)
53 {
54 if (WARN_ON(!fuse->base))
55 return 0;
56
57 return readl_relaxed(fuse->base + FUSE_BEGIN + offset);
58 }
59
tegra30_fuse_read(struct tegra_fuse * fuse,unsigned int offset)60 static u32 tegra30_fuse_read(struct tegra_fuse *fuse, unsigned int offset)
61 {
62 u32 value;
63 int err;
64
65 err = clk_prepare_enable(fuse->clk);
66 if (err < 0) {
67 dev_err(fuse->dev, "failed to enable FUSE clock: %d\n", err);
68 return 0;
69 }
70
71 value = readl_relaxed(fuse->base + FUSE_BEGIN + offset);
72
73 clk_disable_unprepare(fuse->clk);
74
75 return value;
76 }
77
tegra30_fuse_add_randomness(void)78 static void __init tegra30_fuse_add_randomness(void)
79 {
80 u32 randomness[12];
81
82 randomness[0] = tegra_sku_info.sku_id;
83 randomness[1] = tegra_read_straps();
84 randomness[2] = tegra_read_chipid();
85 randomness[3] = tegra_sku_info.cpu_process_id << 16;
86 randomness[3] |= tegra_sku_info.soc_process_id;
87 randomness[4] = tegra_sku_info.cpu_speedo_id << 16;
88 randomness[4] |= tegra_sku_info.soc_speedo_id;
89 randomness[5] = tegra_fuse_read_early(FUSE_VENDOR_CODE);
90 randomness[6] = tegra_fuse_read_early(FUSE_FAB_CODE);
91 randomness[7] = tegra_fuse_read_early(FUSE_LOT_CODE_0);
92 randomness[8] = tegra_fuse_read_early(FUSE_LOT_CODE_1);
93 randomness[9] = tegra_fuse_read_early(FUSE_WAFER_ID);
94 randomness[10] = tegra_fuse_read_early(FUSE_X_COORDINATE);
95 randomness[11] = tegra_fuse_read_early(FUSE_Y_COORDINATE);
96
97 add_device_randomness(randomness, sizeof(randomness));
98 }
99
tegra30_fuse_init(struct tegra_fuse * fuse)100 static void __init tegra30_fuse_init(struct tegra_fuse *fuse)
101 {
102 fuse->read_early = tegra30_fuse_read_early;
103 fuse->read = tegra30_fuse_read;
104
105 tegra_init_revision();
106
107 if (fuse->soc->speedo_init)
108 fuse->soc->speedo_init(&tegra_sku_info);
109
110 tegra30_fuse_add_randomness();
111 }
112 #endif
113
114 #ifdef CONFIG_ARCH_TEGRA_3x_SOC
115 static const struct tegra_fuse_info tegra30_fuse_info = {
116 .read = tegra30_fuse_read,
117 .size = 0x2a4,
118 .spare = 0x144,
119 };
120
121 const struct tegra_fuse_soc tegra30_fuse_soc = {
122 .init = tegra30_fuse_init,
123 .speedo_init = tegra30_init_speedo_data,
124 .info = &tegra30_fuse_info,
125 };
126 #endif
127
128 #ifdef CONFIG_ARCH_TEGRA_114_SOC
129 static const struct tegra_fuse_info tegra114_fuse_info = {
130 .read = tegra30_fuse_read,
131 .size = 0x2a0,
132 .spare = 0x180,
133 };
134
135 const struct tegra_fuse_soc tegra114_fuse_soc = {
136 .init = tegra30_fuse_init,
137 .speedo_init = tegra114_init_speedo_data,
138 .info = &tegra114_fuse_info,
139 };
140 #endif
141
142 #if defined(CONFIG_ARCH_TEGRA_124_SOC) || defined(CONFIG_ARCH_TEGRA_132_SOC)
143 static const struct tegra_fuse_info tegra124_fuse_info = {
144 .read = tegra30_fuse_read,
145 .size = 0x300,
146 .spare = 0x200,
147 };
148
149 const struct tegra_fuse_soc tegra124_fuse_soc = {
150 .init = tegra30_fuse_init,
151 .speedo_init = tegra124_init_speedo_data,
152 .info = &tegra124_fuse_info,
153 };
154 #endif
155
156 #if defined(CONFIG_ARCH_TEGRA_210_SOC)
157 static const struct tegra_fuse_info tegra210_fuse_info = {
158 .read = tegra30_fuse_read,
159 .size = 0x300,
160 .spare = 0x280,
161 };
162
163 const struct tegra_fuse_soc tegra210_fuse_soc = {
164 .init = tegra30_fuse_init,
165 .speedo_init = tegra210_init_speedo_data,
166 .info = &tegra210_fuse_info,
167 };
168 #endif
169
170 #if defined(CONFIG_ARCH_TEGRA_186_SOC)
171 static const struct tegra_fuse_info tegra186_fuse_info = {
172 .read = tegra30_fuse_read,
173 .size = 0x300,
174 .spare = 0x280,
175 };
176
177 const struct tegra_fuse_soc tegra186_fuse_soc = {
178 .init = tegra30_fuse_init,
179 .info = &tegra186_fuse_info,
180 };
181 #endif
182