1 /*
2 * Designware SPI core controller driver (refer pxa2xx_spi.c)
3 *
4 * Copyright (c) 2009, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16 #include <linux/dma-mapping.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/highmem.h>
20 #include <linux/delay.h>
21 #include <linux/slab.h>
22 #include <linux/spi/spi.h>
23 #include <linux/gpio.h>
24
25 #include "spi-dw.h"
26
27 #ifdef CONFIG_DEBUG_FS
28 #include <linux/debugfs.h>
29 #endif
30
31 /* Slave spi_dev related */
32 struct chip_data {
33 u8 tmode; /* TR/TO/RO/EEPROM */
34 u8 type; /* SPI/SSP/MicroWire */
35
36 u8 poll_mode; /* 1 means use poll mode */
37
38 u16 clk_div; /* baud rate divider */
39 u32 speed_hz; /* baud rate */
40 void (*cs_control)(u32 command);
41 };
42
43 #ifdef CONFIG_DEBUG_FS
44 #define SPI_REGS_BUFSIZE 1024
dw_spi_show_regs(struct file * file,char __user * user_buf,size_t count,loff_t * ppos)45 static ssize_t dw_spi_show_regs(struct file *file, char __user *user_buf,
46 size_t count, loff_t *ppos)
47 {
48 struct dw_spi *dws = file->private_data;
49 char *buf;
50 u32 len = 0;
51 ssize_t ret;
52
53 buf = kzalloc(SPI_REGS_BUFSIZE, GFP_KERNEL);
54 if (!buf)
55 return 0;
56
57 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
58 "%s registers:\n", dev_name(&dws->master->dev));
59 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
60 "=================================\n");
61 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
62 "CTRL0: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL0));
63 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
64 "CTRL1: \t\t0x%08x\n", dw_readl(dws, DW_SPI_CTRL1));
65 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
66 "SSIENR: \t0x%08x\n", dw_readl(dws, DW_SPI_SSIENR));
67 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
68 "SER: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SER));
69 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
70 "BAUDR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_BAUDR));
71 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
72 "TXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_TXFLTR));
73 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
74 "RXFTLR: \t0x%08x\n", dw_readl(dws, DW_SPI_RXFLTR));
75 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
76 "TXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_TXFLR));
77 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
78 "RXFLR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_RXFLR));
79 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
80 "SR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_SR));
81 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
82 "IMR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_IMR));
83 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
84 "ISR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_ISR));
85 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
86 "DMACR: \t\t0x%08x\n", dw_readl(dws, DW_SPI_DMACR));
87 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
88 "DMATDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMATDLR));
89 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
90 "DMARDLR: \t0x%08x\n", dw_readl(dws, DW_SPI_DMARDLR));
91 len += snprintf(buf + len, SPI_REGS_BUFSIZE - len,
92 "=================================\n");
93
94 ret = simple_read_from_buffer(user_buf, count, ppos, buf, len);
95 kfree(buf);
96 return ret;
97 }
98
99 static const struct file_operations dw_spi_regs_ops = {
100 .owner = THIS_MODULE,
101 .open = simple_open,
102 .read = dw_spi_show_regs,
103 .llseek = default_llseek,
104 };
105
dw_spi_debugfs_init(struct dw_spi * dws)106 static int dw_spi_debugfs_init(struct dw_spi *dws)
107 {
108 char name[32];
109
110 snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
111 dws->debugfs = debugfs_create_dir(name, NULL);
112 if (!dws->debugfs)
113 return -ENOMEM;
114
115 debugfs_create_file("registers", S_IFREG | S_IRUGO,
116 dws->debugfs, (void *)dws, &dw_spi_regs_ops);
117 return 0;
118 }
119
dw_spi_debugfs_remove(struct dw_spi * dws)120 static void dw_spi_debugfs_remove(struct dw_spi *dws)
121 {
122 debugfs_remove_recursive(dws->debugfs);
123 }
124
125 #else
dw_spi_debugfs_init(struct dw_spi * dws)126 static inline int dw_spi_debugfs_init(struct dw_spi *dws)
127 {
128 return 0;
129 }
130
dw_spi_debugfs_remove(struct dw_spi * dws)131 static inline void dw_spi_debugfs_remove(struct dw_spi *dws)
132 {
133 }
134 #endif /* CONFIG_DEBUG_FS */
135
dw_spi_set_cs(struct spi_device * spi,bool enable)136 void dw_spi_set_cs(struct spi_device *spi, bool enable)
137 {
138 struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
139 struct chip_data *chip = spi_get_ctldata(spi);
140
141 /* Chip select logic is inverted from spi_set_cs() */
142 if (chip && chip->cs_control)
143 chip->cs_control(!enable);
144
145 if (!enable)
146 dw_writel(dws, DW_SPI_SER, BIT(spi->chip_select));
147 }
148 EXPORT_SYMBOL_GPL(dw_spi_set_cs);
149
150 /* Return the max entries we can fill into tx fifo */
tx_max(struct dw_spi * dws)151 static inline u32 tx_max(struct dw_spi *dws)
152 {
153 u32 tx_left, tx_room, rxtx_gap;
154
155 tx_left = (dws->tx_end - dws->tx) / dws->n_bytes;
156 tx_room = dws->fifo_len - dw_readl(dws, DW_SPI_TXFLR);
157
158 /*
159 * Another concern is about the tx/rx mismatch, we
160 * though to use (dws->fifo_len - rxflr - txflr) as
161 * one maximum value for tx, but it doesn't cover the
162 * data which is out of tx/rx fifo and inside the
163 * shift registers. So a control from sw point of
164 * view is taken.
165 */
166 rxtx_gap = ((dws->rx_end - dws->rx) - (dws->tx_end - dws->tx))
167 / dws->n_bytes;
168
169 return min3(tx_left, tx_room, (u32) (dws->fifo_len - rxtx_gap));
170 }
171
172 /* Return the max entries we should read out of rx fifo */
rx_max(struct dw_spi * dws)173 static inline u32 rx_max(struct dw_spi *dws)
174 {
175 u32 rx_left = (dws->rx_end - dws->rx) / dws->n_bytes;
176
177 return min_t(u32, rx_left, dw_readl(dws, DW_SPI_RXFLR));
178 }
179
dw_writer(struct dw_spi * dws)180 static void dw_writer(struct dw_spi *dws)
181 {
182 u32 max;
183 u16 txw = 0;
184
185 spin_lock(&dws->buf_lock);
186 max = tx_max(dws);
187 while (max--) {
188 /* Set the tx word if the transfer's original "tx" is not null */
189 if (dws->tx_end - dws->len) {
190 if (dws->n_bytes == 1)
191 txw = *(u8 *)(dws->tx);
192 else
193 txw = *(u16 *)(dws->tx);
194 }
195 dw_write_io_reg(dws, DW_SPI_DR, txw);
196 dws->tx += dws->n_bytes;
197 }
198 spin_unlock(&dws->buf_lock);
199 }
200
dw_reader(struct dw_spi * dws)201 static void dw_reader(struct dw_spi *dws)
202 {
203 u32 max;
204 u16 rxw;
205
206 spin_lock(&dws->buf_lock);
207 max = rx_max(dws);
208 while (max--) {
209 rxw = dw_read_io_reg(dws, DW_SPI_DR);
210 /* Care rx only if the transfer's original "rx" is not null */
211 if (dws->rx_end - dws->len) {
212 if (dws->n_bytes == 1)
213 *(u8 *)(dws->rx) = rxw;
214 else
215 *(u16 *)(dws->rx) = rxw;
216 }
217 dws->rx += dws->n_bytes;
218 }
219 spin_unlock(&dws->buf_lock);
220 }
221
int_error_stop(struct dw_spi * dws,const char * msg)222 static void int_error_stop(struct dw_spi *dws, const char *msg)
223 {
224 spi_reset_chip(dws);
225
226 dev_err(&dws->master->dev, "%s\n", msg);
227 dws->master->cur_msg->status = -EIO;
228 spi_finalize_current_transfer(dws->master);
229 }
230
interrupt_transfer(struct dw_spi * dws)231 static irqreturn_t interrupt_transfer(struct dw_spi *dws)
232 {
233 u16 irq_status = dw_readl(dws, DW_SPI_ISR);
234
235 /* Error handling */
236 if (irq_status & (SPI_INT_TXOI | SPI_INT_RXOI | SPI_INT_RXUI)) {
237 dw_readl(dws, DW_SPI_ICR);
238 int_error_stop(dws, "interrupt_transfer: fifo overrun/underrun");
239 return IRQ_HANDLED;
240 }
241
242 dw_reader(dws);
243 if (dws->rx_end == dws->rx) {
244 spi_mask_intr(dws, SPI_INT_TXEI);
245 spi_finalize_current_transfer(dws->master);
246 return IRQ_HANDLED;
247 }
248 if (irq_status & SPI_INT_TXEI) {
249 spi_mask_intr(dws, SPI_INT_TXEI);
250 dw_writer(dws);
251 /* Enable TX irq always, it will be disabled when RX finished */
252 spi_umask_intr(dws, SPI_INT_TXEI);
253 }
254
255 return IRQ_HANDLED;
256 }
257
dw_spi_irq(int irq,void * dev_id)258 static irqreturn_t dw_spi_irq(int irq, void *dev_id)
259 {
260 struct spi_controller *master = dev_id;
261 struct dw_spi *dws = spi_controller_get_devdata(master);
262 u16 irq_status = dw_readl(dws, DW_SPI_ISR) & 0x3f;
263
264 if (!irq_status)
265 return IRQ_NONE;
266
267 if (!master->cur_msg) {
268 spi_mask_intr(dws, SPI_INT_TXEI);
269 return IRQ_HANDLED;
270 }
271
272 return dws->transfer_handler(dws);
273 }
274
275 /* Must be called inside pump_transfers() */
poll_transfer(struct dw_spi * dws)276 static int poll_transfer(struct dw_spi *dws)
277 {
278 do {
279 dw_writer(dws);
280 dw_reader(dws);
281 cpu_relax();
282 } while (dws->rx_end > dws->rx);
283
284 return 0;
285 }
286
dw_spi_transfer_one(struct spi_controller * master,struct spi_device * spi,struct spi_transfer * transfer)287 static int dw_spi_transfer_one(struct spi_controller *master,
288 struct spi_device *spi, struct spi_transfer *transfer)
289 {
290 struct dw_spi *dws = spi_controller_get_devdata(master);
291 struct chip_data *chip = spi_get_ctldata(spi);
292 unsigned long flags;
293 u8 imask = 0;
294 u16 txlevel = 0;
295 u32 cr0;
296 int ret;
297
298 dws->dma_mapped = 0;
299 spin_lock_irqsave(&dws->buf_lock, flags);
300 dws->tx = (void *)transfer->tx_buf;
301 dws->tx_end = dws->tx + transfer->len;
302 dws->rx = transfer->rx_buf;
303 dws->rx_end = dws->rx + transfer->len;
304 dws->len = transfer->len;
305 spin_unlock_irqrestore(&dws->buf_lock, flags);
306
307 /* Ensure dw->rx and dw->rx_end are visible */
308 smp_mb();
309
310 spi_enable_chip(dws, 0);
311
312 /* Handle per transfer options for bpw and speed */
313 if (transfer->speed_hz != dws->current_freq) {
314 if (transfer->speed_hz != chip->speed_hz) {
315 /* clk_div doesn't support odd number */
316 chip->clk_div = (DIV_ROUND_UP(dws->max_freq, transfer->speed_hz) + 1) & 0xfffe;
317 chip->speed_hz = transfer->speed_hz;
318 }
319 dws->current_freq = transfer->speed_hz;
320 spi_set_clk(dws, chip->clk_div);
321 }
322 if (transfer->bits_per_word == 8) {
323 dws->n_bytes = 1;
324 dws->dma_width = 1;
325 } else if (transfer->bits_per_word == 16) {
326 dws->n_bytes = 2;
327 dws->dma_width = 2;
328 } else {
329 return -EINVAL;
330 }
331 /* Default SPI mode is SCPOL = 0, SCPH = 0 */
332 cr0 = (transfer->bits_per_word - 1)
333 | (chip->type << SPI_FRF_OFFSET)
334 | (spi->mode << SPI_MODE_OFFSET)
335 | (chip->tmode << SPI_TMOD_OFFSET);
336
337 /*
338 * Adjust transfer mode if necessary. Requires platform dependent
339 * chipselect mechanism.
340 */
341 if (chip->cs_control) {
342 if (dws->rx && dws->tx)
343 chip->tmode = SPI_TMOD_TR;
344 else if (dws->rx)
345 chip->tmode = SPI_TMOD_RO;
346 else
347 chip->tmode = SPI_TMOD_TO;
348
349 cr0 &= ~SPI_TMOD_MASK;
350 cr0 |= (chip->tmode << SPI_TMOD_OFFSET);
351 }
352
353 dw_writel(dws, DW_SPI_CTRL0, cr0);
354
355 /* Check if current transfer is a DMA transaction */
356 if (master->can_dma && master->can_dma(master, spi, transfer))
357 dws->dma_mapped = master->cur_msg_mapped;
358
359 /* For poll mode just disable all interrupts */
360 spi_mask_intr(dws, 0xff);
361
362 /*
363 * Interrupt mode
364 * we only need set the TXEI IRQ, as TX/RX always happen syncronizely
365 */
366 if (dws->dma_mapped) {
367 ret = dws->dma_ops->dma_setup(dws, transfer);
368 if (ret < 0) {
369 spi_enable_chip(dws, 1);
370 return ret;
371 }
372 } else if (!chip->poll_mode) {
373 txlevel = min_t(u16, dws->fifo_len / 2, dws->len / dws->n_bytes);
374 dw_writel(dws, DW_SPI_TXFLTR, txlevel);
375
376 /* Set the interrupt mask */
377 imask |= SPI_INT_TXEI | SPI_INT_TXOI |
378 SPI_INT_RXUI | SPI_INT_RXOI;
379 spi_umask_intr(dws, imask);
380
381 dws->transfer_handler = interrupt_transfer;
382 }
383
384 spi_enable_chip(dws, 1);
385
386 if (dws->dma_mapped)
387 return dws->dma_ops->dma_transfer(dws, transfer);
388
389 if (chip->poll_mode)
390 return poll_transfer(dws);
391
392 return 1;
393 }
394
dw_spi_handle_err(struct spi_controller * master,struct spi_message * msg)395 static void dw_spi_handle_err(struct spi_controller *master,
396 struct spi_message *msg)
397 {
398 struct dw_spi *dws = spi_controller_get_devdata(master);
399
400 if (dws->dma_mapped)
401 dws->dma_ops->dma_stop(dws);
402
403 spi_reset_chip(dws);
404 }
405
406 /* This may be called twice for each spi dev */
dw_spi_setup(struct spi_device * spi)407 static int dw_spi_setup(struct spi_device *spi)
408 {
409 struct dw_spi_chip *chip_info = NULL;
410 struct chip_data *chip;
411 int ret;
412
413 /* Only alloc on first setup */
414 chip = spi_get_ctldata(spi);
415 if (!chip) {
416 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL);
417 if (!chip)
418 return -ENOMEM;
419 spi_set_ctldata(spi, chip);
420 }
421
422 /*
423 * Protocol drivers may change the chip settings, so...
424 * if chip_info exists, use it
425 */
426 chip_info = spi->controller_data;
427
428 /* chip_info doesn't always exist */
429 if (chip_info) {
430 if (chip_info->cs_control)
431 chip->cs_control = chip_info->cs_control;
432
433 chip->poll_mode = chip_info->poll_mode;
434 chip->type = chip_info->type;
435 }
436
437 chip->tmode = SPI_TMOD_TR;
438
439 if (gpio_is_valid(spi->cs_gpio)) {
440 ret = gpio_direction_output(spi->cs_gpio,
441 !(spi->mode & SPI_CS_HIGH));
442 if (ret)
443 return ret;
444 }
445
446 return 0;
447 }
448
dw_spi_cleanup(struct spi_device * spi)449 static void dw_spi_cleanup(struct spi_device *spi)
450 {
451 struct chip_data *chip = spi_get_ctldata(spi);
452
453 kfree(chip);
454 spi_set_ctldata(spi, NULL);
455 }
456
457 /* Restart the controller, disable all interrupts, clean rx fifo */
spi_hw_init(struct device * dev,struct dw_spi * dws)458 static void spi_hw_init(struct device *dev, struct dw_spi *dws)
459 {
460 spi_reset_chip(dws);
461
462 /*
463 * Try to detect the FIFO depth if not set by interface driver,
464 * the depth could be from 2 to 256 from HW spec
465 */
466 if (!dws->fifo_len) {
467 u32 fifo;
468
469 for (fifo = 1; fifo < 256; fifo++) {
470 dw_writel(dws, DW_SPI_TXFLTR, fifo);
471 if (fifo != dw_readl(dws, DW_SPI_TXFLTR))
472 break;
473 }
474 dw_writel(dws, DW_SPI_TXFLTR, 0);
475
476 dws->fifo_len = (fifo == 1) ? 0 : fifo;
477 dev_dbg(dev, "Detected FIFO size: %u bytes\n", dws->fifo_len);
478 }
479 }
480
dw_spi_add_host(struct device * dev,struct dw_spi * dws)481 int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
482 {
483 struct spi_controller *master;
484 int ret;
485
486 BUG_ON(dws == NULL);
487
488 master = spi_alloc_master(dev, 0);
489 if (!master)
490 return -ENOMEM;
491
492 dws->master = master;
493 dws->type = SSI_MOTO_SPI;
494 dws->dma_inited = 0;
495 dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
496 spin_lock_init(&dws->buf_lock);
497
498 spi_controller_set_devdata(master, dws);
499
500 ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
501 master);
502 if (ret < 0) {
503 dev_err(dev, "can not get IRQ\n");
504 goto err_free_master;
505 }
506
507 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
508 master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
509 master->bus_num = dws->bus_num;
510 master->num_chipselect = dws->num_cs;
511 master->setup = dw_spi_setup;
512 master->cleanup = dw_spi_cleanup;
513 master->set_cs = dw_spi_set_cs;
514 master->transfer_one = dw_spi_transfer_one;
515 master->handle_err = dw_spi_handle_err;
516 master->max_speed_hz = dws->max_freq;
517 master->dev.of_node = dev->of_node;
518 master->flags = SPI_MASTER_GPIO_SS;
519
520 if (dws->set_cs)
521 master->set_cs = dws->set_cs;
522
523 /* Basic HW init */
524 spi_hw_init(dev, dws);
525
526 if (dws->dma_ops && dws->dma_ops->dma_init) {
527 ret = dws->dma_ops->dma_init(dws);
528 if (ret) {
529 dev_warn(dev, "DMA init failed\n");
530 dws->dma_inited = 0;
531 } else {
532 master->can_dma = dws->dma_ops->can_dma;
533 master->flags |= SPI_CONTROLLER_MUST_TX;
534 }
535 }
536
537 ret = spi_register_controller(master);
538 if (ret) {
539 dev_err(&master->dev, "problem registering spi master\n");
540 goto err_dma_exit;
541 }
542
543 dw_spi_debugfs_init(dws);
544 return 0;
545
546 err_dma_exit:
547 if (dws->dma_ops && dws->dma_ops->dma_exit)
548 dws->dma_ops->dma_exit(dws);
549 spi_enable_chip(dws, 0);
550 free_irq(dws->irq, master);
551 err_free_master:
552 spi_controller_put(master);
553 return ret;
554 }
555 EXPORT_SYMBOL_GPL(dw_spi_add_host);
556
dw_spi_remove_host(struct dw_spi * dws)557 void dw_spi_remove_host(struct dw_spi *dws)
558 {
559 dw_spi_debugfs_remove(dws);
560
561 spi_unregister_controller(dws->master);
562
563 if (dws->dma_ops && dws->dma_ops->dma_exit)
564 dws->dma_ops->dma_exit(dws);
565
566 spi_shutdown_chip(dws);
567
568 free_irq(dws->irq, dws->master);
569 }
570 EXPORT_SYMBOL_GPL(dw_spi_remove_host);
571
dw_spi_suspend_host(struct dw_spi * dws)572 int dw_spi_suspend_host(struct dw_spi *dws)
573 {
574 int ret;
575
576 ret = spi_controller_suspend(dws->master);
577 if (ret)
578 return ret;
579
580 spi_shutdown_chip(dws);
581 return 0;
582 }
583 EXPORT_SYMBOL_GPL(dw_spi_suspend_host);
584
dw_spi_resume_host(struct dw_spi * dws)585 int dw_spi_resume_host(struct dw_spi *dws)
586 {
587 int ret;
588
589 spi_hw_init(&dws->master->dev, dws);
590 ret = spi_controller_resume(dws->master);
591 if (ret)
592 dev_err(&dws->master->dev, "fail to start queue (%d)\n", ret);
593 return ret;
594 }
595 EXPORT_SYMBOL_GPL(dw_spi_resume_host);
596
597 MODULE_AUTHOR("Feng Tang <feng.tang@intel.com>");
598 MODULE_DESCRIPTION("Driver for DesignWare SPI controller core");
599 MODULE_LICENSE("GPL v2");
600