1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Copyright (c) 2009 Samsung Electronics Co., Ltd.
4 // Jaswinder Singh <jassi.brar@samsung.com>
5
6 #include <linux/init.h>
7 #include <linux/module.h>
8 #include <linux/interrupt.h>
9 #include <linux/delay.h>
10 #include <linux/clk.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/dmaengine.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/spi/spi.h>
16 #include <linux/gpio.h>
17 #include <linux/of.h>
18 #include <linux/of_gpio.h>
19
20 #include <linux/platform_data/spi-s3c64xx.h>
21
22 #define MAX_SPI_PORTS 6
23 #define S3C64XX_SPI_QUIRK_POLL (1 << 0)
24 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1)
25 #define AUTOSUSPEND_TIMEOUT 2000
26
27 /* Registers and bit-fields */
28
29 #define S3C64XX_SPI_CH_CFG 0x00
30 #define S3C64XX_SPI_CLK_CFG 0x04
31 #define S3C64XX_SPI_MODE_CFG 0x08
32 #define S3C64XX_SPI_SLAVE_SEL 0x0C
33 #define S3C64XX_SPI_INT_EN 0x10
34 #define S3C64XX_SPI_STATUS 0x14
35 #define S3C64XX_SPI_TX_DATA 0x18
36 #define S3C64XX_SPI_RX_DATA 0x1C
37 #define S3C64XX_SPI_PACKET_CNT 0x20
38 #define S3C64XX_SPI_PENDING_CLR 0x24
39 #define S3C64XX_SPI_SWAP_CFG 0x28
40 #define S3C64XX_SPI_FB_CLK 0x2C
41
42 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */
43 #define S3C64XX_SPI_CH_SW_RST (1<<5)
44 #define S3C64XX_SPI_CH_SLAVE (1<<4)
45 #define S3C64XX_SPI_CPOL_L (1<<3)
46 #define S3C64XX_SPI_CPHA_B (1<<2)
47 #define S3C64XX_SPI_CH_RXCH_ON (1<<1)
48 #define S3C64XX_SPI_CH_TXCH_ON (1<<0)
49
50 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9)
51 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9
52 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8)
53 #define S3C64XX_SPI_PSR_MASK 0xff
54
55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29)
56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29)
57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29)
58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29)
59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17)
60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17)
61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17)
62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17)
63 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2)
64 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1)
65 #define S3C64XX_SPI_MODE_4BURST (1<<0)
66
67 #define S3C64XX_SPI_SLAVE_AUTO (1<<1)
68 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0)
69 #define S3C64XX_SPI_SLAVE_NSC_CNT_2 (2<<4)
70
71 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6)
72 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5)
73 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4)
74 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3)
75 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2)
76 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1)
77 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0)
78
79 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5)
80 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4)
81 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3)
82 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2)
83 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1)
84 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0)
85
86 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16)
87
88 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4)
89 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3)
90 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2)
91 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1)
92 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0)
93
94 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7)
95 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6)
96 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5)
97 #define S3C64XX_SPI_SWAP_RX_EN (1<<4)
98 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3)
99 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2)
100 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1)
101 #define S3C64XX_SPI_SWAP_TX_EN (1<<0)
102
103 #define S3C64XX_SPI_FBCLK_MSK (3<<0)
104
105 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
106 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
107 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
108 #define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
109 #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
110 FIFO_LVL_MASK(i))
111
112 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff
113 #define S3C64XX_SPI_TRAILCNT_OFF 19
114
115 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT
116
117 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
118 #define is_polling(x) (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
119
120 #define RXBUSY (1<<2)
121 #define TXBUSY (1<<3)
122
123 struct s3c64xx_spi_dma_data {
124 struct dma_chan *ch;
125 dma_cookie_t cookie;
126 enum dma_transfer_direction direction;
127 };
128
129 /**
130 * struct s3c64xx_spi_info - SPI Controller hardware info
131 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
132 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
133 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
134 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
135 * @clk_from_cmu: True, if the controller does not include a clock mux and
136 * prescaler unit.
137 *
138 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
139 * differ in some aspects such as the size of the fifo and spi bus clock
140 * setup. Such differences are specified to the driver using this structure
141 * which is provided as driver data to the driver.
142 */
143 struct s3c64xx_spi_port_config {
144 int fifo_lvl_mask[MAX_SPI_PORTS];
145 int rx_lvl_offset;
146 int tx_st_done;
147 int quirks;
148 bool high_speed;
149 bool clk_from_cmu;
150 bool clk_ioclk;
151 };
152
153 /**
154 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
155 * @clk: Pointer to the spi clock.
156 * @src_clk: Pointer to the clock used to generate SPI signals.
157 * @ioclk: Pointer to the i/o clock between master and slave
158 * @master: Pointer to the SPI Protocol master.
159 * @cntrlr_info: Platform specific data for the controller this driver manages.
160 * @lock: Controller specific lock.
161 * @state: Set of FLAGS to indicate status.
162 * @rx_dmach: Controller's DMA channel for Rx.
163 * @tx_dmach: Controller's DMA channel for Tx.
164 * @sfr_start: BUS address of SPI controller regs.
165 * @regs: Pointer to ioremap'ed controller registers.
166 * @irq: interrupt
167 * @xfer_completion: To indicate completion of xfer task.
168 * @cur_mode: Stores the active configuration of the controller.
169 * @cur_bpw: Stores the active bits per word settings.
170 * @cur_speed: Stores the active xfer clock speed.
171 */
172 struct s3c64xx_spi_driver_data {
173 void __iomem *regs;
174 struct clk *clk;
175 struct clk *src_clk;
176 struct clk *ioclk;
177 struct platform_device *pdev;
178 struct spi_master *master;
179 struct s3c64xx_spi_info *cntrlr_info;
180 spinlock_t lock;
181 unsigned long sfr_start;
182 struct completion xfer_completion;
183 unsigned state;
184 unsigned cur_mode, cur_bpw;
185 unsigned cur_speed;
186 struct s3c64xx_spi_dma_data rx_dma;
187 struct s3c64xx_spi_dma_data tx_dma;
188 struct s3c64xx_spi_port_config *port_conf;
189 unsigned int port_id;
190 };
191
s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data * sdd)192 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
193 {
194 void __iomem *regs = sdd->regs;
195 unsigned long loops;
196 u32 val;
197
198 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
199
200 val = readl(regs + S3C64XX_SPI_CH_CFG);
201 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
202 writel(val, regs + S3C64XX_SPI_CH_CFG);
203
204 val = readl(regs + S3C64XX_SPI_CH_CFG);
205 val |= S3C64XX_SPI_CH_SW_RST;
206 val &= ~S3C64XX_SPI_CH_HS_EN;
207 writel(val, regs + S3C64XX_SPI_CH_CFG);
208
209 /* Flush TxFIFO*/
210 loops = msecs_to_loops(1);
211 do {
212 val = readl(regs + S3C64XX_SPI_STATUS);
213 } while (TX_FIFO_LVL(val, sdd) && loops--);
214
215 if (loops == 0)
216 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
217
218 /* Flush RxFIFO*/
219 loops = msecs_to_loops(1);
220 do {
221 val = readl(regs + S3C64XX_SPI_STATUS);
222 if (RX_FIFO_LVL(val, sdd))
223 readl(regs + S3C64XX_SPI_RX_DATA);
224 else
225 break;
226 } while (loops--);
227
228 if (loops == 0)
229 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
230
231 val = readl(regs + S3C64XX_SPI_CH_CFG);
232 val &= ~S3C64XX_SPI_CH_SW_RST;
233 writel(val, regs + S3C64XX_SPI_CH_CFG);
234
235 val = readl(regs + S3C64XX_SPI_MODE_CFG);
236 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
237 writel(val, regs + S3C64XX_SPI_MODE_CFG);
238 }
239
s3c64xx_spi_dmacb(void * data)240 static void s3c64xx_spi_dmacb(void *data)
241 {
242 struct s3c64xx_spi_driver_data *sdd;
243 struct s3c64xx_spi_dma_data *dma = data;
244 unsigned long flags;
245
246 if (dma->direction == DMA_DEV_TO_MEM)
247 sdd = container_of(data,
248 struct s3c64xx_spi_driver_data, rx_dma);
249 else
250 sdd = container_of(data,
251 struct s3c64xx_spi_driver_data, tx_dma);
252
253 spin_lock_irqsave(&sdd->lock, flags);
254
255 if (dma->direction == DMA_DEV_TO_MEM) {
256 sdd->state &= ~RXBUSY;
257 if (!(sdd->state & TXBUSY))
258 complete(&sdd->xfer_completion);
259 } else {
260 sdd->state &= ~TXBUSY;
261 if (!(sdd->state & RXBUSY))
262 complete(&sdd->xfer_completion);
263 }
264
265 spin_unlock_irqrestore(&sdd->lock, flags);
266 }
267
prepare_dma(struct s3c64xx_spi_dma_data * dma,struct sg_table * sgt)268 static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
269 struct sg_table *sgt)
270 {
271 struct s3c64xx_spi_driver_data *sdd;
272 struct dma_slave_config config;
273 struct dma_async_tx_descriptor *desc;
274 int ret;
275
276 memset(&config, 0, sizeof(config));
277
278 if (dma->direction == DMA_DEV_TO_MEM) {
279 sdd = container_of((void *)dma,
280 struct s3c64xx_spi_driver_data, rx_dma);
281 config.direction = dma->direction;
282 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
283 config.src_addr_width = sdd->cur_bpw / 8;
284 config.src_maxburst = 1;
285 dmaengine_slave_config(dma->ch, &config);
286 } else {
287 sdd = container_of((void *)dma,
288 struct s3c64xx_spi_driver_data, tx_dma);
289 config.direction = dma->direction;
290 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
291 config.dst_addr_width = sdd->cur_bpw / 8;
292 config.dst_maxburst = 1;
293 dmaengine_slave_config(dma->ch, &config);
294 }
295
296 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
297 dma->direction, DMA_PREP_INTERRUPT);
298 if (!desc) {
299 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
300 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
301 return -ENOMEM;
302 }
303
304 desc->callback = s3c64xx_spi_dmacb;
305 desc->callback_param = dma;
306
307 dma->cookie = dmaengine_submit(desc);
308 ret = dma_submit_error(dma->cookie);
309 if (ret) {
310 dev_err(&sdd->pdev->dev, "DMA submission failed");
311 return -EIO;
312 }
313
314 dma_async_issue_pending(dma->ch);
315 return 0;
316 }
317
s3c64xx_spi_set_cs(struct spi_device * spi,bool enable)318 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
319 {
320 struct s3c64xx_spi_driver_data *sdd =
321 spi_master_get_devdata(spi->master);
322
323 if (sdd->cntrlr_info->no_cs)
324 return;
325
326 if (enable) {
327 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
328 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
329 } else {
330 u32 ssel = readl(sdd->regs + S3C64XX_SPI_SLAVE_SEL);
331
332 ssel |= (S3C64XX_SPI_SLAVE_AUTO |
333 S3C64XX_SPI_SLAVE_NSC_CNT_2);
334 writel(ssel, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
335 }
336 } else {
337 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
338 writel(S3C64XX_SPI_SLAVE_SIG_INACT,
339 sdd->regs + S3C64XX_SPI_SLAVE_SEL);
340 }
341 }
342
s3c64xx_spi_prepare_transfer(struct spi_master * spi)343 static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
344 {
345 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
346
347 if (is_polling(sdd))
348 return 0;
349
350 spi->dma_rx = sdd->rx_dma.ch;
351 spi->dma_tx = sdd->tx_dma.ch;
352
353 return 0;
354 }
355
s3c64xx_spi_can_dma(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)356 static bool s3c64xx_spi_can_dma(struct spi_master *master,
357 struct spi_device *spi,
358 struct spi_transfer *xfer)
359 {
360 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
361
362 return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
363 }
364
s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer,int dma_mode)365 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
366 struct spi_transfer *xfer, int dma_mode)
367 {
368 void __iomem *regs = sdd->regs;
369 u32 modecfg, chcfg;
370 int ret = 0;
371
372 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
373 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
374
375 chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
376 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
377
378 if (dma_mode) {
379 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
380 } else {
381 /* Always shift in data in FIFO, even if xfer is Tx only,
382 * this helps setting PCKT_CNT value for generating clocks
383 * as exactly needed.
384 */
385 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
386 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
387 | S3C64XX_SPI_PACKET_CNT_EN,
388 regs + S3C64XX_SPI_PACKET_CNT);
389 }
390
391 if (xfer->tx_buf != NULL) {
392 sdd->state |= TXBUSY;
393 chcfg |= S3C64XX_SPI_CH_TXCH_ON;
394 if (dma_mode) {
395 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
396 ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
397 } else {
398 switch (sdd->cur_bpw) {
399 case 32:
400 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
401 xfer->tx_buf, xfer->len / 4);
402 break;
403 case 16:
404 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
405 xfer->tx_buf, xfer->len / 2);
406 break;
407 default:
408 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
409 xfer->tx_buf, xfer->len);
410 break;
411 }
412 }
413 }
414
415 if (xfer->rx_buf != NULL) {
416 sdd->state |= RXBUSY;
417
418 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
419 && !(sdd->cur_mode & SPI_CPHA))
420 chcfg |= S3C64XX_SPI_CH_HS_EN;
421
422 if (dma_mode) {
423 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
424 chcfg |= S3C64XX_SPI_CH_RXCH_ON;
425 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
426 | S3C64XX_SPI_PACKET_CNT_EN,
427 regs + S3C64XX_SPI_PACKET_CNT);
428 ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
429 }
430 }
431
432 if (ret)
433 return ret;
434
435 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
436 writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
437
438 return 0;
439 }
440
s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data * sdd,int timeout_ms)441 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
442 int timeout_ms)
443 {
444 void __iomem *regs = sdd->regs;
445 unsigned long val = 1;
446 u32 status;
447
448 /* max fifo depth available */
449 u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
450
451 if (timeout_ms)
452 val = msecs_to_loops(timeout_ms);
453
454 do {
455 status = readl(regs + S3C64XX_SPI_STATUS);
456 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
457
458 /* return the actual received data length */
459 return RX_FIFO_LVL(status, sdd);
460 }
461
s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer)462 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
463 struct spi_transfer *xfer)
464 {
465 void __iomem *regs = sdd->regs;
466 unsigned long val;
467 u32 status;
468 int ms;
469
470 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
471 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
472 ms += 10; /* some tolerance */
473
474 val = msecs_to_jiffies(ms) + 10;
475 val = wait_for_completion_timeout(&sdd->xfer_completion, val);
476
477 /*
478 * If the previous xfer was completed within timeout, then
479 * proceed further else return -EIO.
480 * DmaTx returns after simply writing data in the FIFO,
481 * w/o waiting for real transmission on the bus to finish.
482 * DmaRx returns only after Dma read data from FIFO which
483 * needs bus transmission to finish, so we don't worry if
484 * Xfer involved Rx(with or without Tx).
485 */
486 if (val && !xfer->rx_buf) {
487 val = msecs_to_loops(10);
488 status = readl(regs + S3C64XX_SPI_STATUS);
489 while ((TX_FIFO_LVL(status, sdd)
490 || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
491 && --val) {
492 cpu_relax();
493 status = readl(regs + S3C64XX_SPI_STATUS);
494 }
495
496 }
497
498 /* If timed out while checking rx/tx status return error */
499 if (!val)
500 return -EIO;
501
502 return 0;
503 }
504
s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data * sdd,struct spi_transfer * xfer)505 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
506 struct spi_transfer *xfer)
507 {
508 void __iomem *regs = sdd->regs;
509 unsigned long val;
510 u32 status;
511 int loops;
512 u32 cpy_len;
513 u8 *buf;
514 int ms;
515
516 /* millisecs to xfer 'len' bytes @ 'cur_speed' */
517 ms = xfer->len * 8 * 1000 / sdd->cur_speed;
518 ms += 10; /* some tolerance */
519
520 val = msecs_to_loops(ms);
521 do {
522 status = readl(regs + S3C64XX_SPI_STATUS);
523 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
524
525 if (!val)
526 return -EIO;
527
528 /* If it was only Tx */
529 if (!xfer->rx_buf) {
530 sdd->state &= ~TXBUSY;
531 return 0;
532 }
533
534 /*
535 * If the receive length is bigger than the controller fifo
536 * size, calculate the loops and read the fifo as many times.
537 * loops = length / max fifo size (calculated by using the
538 * fifo mask).
539 * For any size less than the fifo size the below code is
540 * executed atleast once.
541 */
542 loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
543 buf = xfer->rx_buf;
544 do {
545 /* wait for data to be received in the fifo */
546 cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
547 (loops ? ms : 0));
548
549 switch (sdd->cur_bpw) {
550 case 32:
551 ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
552 buf, cpy_len / 4);
553 break;
554 case 16:
555 ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
556 buf, cpy_len / 2);
557 break;
558 default:
559 ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
560 buf, cpy_len);
561 break;
562 }
563
564 buf = buf + cpy_len;
565 } while (loops--);
566 sdd->state &= ~RXBUSY;
567
568 return 0;
569 }
570
s3c64xx_spi_config(struct s3c64xx_spi_driver_data * sdd)571 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
572 {
573 void __iomem *regs = sdd->regs;
574 int ret;
575 u32 val;
576
577 /* Disable Clock */
578 if (!sdd->port_conf->clk_from_cmu) {
579 val = readl(regs + S3C64XX_SPI_CLK_CFG);
580 val &= ~S3C64XX_SPI_ENCLK_ENABLE;
581 writel(val, regs + S3C64XX_SPI_CLK_CFG);
582 }
583
584 /* Set Polarity and Phase */
585 val = readl(regs + S3C64XX_SPI_CH_CFG);
586 val &= ~(S3C64XX_SPI_CH_SLAVE |
587 S3C64XX_SPI_CPOL_L |
588 S3C64XX_SPI_CPHA_B);
589
590 if (sdd->cur_mode & SPI_CPOL)
591 val |= S3C64XX_SPI_CPOL_L;
592
593 if (sdd->cur_mode & SPI_CPHA)
594 val |= S3C64XX_SPI_CPHA_B;
595
596 writel(val, regs + S3C64XX_SPI_CH_CFG);
597
598 /* Set Channel & DMA Mode */
599 val = readl(regs + S3C64XX_SPI_MODE_CFG);
600 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
601 | S3C64XX_SPI_MODE_CH_TSZ_MASK);
602
603 switch (sdd->cur_bpw) {
604 case 32:
605 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
606 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
607 break;
608 case 16:
609 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
610 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
611 break;
612 default:
613 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
614 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
615 break;
616 }
617
618 writel(val, regs + S3C64XX_SPI_MODE_CFG);
619
620 if (sdd->port_conf->clk_from_cmu) {
621 /* The src_clk clock is divided internally by 2 */
622 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
623 if (ret)
624 return ret;
625 } else {
626 /* Configure Clock */
627 val = readl(regs + S3C64XX_SPI_CLK_CFG);
628 val &= ~S3C64XX_SPI_PSR_MASK;
629 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
630 & S3C64XX_SPI_PSR_MASK);
631 writel(val, regs + S3C64XX_SPI_CLK_CFG);
632
633 /* Enable Clock */
634 val = readl(regs + S3C64XX_SPI_CLK_CFG);
635 val |= S3C64XX_SPI_ENCLK_ENABLE;
636 writel(val, regs + S3C64XX_SPI_CLK_CFG);
637 }
638
639 return 0;
640 }
641
642 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
643
s3c64xx_spi_prepare_message(struct spi_master * master,struct spi_message * msg)644 static int s3c64xx_spi_prepare_message(struct spi_master *master,
645 struct spi_message *msg)
646 {
647 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
648 struct spi_device *spi = msg->spi;
649 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
650
651 /* Configure feedback delay */
652 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
653
654 return 0;
655 }
656
s3c64xx_spi_transfer_one(struct spi_master * master,struct spi_device * spi,struct spi_transfer * xfer)657 static int s3c64xx_spi_transfer_one(struct spi_master *master,
658 struct spi_device *spi,
659 struct spi_transfer *xfer)
660 {
661 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
662 const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
663 const void *tx_buf = NULL;
664 void *rx_buf = NULL;
665 int target_len = 0, origin_len = 0;
666 int use_dma = 0;
667 int status;
668 u32 speed;
669 u8 bpw;
670 unsigned long flags;
671
672 reinit_completion(&sdd->xfer_completion);
673
674 /* Only BPW and Speed may change across transfers */
675 bpw = xfer->bits_per_word;
676 speed = xfer->speed_hz;
677
678 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
679 sdd->cur_bpw = bpw;
680 sdd->cur_speed = speed;
681 sdd->cur_mode = spi->mode;
682 status = s3c64xx_spi_config(sdd);
683 if (status)
684 return status;
685 }
686
687 if (!is_polling(sdd) && (xfer->len > fifo_len) &&
688 sdd->rx_dma.ch && sdd->tx_dma.ch) {
689 use_dma = 1;
690
691 } else if (is_polling(sdd) && xfer->len > fifo_len) {
692 tx_buf = xfer->tx_buf;
693 rx_buf = xfer->rx_buf;
694 origin_len = xfer->len;
695
696 target_len = xfer->len;
697 if (xfer->len > fifo_len)
698 xfer->len = fifo_len;
699 }
700
701 do {
702 spin_lock_irqsave(&sdd->lock, flags);
703
704 /* Pending only which is to be done */
705 sdd->state &= ~RXBUSY;
706 sdd->state &= ~TXBUSY;
707
708 /* Start the signals */
709 s3c64xx_spi_set_cs(spi, true);
710
711 status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
712
713 spin_unlock_irqrestore(&sdd->lock, flags);
714
715 if (status) {
716 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
717 break;
718 }
719
720 if (use_dma)
721 status = s3c64xx_wait_for_dma(sdd, xfer);
722 else
723 status = s3c64xx_wait_for_pio(sdd, xfer);
724
725 if (status) {
726 dev_err(&spi->dev,
727 "I/O Error: rx-%d tx-%d res:rx-%c tx-%c len-%d\n",
728 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
729 (sdd->state & RXBUSY) ? 'f' : 'p',
730 (sdd->state & TXBUSY) ? 'f' : 'p',
731 xfer->len);
732
733 if (use_dma) {
734 if (xfer->tx_buf && (sdd->state & TXBUSY))
735 dmaengine_terminate_all(sdd->tx_dma.ch);
736 if (xfer->rx_buf && (sdd->state & RXBUSY))
737 dmaengine_terminate_all(sdd->rx_dma.ch);
738 }
739 } else {
740 s3c64xx_flush_fifo(sdd);
741 }
742 if (target_len > 0) {
743 target_len -= xfer->len;
744
745 if (xfer->tx_buf)
746 xfer->tx_buf += xfer->len;
747
748 if (xfer->rx_buf)
749 xfer->rx_buf += xfer->len;
750
751 if (target_len > fifo_len)
752 xfer->len = fifo_len;
753 else
754 xfer->len = target_len;
755 }
756 } while (target_len > 0);
757
758 if (origin_len) {
759 /* Restore original xfer buffers and length */
760 xfer->tx_buf = tx_buf;
761 xfer->rx_buf = rx_buf;
762 xfer->len = origin_len;
763 }
764
765 return status;
766 }
767
s3c64xx_get_slave_ctrldata(struct spi_device * spi)768 static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
769 struct spi_device *spi)
770 {
771 struct s3c64xx_spi_csinfo *cs;
772 struct device_node *slave_np, *data_np = NULL;
773 u32 fb_delay = 0;
774
775 slave_np = spi->dev.of_node;
776 if (!slave_np) {
777 dev_err(&spi->dev, "device node not found\n");
778 return ERR_PTR(-EINVAL);
779 }
780
781 data_np = of_get_child_by_name(slave_np, "controller-data");
782 if (!data_np) {
783 dev_err(&spi->dev, "child node 'controller-data' not found\n");
784 return ERR_PTR(-EINVAL);
785 }
786
787 cs = kzalloc(sizeof(*cs), GFP_KERNEL);
788 if (!cs) {
789 of_node_put(data_np);
790 return ERR_PTR(-ENOMEM);
791 }
792
793 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
794 cs->fb_delay = fb_delay;
795 of_node_put(data_np);
796 return cs;
797 }
798
799 /*
800 * Here we only check the validity of requested configuration
801 * and save the configuration in a local data-structure.
802 * The controller is actually configured only just before we
803 * get a message to transfer.
804 */
s3c64xx_spi_setup(struct spi_device * spi)805 static int s3c64xx_spi_setup(struct spi_device *spi)
806 {
807 struct s3c64xx_spi_csinfo *cs = spi->controller_data;
808 struct s3c64xx_spi_driver_data *sdd;
809 int err;
810
811 sdd = spi_master_get_devdata(spi->master);
812 if (spi->dev.of_node) {
813 cs = s3c64xx_get_slave_ctrldata(spi);
814 spi->controller_data = cs;
815 } else if (cs) {
816 /* On non-DT platforms the SPI core will set spi->cs_gpio
817 * to -ENOENT. The GPIO pin used to drive the chip select
818 * is defined by using platform data so spi->cs_gpio value
819 * has to be override to have the proper GPIO pin number.
820 */
821 spi->cs_gpio = cs->line;
822 }
823
824 if (IS_ERR_OR_NULL(cs)) {
825 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
826 return -ENODEV;
827 }
828
829 if (!spi_get_ctldata(spi)) {
830 if (gpio_is_valid(spi->cs_gpio)) {
831 err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
832 dev_name(&spi->dev));
833 if (err) {
834 dev_err(&spi->dev,
835 "Failed to get /CS gpio [%d]: %d\n",
836 spi->cs_gpio, err);
837 goto err_gpio_req;
838 }
839 }
840
841 spi_set_ctldata(spi, cs);
842 }
843
844 pm_runtime_get_sync(&sdd->pdev->dev);
845
846 /* Check if we can provide the requested rate */
847 if (!sdd->port_conf->clk_from_cmu) {
848 u32 psr, speed;
849
850 /* Max possible */
851 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
852
853 if (spi->max_speed_hz > speed)
854 spi->max_speed_hz = speed;
855
856 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
857 psr &= S3C64XX_SPI_PSR_MASK;
858 if (psr == S3C64XX_SPI_PSR_MASK)
859 psr--;
860
861 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
862 if (spi->max_speed_hz < speed) {
863 if (psr+1 < S3C64XX_SPI_PSR_MASK) {
864 psr++;
865 } else {
866 err = -EINVAL;
867 goto setup_exit;
868 }
869 }
870
871 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
872 if (spi->max_speed_hz >= speed) {
873 spi->max_speed_hz = speed;
874 } else {
875 dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
876 spi->max_speed_hz);
877 err = -EINVAL;
878 goto setup_exit;
879 }
880 }
881
882 pm_runtime_mark_last_busy(&sdd->pdev->dev);
883 pm_runtime_put_autosuspend(&sdd->pdev->dev);
884 s3c64xx_spi_set_cs(spi, false);
885
886 return 0;
887
888 setup_exit:
889 pm_runtime_mark_last_busy(&sdd->pdev->dev);
890 pm_runtime_put_autosuspend(&sdd->pdev->dev);
891 /* setup() returns with device de-selected */
892 s3c64xx_spi_set_cs(spi, false);
893
894 if (gpio_is_valid(spi->cs_gpio))
895 gpio_free(spi->cs_gpio);
896 spi_set_ctldata(spi, NULL);
897
898 err_gpio_req:
899 if (spi->dev.of_node)
900 kfree(cs);
901
902 return err;
903 }
904
s3c64xx_spi_cleanup(struct spi_device * spi)905 static void s3c64xx_spi_cleanup(struct spi_device *spi)
906 {
907 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
908
909 if (gpio_is_valid(spi->cs_gpio)) {
910 gpio_free(spi->cs_gpio);
911 if (spi->dev.of_node)
912 kfree(cs);
913 else {
914 /* On non-DT platforms, the SPI core sets
915 * spi->cs_gpio to -ENOENT and .setup()
916 * overrides it with the GPIO pin value
917 * passed using platform data.
918 */
919 spi->cs_gpio = -ENOENT;
920 }
921 }
922
923 spi_set_ctldata(spi, NULL);
924 }
925
s3c64xx_spi_irq(int irq,void * data)926 static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
927 {
928 struct s3c64xx_spi_driver_data *sdd = data;
929 struct spi_master *spi = sdd->master;
930 unsigned int val, clr = 0;
931
932 val = readl(sdd->regs + S3C64XX_SPI_STATUS);
933
934 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
935 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
936 dev_err(&spi->dev, "RX overrun\n");
937 }
938 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
939 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
940 dev_err(&spi->dev, "RX underrun\n");
941 }
942 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
943 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
944 dev_err(&spi->dev, "TX overrun\n");
945 }
946 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
947 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
948 dev_err(&spi->dev, "TX underrun\n");
949 }
950
951 /* Clear the pending irq by setting and then clearing it */
952 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
953 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
954
955 return IRQ_HANDLED;
956 }
957
s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data * sdd)958 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
959 {
960 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
961 void __iomem *regs = sdd->regs;
962 unsigned int val;
963
964 sdd->cur_speed = 0;
965
966 if (sci->no_cs)
967 writel(0, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
968 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
969 writel(S3C64XX_SPI_SLAVE_SIG_INACT, sdd->regs + S3C64XX_SPI_SLAVE_SEL);
970
971 /* Disable Interrupts - we use Polling if not DMA mode */
972 writel(0, regs + S3C64XX_SPI_INT_EN);
973
974 if (!sdd->port_conf->clk_from_cmu)
975 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
976 regs + S3C64XX_SPI_CLK_CFG);
977 writel(0, regs + S3C64XX_SPI_MODE_CFG);
978 writel(0, regs + S3C64XX_SPI_PACKET_CNT);
979
980 /* Clear any irq pending bits, should set and clear the bits */
981 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
982 S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
983 S3C64XX_SPI_PND_TX_OVERRUN_CLR |
984 S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
985 writel(val, regs + S3C64XX_SPI_PENDING_CLR);
986 writel(0, regs + S3C64XX_SPI_PENDING_CLR);
987
988 writel(0, regs + S3C64XX_SPI_SWAP_CFG);
989
990 val = readl(regs + S3C64XX_SPI_MODE_CFG);
991 val &= ~S3C64XX_SPI_MODE_4BURST;
992 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
993 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
994 writel(val, regs + S3C64XX_SPI_MODE_CFG);
995
996 s3c64xx_flush_fifo(sdd);
997 }
998
999 #ifdef CONFIG_OF
s3c64xx_spi_parse_dt(struct device * dev)1000 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1001 {
1002 struct s3c64xx_spi_info *sci;
1003 u32 temp;
1004
1005 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1006 if (!sci)
1007 return ERR_PTR(-ENOMEM);
1008
1009 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1010 dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1011 sci->src_clk_nr = 0;
1012 } else {
1013 sci->src_clk_nr = temp;
1014 }
1015
1016 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1017 dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1018 sci->num_cs = 1;
1019 } else {
1020 sci->num_cs = temp;
1021 }
1022
1023 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1024
1025 return sci;
1026 }
1027 #else
s3c64xx_spi_parse_dt(struct device * dev)1028 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1029 {
1030 return dev_get_platdata(dev);
1031 }
1032 #endif
1033
1034 static const struct of_device_id s3c64xx_spi_dt_match[];
1035
s3c64xx_spi_get_port_config(struct platform_device * pdev)1036 static inline struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1037 struct platform_device *pdev)
1038 {
1039 #ifdef CONFIG_OF
1040 if (pdev->dev.of_node) {
1041 const struct of_device_id *match;
1042 match = of_match_node(s3c64xx_spi_dt_match, pdev->dev.of_node);
1043 return (struct s3c64xx_spi_port_config *)match->data;
1044 }
1045 #endif
1046 return (struct s3c64xx_spi_port_config *)
1047 platform_get_device_id(pdev)->driver_data;
1048 }
1049
s3c64xx_spi_probe(struct platform_device * pdev)1050 static int s3c64xx_spi_probe(struct platform_device *pdev)
1051 {
1052 struct resource *mem_res;
1053 struct s3c64xx_spi_driver_data *sdd;
1054 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1055 struct spi_master *master;
1056 int ret, irq;
1057 char clk_name[16];
1058
1059 if (!sci && pdev->dev.of_node) {
1060 sci = s3c64xx_spi_parse_dt(&pdev->dev);
1061 if (IS_ERR(sci))
1062 return PTR_ERR(sci);
1063 }
1064
1065 if (!sci) {
1066 dev_err(&pdev->dev, "platform_data missing!\n");
1067 return -ENODEV;
1068 }
1069
1070 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1071 if (mem_res == NULL) {
1072 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1073 return -ENXIO;
1074 }
1075
1076 irq = platform_get_irq(pdev, 0);
1077 if (irq < 0) {
1078 dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1079 return irq;
1080 }
1081
1082 master = spi_alloc_master(&pdev->dev,
1083 sizeof(struct s3c64xx_spi_driver_data));
1084 if (master == NULL) {
1085 dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1086 return -ENOMEM;
1087 }
1088
1089 platform_set_drvdata(pdev, master);
1090
1091 sdd = spi_master_get_devdata(master);
1092 sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1093 sdd->master = master;
1094 sdd->cntrlr_info = sci;
1095 sdd->pdev = pdev;
1096 sdd->sfr_start = mem_res->start;
1097 if (pdev->dev.of_node) {
1098 ret = of_alias_get_id(pdev->dev.of_node, "spi");
1099 if (ret < 0) {
1100 dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1101 ret);
1102 goto err_deref_master;
1103 }
1104 sdd->port_id = ret;
1105 } else {
1106 sdd->port_id = pdev->id;
1107 }
1108
1109 sdd->cur_bpw = 8;
1110
1111 sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1112 sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1113
1114 master->dev.of_node = pdev->dev.of_node;
1115 master->bus_num = sdd->port_id;
1116 master->setup = s3c64xx_spi_setup;
1117 master->cleanup = s3c64xx_spi_cleanup;
1118 master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1119 master->prepare_message = s3c64xx_spi_prepare_message;
1120 master->transfer_one = s3c64xx_spi_transfer_one;
1121 master->num_chipselect = sci->num_cs;
1122 master->dma_alignment = 8;
1123 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1124 SPI_BPW_MASK(8);
1125 /* the spi->mode bits understood by this driver: */
1126 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1127 master->auto_runtime_pm = true;
1128 if (!is_polling(sdd))
1129 master->can_dma = s3c64xx_spi_can_dma;
1130
1131 sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1132 if (IS_ERR(sdd->regs)) {
1133 ret = PTR_ERR(sdd->regs);
1134 goto err_deref_master;
1135 }
1136
1137 if (sci->cfg_gpio && sci->cfg_gpio()) {
1138 dev_err(&pdev->dev, "Unable to config gpio\n");
1139 ret = -EBUSY;
1140 goto err_deref_master;
1141 }
1142
1143 /* Setup clocks */
1144 sdd->clk = devm_clk_get(&pdev->dev, "spi");
1145 if (IS_ERR(sdd->clk)) {
1146 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1147 ret = PTR_ERR(sdd->clk);
1148 goto err_deref_master;
1149 }
1150
1151 ret = clk_prepare_enable(sdd->clk);
1152 if (ret) {
1153 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1154 goto err_deref_master;
1155 }
1156
1157 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1158 sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1159 if (IS_ERR(sdd->src_clk)) {
1160 dev_err(&pdev->dev,
1161 "Unable to acquire clock '%s'\n", clk_name);
1162 ret = PTR_ERR(sdd->src_clk);
1163 goto err_disable_clk;
1164 }
1165
1166 ret = clk_prepare_enable(sdd->src_clk);
1167 if (ret) {
1168 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1169 goto err_disable_clk;
1170 }
1171
1172 if (sdd->port_conf->clk_ioclk) {
1173 sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1174 if (IS_ERR(sdd->ioclk)) {
1175 dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1176 ret = PTR_ERR(sdd->ioclk);
1177 goto err_disable_src_clk;
1178 }
1179
1180 ret = clk_prepare_enable(sdd->ioclk);
1181 if (ret) {
1182 dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1183 goto err_disable_src_clk;
1184 }
1185 }
1186
1187 if (!is_polling(sdd)) {
1188 /* Acquire DMA channels */
1189 sdd->rx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1190 "rx");
1191 if (IS_ERR(sdd->rx_dma.ch)) {
1192 dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1193 ret = PTR_ERR(sdd->rx_dma.ch);
1194 goto err_disable_io_clk;
1195 }
1196 sdd->tx_dma.ch = dma_request_slave_channel_reason(&pdev->dev,
1197 "tx");
1198 if (IS_ERR(sdd->tx_dma.ch)) {
1199 dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1200 ret = PTR_ERR(sdd->tx_dma.ch);
1201 goto err_release_rx_dma;
1202 }
1203 }
1204
1205 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1206 pm_runtime_use_autosuspend(&pdev->dev);
1207 pm_runtime_set_active(&pdev->dev);
1208 pm_runtime_enable(&pdev->dev);
1209 pm_runtime_get_sync(&pdev->dev);
1210
1211 /* Setup Deufult Mode */
1212 s3c64xx_spi_hwinit(sdd);
1213
1214 spin_lock_init(&sdd->lock);
1215 init_completion(&sdd->xfer_completion);
1216
1217 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1218 "spi-s3c64xx", sdd);
1219 if (ret != 0) {
1220 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1221 irq, ret);
1222 goto err_pm_put;
1223 }
1224
1225 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1226 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1227 sdd->regs + S3C64XX_SPI_INT_EN);
1228
1229 ret = devm_spi_register_master(&pdev->dev, master);
1230 if (ret != 0) {
1231 dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1232 goto err_pm_put;
1233 }
1234
1235 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1236 sdd->port_id, master->num_chipselect);
1237 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1238 mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1239
1240 pm_runtime_mark_last_busy(&pdev->dev);
1241 pm_runtime_put_autosuspend(&pdev->dev);
1242
1243 return 0;
1244
1245 err_pm_put:
1246 pm_runtime_put_noidle(&pdev->dev);
1247 pm_runtime_disable(&pdev->dev);
1248 pm_runtime_set_suspended(&pdev->dev);
1249
1250 if (!is_polling(sdd))
1251 dma_release_channel(sdd->tx_dma.ch);
1252 err_release_rx_dma:
1253 if (!is_polling(sdd))
1254 dma_release_channel(sdd->rx_dma.ch);
1255 err_disable_io_clk:
1256 clk_disable_unprepare(sdd->ioclk);
1257 err_disable_src_clk:
1258 clk_disable_unprepare(sdd->src_clk);
1259 err_disable_clk:
1260 clk_disable_unprepare(sdd->clk);
1261 err_deref_master:
1262 spi_master_put(master);
1263
1264 return ret;
1265 }
1266
s3c64xx_spi_remove(struct platform_device * pdev)1267 static int s3c64xx_spi_remove(struct platform_device *pdev)
1268 {
1269 struct spi_master *master = platform_get_drvdata(pdev);
1270 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1271
1272 pm_runtime_get_sync(&pdev->dev);
1273
1274 writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1275
1276 if (!is_polling(sdd)) {
1277 dma_release_channel(sdd->rx_dma.ch);
1278 dma_release_channel(sdd->tx_dma.ch);
1279 }
1280
1281 clk_disable_unprepare(sdd->ioclk);
1282
1283 clk_disable_unprepare(sdd->src_clk);
1284
1285 clk_disable_unprepare(sdd->clk);
1286
1287 pm_runtime_put_noidle(&pdev->dev);
1288 pm_runtime_disable(&pdev->dev);
1289 pm_runtime_set_suspended(&pdev->dev);
1290
1291 return 0;
1292 }
1293
1294 #ifdef CONFIG_PM_SLEEP
s3c64xx_spi_suspend(struct device * dev)1295 static int s3c64xx_spi_suspend(struct device *dev)
1296 {
1297 struct spi_master *master = dev_get_drvdata(dev);
1298 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1299
1300 int ret = spi_master_suspend(master);
1301 if (ret)
1302 return ret;
1303
1304 ret = pm_runtime_force_suspend(dev);
1305 if (ret < 0)
1306 return ret;
1307
1308 sdd->cur_speed = 0; /* Output Clock is stopped */
1309
1310 return 0;
1311 }
1312
s3c64xx_spi_resume(struct device * dev)1313 static int s3c64xx_spi_resume(struct device *dev)
1314 {
1315 struct spi_master *master = dev_get_drvdata(dev);
1316 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1317 struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1318 int ret;
1319
1320 if (sci->cfg_gpio)
1321 sci->cfg_gpio();
1322
1323 ret = pm_runtime_force_resume(dev);
1324 if (ret < 0)
1325 return ret;
1326
1327 return spi_master_resume(master);
1328 }
1329 #endif /* CONFIG_PM_SLEEP */
1330
1331 #ifdef CONFIG_PM
s3c64xx_spi_runtime_suspend(struct device * dev)1332 static int s3c64xx_spi_runtime_suspend(struct device *dev)
1333 {
1334 struct spi_master *master = dev_get_drvdata(dev);
1335 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1336
1337 clk_disable_unprepare(sdd->clk);
1338 clk_disable_unprepare(sdd->src_clk);
1339 clk_disable_unprepare(sdd->ioclk);
1340
1341 return 0;
1342 }
1343
s3c64xx_spi_runtime_resume(struct device * dev)1344 static int s3c64xx_spi_runtime_resume(struct device *dev)
1345 {
1346 struct spi_master *master = dev_get_drvdata(dev);
1347 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1348 int ret;
1349
1350 if (sdd->port_conf->clk_ioclk) {
1351 ret = clk_prepare_enable(sdd->ioclk);
1352 if (ret != 0)
1353 return ret;
1354 }
1355
1356 ret = clk_prepare_enable(sdd->src_clk);
1357 if (ret != 0)
1358 goto err_disable_ioclk;
1359
1360 ret = clk_prepare_enable(sdd->clk);
1361 if (ret != 0)
1362 goto err_disable_src_clk;
1363
1364 s3c64xx_spi_hwinit(sdd);
1365
1366 return 0;
1367
1368 err_disable_src_clk:
1369 clk_disable_unprepare(sdd->src_clk);
1370 err_disable_ioclk:
1371 clk_disable_unprepare(sdd->ioclk);
1372
1373 return ret;
1374 }
1375 #endif /* CONFIG_PM */
1376
1377 static const struct dev_pm_ops s3c64xx_spi_pm = {
1378 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1379 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1380 s3c64xx_spi_runtime_resume, NULL)
1381 };
1382
1383 static struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1384 .fifo_lvl_mask = { 0x7f },
1385 .rx_lvl_offset = 13,
1386 .tx_st_done = 21,
1387 .high_speed = true,
1388 };
1389
1390 static struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1391 .fifo_lvl_mask = { 0x7f, 0x7F },
1392 .rx_lvl_offset = 13,
1393 .tx_st_done = 21,
1394 };
1395
1396 static struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1397 .fifo_lvl_mask = { 0x1ff, 0x7F },
1398 .rx_lvl_offset = 15,
1399 .tx_st_done = 25,
1400 .high_speed = true,
1401 };
1402
1403 static struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1404 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F },
1405 .rx_lvl_offset = 15,
1406 .tx_st_done = 25,
1407 .high_speed = true,
1408 .clk_from_cmu = true,
1409 };
1410
1411 static struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1412 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1413 .rx_lvl_offset = 15,
1414 .tx_st_done = 25,
1415 .high_speed = true,
1416 .clk_from_cmu = true,
1417 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1418 };
1419
1420 static struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1421 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1422 .rx_lvl_offset = 15,
1423 .tx_st_done = 25,
1424 .high_speed = true,
1425 .clk_from_cmu = true,
1426 .clk_ioclk = true,
1427 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO,
1428 };
1429
1430 static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1431 {
1432 .name = "s3c2443-spi",
1433 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config,
1434 }, {
1435 .name = "s3c6410-spi",
1436 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config,
1437 },
1438 { },
1439 };
1440
1441 static const struct of_device_id s3c64xx_spi_dt_match[] = {
1442 { .compatible = "samsung,s3c2443-spi",
1443 .data = (void *)&s3c2443_spi_port_config,
1444 },
1445 { .compatible = "samsung,s3c6410-spi",
1446 .data = (void *)&s3c6410_spi_port_config,
1447 },
1448 { .compatible = "samsung,s5pv210-spi",
1449 .data = (void *)&s5pv210_spi_port_config,
1450 },
1451 { .compatible = "samsung,exynos4210-spi",
1452 .data = (void *)&exynos4_spi_port_config,
1453 },
1454 { .compatible = "samsung,exynos7-spi",
1455 .data = (void *)&exynos7_spi_port_config,
1456 },
1457 { .compatible = "samsung,exynos5433-spi",
1458 .data = (void *)&exynos5433_spi_port_config,
1459 },
1460 { },
1461 };
1462 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1463
1464 static struct platform_driver s3c64xx_spi_driver = {
1465 .driver = {
1466 .name = "s3c64xx-spi",
1467 .pm = &s3c64xx_spi_pm,
1468 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1469 },
1470 .probe = s3c64xx_spi_probe,
1471 .remove = s3c64xx_spi_remove,
1472 .id_table = s3c64xx_spi_driver_ids,
1473 };
1474 MODULE_ALIAS("platform:s3c64xx-spi");
1475
1476 module_platform_driver(s3c64xx_spi_driver);
1477
1478 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1479 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1480 MODULE_LICENSE("GPL");
1481