1 /*
2 * SPI driver for NVIDIA's Tegra114 SPI Controller.
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 */
18
19 #include <linux/clk.h>
20 #include <linux/completion.h>
21 #include <linux/delay.h>
22 #include <linux/dmaengine.h>
23 #include <linux/dma-mapping.h>
24 #include <linux/dmapool.h>
25 #include <linux/err.h>
26 #include <linux/interrupt.h>
27 #include <linux/io.h>
28 #include <linux/kernel.h>
29 #include <linux/kthread.h>
30 #include <linux/module.h>
31 #include <linux/platform_device.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/of.h>
34 #include <linux/of_device.h>
35 #include <linux/reset.h>
36 #include <linux/spi/spi.h>
37
38 #define SPI_COMMAND1 0x000
39 #define SPI_BIT_LENGTH(x) (((x) & 0x1f) << 0)
40 #define SPI_PACKED (1 << 5)
41 #define SPI_TX_EN (1 << 11)
42 #define SPI_RX_EN (1 << 12)
43 #define SPI_BOTH_EN_BYTE (1 << 13)
44 #define SPI_BOTH_EN_BIT (1 << 14)
45 #define SPI_LSBYTE_FE (1 << 15)
46 #define SPI_LSBIT_FE (1 << 16)
47 #define SPI_BIDIROE (1 << 17)
48 #define SPI_IDLE_SDA_DRIVE_LOW (0 << 18)
49 #define SPI_IDLE_SDA_DRIVE_HIGH (1 << 18)
50 #define SPI_IDLE_SDA_PULL_LOW (2 << 18)
51 #define SPI_IDLE_SDA_PULL_HIGH (3 << 18)
52 #define SPI_IDLE_SDA_MASK (3 << 18)
53 #define SPI_CS_SW_VAL (1 << 20)
54 #define SPI_CS_SW_HW (1 << 21)
55 /* SPI_CS_POL_INACTIVE bits are default high */
56 /* n from 0 to 3 */
57 #define SPI_CS_POL_INACTIVE(n) (1 << (22 + (n)))
58 #define SPI_CS_POL_INACTIVE_MASK (0xF << 22)
59
60 #define SPI_CS_SEL_0 (0 << 26)
61 #define SPI_CS_SEL_1 (1 << 26)
62 #define SPI_CS_SEL_2 (2 << 26)
63 #define SPI_CS_SEL_3 (3 << 26)
64 #define SPI_CS_SEL_MASK (3 << 26)
65 #define SPI_CS_SEL(x) (((x) & 0x3) << 26)
66 #define SPI_CONTROL_MODE_0 (0 << 28)
67 #define SPI_CONTROL_MODE_1 (1 << 28)
68 #define SPI_CONTROL_MODE_2 (2 << 28)
69 #define SPI_CONTROL_MODE_3 (3 << 28)
70 #define SPI_CONTROL_MODE_MASK (3 << 28)
71 #define SPI_MODE_SEL(x) (((x) & 0x3) << 28)
72 #define SPI_M_S (1 << 30)
73 #define SPI_PIO (1 << 31)
74
75 #define SPI_COMMAND2 0x004
76 #define SPI_TX_TAP_DELAY(x) (((x) & 0x3F) << 6)
77 #define SPI_RX_TAP_DELAY(x) (((x) & 0x3F) << 0)
78
79 #define SPI_CS_TIMING1 0x008
80 #define SPI_SETUP_HOLD(setup, hold) (((setup) << 4) | (hold))
81 #define SPI_CS_SETUP_HOLD(reg, cs, val) \
82 ((((val) & 0xFFu) << ((cs) * 8)) | \
83 ((reg) & ~(0xFFu << ((cs) * 8))))
84
85 #define SPI_CS_TIMING2 0x00C
86 #define CYCLES_BETWEEN_PACKETS_0(x) (((x) & 0x1F) << 0)
87 #define CS_ACTIVE_BETWEEN_PACKETS_0 (1 << 5)
88 #define CYCLES_BETWEEN_PACKETS_1(x) (((x) & 0x1F) << 8)
89 #define CS_ACTIVE_BETWEEN_PACKETS_1 (1 << 13)
90 #define CYCLES_BETWEEN_PACKETS_2(x) (((x) & 0x1F) << 16)
91 #define CS_ACTIVE_BETWEEN_PACKETS_2 (1 << 21)
92 #define CYCLES_BETWEEN_PACKETS_3(x) (((x) & 0x1F) << 24)
93 #define CS_ACTIVE_BETWEEN_PACKETS_3 (1 << 29)
94 #define SPI_SET_CS_ACTIVE_BETWEEN_PACKETS(reg, cs, val) \
95 (reg = (((val) & 0x1) << ((cs) * 8 + 5)) | \
96 ((reg) & ~(1 << ((cs) * 8 + 5))))
97 #define SPI_SET_CYCLES_BETWEEN_PACKETS(reg, cs, val) \
98 (reg = (((val) & 0xF) << ((cs) * 8)) | \
99 ((reg) & ~(0xF << ((cs) * 8))))
100
101 #define SPI_TRANS_STATUS 0x010
102 #define SPI_BLK_CNT(val) (((val) >> 0) & 0xFFFF)
103 #define SPI_SLV_IDLE_COUNT(val) (((val) >> 16) & 0xFF)
104 #define SPI_RDY (1 << 30)
105
106 #define SPI_FIFO_STATUS 0x014
107 #define SPI_RX_FIFO_EMPTY (1 << 0)
108 #define SPI_RX_FIFO_FULL (1 << 1)
109 #define SPI_TX_FIFO_EMPTY (1 << 2)
110 #define SPI_TX_FIFO_FULL (1 << 3)
111 #define SPI_RX_FIFO_UNF (1 << 4)
112 #define SPI_RX_FIFO_OVF (1 << 5)
113 #define SPI_TX_FIFO_UNF (1 << 6)
114 #define SPI_TX_FIFO_OVF (1 << 7)
115 #define SPI_ERR (1 << 8)
116 #define SPI_TX_FIFO_FLUSH (1 << 14)
117 #define SPI_RX_FIFO_FLUSH (1 << 15)
118 #define SPI_TX_FIFO_EMPTY_COUNT(val) (((val) >> 16) & 0x7F)
119 #define SPI_RX_FIFO_FULL_COUNT(val) (((val) >> 23) & 0x7F)
120 #define SPI_FRAME_END (1 << 30)
121 #define SPI_CS_INACTIVE (1 << 31)
122
123 #define SPI_FIFO_ERROR (SPI_RX_FIFO_UNF | \
124 SPI_RX_FIFO_OVF | SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF)
125 #define SPI_FIFO_EMPTY (SPI_RX_FIFO_EMPTY | SPI_TX_FIFO_EMPTY)
126
127 #define SPI_TX_DATA 0x018
128 #define SPI_RX_DATA 0x01C
129
130 #define SPI_DMA_CTL 0x020
131 #define SPI_TX_TRIG_1 (0 << 15)
132 #define SPI_TX_TRIG_4 (1 << 15)
133 #define SPI_TX_TRIG_8 (2 << 15)
134 #define SPI_TX_TRIG_16 (3 << 15)
135 #define SPI_TX_TRIG_MASK (3 << 15)
136 #define SPI_RX_TRIG_1 (0 << 19)
137 #define SPI_RX_TRIG_4 (1 << 19)
138 #define SPI_RX_TRIG_8 (2 << 19)
139 #define SPI_RX_TRIG_16 (3 << 19)
140 #define SPI_RX_TRIG_MASK (3 << 19)
141 #define SPI_IE_TX (1 << 28)
142 #define SPI_IE_RX (1 << 29)
143 #define SPI_CONT (1 << 30)
144 #define SPI_DMA (1 << 31)
145 #define SPI_DMA_EN SPI_DMA
146
147 #define SPI_DMA_BLK 0x024
148 #define SPI_DMA_BLK_SET(x) (((x) & 0xFFFF) << 0)
149
150 #define SPI_TX_FIFO 0x108
151 #define SPI_RX_FIFO 0x188
152 #define MAX_CHIP_SELECT 4
153 #define SPI_FIFO_DEPTH 64
154 #define DATA_DIR_TX (1 << 0)
155 #define DATA_DIR_RX (1 << 1)
156
157 #define SPI_DMA_TIMEOUT (msecs_to_jiffies(1000))
158 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024)
159 #define TX_FIFO_EMPTY_COUNT_MAX SPI_TX_FIFO_EMPTY_COUNT(0x40)
160 #define RX_FIFO_FULL_COUNT_ZERO SPI_RX_FIFO_FULL_COUNT(0)
161 #define MAX_HOLD_CYCLES 16
162 #define SPI_DEFAULT_SPEED 25000000
163
164 struct tegra_spi_data {
165 struct device *dev;
166 struct spi_master *master;
167 spinlock_t lock;
168
169 struct clk *clk;
170 struct reset_control *rst;
171 void __iomem *base;
172 phys_addr_t phys;
173 unsigned irq;
174 u32 cur_speed;
175
176 struct spi_device *cur_spi;
177 struct spi_device *cs_control;
178 unsigned cur_pos;
179 unsigned words_per_32bit;
180 unsigned bytes_per_word;
181 unsigned curr_dma_words;
182 unsigned cur_direction;
183
184 unsigned cur_rx_pos;
185 unsigned cur_tx_pos;
186
187 unsigned dma_buf_size;
188 unsigned max_buf_size;
189 bool is_curr_dma_xfer;
190
191 struct completion rx_dma_complete;
192 struct completion tx_dma_complete;
193
194 u32 tx_status;
195 u32 rx_status;
196 u32 status_reg;
197 bool is_packed;
198
199 u32 command1_reg;
200 u32 dma_control_reg;
201 u32 def_command1_reg;
202
203 struct completion xfer_completion;
204 struct spi_transfer *curr_xfer;
205 struct dma_chan *rx_dma_chan;
206 u32 *rx_dma_buf;
207 dma_addr_t rx_dma_phys;
208 struct dma_async_tx_descriptor *rx_dma_desc;
209
210 struct dma_chan *tx_dma_chan;
211 u32 *tx_dma_buf;
212 dma_addr_t tx_dma_phys;
213 struct dma_async_tx_descriptor *tx_dma_desc;
214 };
215
216 static int tegra_spi_runtime_suspend(struct device *dev);
217 static int tegra_spi_runtime_resume(struct device *dev);
218
tegra_spi_readl(struct tegra_spi_data * tspi,unsigned long reg)219 static inline u32 tegra_spi_readl(struct tegra_spi_data *tspi,
220 unsigned long reg)
221 {
222 return readl(tspi->base + reg);
223 }
224
tegra_spi_writel(struct tegra_spi_data * tspi,u32 val,unsigned long reg)225 static inline void tegra_spi_writel(struct tegra_spi_data *tspi,
226 u32 val, unsigned long reg)
227 {
228 writel(val, tspi->base + reg);
229
230 /* Read back register to make sure that register writes completed */
231 if (reg != SPI_TX_FIFO)
232 readl(tspi->base + SPI_COMMAND1);
233 }
234
tegra_spi_clear_status(struct tegra_spi_data * tspi)235 static void tegra_spi_clear_status(struct tegra_spi_data *tspi)
236 {
237 u32 val;
238
239 /* Write 1 to clear status register */
240 val = tegra_spi_readl(tspi, SPI_TRANS_STATUS);
241 tegra_spi_writel(tspi, val, SPI_TRANS_STATUS);
242
243 /* Clear fifo status error if any */
244 val = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
245 if (val & SPI_ERR)
246 tegra_spi_writel(tspi, SPI_ERR | SPI_FIFO_ERROR,
247 SPI_FIFO_STATUS);
248 }
249
tegra_spi_calculate_curr_xfer_param(struct spi_device * spi,struct tegra_spi_data * tspi,struct spi_transfer * t)250 static unsigned tegra_spi_calculate_curr_xfer_param(
251 struct spi_device *spi, struct tegra_spi_data *tspi,
252 struct spi_transfer *t)
253 {
254 unsigned remain_len = t->len - tspi->cur_pos;
255 unsigned max_word;
256 unsigned bits_per_word = t->bits_per_word;
257 unsigned max_len;
258 unsigned total_fifo_words;
259
260 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8);
261
262 if (bits_per_word == 8 || bits_per_word == 16) {
263 tspi->is_packed = 1;
264 tspi->words_per_32bit = 32/bits_per_word;
265 } else {
266 tspi->is_packed = 0;
267 tspi->words_per_32bit = 1;
268 }
269
270 if (tspi->is_packed) {
271 max_len = min(remain_len, tspi->max_buf_size);
272 tspi->curr_dma_words = max_len/tspi->bytes_per_word;
273 total_fifo_words = (max_len + 3) / 4;
274 } else {
275 max_word = (remain_len - 1) / tspi->bytes_per_word + 1;
276 max_word = min(max_word, tspi->max_buf_size/4);
277 tspi->curr_dma_words = max_word;
278 total_fifo_words = max_word;
279 }
280 return total_fifo_words;
281 }
282
tegra_spi_fill_tx_fifo_from_client_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)283 static unsigned tegra_spi_fill_tx_fifo_from_client_txbuf(
284 struct tegra_spi_data *tspi, struct spi_transfer *t)
285 {
286 unsigned nbytes;
287 unsigned tx_empty_count;
288 u32 fifo_status;
289 unsigned max_n_32bit;
290 unsigned i, count;
291 unsigned int written_words;
292 unsigned fifo_words_left;
293 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
294
295 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
296 tx_empty_count = SPI_TX_FIFO_EMPTY_COUNT(fifo_status);
297
298 if (tspi->is_packed) {
299 fifo_words_left = tx_empty_count * tspi->words_per_32bit;
300 written_words = min(fifo_words_left, tspi->curr_dma_words);
301 nbytes = written_words * tspi->bytes_per_word;
302 max_n_32bit = DIV_ROUND_UP(nbytes, 4);
303 for (count = 0; count < max_n_32bit; count++) {
304 u32 x = 0;
305
306 for (i = 0; (i < 4) && nbytes; i++, nbytes--)
307 x |= (u32)(*tx_buf++) << (i * 8);
308 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
309 }
310
311 tspi->cur_tx_pos += written_words * tspi->bytes_per_word;
312 } else {
313 unsigned int write_bytes;
314 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count);
315 written_words = max_n_32bit;
316 nbytes = written_words * tspi->bytes_per_word;
317 if (nbytes > t->len - tspi->cur_pos)
318 nbytes = t->len - tspi->cur_pos;
319 write_bytes = nbytes;
320 for (count = 0; count < max_n_32bit; count++) {
321 u32 x = 0;
322
323 for (i = 0; nbytes && (i < tspi->bytes_per_word);
324 i++, nbytes--)
325 x |= (u32)(*tx_buf++) << (i * 8);
326 tegra_spi_writel(tspi, x, SPI_TX_FIFO);
327 }
328
329 tspi->cur_tx_pos += write_bytes;
330 }
331
332 return written_words;
333 }
334
tegra_spi_read_rx_fifo_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)335 static unsigned int tegra_spi_read_rx_fifo_to_client_rxbuf(
336 struct tegra_spi_data *tspi, struct spi_transfer *t)
337 {
338 unsigned rx_full_count;
339 u32 fifo_status;
340 unsigned i, count;
341 unsigned int read_words = 0;
342 unsigned len;
343 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos;
344
345 fifo_status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
346 rx_full_count = SPI_RX_FIFO_FULL_COUNT(fifo_status);
347 if (tspi->is_packed) {
348 len = tspi->curr_dma_words * tspi->bytes_per_word;
349 for (count = 0; count < rx_full_count; count++) {
350 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO);
351
352 for (i = 0; len && (i < 4); i++, len--)
353 *rx_buf++ = (x >> i*8) & 0xFF;
354 }
355 read_words += tspi->curr_dma_words;
356 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
357 } else {
358 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
359 u8 bytes_per_word = tspi->bytes_per_word;
360 unsigned int read_bytes;
361
362 len = rx_full_count * bytes_per_word;
363 if (len > t->len - tspi->cur_pos)
364 len = t->len - tspi->cur_pos;
365 read_bytes = len;
366 for (count = 0; count < rx_full_count; count++) {
367 u32 x = tegra_spi_readl(tspi, SPI_RX_FIFO) & rx_mask;
368
369 for (i = 0; len && (i < bytes_per_word); i++, len--)
370 *rx_buf++ = (x >> (i*8)) & 0xFF;
371 }
372 read_words += rx_full_count;
373 tspi->cur_rx_pos += read_bytes;
374 }
375
376 return read_words;
377 }
378
tegra_spi_copy_client_txbuf_to_spi_txbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)379 static void tegra_spi_copy_client_txbuf_to_spi_txbuf(
380 struct tegra_spi_data *tspi, struct spi_transfer *t)
381 {
382 /* Make the dma buffer to read by cpu */
383 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys,
384 tspi->dma_buf_size, DMA_TO_DEVICE);
385
386 if (tspi->is_packed) {
387 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
388
389 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len);
390 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
391 } else {
392 unsigned int i;
393 unsigned int count;
394 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos;
395 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
396 unsigned int write_bytes;
397
398 if (consume > t->len - tspi->cur_pos)
399 consume = t->len - tspi->cur_pos;
400 write_bytes = consume;
401 for (count = 0; count < tspi->curr_dma_words; count++) {
402 u32 x = 0;
403
404 for (i = 0; consume && (i < tspi->bytes_per_word);
405 i++, consume--)
406 x |= (u32)(*tx_buf++) << (i * 8);
407 tspi->tx_dma_buf[count] = x;
408 }
409
410 tspi->cur_tx_pos += write_bytes;
411 }
412
413 /* Make the dma buffer to read by dma */
414 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys,
415 tspi->dma_buf_size, DMA_TO_DEVICE);
416 }
417
tegra_spi_copy_spi_rxbuf_to_client_rxbuf(struct tegra_spi_data * tspi,struct spi_transfer * t)418 static void tegra_spi_copy_spi_rxbuf_to_client_rxbuf(
419 struct tegra_spi_data *tspi, struct spi_transfer *t)
420 {
421 /* Make the dma buffer to read by cpu */
422 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys,
423 tspi->dma_buf_size, DMA_FROM_DEVICE);
424
425 if (tspi->is_packed) {
426 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word;
427
428 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len);
429 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word;
430 } else {
431 unsigned int i;
432 unsigned int count;
433 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos;
434 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1;
435 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word;
436 unsigned int read_bytes;
437
438 if (consume > t->len - tspi->cur_pos)
439 consume = t->len - tspi->cur_pos;
440 read_bytes = consume;
441 for (count = 0; count < tspi->curr_dma_words; count++) {
442 u32 x = tspi->rx_dma_buf[count] & rx_mask;
443
444 for (i = 0; consume && (i < tspi->bytes_per_word);
445 i++, consume--)
446 *rx_buf++ = (x >> (i*8)) & 0xFF;
447 }
448
449 tspi->cur_rx_pos += read_bytes;
450 }
451
452 /* Make the dma buffer to read by dma */
453 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
454 tspi->dma_buf_size, DMA_FROM_DEVICE);
455 }
456
tegra_spi_dma_complete(void * args)457 static void tegra_spi_dma_complete(void *args)
458 {
459 struct completion *dma_complete = args;
460
461 complete(dma_complete);
462 }
463
tegra_spi_start_tx_dma(struct tegra_spi_data * tspi,int len)464 static int tegra_spi_start_tx_dma(struct tegra_spi_data *tspi, int len)
465 {
466 reinit_completion(&tspi->tx_dma_complete);
467 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan,
468 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV,
469 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
470 if (!tspi->tx_dma_desc) {
471 dev_err(tspi->dev, "Not able to get desc for Tx\n");
472 return -EIO;
473 }
474
475 tspi->tx_dma_desc->callback = tegra_spi_dma_complete;
476 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete;
477
478 dmaengine_submit(tspi->tx_dma_desc);
479 dma_async_issue_pending(tspi->tx_dma_chan);
480 return 0;
481 }
482
tegra_spi_start_rx_dma(struct tegra_spi_data * tspi,int len)483 static int tegra_spi_start_rx_dma(struct tegra_spi_data *tspi, int len)
484 {
485 reinit_completion(&tspi->rx_dma_complete);
486 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan,
487 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM,
488 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
489 if (!tspi->rx_dma_desc) {
490 dev_err(tspi->dev, "Not able to get desc for Rx\n");
491 return -EIO;
492 }
493
494 tspi->rx_dma_desc->callback = tegra_spi_dma_complete;
495 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete;
496
497 dmaengine_submit(tspi->rx_dma_desc);
498 dma_async_issue_pending(tspi->rx_dma_chan);
499 return 0;
500 }
501
tegra_spi_flush_fifos(struct tegra_spi_data * tspi)502 static int tegra_spi_flush_fifos(struct tegra_spi_data *tspi)
503 {
504 unsigned long timeout = jiffies + HZ;
505 u32 status;
506
507 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
508 if ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
509 status |= SPI_RX_FIFO_FLUSH | SPI_TX_FIFO_FLUSH;
510 tegra_spi_writel(tspi, status, SPI_FIFO_STATUS);
511 while ((status & SPI_FIFO_EMPTY) != SPI_FIFO_EMPTY) {
512 status = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
513 if (time_after(jiffies, timeout)) {
514 dev_err(tspi->dev,
515 "timeout waiting for fifo flush\n");
516 return -EIO;
517 }
518
519 udelay(1);
520 }
521 }
522
523 return 0;
524 }
525
tegra_spi_start_dma_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)526 static int tegra_spi_start_dma_based_transfer(
527 struct tegra_spi_data *tspi, struct spi_transfer *t)
528 {
529 u32 val;
530 unsigned int len;
531 int ret = 0;
532 u8 dma_burst;
533 struct dma_slave_config dma_sconfig = {0};
534
535 val = SPI_DMA_BLK_SET(tspi->curr_dma_words - 1);
536 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
537
538 if (tspi->is_packed)
539 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word,
540 4) * 4;
541 else
542 len = tspi->curr_dma_words * 4;
543
544 /* Set attention level based on length of transfer */
545 if (len & 0xF) {
546 val |= SPI_TX_TRIG_1 | SPI_RX_TRIG_1;
547 dma_burst = 1;
548 } else if (((len) >> 4) & 0x1) {
549 val |= SPI_TX_TRIG_4 | SPI_RX_TRIG_4;
550 dma_burst = 4;
551 } else {
552 val |= SPI_TX_TRIG_8 | SPI_RX_TRIG_8;
553 dma_burst = 8;
554 }
555
556 if (tspi->cur_direction & DATA_DIR_TX)
557 val |= SPI_IE_TX;
558
559 if (tspi->cur_direction & DATA_DIR_RX)
560 val |= SPI_IE_RX;
561
562 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
563 tspi->dma_control_reg = val;
564
565 dma_sconfig.device_fc = true;
566 if (tspi->cur_direction & DATA_DIR_TX) {
567 dma_sconfig.dst_addr = tspi->phys + SPI_TX_FIFO;
568 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
569 dma_sconfig.dst_maxburst = dma_burst;
570 ret = dmaengine_slave_config(tspi->tx_dma_chan, &dma_sconfig);
571 if (ret < 0) {
572 dev_err(tspi->dev,
573 "DMA slave config failed: %d\n", ret);
574 return ret;
575 }
576
577 tegra_spi_copy_client_txbuf_to_spi_txbuf(tspi, t);
578 ret = tegra_spi_start_tx_dma(tspi, len);
579 if (ret < 0) {
580 dev_err(tspi->dev,
581 "Starting tx dma failed, err %d\n", ret);
582 return ret;
583 }
584 }
585
586 if (tspi->cur_direction & DATA_DIR_RX) {
587 dma_sconfig.src_addr = tspi->phys + SPI_RX_FIFO;
588 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
589 dma_sconfig.src_maxburst = dma_burst;
590 ret = dmaengine_slave_config(tspi->rx_dma_chan, &dma_sconfig);
591 if (ret < 0) {
592 dev_err(tspi->dev,
593 "DMA slave config failed: %d\n", ret);
594 return ret;
595 }
596
597 /* Make the dma buffer to read by dma */
598 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys,
599 tspi->dma_buf_size, DMA_FROM_DEVICE);
600
601 ret = tegra_spi_start_rx_dma(tspi, len);
602 if (ret < 0) {
603 dev_err(tspi->dev,
604 "Starting rx dma failed, err %d\n", ret);
605 if (tspi->cur_direction & DATA_DIR_TX)
606 dmaengine_terminate_all(tspi->tx_dma_chan);
607 return ret;
608 }
609 }
610 tspi->is_curr_dma_xfer = true;
611 tspi->dma_control_reg = val;
612
613 val |= SPI_DMA_EN;
614 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
615 return ret;
616 }
617
tegra_spi_start_cpu_based_transfer(struct tegra_spi_data * tspi,struct spi_transfer * t)618 static int tegra_spi_start_cpu_based_transfer(
619 struct tegra_spi_data *tspi, struct spi_transfer *t)
620 {
621 u32 val;
622 unsigned cur_words;
623
624 if (tspi->cur_direction & DATA_DIR_TX)
625 cur_words = tegra_spi_fill_tx_fifo_from_client_txbuf(tspi, t);
626 else
627 cur_words = tspi->curr_dma_words;
628
629 val = SPI_DMA_BLK_SET(cur_words - 1);
630 tegra_spi_writel(tspi, val, SPI_DMA_BLK);
631
632 val = 0;
633 if (tspi->cur_direction & DATA_DIR_TX)
634 val |= SPI_IE_TX;
635
636 if (tspi->cur_direction & DATA_DIR_RX)
637 val |= SPI_IE_RX;
638
639 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
640 tspi->dma_control_reg = val;
641
642 tspi->is_curr_dma_xfer = false;
643
644 val |= SPI_DMA_EN;
645 tegra_spi_writel(tspi, val, SPI_DMA_CTL);
646 return 0;
647 }
648
tegra_spi_init_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)649 static int tegra_spi_init_dma_param(struct tegra_spi_data *tspi,
650 bool dma_to_memory)
651 {
652 struct dma_chan *dma_chan;
653 u32 *dma_buf;
654 dma_addr_t dma_phys;
655 int ret;
656
657 dma_chan = dma_request_slave_channel_reason(tspi->dev,
658 dma_to_memory ? "rx" : "tx");
659 if (IS_ERR(dma_chan)) {
660 ret = PTR_ERR(dma_chan);
661 if (ret != -EPROBE_DEFER)
662 dev_err(tspi->dev,
663 "Dma channel is not available: %d\n", ret);
664 return ret;
665 }
666
667 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size,
668 &dma_phys, GFP_KERNEL);
669 if (!dma_buf) {
670 dev_err(tspi->dev, " Not able to allocate the dma buffer\n");
671 dma_release_channel(dma_chan);
672 return -ENOMEM;
673 }
674
675 if (dma_to_memory) {
676 tspi->rx_dma_chan = dma_chan;
677 tspi->rx_dma_buf = dma_buf;
678 tspi->rx_dma_phys = dma_phys;
679 } else {
680 tspi->tx_dma_chan = dma_chan;
681 tspi->tx_dma_buf = dma_buf;
682 tspi->tx_dma_phys = dma_phys;
683 }
684 return 0;
685 }
686
tegra_spi_deinit_dma_param(struct tegra_spi_data * tspi,bool dma_to_memory)687 static void tegra_spi_deinit_dma_param(struct tegra_spi_data *tspi,
688 bool dma_to_memory)
689 {
690 u32 *dma_buf;
691 dma_addr_t dma_phys;
692 struct dma_chan *dma_chan;
693
694 if (dma_to_memory) {
695 dma_buf = tspi->rx_dma_buf;
696 dma_chan = tspi->rx_dma_chan;
697 dma_phys = tspi->rx_dma_phys;
698 tspi->rx_dma_chan = NULL;
699 tspi->rx_dma_buf = NULL;
700 } else {
701 dma_buf = tspi->tx_dma_buf;
702 dma_chan = tspi->tx_dma_chan;
703 dma_phys = tspi->tx_dma_phys;
704 tspi->tx_dma_buf = NULL;
705 tspi->tx_dma_chan = NULL;
706 }
707 if (!dma_chan)
708 return;
709
710 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys);
711 dma_release_channel(dma_chan);
712 }
713
tegra_spi_setup_transfer_one(struct spi_device * spi,struct spi_transfer * t,bool is_first_of_msg)714 static u32 tegra_spi_setup_transfer_one(struct spi_device *spi,
715 struct spi_transfer *t, bool is_first_of_msg)
716 {
717 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
718 u32 speed = t->speed_hz;
719 u8 bits_per_word = t->bits_per_word;
720 u32 command1;
721 int req_mode;
722
723 if (speed != tspi->cur_speed) {
724 clk_set_rate(tspi->clk, speed);
725 tspi->cur_speed = speed;
726 }
727
728 tspi->cur_spi = spi;
729 tspi->cur_pos = 0;
730 tspi->cur_rx_pos = 0;
731 tspi->cur_tx_pos = 0;
732 tspi->curr_xfer = t;
733
734 if (is_first_of_msg) {
735 tegra_spi_clear_status(tspi);
736
737 command1 = tspi->def_command1_reg;
738 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
739
740 command1 &= ~SPI_CONTROL_MODE_MASK;
741 req_mode = spi->mode & 0x3;
742 if (req_mode == SPI_MODE_0)
743 command1 |= SPI_CONTROL_MODE_0;
744 else if (req_mode == SPI_MODE_1)
745 command1 |= SPI_CONTROL_MODE_1;
746 else if (req_mode == SPI_MODE_2)
747 command1 |= SPI_CONTROL_MODE_2;
748 else if (req_mode == SPI_MODE_3)
749 command1 |= SPI_CONTROL_MODE_3;
750
751 if (tspi->cs_control) {
752 if (tspi->cs_control != spi)
753 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
754 tspi->cs_control = NULL;
755 } else
756 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
757
758 command1 |= SPI_CS_SW_HW;
759 if (spi->mode & SPI_CS_HIGH)
760 command1 |= SPI_CS_SW_VAL;
761 else
762 command1 &= ~SPI_CS_SW_VAL;
763
764 tegra_spi_writel(tspi, 0, SPI_COMMAND2);
765 } else {
766 command1 = tspi->command1_reg;
767 command1 &= ~SPI_BIT_LENGTH(~0);
768 command1 |= SPI_BIT_LENGTH(bits_per_word - 1);
769 }
770
771 return command1;
772 }
773
tegra_spi_start_transfer_one(struct spi_device * spi,struct spi_transfer * t,u32 command1)774 static int tegra_spi_start_transfer_one(struct spi_device *spi,
775 struct spi_transfer *t, u32 command1)
776 {
777 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
778 unsigned total_fifo_words;
779 int ret;
780
781 total_fifo_words = tegra_spi_calculate_curr_xfer_param(spi, tspi, t);
782
783 if (tspi->is_packed)
784 command1 |= SPI_PACKED;
785 else
786 command1 &= ~SPI_PACKED;
787
788 command1 &= ~(SPI_CS_SEL_MASK | SPI_TX_EN | SPI_RX_EN);
789 tspi->cur_direction = 0;
790 if (t->rx_buf) {
791 command1 |= SPI_RX_EN;
792 tspi->cur_direction |= DATA_DIR_RX;
793 }
794 if (t->tx_buf) {
795 command1 |= SPI_TX_EN;
796 tspi->cur_direction |= DATA_DIR_TX;
797 }
798 command1 |= SPI_CS_SEL(spi->chip_select);
799 tegra_spi_writel(tspi, command1, SPI_COMMAND1);
800 tspi->command1_reg = command1;
801
802 dev_dbg(tspi->dev, "The def 0x%x and written 0x%x\n",
803 tspi->def_command1_reg, (unsigned)command1);
804
805 ret = tegra_spi_flush_fifos(tspi);
806 if (ret < 0)
807 return ret;
808 if (total_fifo_words > SPI_FIFO_DEPTH)
809 ret = tegra_spi_start_dma_based_transfer(tspi, t);
810 else
811 ret = tegra_spi_start_cpu_based_transfer(tspi, t);
812 return ret;
813 }
814
tegra_spi_setup(struct spi_device * spi)815 static int tegra_spi_setup(struct spi_device *spi)
816 {
817 struct tegra_spi_data *tspi = spi_master_get_devdata(spi->master);
818 u32 val;
819 unsigned long flags;
820 int ret;
821
822 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n",
823 spi->bits_per_word,
824 spi->mode & SPI_CPOL ? "" : "~",
825 spi->mode & SPI_CPHA ? "" : "~",
826 spi->max_speed_hz);
827
828 ret = pm_runtime_get_sync(tspi->dev);
829 if (ret < 0) {
830 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret);
831 return ret;
832 }
833
834 spin_lock_irqsave(&tspi->lock, flags);
835 val = tspi->def_command1_reg;
836 if (spi->mode & SPI_CS_HIGH)
837 val &= ~SPI_CS_POL_INACTIVE(spi->chip_select);
838 else
839 val |= SPI_CS_POL_INACTIVE(spi->chip_select);
840 tspi->def_command1_reg = val;
841 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
842 spin_unlock_irqrestore(&tspi->lock, flags);
843
844 pm_runtime_put(tspi->dev);
845 return 0;
846 }
847
tegra_spi_transfer_delay(int delay)848 static void tegra_spi_transfer_delay(int delay)
849 {
850 if (!delay)
851 return;
852
853 if (delay >= 1000)
854 mdelay(delay / 1000);
855
856 udelay(delay % 1000);
857 }
858
tegra_spi_transfer_one_message(struct spi_master * master,struct spi_message * msg)859 static int tegra_spi_transfer_one_message(struct spi_master *master,
860 struct spi_message *msg)
861 {
862 bool is_first_msg = true;
863 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
864 struct spi_transfer *xfer;
865 struct spi_device *spi = msg->spi;
866 int ret;
867 bool skip = false;
868
869 msg->status = 0;
870 msg->actual_length = 0;
871
872 list_for_each_entry(xfer, &msg->transfers, transfer_list) {
873 u32 cmd1;
874
875 reinit_completion(&tspi->xfer_completion);
876
877 cmd1 = tegra_spi_setup_transfer_one(spi, xfer, is_first_msg);
878
879 if (!xfer->len) {
880 ret = 0;
881 skip = true;
882 goto complete_xfer;
883 }
884
885 ret = tegra_spi_start_transfer_one(spi, xfer, cmd1);
886 if (ret < 0) {
887 dev_err(tspi->dev,
888 "spi can not start transfer, err %d\n", ret);
889 goto complete_xfer;
890 }
891
892 is_first_msg = false;
893 ret = wait_for_completion_timeout(&tspi->xfer_completion,
894 SPI_DMA_TIMEOUT);
895 if (WARN_ON(ret == 0)) {
896 dev_err(tspi->dev,
897 "spi transfer timeout, err %d\n", ret);
898 if (tspi->is_curr_dma_xfer &&
899 (tspi->cur_direction & DATA_DIR_TX))
900 dmaengine_terminate_all(tspi->tx_dma_chan);
901 if (tspi->is_curr_dma_xfer &&
902 (tspi->cur_direction & DATA_DIR_RX))
903 dmaengine_terminate_all(tspi->rx_dma_chan);
904 ret = -EIO;
905 tegra_spi_flush_fifos(tspi);
906 reset_control_assert(tspi->rst);
907 udelay(2);
908 reset_control_deassert(tspi->rst);
909 goto complete_xfer;
910 }
911
912 if (tspi->tx_status || tspi->rx_status) {
913 dev_err(tspi->dev, "Error in Transfer\n");
914 ret = -EIO;
915 goto complete_xfer;
916 }
917 msg->actual_length += xfer->len;
918
919 complete_xfer:
920 if (ret < 0 || skip) {
921 tegra_spi_writel(tspi, tspi->def_command1_reg,
922 SPI_COMMAND1);
923 tegra_spi_transfer_delay(xfer->delay_usecs);
924 goto exit;
925 } else if (list_is_last(&xfer->transfer_list,
926 &msg->transfers)) {
927 if (xfer->cs_change)
928 tspi->cs_control = spi;
929 else {
930 tegra_spi_writel(tspi, tspi->def_command1_reg,
931 SPI_COMMAND1);
932 tegra_spi_transfer_delay(xfer->delay_usecs);
933 }
934 } else if (xfer->cs_change) {
935 tegra_spi_writel(tspi, tspi->def_command1_reg,
936 SPI_COMMAND1);
937 tegra_spi_transfer_delay(xfer->delay_usecs);
938 }
939
940 }
941 ret = 0;
942 exit:
943 msg->status = ret;
944 spi_finalize_current_message(master);
945 return ret;
946 }
947
handle_cpu_based_xfer(struct tegra_spi_data * tspi)948 static irqreturn_t handle_cpu_based_xfer(struct tegra_spi_data *tspi)
949 {
950 struct spi_transfer *t = tspi->curr_xfer;
951 unsigned long flags;
952
953 spin_lock_irqsave(&tspi->lock, flags);
954 if (tspi->tx_status || tspi->rx_status) {
955 dev_err(tspi->dev, "CpuXfer ERROR bit set 0x%x\n",
956 tspi->status_reg);
957 dev_err(tspi->dev, "CpuXfer 0x%08x:0x%08x\n",
958 tspi->command1_reg, tspi->dma_control_reg);
959 tegra_spi_flush_fifos(tspi);
960 reset_control_assert(tspi->rst);
961 udelay(2);
962 reset_control_deassert(tspi->rst);
963 complete(&tspi->xfer_completion);
964 goto exit;
965 }
966
967 if (tspi->cur_direction & DATA_DIR_RX)
968 tegra_spi_read_rx_fifo_to_client_rxbuf(tspi, t);
969
970 if (tspi->cur_direction & DATA_DIR_TX)
971 tspi->cur_pos = tspi->cur_tx_pos;
972 else
973 tspi->cur_pos = tspi->cur_rx_pos;
974
975 if (tspi->cur_pos == t->len) {
976 complete(&tspi->xfer_completion);
977 goto exit;
978 }
979
980 tegra_spi_calculate_curr_xfer_param(tspi->cur_spi, tspi, t);
981 tegra_spi_start_cpu_based_transfer(tspi, t);
982 exit:
983 spin_unlock_irqrestore(&tspi->lock, flags);
984 return IRQ_HANDLED;
985 }
986
handle_dma_based_xfer(struct tegra_spi_data * tspi)987 static irqreturn_t handle_dma_based_xfer(struct tegra_spi_data *tspi)
988 {
989 struct spi_transfer *t = tspi->curr_xfer;
990 long wait_status;
991 int err = 0;
992 unsigned total_fifo_words;
993 unsigned long flags;
994
995 /* Abort dmas if any error */
996 if (tspi->cur_direction & DATA_DIR_TX) {
997 if (tspi->tx_status) {
998 dmaengine_terminate_all(tspi->tx_dma_chan);
999 err += 1;
1000 } else {
1001 wait_status = wait_for_completion_interruptible_timeout(
1002 &tspi->tx_dma_complete, SPI_DMA_TIMEOUT);
1003 if (wait_status <= 0) {
1004 dmaengine_terminate_all(tspi->tx_dma_chan);
1005 dev_err(tspi->dev, "TxDma Xfer failed\n");
1006 err += 1;
1007 }
1008 }
1009 }
1010
1011 if (tspi->cur_direction & DATA_DIR_RX) {
1012 if (tspi->rx_status) {
1013 dmaengine_terminate_all(tspi->rx_dma_chan);
1014 err += 2;
1015 } else {
1016 wait_status = wait_for_completion_interruptible_timeout(
1017 &tspi->rx_dma_complete, SPI_DMA_TIMEOUT);
1018 if (wait_status <= 0) {
1019 dmaengine_terminate_all(tspi->rx_dma_chan);
1020 dev_err(tspi->dev, "RxDma Xfer failed\n");
1021 err += 2;
1022 }
1023 }
1024 }
1025
1026 spin_lock_irqsave(&tspi->lock, flags);
1027 if (err) {
1028 dev_err(tspi->dev, "DmaXfer: ERROR bit set 0x%x\n",
1029 tspi->status_reg);
1030 dev_err(tspi->dev, "DmaXfer 0x%08x:0x%08x\n",
1031 tspi->command1_reg, tspi->dma_control_reg);
1032 tegra_spi_flush_fifos(tspi);
1033 reset_control_assert(tspi->rst);
1034 udelay(2);
1035 reset_control_deassert(tspi->rst);
1036 complete(&tspi->xfer_completion);
1037 spin_unlock_irqrestore(&tspi->lock, flags);
1038 return IRQ_HANDLED;
1039 }
1040
1041 if (tspi->cur_direction & DATA_DIR_RX)
1042 tegra_spi_copy_spi_rxbuf_to_client_rxbuf(tspi, t);
1043
1044 if (tspi->cur_direction & DATA_DIR_TX)
1045 tspi->cur_pos = tspi->cur_tx_pos;
1046 else
1047 tspi->cur_pos = tspi->cur_rx_pos;
1048
1049 if (tspi->cur_pos == t->len) {
1050 complete(&tspi->xfer_completion);
1051 goto exit;
1052 }
1053
1054 /* Continue transfer in current message */
1055 total_fifo_words = tegra_spi_calculate_curr_xfer_param(tspi->cur_spi,
1056 tspi, t);
1057 if (total_fifo_words > SPI_FIFO_DEPTH)
1058 err = tegra_spi_start_dma_based_transfer(tspi, t);
1059 else
1060 err = tegra_spi_start_cpu_based_transfer(tspi, t);
1061
1062 exit:
1063 spin_unlock_irqrestore(&tspi->lock, flags);
1064 return IRQ_HANDLED;
1065 }
1066
tegra_spi_isr_thread(int irq,void * context_data)1067 static irqreturn_t tegra_spi_isr_thread(int irq, void *context_data)
1068 {
1069 struct tegra_spi_data *tspi = context_data;
1070
1071 if (!tspi->is_curr_dma_xfer)
1072 return handle_cpu_based_xfer(tspi);
1073 return handle_dma_based_xfer(tspi);
1074 }
1075
tegra_spi_isr(int irq,void * context_data)1076 static irqreturn_t tegra_spi_isr(int irq, void *context_data)
1077 {
1078 struct tegra_spi_data *tspi = context_data;
1079
1080 tspi->status_reg = tegra_spi_readl(tspi, SPI_FIFO_STATUS);
1081 if (tspi->cur_direction & DATA_DIR_TX)
1082 tspi->tx_status = tspi->status_reg &
1083 (SPI_TX_FIFO_UNF | SPI_TX_FIFO_OVF);
1084
1085 if (tspi->cur_direction & DATA_DIR_RX)
1086 tspi->rx_status = tspi->status_reg &
1087 (SPI_RX_FIFO_OVF | SPI_RX_FIFO_UNF);
1088 tegra_spi_clear_status(tspi);
1089
1090 return IRQ_WAKE_THREAD;
1091 }
1092
1093 static const struct of_device_id tegra_spi_of_match[] = {
1094 { .compatible = "nvidia,tegra114-spi", },
1095 {}
1096 };
1097 MODULE_DEVICE_TABLE(of, tegra_spi_of_match);
1098
tegra_spi_probe(struct platform_device * pdev)1099 static int tegra_spi_probe(struct platform_device *pdev)
1100 {
1101 struct spi_master *master;
1102 struct tegra_spi_data *tspi;
1103 struct resource *r;
1104 int ret, spi_irq;
1105
1106 master = spi_alloc_master(&pdev->dev, sizeof(*tspi));
1107 if (!master) {
1108 dev_err(&pdev->dev, "master allocation failed\n");
1109 return -ENOMEM;
1110 }
1111 platform_set_drvdata(pdev, master);
1112 tspi = spi_master_get_devdata(master);
1113
1114 if (of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
1115 &master->max_speed_hz))
1116 master->max_speed_hz = 25000000; /* 25MHz */
1117
1118 /* the spi->mode bits understood by this driver: */
1119 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1120 master->setup = tegra_spi_setup;
1121 master->transfer_one_message = tegra_spi_transfer_one_message;
1122 master->num_chipselect = MAX_CHIP_SELECT;
1123 master->auto_runtime_pm = true;
1124
1125 tspi->master = master;
1126 tspi->dev = &pdev->dev;
1127 spin_lock_init(&tspi->lock);
1128
1129 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1130 tspi->base = devm_ioremap_resource(&pdev->dev, r);
1131 if (IS_ERR(tspi->base)) {
1132 ret = PTR_ERR(tspi->base);
1133 goto exit_free_master;
1134 }
1135 tspi->phys = r->start;
1136
1137 spi_irq = platform_get_irq(pdev, 0);
1138 tspi->irq = spi_irq;
1139
1140 tspi->clk = devm_clk_get(&pdev->dev, "spi");
1141 if (IS_ERR(tspi->clk)) {
1142 dev_err(&pdev->dev, "can not get clock\n");
1143 ret = PTR_ERR(tspi->clk);
1144 goto exit_free_master;
1145 }
1146
1147 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi");
1148 if (IS_ERR(tspi->rst)) {
1149 dev_err(&pdev->dev, "can not get reset\n");
1150 ret = PTR_ERR(tspi->rst);
1151 goto exit_free_master;
1152 }
1153
1154 tspi->max_buf_size = SPI_FIFO_DEPTH << 2;
1155 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN;
1156
1157 ret = tegra_spi_init_dma_param(tspi, true);
1158 if (ret < 0)
1159 goto exit_free_master;
1160 ret = tegra_spi_init_dma_param(tspi, false);
1161 if (ret < 0)
1162 goto exit_rx_dma_free;
1163 tspi->max_buf_size = tspi->dma_buf_size;
1164 init_completion(&tspi->tx_dma_complete);
1165 init_completion(&tspi->rx_dma_complete);
1166
1167 init_completion(&tspi->xfer_completion);
1168
1169 pm_runtime_enable(&pdev->dev);
1170 if (!pm_runtime_enabled(&pdev->dev)) {
1171 ret = tegra_spi_runtime_resume(&pdev->dev);
1172 if (ret)
1173 goto exit_pm_disable;
1174 }
1175
1176 ret = pm_runtime_get_sync(&pdev->dev);
1177 if (ret < 0) {
1178 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret);
1179 goto exit_pm_disable;
1180 }
1181
1182 reset_control_assert(tspi->rst);
1183 udelay(2);
1184 reset_control_deassert(tspi->rst);
1185 tspi->def_command1_reg = SPI_M_S;
1186 tegra_spi_writel(tspi, tspi->def_command1_reg, SPI_COMMAND1);
1187 pm_runtime_put(&pdev->dev);
1188 ret = request_threaded_irq(tspi->irq, tegra_spi_isr,
1189 tegra_spi_isr_thread, IRQF_ONESHOT,
1190 dev_name(&pdev->dev), tspi);
1191 if (ret < 0) {
1192 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n",
1193 tspi->irq);
1194 goto exit_pm_disable;
1195 }
1196
1197 master->dev.of_node = pdev->dev.of_node;
1198 ret = devm_spi_register_master(&pdev->dev, master);
1199 if (ret < 0) {
1200 dev_err(&pdev->dev, "can not register to master err %d\n", ret);
1201 goto exit_free_irq;
1202 }
1203 return ret;
1204
1205 exit_free_irq:
1206 free_irq(spi_irq, tspi);
1207 exit_pm_disable:
1208 pm_runtime_disable(&pdev->dev);
1209 if (!pm_runtime_status_suspended(&pdev->dev))
1210 tegra_spi_runtime_suspend(&pdev->dev);
1211 tegra_spi_deinit_dma_param(tspi, false);
1212 exit_rx_dma_free:
1213 tegra_spi_deinit_dma_param(tspi, true);
1214 exit_free_master:
1215 spi_master_put(master);
1216 return ret;
1217 }
1218
tegra_spi_remove(struct platform_device * pdev)1219 static int tegra_spi_remove(struct platform_device *pdev)
1220 {
1221 struct spi_master *master = platform_get_drvdata(pdev);
1222 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1223
1224 free_irq(tspi->irq, tspi);
1225
1226 if (tspi->tx_dma_chan)
1227 tegra_spi_deinit_dma_param(tspi, false);
1228
1229 if (tspi->rx_dma_chan)
1230 tegra_spi_deinit_dma_param(tspi, true);
1231
1232 pm_runtime_disable(&pdev->dev);
1233 if (!pm_runtime_status_suspended(&pdev->dev))
1234 tegra_spi_runtime_suspend(&pdev->dev);
1235
1236 return 0;
1237 }
1238
1239 #ifdef CONFIG_PM_SLEEP
tegra_spi_suspend(struct device * dev)1240 static int tegra_spi_suspend(struct device *dev)
1241 {
1242 struct spi_master *master = dev_get_drvdata(dev);
1243
1244 return spi_master_suspend(master);
1245 }
1246
tegra_spi_resume(struct device * dev)1247 static int tegra_spi_resume(struct device *dev)
1248 {
1249 struct spi_master *master = dev_get_drvdata(dev);
1250 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1251 int ret;
1252
1253 ret = pm_runtime_get_sync(dev);
1254 if (ret < 0) {
1255 dev_err(dev, "pm runtime failed, e = %d\n", ret);
1256 return ret;
1257 }
1258 tegra_spi_writel(tspi, tspi->command1_reg, SPI_COMMAND1);
1259 pm_runtime_put(dev);
1260
1261 return spi_master_resume(master);
1262 }
1263 #endif
1264
tegra_spi_runtime_suspend(struct device * dev)1265 static int tegra_spi_runtime_suspend(struct device *dev)
1266 {
1267 struct spi_master *master = dev_get_drvdata(dev);
1268 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1269
1270 /* Flush all write which are in PPSB queue by reading back */
1271 tegra_spi_readl(tspi, SPI_COMMAND1);
1272
1273 clk_disable_unprepare(tspi->clk);
1274 return 0;
1275 }
1276
tegra_spi_runtime_resume(struct device * dev)1277 static int tegra_spi_runtime_resume(struct device *dev)
1278 {
1279 struct spi_master *master = dev_get_drvdata(dev);
1280 struct tegra_spi_data *tspi = spi_master_get_devdata(master);
1281 int ret;
1282
1283 ret = clk_prepare_enable(tspi->clk);
1284 if (ret < 0) {
1285 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret);
1286 return ret;
1287 }
1288 return 0;
1289 }
1290
1291 static const struct dev_pm_ops tegra_spi_pm_ops = {
1292 SET_RUNTIME_PM_OPS(tegra_spi_runtime_suspend,
1293 tegra_spi_runtime_resume, NULL)
1294 SET_SYSTEM_SLEEP_PM_OPS(tegra_spi_suspend, tegra_spi_resume)
1295 };
1296 static struct platform_driver tegra_spi_driver = {
1297 .driver = {
1298 .name = "spi-tegra114",
1299 .pm = &tegra_spi_pm_ops,
1300 .of_match_table = tegra_spi_of_match,
1301 },
1302 .probe = tegra_spi_probe,
1303 .remove = tegra_spi_remove,
1304 };
1305 module_platform_driver(tegra_spi_driver);
1306
1307 MODULE_ALIAS("platform:spi-tegra114");
1308 MODULE_DESCRIPTION("NVIDIA Tegra114 SPI Controller Driver");
1309 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>");
1310 MODULE_LICENSE("GPL v2");
1311