1 /*
2 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver
3 * (master mode only)
4 *
5 * Copyright (C) 2009 - 2015 Xilinx, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/dma-mapping.h>
16 #include <linux/dmaengine.h>
17 #include <linux/interrupt.h>
18 #include <linux/io.h>
19 #include <linux/module.h>
20 #include <linux/of_irq.h>
21 #include <linux/of_address.h>
22 #include <linux/platform_device.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/spi/spi.h>
25 #include <linux/spinlock.h>
26 #include <linux/workqueue.h>
27
28 /* Generic QSPI register offsets */
29 #define GQSPI_CONFIG_OFST 0x00000100
30 #define GQSPI_ISR_OFST 0x00000104
31 #define GQSPI_IDR_OFST 0x0000010C
32 #define GQSPI_IER_OFST 0x00000108
33 #define GQSPI_IMASK_OFST 0x00000110
34 #define GQSPI_EN_OFST 0x00000114
35 #define GQSPI_TXD_OFST 0x0000011C
36 #define GQSPI_RXD_OFST 0x00000120
37 #define GQSPI_TX_THRESHOLD_OFST 0x00000128
38 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C
39 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138
40 #define GQSPI_GEN_FIFO_OFST 0x00000140
41 #define GQSPI_SEL_OFST 0x00000144
42 #define GQSPI_GF_THRESHOLD_OFST 0x00000150
43 #define GQSPI_FIFO_CTRL_OFST 0x0000014C
44 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C
45 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804
46 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808
47 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814
48 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818
49 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C
50 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820
51 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800
52 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828
53
54 /* GQSPI register bit masks */
55 #define GQSPI_SEL_MASK 0x00000001
56 #define GQSPI_EN_MASK 0x00000001
57 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020
58 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002
59 #define GQSPI_IDR_ALL_MASK 0x00000FBE
60 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000
61 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000
62 #define GQSPI_CFG_ENDIAN_MASK 0x04000000
63 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000
64 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000
65 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038
66 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004
67 #define GQSPI_CFG_CLK_POL_MASK 0x00000002
68 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000
69 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF
70 #define GQSPI_GENFIFO_DATA_XFER 0x00000100
71 #define GQSPI_GENFIFO_EXP 0x00000200
72 #define GQSPI_GENFIFO_MODE_SPI 0x00000400
73 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800
74 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00
75 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00
76 #define GQSPI_GENFIFO_CS_LOWER 0x00001000
77 #define GQSPI_GENFIFO_CS_UPPER 0x00002000
78 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000
79 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000
80 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000
81 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000
82 #define GQSPI_GENFIFO_TX 0x00010000
83 #define GQSPI_GENFIFO_RX 0x00020000
84 #define GQSPI_GENFIFO_STRIPE 0x00040000
85 #define GQSPI_GENFIFO_POLL 0x00080000
86 #define GQSPI_GENFIFO_EXP_START 0x00000100
87 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004
88 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002
89 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001
90 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800
91 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400
92 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200
93 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100
94 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080
95 #define GQSPI_ISR_RXFULL_MASK 0x00000020
96 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010
97 #define GQSPI_ISR_TXFULL_MASK 0x00000008
98 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004
99 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002
100 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004
101 #define GQSPI_IER_RXEMPTY_MASK 0x00000800
102 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002
103 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010
104 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080
105 #define GQSPI_IER_TXEMPTY_MASK 0x00000100
106 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE
107 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000
108 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000
109 #define GQSPI_ISR_IDR_MASK 0x00000994
110 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002
111 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002
112 #define GQSPI_IRQ_MASK 0x00000980
113
114 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3
115 #define GQSPI_GENFIFO_CS_SETUP 0x4
116 #define GQSPI_GENFIFO_CS_HOLD 0x3
117 #define GQSPI_TXD_DEPTH 64
118 #define GQSPI_RX_FIFO_THRESHOLD 32
119 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4)
120 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32
121 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\
122 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL)
123 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10
124 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00
125 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1
126 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2
127 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3
128 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1
129 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2
130 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3
131 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
132 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */
133 #define GQSPI_SELECT_MODE_SPI 0x1
134 #define GQSPI_SELECT_MODE_DUALSPI 0x2
135 #define GQSPI_SELECT_MODE_QUADSPI 0x4
136 #define GQSPI_DMA_UNALIGN 0x3
137 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */
138
139 #define SPI_AUTOSUSPEND_TIMEOUT 3000
140 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA};
141
142 /**
143 * struct zynqmp_qspi - Defines qspi driver instance
144 * @regs: Virtual address of the QSPI controller registers
145 * @refclk: Pointer to the peripheral clock
146 * @pclk: Pointer to the APB clock
147 * @irq: IRQ number
148 * @dev: Pointer to struct device
149 * @txbuf: Pointer to the TX buffer
150 * @rxbuf: Pointer to the RX buffer
151 * @bytes_to_transfer: Number of bytes left to transfer
152 * @bytes_to_receive: Number of bytes left to receive
153 * @genfifocs: Used for chip select
154 * @genfifobus: Used to select the upper or lower bus
155 * @dma_rx_bytes: Remaining bytes to receive by DMA mode
156 * @dma_addr: DMA address after mapping the kernel buffer
157 * @genfifoentry: Used for storing the genfifoentry instruction.
158 * @mode: Defines the mode in which QSPI is operating
159 */
160 struct zynqmp_qspi {
161 void __iomem *regs;
162 struct clk *refclk;
163 struct clk *pclk;
164 int irq;
165 struct device *dev;
166 const void *txbuf;
167 void *rxbuf;
168 int bytes_to_transfer;
169 int bytes_to_receive;
170 u32 genfifocs;
171 u32 genfifobus;
172 u32 dma_rx_bytes;
173 dma_addr_t dma_addr;
174 u32 genfifoentry;
175 enum mode_type mode;
176 };
177
178 /**
179 * zynqmp_gqspi_read: For GQSPI controller read operation
180 * @xqspi: Pointer to the zynqmp_qspi structure
181 * @offset: Offset from where to read
182 */
zynqmp_gqspi_read(struct zynqmp_qspi * xqspi,u32 offset)183 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset)
184 {
185 return readl_relaxed(xqspi->regs + offset);
186 }
187
188 /**
189 * zynqmp_gqspi_write: For GQSPI controller write operation
190 * @xqspi: Pointer to the zynqmp_qspi structure
191 * @offset: Offset where to write
192 * @val: Value to be written
193 */
zynqmp_gqspi_write(struct zynqmp_qspi * xqspi,u32 offset,u32 val)194 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset,
195 u32 val)
196 {
197 writel_relaxed(val, (xqspi->regs + offset));
198 }
199
200 /**
201 * zynqmp_gqspi_selectslave: For selection of slave device
202 * @instanceptr: Pointer to the zynqmp_qspi structure
203 * @flashcs: For chip select
204 * @flashbus: To check which bus is selected- upper or lower
205 */
zynqmp_gqspi_selectslave(struct zynqmp_qspi * instanceptr,u8 slavecs,u8 slavebus)206 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr,
207 u8 slavecs, u8 slavebus)
208 {
209 /*
210 * Bus and CS lines selected here will be updated in the instance and
211 * used for subsequent GENFIFO entries during transfer.
212 */
213
214 /* Choose slave select line */
215 switch (slavecs) {
216 case GQSPI_SELECT_FLASH_CS_BOTH:
217 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER |
218 GQSPI_GENFIFO_CS_UPPER;
219 break;
220 case GQSPI_SELECT_FLASH_CS_UPPER:
221 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER;
222 break;
223 case GQSPI_SELECT_FLASH_CS_LOWER:
224 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER;
225 break;
226 default:
227 dev_warn(instanceptr->dev, "Invalid slave select\n");
228 }
229
230 /* Choose the bus */
231 switch (slavebus) {
232 case GQSPI_SELECT_FLASH_BUS_BOTH:
233 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER |
234 GQSPI_GENFIFO_BUS_UPPER;
235 break;
236 case GQSPI_SELECT_FLASH_BUS_UPPER:
237 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER;
238 break;
239 case GQSPI_SELECT_FLASH_BUS_LOWER:
240 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER;
241 break;
242 default:
243 dev_warn(instanceptr->dev, "Invalid slave bus\n");
244 }
245 }
246
247 /**
248 * zynqmp_qspi_init_hw: Initialize the hardware
249 * @xqspi: Pointer to the zynqmp_qspi structure
250 *
251 * The default settings of the QSPI controller's configurable parameters on
252 * reset are
253 * - Master mode
254 * - TX threshold set to 1
255 * - RX threshold set to 1
256 * - Flash memory interface mode enabled
257 * This function performs the following actions
258 * - Disable and clear all the interrupts
259 * - Enable manual slave select
260 * - Enable manual start
261 * - Deselect all the chip select lines
262 * - Set the little endian mode of TX FIFO and
263 * - Enable the QSPI controller
264 */
zynqmp_qspi_init_hw(struct zynqmp_qspi * xqspi)265 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi)
266 {
267 u32 config_reg;
268
269 /* Select the GQSPI mode */
270 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK);
271 /* Clear and disable interrupts */
272 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST,
273 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) |
274 GQSPI_ISR_WR_TO_CLR_MASK);
275 /* Clear the DMA STS */
276 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
277 zynqmp_gqspi_read(xqspi,
278 GQSPI_QSPIDMA_DST_I_STS_OFST));
279 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST,
280 zynqmp_gqspi_read(xqspi,
281 GQSPI_QSPIDMA_DST_STS_OFST) |
282 GQSPI_QSPIDMA_DST_STS_WTC);
283 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK);
284 zynqmp_gqspi_write(xqspi,
285 GQSPI_QSPIDMA_DST_I_DIS_OFST,
286 GQSPI_QSPIDMA_DST_INTR_ALL_MASK);
287 /* Disable the GQSPI */
288 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
289 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
290 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
291 /* Manual start */
292 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK;
293 /* Little endian by default */
294 config_reg &= ~GQSPI_CFG_ENDIAN_MASK;
295 /* Disable poll time out */
296 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK;
297 /* Set hold bit */
298 config_reg |= GQSPI_CFG_WP_HOLD_MASK;
299 /* Clear pre-scalar by default */
300 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
301 /* CPHA 0 */
302 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK;
303 /* CPOL 0 */
304 config_reg &= ~GQSPI_CFG_CLK_POL_MASK;
305 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
306
307 /* Clear the TX and RX FIFO */
308 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST,
309 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK |
310 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK |
311 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK);
312 /* Set by default to allow for high frequencies */
313 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST,
314 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) |
315 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK);
316 /* Reset thresholds */
317 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST,
318 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL);
319 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST,
320 GQSPI_RX_FIFO_THRESHOLD);
321 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST,
322 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL);
323 zynqmp_gqspi_selectslave(xqspi,
324 GQSPI_SELECT_FLASH_CS_LOWER,
325 GQSPI_SELECT_FLASH_BUS_LOWER);
326 /* Initialize DMA */
327 zynqmp_gqspi_write(xqspi,
328 GQSPI_QSPIDMA_DST_CTRL_OFST,
329 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL);
330
331 /* Enable the GQSPI */
332 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
333 }
334
335 /**
336 * zynqmp_qspi_copy_read_data: Copy data to RX buffer
337 * @xqspi: Pointer to the zynqmp_qspi structure
338 * @data: The variable where data is stored
339 * @size: Number of bytes to be copied from data to RX buffer
340 */
zynqmp_qspi_copy_read_data(struct zynqmp_qspi * xqspi,ulong data,u8 size)341 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi,
342 ulong data, u8 size)
343 {
344 memcpy(xqspi->rxbuf, &data, size);
345 xqspi->rxbuf += size;
346 xqspi->bytes_to_receive -= size;
347 }
348
349 /**
350 * zynqmp_prepare_transfer_hardware: Prepares hardware for transfer.
351 * @master: Pointer to the spi_master structure which provides
352 * information about the controller.
353 *
354 * This function enables SPI master controller.
355 *
356 * Return: 0 on success; error value otherwise
357 */
zynqmp_prepare_transfer_hardware(struct spi_master * master)358 static int zynqmp_prepare_transfer_hardware(struct spi_master *master)
359 {
360 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
361
362 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK);
363 return 0;
364 }
365
366 /**
367 * zynqmp_unprepare_transfer_hardware: Relaxes hardware after transfer
368 * @master: Pointer to the spi_master structure which provides
369 * information about the controller.
370 *
371 * This function disables the SPI master controller.
372 *
373 * Return: Always 0
374 */
zynqmp_unprepare_transfer_hardware(struct spi_master * master)375 static int zynqmp_unprepare_transfer_hardware(struct spi_master *master)
376 {
377 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
378
379 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
380 return 0;
381 }
382
383 /**
384 * zynqmp_qspi_chipselect: Select or deselect the chip select line
385 * @qspi: Pointer to the spi_device structure
386 * @is_high: Select(0) or deselect (1) the chip select line
387 */
zynqmp_qspi_chipselect(struct spi_device * qspi,bool is_high)388 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high)
389 {
390 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
391 ulong timeout;
392 u32 genfifoentry = 0x0, statusreg;
393
394 genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
395 genfifoentry |= xqspi->genfifobus;
396
397 if (!is_high) {
398 genfifoentry |= xqspi->genfifocs;
399 genfifoentry |= GQSPI_GENFIFO_CS_SETUP;
400 } else {
401 genfifoentry |= GQSPI_GENFIFO_CS_HOLD;
402 }
403
404 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
405
406 /* Manually start the generic FIFO command */
407 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
408 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
409 GQSPI_CFG_START_GEN_FIFO_MASK);
410
411 timeout = jiffies + msecs_to_jiffies(1000);
412
413 /* Wait until the generic FIFO command is empty */
414 do {
415 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
416
417 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) &&
418 (statusreg & GQSPI_ISR_TXEMPTY_MASK))
419 break;
420 else
421 cpu_relax();
422 } while (!time_after_eq(jiffies, timeout));
423
424 if (time_after_eq(jiffies, timeout))
425 dev_err(xqspi->dev, "Chip select timed out\n");
426 }
427
428 /**
429 * zynqmp_qspi_setup_transfer: Configure QSPI controller for specified
430 * transfer
431 * @qspi: Pointer to the spi_device structure
432 * @transfer: Pointer to the spi_transfer structure which provides
433 * information about next transfer setup parameters
434 *
435 * Sets the operational mode of QSPI controller for the next QSPI transfer and
436 * sets the requested clock frequency.
437 *
438 * Return: Always 0
439 *
440 * Note:
441 * If the requested frequency is not an exact match with what can be
442 * obtained using the pre-scalar value, the driver sets the clock
443 * frequency which is lower than the requested frequency (maximum lower)
444 * for the transfer.
445 *
446 * If the requested frequency is higher or lower than that is supported
447 * by the QSPI controller the driver will set the highest or lowest
448 * frequency supported by controller.
449 */
zynqmp_qspi_setup_transfer(struct spi_device * qspi,struct spi_transfer * transfer)450 static int zynqmp_qspi_setup_transfer(struct spi_device *qspi,
451 struct spi_transfer *transfer)
452 {
453 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
454 ulong clk_rate;
455 u32 config_reg, req_hz, baud_rate_val = 0;
456
457 if (transfer)
458 req_hz = transfer->speed_hz;
459 else
460 req_hz = qspi->max_speed_hz;
461
462 /* Set the clock frequency */
463 /* If req_hz == 0, default to lowest speed */
464 clk_rate = clk_get_rate(xqspi->refclk);
465
466 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) &&
467 (clk_rate /
468 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > req_hz)
469 baud_rate_val++;
470
471 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
472
473 /* Set the QSPI clock phase and clock polarity */
474 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK);
475
476 if (qspi->mode & SPI_CPHA)
477 config_reg |= GQSPI_CFG_CLK_PHA_MASK;
478 if (qspi->mode & SPI_CPOL)
479 config_reg |= GQSPI_CFG_CLK_POL_MASK;
480
481 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK;
482 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT);
483 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
484 return 0;
485 }
486
487 /**
488 * zynqmp_qspi_setup: Configure the QSPI controller
489 * @qspi: Pointer to the spi_device structure
490 *
491 * Sets the operational mode of QSPI controller for the next QSPI transfer,
492 * baud rate and divisor value to setup the requested qspi clock.
493 *
494 * Return: 0 on success; error value otherwise.
495 */
zynqmp_qspi_setup(struct spi_device * qspi)496 static int zynqmp_qspi_setup(struct spi_device *qspi)
497 {
498 if (qspi->master->busy)
499 return -EBUSY;
500 return 0;
501 }
502
503 /**
504 * zynqmp_qspi_filltxfifo: Fills the TX FIFO as long as there is room in
505 * the FIFO or the bytes required to be
506 * transmitted.
507 * @xqspi: Pointer to the zynqmp_qspi structure
508 * @size: Number of bytes to be copied from TX buffer to TX FIFO
509 */
zynqmp_qspi_filltxfifo(struct zynqmp_qspi * xqspi,int size)510 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size)
511 {
512 u32 count = 0, intermediate;
513
514 while ((xqspi->bytes_to_transfer > 0) && (count < size)) {
515 memcpy(&intermediate, xqspi->txbuf, 4);
516 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate);
517
518 if (xqspi->bytes_to_transfer >= 4) {
519 xqspi->txbuf += 4;
520 xqspi->bytes_to_transfer -= 4;
521 } else {
522 xqspi->txbuf += xqspi->bytes_to_transfer;
523 xqspi->bytes_to_transfer = 0;
524 }
525 count++;
526 }
527 }
528
529 /**
530 * zynqmp_qspi_readrxfifo: Fills the RX FIFO as long as there is room in
531 * the FIFO.
532 * @xqspi: Pointer to the zynqmp_qspi structure
533 * @size: Number of bytes to be copied from RX buffer to RX FIFO
534 */
zynqmp_qspi_readrxfifo(struct zynqmp_qspi * xqspi,u32 size)535 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size)
536 {
537 ulong data;
538 int count = 0;
539
540 while ((count < size) && (xqspi->bytes_to_receive > 0)) {
541 if (xqspi->bytes_to_receive >= 4) {
542 (*(u32 *) xqspi->rxbuf) =
543 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
544 xqspi->rxbuf += 4;
545 xqspi->bytes_to_receive -= 4;
546 count += 4;
547 } else {
548 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST);
549 count += xqspi->bytes_to_receive;
550 zynqmp_qspi_copy_read_data(xqspi, data,
551 xqspi->bytes_to_receive);
552 xqspi->bytes_to_receive = 0;
553 }
554 }
555 }
556
557 /**
558 * zynqmp_process_dma_irq: Handler for DMA done interrupt of QSPI
559 * controller
560 * @xqspi: zynqmp_qspi instance pointer
561 *
562 * This function handles DMA interrupt only.
563 */
zynqmp_process_dma_irq(struct zynqmp_qspi * xqspi)564 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi)
565 {
566 u32 config_reg, genfifoentry;
567
568 dma_unmap_single(xqspi->dev, xqspi->dma_addr,
569 xqspi->dma_rx_bytes, DMA_FROM_DEVICE);
570 xqspi->rxbuf += xqspi->dma_rx_bytes;
571 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes;
572 xqspi->dma_rx_bytes = 0;
573
574 /* Disabling the DMA interrupts */
575 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST,
576 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
577
578 if (xqspi->bytes_to_receive > 0) {
579 /* Switch to IO mode,for remaining bytes to receive */
580 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
581 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
582 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
583
584 /* Initiate the transfer of remaining bytes */
585 genfifoentry = xqspi->genfifoentry;
586 genfifoentry |= xqspi->bytes_to_receive;
587 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
588
589 /* Dummy generic FIFO entry */
590 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
591
592 /* Manual start */
593 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
594 (zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
595 GQSPI_CFG_START_GEN_FIFO_MASK));
596
597 /* Enable the RX interrupts for IO mode */
598 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
599 GQSPI_IER_GENFIFOEMPTY_MASK |
600 GQSPI_IER_RXNEMPTY_MASK |
601 GQSPI_IER_RXEMPTY_MASK);
602 }
603 }
604
605 /**
606 * zynqmp_qspi_irq: Interrupt service routine of the QSPI controller
607 * @irq: IRQ number
608 * @dev_id: Pointer to the xqspi structure
609 *
610 * This function handles TX empty only.
611 * On TX empty interrupt this function reads the received data from RX FIFO
612 * and fills the TX FIFO if there is any data remaining to be transferred.
613 *
614 * Return: IRQ_HANDLED when interrupt is handled
615 * IRQ_NONE otherwise.
616 */
zynqmp_qspi_irq(int irq,void * dev_id)617 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id)
618 {
619 struct spi_master *master = dev_id;
620 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
621 int ret = IRQ_NONE;
622 u32 status, mask, dma_status = 0;
623
624 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST);
625 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status);
626 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST)));
627
628 /* Read and clear DMA status */
629 if (xqspi->mode == GQSPI_MODE_DMA) {
630 dma_status =
631 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST);
632 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST,
633 dma_status);
634 }
635
636 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) {
637 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL);
638 ret = IRQ_HANDLED;
639 }
640
641 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) {
642 zynqmp_process_dma_irq(xqspi);
643 ret = IRQ_HANDLED;
644 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) &&
645 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) {
646 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL);
647 ret = IRQ_HANDLED;
648 }
649
650 if ((xqspi->bytes_to_receive == 0) && (xqspi->bytes_to_transfer == 0)
651 && ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) {
652 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK);
653 spi_finalize_current_transfer(master);
654 ret = IRQ_HANDLED;
655 }
656 return ret;
657 }
658
659 /**
660 * zynqmp_qspi_selectspimode: Selects SPI mode - x1 or x2 or x4.
661 * @xqspi: xqspi is a pointer to the GQSPI instance
662 * @spimode: spimode - SPI or DUAL or QUAD.
663 * Return: Mask to set desired SPI mode in GENFIFO entry.
664 */
zynqmp_qspi_selectspimode(struct zynqmp_qspi * xqspi,u8 spimode)665 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi,
666 u8 spimode)
667 {
668 u32 mask = 0;
669
670 switch (spimode) {
671 case GQSPI_SELECT_MODE_DUALSPI:
672 mask = GQSPI_GENFIFO_MODE_DUALSPI;
673 break;
674 case GQSPI_SELECT_MODE_QUADSPI:
675 mask = GQSPI_GENFIFO_MODE_QUADSPI;
676 break;
677 case GQSPI_SELECT_MODE_SPI:
678 mask = GQSPI_GENFIFO_MODE_SPI;
679 break;
680 default:
681 dev_warn(xqspi->dev, "Invalid SPI mode\n");
682 }
683
684 return mask;
685 }
686
687 /**
688 * zynq_qspi_setuprxdma: This function sets up the RX DMA operation
689 * @xqspi: xqspi is a pointer to the GQSPI instance.
690 */
zynq_qspi_setuprxdma(struct zynqmp_qspi * xqspi)691 static void zynq_qspi_setuprxdma(struct zynqmp_qspi *xqspi)
692 {
693 u32 rx_bytes, rx_rem, config_reg;
694 dma_addr_t addr;
695 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf;
696
697 if ((xqspi->bytes_to_receive < 8) ||
698 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) {
699 /* Setting to IO mode */
700 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
701 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
702 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
703 xqspi->mode = GQSPI_MODE_IO;
704 xqspi->dma_rx_bytes = 0;
705 return;
706 }
707
708 rx_rem = xqspi->bytes_to_receive % 4;
709 rx_bytes = (xqspi->bytes_to_receive - rx_rem);
710
711 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf,
712 rx_bytes, DMA_FROM_DEVICE);
713 if (dma_mapping_error(xqspi->dev, addr))
714 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n");
715
716 xqspi->dma_rx_bytes = rx_bytes;
717 xqspi->dma_addr = addr;
718 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST,
719 (u32)(addr & 0xffffffff));
720 addr = ((addr >> 16) >> 16);
721 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST,
722 ((u32)addr) & 0xfff);
723
724 /* Enabling the DMA mode */
725 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST);
726 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
727 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK;
728 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg);
729
730 /* Switch to DMA mode */
731 xqspi->mode = GQSPI_MODE_DMA;
732
733 /* Write the number of bytes to transfer */
734 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes);
735 }
736
737 /**
738 * zynqmp_qspi_txrxsetup: This function checks the TX/RX buffers in
739 * the transfer and sets up the GENFIFO entries,
740 * TX FIFO as required.
741 * @xqspi: xqspi is a pointer to the GQSPI instance.
742 * @transfer: It is a pointer to the structure containing transfer data.
743 * @genfifoentry: genfifoentry is pointer to the variable in which
744 * GENFIFO mask is returned to calling function
745 */
zynqmp_qspi_txrxsetup(struct zynqmp_qspi * xqspi,struct spi_transfer * transfer,u32 * genfifoentry)746 static void zynqmp_qspi_txrxsetup(struct zynqmp_qspi *xqspi,
747 struct spi_transfer *transfer,
748 u32 *genfifoentry)
749 {
750 u32 config_reg;
751
752 /* Transmit */
753 if ((xqspi->txbuf != NULL) && (xqspi->rxbuf == NULL)) {
754 /* Setup data to be TXed */
755 *genfifoentry &= ~GQSPI_GENFIFO_RX;
756 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
757 *genfifoentry |= GQSPI_GENFIFO_TX;
758 *genfifoentry |=
759 zynqmp_qspi_selectspimode(xqspi, transfer->tx_nbits);
760 xqspi->bytes_to_transfer = transfer->len;
761 if (xqspi->mode == GQSPI_MODE_DMA) {
762 config_reg = zynqmp_gqspi_read(xqspi,
763 GQSPI_CONFIG_OFST);
764 config_reg &= ~GQSPI_CFG_MODE_EN_MASK;
765 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
766 config_reg);
767 xqspi->mode = GQSPI_MODE_IO;
768 }
769 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH);
770 /* Discard RX data */
771 xqspi->bytes_to_receive = 0;
772 } else if ((xqspi->txbuf == NULL) && (xqspi->rxbuf != NULL)) {
773 /* Receive */
774
775 /* TX auto fill */
776 *genfifoentry &= ~GQSPI_GENFIFO_TX;
777 /* Setup RX */
778 *genfifoentry |= GQSPI_GENFIFO_DATA_XFER;
779 *genfifoentry |= GQSPI_GENFIFO_RX;
780 *genfifoentry |=
781 zynqmp_qspi_selectspimode(xqspi, transfer->rx_nbits);
782 xqspi->bytes_to_transfer = 0;
783 xqspi->bytes_to_receive = transfer->len;
784 zynq_qspi_setuprxdma(xqspi);
785 }
786 }
787
788 /**
789 * zynqmp_qspi_start_transfer: Initiates the QSPI transfer
790 * @master: Pointer to the spi_master structure which provides
791 * information about the controller.
792 * @qspi: Pointer to the spi_device structure
793 * @transfer: Pointer to the spi_transfer structure which provide information
794 * about next transfer parameters
795 *
796 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
797 * transfer to be completed.
798 *
799 * Return: Number of bytes transferred in the last transfer
800 */
zynqmp_qspi_start_transfer(struct spi_master * master,struct spi_device * qspi,struct spi_transfer * transfer)801 static int zynqmp_qspi_start_transfer(struct spi_master *master,
802 struct spi_device *qspi,
803 struct spi_transfer *transfer)
804 {
805 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
806 u32 genfifoentry = 0x0, transfer_len;
807
808 xqspi->txbuf = transfer->tx_buf;
809 xqspi->rxbuf = transfer->rx_buf;
810
811 zynqmp_qspi_setup_transfer(qspi, transfer);
812
813 genfifoentry |= xqspi->genfifocs;
814 genfifoentry |= xqspi->genfifobus;
815
816 zynqmp_qspi_txrxsetup(xqspi, transfer, &genfifoentry);
817
818 if (xqspi->mode == GQSPI_MODE_DMA)
819 transfer_len = xqspi->dma_rx_bytes;
820 else
821 transfer_len = transfer->len;
822
823 xqspi->genfifoentry = genfifoentry;
824 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) {
825 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
826 genfifoentry |= transfer_len;
827 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry);
828 } else {
829 int tempcount = transfer_len;
830 u32 exponent = 8; /* 2^8 = 256 */
831 u8 imm_data = tempcount & 0xFF;
832
833 tempcount &= ~(tempcount & 0xFF);
834 /* Immediate entry */
835 if (tempcount != 0) {
836 /* Exponent entries */
837 genfifoentry |= GQSPI_GENFIFO_EXP;
838 while (tempcount != 0) {
839 if (tempcount & GQSPI_GENFIFO_EXP_START) {
840 genfifoentry &=
841 ~GQSPI_GENFIFO_IMM_DATA_MASK;
842 genfifoentry |= exponent;
843 zynqmp_gqspi_write(xqspi,
844 GQSPI_GEN_FIFO_OFST,
845 genfifoentry);
846 }
847 tempcount = tempcount >> 1;
848 exponent++;
849 }
850 }
851 if (imm_data != 0) {
852 genfifoentry &= ~GQSPI_GENFIFO_EXP;
853 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK;
854 genfifoentry |= (u8) (imm_data & 0xFF);
855 zynqmp_gqspi_write(xqspi,
856 GQSPI_GEN_FIFO_OFST, genfifoentry);
857 }
858 }
859
860 if ((xqspi->mode == GQSPI_MODE_IO) &&
861 (xqspi->rxbuf != NULL)) {
862 /* Dummy generic FIFO entry */
863 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0);
864 }
865
866 /* Since we are using manual mode */
867 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST,
868 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) |
869 GQSPI_CFG_START_GEN_FIFO_MASK);
870
871 if (xqspi->txbuf != NULL)
872 /* Enable interrupts for TX */
873 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
874 GQSPI_IER_TXEMPTY_MASK |
875 GQSPI_IER_GENFIFOEMPTY_MASK |
876 GQSPI_IER_TXNOT_FULL_MASK);
877
878 if (xqspi->rxbuf != NULL) {
879 /* Enable interrupts for RX */
880 if (xqspi->mode == GQSPI_MODE_DMA) {
881 /* Enable DMA interrupts */
882 zynqmp_gqspi_write(xqspi,
883 GQSPI_QSPIDMA_DST_I_EN_OFST,
884 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK);
885 } else {
886 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST,
887 GQSPI_IER_GENFIFOEMPTY_MASK |
888 GQSPI_IER_RXNEMPTY_MASK |
889 GQSPI_IER_RXEMPTY_MASK);
890 }
891 }
892
893 return transfer->len;
894 }
895
896 /**
897 * zynqmp_qspi_suspend: Suspend method for the QSPI driver
898 * @_dev: Address of the platform_device structure
899 *
900 * This function stops the QSPI driver queue and disables the QSPI controller
901 *
902 * Return: Always 0
903 */
zynqmp_qspi_suspend(struct device * dev)904 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev)
905 {
906 struct spi_master *master = dev_get_drvdata(dev);
907
908 spi_master_suspend(master);
909
910 zynqmp_unprepare_transfer_hardware(master);
911
912 return 0;
913 }
914
915 /**
916 * zynqmp_qspi_resume: Resume method for the QSPI driver
917 * @dev: Address of the platform_device structure
918 *
919 * The function starts the QSPI driver queue and initializes the QSPI
920 * controller
921 *
922 * Return: 0 on success; error value otherwise
923 */
zynqmp_qspi_resume(struct device * dev)924 static int __maybe_unused zynqmp_qspi_resume(struct device *dev)
925 {
926 struct spi_master *master = dev_get_drvdata(dev);
927 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
928 int ret = 0;
929
930 ret = clk_enable(xqspi->pclk);
931 if (ret) {
932 dev_err(dev, "Cannot enable APB clock.\n");
933 return ret;
934 }
935
936 ret = clk_enable(xqspi->refclk);
937 if (ret) {
938 dev_err(dev, "Cannot enable device clock.\n");
939 clk_disable(xqspi->pclk);
940 return ret;
941 }
942
943 spi_master_resume(master);
944
945 clk_disable(xqspi->refclk);
946 clk_disable(xqspi->pclk);
947 return 0;
948 }
949
950 /**
951 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver
952 * @dev: Address of the platform_device structure
953 *
954 * This function disables the clocks
955 *
956 * Return: Always 0
957 */
zynqmp_runtime_suspend(struct device * dev)958 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev)
959 {
960 struct platform_device *pdev = to_platform_device(dev);
961 struct spi_master *master = platform_get_drvdata(pdev);
962 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
963
964 clk_disable(xqspi->refclk);
965 clk_disable(xqspi->pclk);
966
967 return 0;
968 }
969
970 /**
971 * zynqmp_runtime_resume - Runtime resume method for the SPI driver
972 * @dev: Address of the platform_device structure
973 *
974 * This function enables the clocks
975 *
976 * Return: 0 on success and error value on error
977 */
zynqmp_runtime_resume(struct device * dev)978 static int __maybe_unused zynqmp_runtime_resume(struct device *dev)
979 {
980 struct platform_device *pdev = to_platform_device(dev);
981 struct spi_master *master = platform_get_drvdata(pdev);
982 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
983 int ret;
984
985 ret = clk_enable(xqspi->pclk);
986 if (ret) {
987 dev_err(dev, "Cannot enable APB clock.\n");
988 return ret;
989 }
990
991 ret = clk_enable(xqspi->refclk);
992 if (ret) {
993 dev_err(dev, "Cannot enable device clock.\n");
994 clk_disable(xqspi->pclk);
995 return ret;
996 }
997
998 return 0;
999 }
1000
1001 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = {
1002 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend,
1003 zynqmp_runtime_resume, NULL)
1004 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume)
1005 };
1006
1007 /**
1008 * zynqmp_qspi_probe: Probe method for the QSPI driver
1009 * @pdev: Pointer to the platform_device structure
1010 *
1011 * This function initializes the driver data structures and the hardware.
1012 *
1013 * Return: 0 on success; error value otherwise
1014 */
zynqmp_qspi_probe(struct platform_device * pdev)1015 static int zynqmp_qspi_probe(struct platform_device *pdev)
1016 {
1017 int ret = 0;
1018 struct spi_master *master;
1019 struct zynqmp_qspi *xqspi;
1020 struct resource *res;
1021 struct device *dev = &pdev->dev;
1022
1023 master = spi_alloc_master(&pdev->dev, sizeof(*xqspi));
1024 if (!master)
1025 return -ENOMEM;
1026
1027 xqspi = spi_master_get_devdata(master);
1028 master->dev.of_node = pdev->dev.of_node;
1029 platform_set_drvdata(pdev, master);
1030
1031 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1032 xqspi->regs = devm_ioremap_resource(&pdev->dev, res);
1033 if (IS_ERR(xqspi->regs)) {
1034 ret = PTR_ERR(xqspi->regs);
1035 goto remove_master;
1036 }
1037
1038 xqspi->dev = dev;
1039 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk");
1040 if (IS_ERR(xqspi->pclk)) {
1041 dev_err(dev, "pclk clock not found.\n");
1042 ret = PTR_ERR(xqspi->pclk);
1043 goto remove_master;
1044 }
1045
1046 ret = clk_prepare_enable(xqspi->pclk);
1047 if (ret) {
1048 dev_err(dev, "Unable to enable APB clock.\n");
1049 goto remove_master;
1050 }
1051
1052 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk");
1053 if (IS_ERR(xqspi->refclk)) {
1054 dev_err(dev, "ref_clk clock not found.\n");
1055 ret = PTR_ERR(xqspi->refclk);
1056 goto clk_dis_pclk;
1057 }
1058
1059 ret = clk_prepare_enable(xqspi->refclk);
1060 if (ret) {
1061 dev_err(dev, "Unable to enable device clock.\n");
1062 goto clk_dis_pclk;
1063 }
1064
1065 pm_runtime_use_autosuspend(&pdev->dev);
1066 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT);
1067 pm_runtime_set_active(&pdev->dev);
1068 pm_runtime_enable(&pdev->dev);
1069 /* QSPI controller initializations */
1070 zynqmp_qspi_init_hw(xqspi);
1071
1072 pm_runtime_mark_last_busy(&pdev->dev);
1073 pm_runtime_put_autosuspend(&pdev->dev);
1074 xqspi->irq = platform_get_irq(pdev, 0);
1075 if (xqspi->irq <= 0) {
1076 ret = -ENXIO;
1077 dev_err(dev, "irq resource not found\n");
1078 goto clk_dis_all;
1079 }
1080 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq,
1081 0, pdev->name, master);
1082 if (ret != 0) {
1083 ret = -ENXIO;
1084 dev_err(dev, "request_irq failed\n");
1085 goto clk_dis_all;
1086 }
1087
1088 master->num_chipselect = GQSPI_DEFAULT_NUM_CS;
1089
1090 master->setup = zynqmp_qspi_setup;
1091 master->set_cs = zynqmp_qspi_chipselect;
1092 master->transfer_one = zynqmp_qspi_start_transfer;
1093 master->prepare_transfer_hardware = zynqmp_prepare_transfer_hardware;
1094 master->unprepare_transfer_hardware =
1095 zynqmp_unprepare_transfer_hardware;
1096 master->max_speed_hz = clk_get_rate(xqspi->refclk) / 2;
1097 master->bits_per_word_mask = SPI_BPW_MASK(8);
1098 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD |
1099 SPI_TX_DUAL | SPI_TX_QUAD;
1100
1101 if (master->dev.parent == NULL)
1102 master->dev.parent = &master->dev;
1103
1104 ret = spi_register_master(master);
1105 if (ret)
1106 goto clk_dis_all;
1107
1108 return 0;
1109
1110 clk_dis_all:
1111 pm_runtime_set_suspended(&pdev->dev);
1112 pm_runtime_disable(&pdev->dev);
1113 clk_disable_unprepare(xqspi->refclk);
1114 clk_dis_pclk:
1115 clk_disable_unprepare(xqspi->pclk);
1116 remove_master:
1117 spi_master_put(master);
1118
1119 return ret;
1120 }
1121
1122 /**
1123 * zynqmp_qspi_remove: Remove method for the QSPI driver
1124 * @pdev: Pointer to the platform_device structure
1125 *
1126 * This function is called if a device is physically removed from the system or
1127 * if the driver module is being unloaded. It frees all resources allocated to
1128 * the device.
1129 *
1130 * Return: 0 Always
1131 */
zynqmp_qspi_remove(struct platform_device * pdev)1132 static int zynqmp_qspi_remove(struct platform_device *pdev)
1133 {
1134 struct spi_master *master = platform_get_drvdata(pdev);
1135 struct zynqmp_qspi *xqspi = spi_master_get_devdata(master);
1136
1137 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0);
1138 clk_disable_unprepare(xqspi->refclk);
1139 clk_disable_unprepare(xqspi->pclk);
1140 pm_runtime_set_suspended(&pdev->dev);
1141 pm_runtime_disable(&pdev->dev);
1142
1143 spi_unregister_master(master);
1144
1145 return 0;
1146 }
1147
1148 static const struct of_device_id zynqmp_qspi_of_match[] = {
1149 { .compatible = "xlnx,zynqmp-qspi-1.0", },
1150 { /* End of table */ }
1151 };
1152
1153 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match);
1154
1155 static struct platform_driver zynqmp_qspi_driver = {
1156 .probe = zynqmp_qspi_probe,
1157 .remove = zynqmp_qspi_remove,
1158 .driver = {
1159 .name = "zynqmp-qspi",
1160 .of_match_table = zynqmp_qspi_of_match,
1161 .pm = &zynqmp_qspi_dev_pm_ops,
1162 },
1163 };
1164
1165 module_platform_driver(zynqmp_qspi_driver);
1166
1167 MODULE_AUTHOR("Xilinx, Inc.");
1168 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver");
1169 MODULE_LICENSE("GPL");
1170