1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Probe module for 8250/16550-type PCI serial ports.
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Copyright (C) 2001 Russell King, All Rights Reserved.
8 */
9 #undef DEBUG
10 #include <linux/module.h>
11 #include <linux/pci.h>
12 #include <linux/string.h>
13 #include <linux/kernel.h>
14 #include <linux/slab.h>
15 #include <linux/delay.h>
16 #include <linux/tty.h>
17 #include <linux/serial_reg.h>
18 #include <linux/serial_core.h>
19 #include <linux/8250_pci.h>
20 #include <linux/bitops.h>
21
22 #include <asm/byteorder.h>
23 #include <asm/io.h>
24
25 #include "8250.h"
26
27 /*
28 * init function returns:
29 * > 0 - number of ports
30 * = 0 - use board->num_ports
31 * < 0 - error
32 */
33 struct pci_serial_quirk {
34 u32 vendor;
35 u32 device;
36 u32 subvendor;
37 u32 subdevice;
38 int (*probe)(struct pci_dev *dev);
39 int (*init)(struct pci_dev *dev);
40 int (*setup)(struct serial_private *,
41 const struct pciserial_board *,
42 struct uart_8250_port *, int);
43 void (*exit)(struct pci_dev *dev);
44 };
45
46 #define PCI_NUM_BAR_RESOURCES 6
47
48 struct serial_private {
49 struct pci_dev *dev;
50 unsigned int nr;
51 struct pci_serial_quirk *quirk;
52 const struct pciserial_board *board;
53 int line[0];
54 };
55
56 static int pci_default_setup(struct serial_private*,
57 const struct pciserial_board*, struct uart_8250_port *, int);
58
moan_device(const char * str,struct pci_dev * dev)59 static void moan_device(const char *str, struct pci_dev *dev)
60 {
61 dev_err(&dev->dev,
62 "%s: %s\n"
63 "Please send the output of lspci -vv, this\n"
64 "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
65 "manufacturer and name of serial board or\n"
66 "modem board to <linux-serial@vger.kernel.org>.\n",
67 pci_name(dev), str, dev->vendor, dev->device,
68 dev->subsystem_vendor, dev->subsystem_device);
69 }
70
71 static int
setup_port(struct serial_private * priv,struct uart_8250_port * port,int bar,int offset,int regshift)72 setup_port(struct serial_private *priv, struct uart_8250_port *port,
73 int bar, int offset, int regshift)
74 {
75 struct pci_dev *dev = priv->dev;
76
77 if (bar >= PCI_NUM_BAR_RESOURCES)
78 return -EINVAL;
79
80 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
81 if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
82 return -ENOMEM;
83
84 port->port.iotype = UPIO_MEM;
85 port->port.iobase = 0;
86 port->port.mapbase = pci_resource_start(dev, bar) + offset;
87 port->port.membase = pcim_iomap_table(dev)[bar] + offset;
88 port->port.regshift = regshift;
89 } else {
90 port->port.iotype = UPIO_PORT;
91 port->port.iobase = pci_resource_start(dev, bar) + offset;
92 port->port.mapbase = 0;
93 port->port.membase = NULL;
94 port->port.regshift = 0;
95 }
96 return 0;
97 }
98
99 /*
100 * ADDI-DATA GmbH communication cards <info@addi-data.com>
101 */
addidata_apci7800_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)102 static int addidata_apci7800_setup(struct serial_private *priv,
103 const struct pciserial_board *board,
104 struct uart_8250_port *port, int idx)
105 {
106 unsigned int bar = 0, offset = board->first_offset;
107 bar = FL_GET_BASE(board->flags);
108
109 if (idx < 2) {
110 offset += idx * board->uart_offset;
111 } else if ((idx >= 2) && (idx < 4)) {
112 bar += 1;
113 offset += ((idx - 2) * board->uart_offset);
114 } else if ((idx >= 4) && (idx < 6)) {
115 bar += 2;
116 offset += ((idx - 4) * board->uart_offset);
117 } else if (idx >= 6) {
118 bar += 3;
119 offset += ((idx - 6) * board->uart_offset);
120 }
121
122 return setup_port(priv, port, bar, offset, board->reg_shift);
123 }
124
125 /*
126 * AFAVLAB uses a different mixture of BARs and offsets
127 * Not that ugly ;) -- HW
128 */
129 static int
afavlab_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)130 afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
131 struct uart_8250_port *port, int idx)
132 {
133 unsigned int bar, offset = board->first_offset;
134
135 bar = FL_GET_BASE(board->flags);
136 if (idx < 4)
137 bar += idx;
138 else {
139 bar = 4;
140 offset += (idx - 4) * board->uart_offset;
141 }
142
143 return setup_port(priv, port, bar, offset, board->reg_shift);
144 }
145
146 /*
147 * HP's Remote Management Console. The Diva chip came in several
148 * different versions. N-class, L2000 and A500 have two Diva chips, each
149 * with 3 UARTs (the third UART on the second chip is unused). Superdome
150 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
151 * one Diva chip, but it has been expanded to 5 UARTs.
152 */
pci_hp_diva_init(struct pci_dev * dev)153 static int pci_hp_diva_init(struct pci_dev *dev)
154 {
155 int rc = 0;
156
157 switch (dev->subsystem_device) {
158 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
159 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
160 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
161 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
162 rc = 3;
163 break;
164 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
165 rc = 2;
166 break;
167 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
168 rc = 4;
169 break;
170 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
171 case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
172 rc = 1;
173 break;
174 }
175
176 return rc;
177 }
178
179 /*
180 * HP's Diva chip puts the 4th/5th serial port further out, and
181 * some serial ports are supposed to be hidden on certain models.
182 */
183 static int
pci_hp_diva_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)184 pci_hp_diva_setup(struct serial_private *priv,
185 const struct pciserial_board *board,
186 struct uart_8250_port *port, int idx)
187 {
188 unsigned int offset = board->first_offset;
189 unsigned int bar = FL_GET_BASE(board->flags);
190
191 switch (priv->dev->subsystem_device) {
192 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
193 if (idx == 3)
194 idx++;
195 break;
196 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
197 if (idx > 0)
198 idx++;
199 if (idx > 2)
200 idx++;
201 break;
202 }
203 if (idx > 2)
204 offset = 0x18;
205
206 offset += idx * board->uart_offset;
207
208 return setup_port(priv, port, bar, offset, board->reg_shift);
209 }
210
211 /*
212 * Added for EKF Intel i960 serial boards
213 */
pci_inteli960ni_init(struct pci_dev * dev)214 static int pci_inteli960ni_init(struct pci_dev *dev)
215 {
216 u32 oldval;
217
218 if (!(dev->subsystem_device & 0x1000))
219 return -ENODEV;
220
221 /* is firmware started? */
222 pci_read_config_dword(dev, 0x44, &oldval);
223 if (oldval == 0x00001000L) { /* RESET value */
224 dev_dbg(&dev->dev, "Local i960 firmware missing\n");
225 return -ENODEV;
226 }
227 return 0;
228 }
229
230 /*
231 * Some PCI serial cards using the PLX 9050 PCI interface chip require
232 * that the card interrupt be explicitly enabled or disabled. This
233 * seems to be mainly needed on card using the PLX which also use I/O
234 * mapped memory.
235 */
pci_plx9050_init(struct pci_dev * dev)236 static int pci_plx9050_init(struct pci_dev *dev)
237 {
238 u8 irq_config;
239 void __iomem *p;
240
241 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
242 moan_device("no memory in bar 0", dev);
243 return 0;
244 }
245
246 irq_config = 0x41;
247 if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
248 dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
249 irq_config = 0x43;
250
251 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
252 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
253 /*
254 * As the megawolf cards have the int pins active
255 * high, and have 2 UART chips, both ints must be
256 * enabled on the 9050. Also, the UARTS are set in
257 * 16450 mode by default, so we have to enable the
258 * 16C950 'enhanced' mode so that we can use the
259 * deep FIFOs
260 */
261 irq_config = 0x5b;
262 /*
263 * enable/disable interrupts
264 */
265 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
266 if (p == NULL)
267 return -ENOMEM;
268 writel(irq_config, p + 0x4c);
269
270 /*
271 * Read the register back to ensure that it took effect.
272 */
273 readl(p + 0x4c);
274 iounmap(p);
275
276 return 0;
277 }
278
pci_plx9050_exit(struct pci_dev * dev)279 static void pci_plx9050_exit(struct pci_dev *dev)
280 {
281 u8 __iomem *p;
282
283 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
284 return;
285
286 /*
287 * disable interrupts
288 */
289 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
290 if (p != NULL) {
291 writel(0, p + 0x4c);
292
293 /*
294 * Read the register back to ensure that it took effect.
295 */
296 readl(p + 0x4c);
297 iounmap(p);
298 }
299 }
300
301 #define NI8420_INT_ENABLE_REG 0x38
302 #define NI8420_INT_ENABLE_BIT 0x2000
303
pci_ni8420_exit(struct pci_dev * dev)304 static void pci_ni8420_exit(struct pci_dev *dev)
305 {
306 void __iomem *p;
307 unsigned int bar = 0;
308
309 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
310 moan_device("no memory in bar", dev);
311 return;
312 }
313
314 p = pci_ioremap_bar(dev, bar);
315 if (p == NULL)
316 return;
317
318 /* Disable the CPU Interrupt */
319 writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
320 p + NI8420_INT_ENABLE_REG);
321 iounmap(p);
322 }
323
324
325 /* MITE registers */
326 #define MITE_IOWBSR1 0xc4
327 #define MITE_IOWCR1 0xf4
328 #define MITE_LCIMR1 0x08
329 #define MITE_LCIMR2 0x10
330
331 #define MITE_LCIMR2_CLR_CPU_IE (1 << 30)
332
pci_ni8430_exit(struct pci_dev * dev)333 static void pci_ni8430_exit(struct pci_dev *dev)
334 {
335 void __iomem *p;
336 unsigned int bar = 0;
337
338 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
339 moan_device("no memory in bar", dev);
340 return;
341 }
342
343 p = pci_ioremap_bar(dev, bar);
344 if (p == NULL)
345 return;
346
347 /* Disable the CPU Interrupt */
348 writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
349 iounmap(p);
350 }
351
352 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
353 static int
sbs_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)354 sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
355 struct uart_8250_port *port, int idx)
356 {
357 unsigned int bar, offset = board->first_offset;
358
359 bar = 0;
360
361 if (idx < 4) {
362 /* first four channels map to 0, 0x100, 0x200, 0x300 */
363 offset += idx * board->uart_offset;
364 } else if (idx < 8) {
365 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
366 offset += idx * board->uart_offset + 0xC00;
367 } else /* we have only 8 ports on PMC-OCTALPRO */
368 return 1;
369
370 return setup_port(priv, port, bar, offset, board->reg_shift);
371 }
372
373 /*
374 * This does initialization for PMC OCTALPRO cards:
375 * maps the device memory, resets the UARTs (needed, bc
376 * if the module is removed and inserted again, the card
377 * is in the sleep mode) and enables global interrupt.
378 */
379
380 /* global control register offset for SBS PMC-OctalPro */
381 #define OCT_REG_CR_OFF 0x500
382
sbs_init(struct pci_dev * dev)383 static int sbs_init(struct pci_dev *dev)
384 {
385 u8 __iomem *p;
386
387 p = pci_ioremap_bar(dev, 0);
388
389 if (p == NULL)
390 return -ENOMEM;
391 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
392 writeb(0x10, p + OCT_REG_CR_OFF);
393 udelay(50);
394 writeb(0x0, p + OCT_REG_CR_OFF);
395
396 /* Set bit-2 (INTENABLE) of Control Register */
397 writeb(0x4, p + OCT_REG_CR_OFF);
398 iounmap(p);
399
400 return 0;
401 }
402
403 /*
404 * Disables the global interrupt of PMC-OctalPro
405 */
406
sbs_exit(struct pci_dev * dev)407 static void sbs_exit(struct pci_dev *dev)
408 {
409 u8 __iomem *p;
410
411 p = pci_ioremap_bar(dev, 0);
412 /* FIXME: What if resource_len < OCT_REG_CR_OFF */
413 if (p != NULL)
414 writeb(0, p + OCT_REG_CR_OFF);
415 iounmap(p);
416 }
417
418 /*
419 * SIIG serial cards have an PCI interface chip which also controls
420 * the UART clocking frequency. Each UART can be clocked independently
421 * (except cards equipped with 4 UARTs) and initial clocking settings
422 * are stored in the EEPROM chip. It can cause problems because this
423 * version of serial driver doesn't support differently clocked UART's
424 * on single PCI card. To prevent this, initialization functions set
425 * high frequency clocking for all UART's on given card. It is safe (I
426 * hope) because it doesn't touch EEPROM settings to prevent conflicts
427 * with other OSes (like M$ DOS).
428 *
429 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
430 *
431 * There is two family of SIIG serial cards with different PCI
432 * interface chip and different configuration methods:
433 * - 10x cards have control registers in IO and/or memory space;
434 * - 20x cards have control registers in standard PCI configuration space.
435 *
436 * Note: all 10x cards have PCI device ids 0x10..
437 * all 20x cards have PCI device ids 0x20..
438 *
439 * There are also Quartet Serial cards which use Oxford Semiconductor
440 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
441 *
442 * Note: some SIIG cards are probed by the parport_serial object.
443 */
444
445 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
446 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
447
pci_siig10x_init(struct pci_dev * dev)448 static int pci_siig10x_init(struct pci_dev *dev)
449 {
450 u16 data;
451 void __iomem *p;
452
453 switch (dev->device & 0xfff8) {
454 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
455 data = 0xffdf;
456 break;
457 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
458 data = 0xf7ff;
459 break;
460 default: /* 1S1P, 4S */
461 data = 0xfffb;
462 break;
463 }
464
465 p = ioremap_nocache(pci_resource_start(dev, 0), 0x80);
466 if (p == NULL)
467 return -ENOMEM;
468
469 writew(readw(p + 0x28) & data, p + 0x28);
470 readw(p + 0x28);
471 iounmap(p);
472 return 0;
473 }
474
475 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
476 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
477
pci_siig20x_init(struct pci_dev * dev)478 static int pci_siig20x_init(struct pci_dev *dev)
479 {
480 u8 data;
481
482 /* Change clock frequency for the first UART. */
483 pci_read_config_byte(dev, 0x6f, &data);
484 pci_write_config_byte(dev, 0x6f, data & 0xef);
485
486 /* If this card has 2 UART, we have to do the same with second UART. */
487 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
488 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
489 pci_read_config_byte(dev, 0x73, &data);
490 pci_write_config_byte(dev, 0x73, data & 0xef);
491 }
492 return 0;
493 }
494
pci_siig_init(struct pci_dev * dev)495 static int pci_siig_init(struct pci_dev *dev)
496 {
497 unsigned int type = dev->device & 0xff00;
498
499 if (type == 0x1000)
500 return pci_siig10x_init(dev);
501 else if (type == 0x2000)
502 return pci_siig20x_init(dev);
503
504 moan_device("Unknown SIIG card", dev);
505 return -ENODEV;
506 }
507
pci_siig_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)508 static int pci_siig_setup(struct serial_private *priv,
509 const struct pciserial_board *board,
510 struct uart_8250_port *port, int idx)
511 {
512 unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
513
514 if (idx > 3) {
515 bar = 4;
516 offset = (idx - 4) * 8;
517 }
518
519 return setup_port(priv, port, bar, offset, 0);
520 }
521
522 /*
523 * Timedia has an explosion of boards, and to avoid the PCI table from
524 * growing *huge*, we use this function to collapse some 70 entries
525 * in the PCI table into one, for sanity's and compactness's sake.
526 */
527 static const unsigned short timedia_single_port[] = {
528 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
529 };
530
531 static const unsigned short timedia_dual_port[] = {
532 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
533 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
534 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
535 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
536 0xD079, 0
537 };
538
539 static const unsigned short timedia_quad_port[] = {
540 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
541 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
542 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
543 0xB157, 0
544 };
545
546 static const unsigned short timedia_eight_port[] = {
547 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
548 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
549 };
550
551 static const struct timedia_struct {
552 int num;
553 const unsigned short *ids;
554 } timedia_data[] = {
555 { 1, timedia_single_port },
556 { 2, timedia_dual_port },
557 { 4, timedia_quad_port },
558 { 8, timedia_eight_port }
559 };
560
561 /*
562 * There are nearly 70 different Timedia/SUNIX PCI serial devices. Instead of
563 * listing them individually, this driver merely grabs them all with
564 * PCI_ANY_ID. Some of these devices, however, also feature a parallel port,
565 * and should be left free to be claimed by parport_serial instead.
566 */
pci_timedia_probe(struct pci_dev * dev)567 static int pci_timedia_probe(struct pci_dev *dev)
568 {
569 /*
570 * Check the third digit of the subdevice ID
571 * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
572 */
573 if ((dev->subsystem_device & 0x00f0) >= 0x70) {
574 dev_info(&dev->dev,
575 "ignoring Timedia subdevice %04x for parport_serial\n",
576 dev->subsystem_device);
577 return -ENODEV;
578 }
579
580 return 0;
581 }
582
pci_timedia_init(struct pci_dev * dev)583 static int pci_timedia_init(struct pci_dev *dev)
584 {
585 const unsigned short *ids;
586 int i, j;
587
588 for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
589 ids = timedia_data[i].ids;
590 for (j = 0; ids[j]; j++)
591 if (dev->subsystem_device == ids[j])
592 return timedia_data[i].num;
593 }
594 return 0;
595 }
596
597 /*
598 * Timedia/SUNIX uses a mixture of BARs and offsets
599 * Ugh, this is ugly as all hell --- TYT
600 */
601 static int
pci_timedia_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)602 pci_timedia_setup(struct serial_private *priv,
603 const struct pciserial_board *board,
604 struct uart_8250_port *port, int idx)
605 {
606 unsigned int bar = 0, offset = board->first_offset;
607
608 switch (idx) {
609 case 0:
610 bar = 0;
611 break;
612 case 1:
613 offset = board->uart_offset;
614 bar = 0;
615 break;
616 case 2:
617 bar = 1;
618 break;
619 case 3:
620 offset = board->uart_offset;
621 /* FALLTHROUGH */
622 case 4: /* BAR 2 */
623 case 5: /* BAR 3 */
624 case 6: /* BAR 4 */
625 case 7: /* BAR 5 */
626 bar = idx - 2;
627 }
628
629 return setup_port(priv, port, bar, offset, board->reg_shift);
630 }
631
632 /*
633 * Some Titan cards are also a little weird
634 */
635 static int
titan_400l_800l_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)636 titan_400l_800l_setup(struct serial_private *priv,
637 const struct pciserial_board *board,
638 struct uart_8250_port *port, int idx)
639 {
640 unsigned int bar, offset = board->first_offset;
641
642 switch (idx) {
643 case 0:
644 bar = 1;
645 break;
646 case 1:
647 bar = 2;
648 break;
649 default:
650 bar = 4;
651 offset = (idx - 2) * board->uart_offset;
652 }
653
654 return setup_port(priv, port, bar, offset, board->reg_shift);
655 }
656
pci_xircom_init(struct pci_dev * dev)657 static int pci_xircom_init(struct pci_dev *dev)
658 {
659 msleep(100);
660 return 0;
661 }
662
pci_ni8420_init(struct pci_dev * dev)663 static int pci_ni8420_init(struct pci_dev *dev)
664 {
665 void __iomem *p;
666 unsigned int bar = 0;
667
668 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
669 moan_device("no memory in bar", dev);
670 return 0;
671 }
672
673 p = pci_ioremap_bar(dev, bar);
674 if (p == NULL)
675 return -ENOMEM;
676
677 /* Enable CPU Interrupt */
678 writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
679 p + NI8420_INT_ENABLE_REG);
680
681 iounmap(p);
682 return 0;
683 }
684
685 #define MITE_IOWBSR1_WSIZE 0xa
686 #define MITE_IOWBSR1_WIN_OFFSET 0x800
687 #define MITE_IOWBSR1_WENAB (1 << 7)
688 #define MITE_LCIMR1_IO_IE_0 (1 << 24)
689 #define MITE_LCIMR2_SET_CPU_IE (1 << 31)
690 #define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
691
pci_ni8430_init(struct pci_dev * dev)692 static int pci_ni8430_init(struct pci_dev *dev)
693 {
694 void __iomem *p;
695 struct pci_bus_region region;
696 u32 device_window;
697 unsigned int bar = 0;
698
699 if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
700 moan_device("no memory in bar", dev);
701 return 0;
702 }
703
704 p = pci_ioremap_bar(dev, bar);
705 if (p == NULL)
706 return -ENOMEM;
707
708 /*
709 * Set device window address and size in BAR0, while acknowledging that
710 * the resource structure may contain a translated address that differs
711 * from the address the device responds to.
712 */
713 pcibios_resource_to_bus(dev->bus, ®ion, &dev->resource[bar]);
714 device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
715 | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
716 writel(device_window, p + MITE_IOWBSR1);
717
718 /* Set window access to go to RAMSEL IO address space */
719 writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
720 p + MITE_IOWCR1);
721
722 /* Enable IO Bus Interrupt 0 */
723 writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
724
725 /* Enable CPU Interrupt */
726 writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
727
728 iounmap(p);
729 return 0;
730 }
731
732 /* UART Port Control Register */
733 #define NI8430_PORTCON 0x0f
734 #define NI8430_PORTCON_TXVR_ENABLE (1 << 3)
735
736 static int
pci_ni8430_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)737 pci_ni8430_setup(struct serial_private *priv,
738 const struct pciserial_board *board,
739 struct uart_8250_port *port, int idx)
740 {
741 struct pci_dev *dev = priv->dev;
742 void __iomem *p;
743 unsigned int bar, offset = board->first_offset;
744
745 if (idx >= board->num_ports)
746 return 1;
747
748 bar = FL_GET_BASE(board->flags);
749 offset += idx * board->uart_offset;
750
751 p = pci_ioremap_bar(dev, bar);
752 if (!p)
753 return -ENOMEM;
754
755 /* enable the transceiver */
756 writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
757 p + offset + NI8430_PORTCON);
758
759 iounmap(p);
760
761 return setup_port(priv, port, bar, offset, board->reg_shift);
762 }
763
pci_netmos_9900_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)764 static int pci_netmos_9900_setup(struct serial_private *priv,
765 const struct pciserial_board *board,
766 struct uart_8250_port *port, int idx)
767 {
768 unsigned int bar;
769
770 if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
771 (priv->dev->subsystem_device & 0xff00) == 0x3000) {
772 /* netmos apparently orders BARs by datasheet layout, so serial
773 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
774 */
775 bar = 3 * idx;
776
777 return setup_port(priv, port, bar, 0, board->reg_shift);
778 } else {
779 return pci_default_setup(priv, board, port, idx);
780 }
781 }
782
783 /* the 99xx series comes with a range of device IDs and a variety
784 * of capabilities:
785 *
786 * 9900 has varying capabilities and can cascade to sub-controllers
787 * (cascading should be purely internal)
788 * 9904 is hardwired with 4 serial ports
789 * 9912 and 9922 are hardwired with 2 serial ports
790 */
pci_netmos_9900_numports(struct pci_dev * dev)791 static int pci_netmos_9900_numports(struct pci_dev *dev)
792 {
793 unsigned int c = dev->class;
794 unsigned int pi;
795 unsigned short sub_serports;
796
797 pi = c & 0xff;
798
799 if (pi == 2)
800 return 1;
801
802 if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
803 /* two possibilities: 0x30ps encodes number of parallel and
804 * serial ports, or 0x1000 indicates *something*. This is not
805 * immediately obvious, since the 2s1p+4s configuration seems
806 * to offer all functionality on functions 0..2, while still
807 * advertising the same function 3 as the 4s+2s1p config.
808 */
809 sub_serports = dev->subsystem_device & 0xf;
810 if (sub_serports > 0)
811 return sub_serports;
812
813 dev_err(&dev->dev,
814 "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
815 return 0;
816 }
817
818 moan_device("unknown NetMos/Mostech program interface", dev);
819 return 0;
820 }
821
pci_netmos_init(struct pci_dev * dev)822 static int pci_netmos_init(struct pci_dev *dev)
823 {
824 /* subdevice 0x00PS means <P> parallel, <S> serial */
825 unsigned int num_serial = dev->subsystem_device & 0xf;
826
827 if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
828 (dev->device == PCI_DEVICE_ID_NETMOS_9865))
829 return 0;
830
831 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
832 dev->subsystem_device == 0x0299)
833 return 0;
834
835 switch (dev->device) { /* FALLTHROUGH on all */
836 case PCI_DEVICE_ID_NETMOS_9904:
837 case PCI_DEVICE_ID_NETMOS_9912:
838 case PCI_DEVICE_ID_NETMOS_9922:
839 case PCI_DEVICE_ID_NETMOS_9900:
840 num_serial = pci_netmos_9900_numports(dev);
841 break;
842
843 default:
844 break;
845 }
846
847 if (num_serial == 0) {
848 moan_device("unknown NetMos/Mostech device", dev);
849 return -ENODEV;
850 }
851
852 return num_serial;
853 }
854
855 /*
856 * These chips are available with optionally one parallel port and up to
857 * two serial ports. Unfortunately they all have the same product id.
858 *
859 * Basic configuration is done over a region of 32 I/O ports. The base
860 * ioport is called INTA or INTC, depending on docs/other drivers.
861 *
862 * The region of the 32 I/O ports is configured in POSIO0R...
863 */
864
865 /* registers */
866 #define ITE_887x_MISCR 0x9c
867 #define ITE_887x_INTCBAR 0x78
868 #define ITE_887x_UARTBAR 0x7c
869 #define ITE_887x_PS0BAR 0x10
870 #define ITE_887x_POSIO0 0x60
871
872 /* I/O space size */
873 #define ITE_887x_IOSIZE 32
874 /* I/O space size (bits 26-24; 8 bytes = 011b) */
875 #define ITE_887x_POSIO_IOSIZE_8 (3 << 24)
876 /* I/O space size (bits 26-24; 32 bytes = 101b) */
877 #define ITE_887x_POSIO_IOSIZE_32 (5 << 24)
878 /* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
879 #define ITE_887x_POSIO_SPEED (3 << 29)
880 /* enable IO_Space bit */
881 #define ITE_887x_POSIO_ENABLE (1 << 31)
882
pci_ite887x_init(struct pci_dev * dev)883 static int pci_ite887x_init(struct pci_dev *dev)
884 {
885 /* inta_addr are the configuration addresses of the ITE */
886 static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
887 0x200, 0x280, 0 };
888 int ret, i, type;
889 struct resource *iobase = NULL;
890 u32 miscr, uartbar, ioport;
891
892 /* search for the base-ioport */
893 i = 0;
894 while (inta_addr[i] && iobase == NULL) {
895 iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
896 "ite887x");
897 if (iobase != NULL) {
898 /* write POSIO0R - speed | size | ioport */
899 pci_write_config_dword(dev, ITE_887x_POSIO0,
900 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
901 ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
902 /* write INTCBAR - ioport */
903 pci_write_config_dword(dev, ITE_887x_INTCBAR,
904 inta_addr[i]);
905 ret = inb(inta_addr[i]);
906 if (ret != 0xff) {
907 /* ioport connected */
908 break;
909 }
910 release_region(iobase->start, ITE_887x_IOSIZE);
911 iobase = NULL;
912 }
913 i++;
914 }
915
916 if (!inta_addr[i]) {
917 dev_err(&dev->dev, "ite887x: could not find iobase\n");
918 return -ENODEV;
919 }
920
921 /* start of undocumented type checking (see parport_pc.c) */
922 type = inb(iobase->start + 0x18) & 0x0f;
923
924 switch (type) {
925 case 0x2: /* ITE8871 (1P) */
926 case 0xa: /* ITE8875 (1P) */
927 ret = 0;
928 break;
929 case 0xe: /* ITE8872 (2S1P) */
930 ret = 2;
931 break;
932 case 0x6: /* ITE8873 (1S) */
933 ret = 1;
934 break;
935 case 0x8: /* ITE8874 (2S) */
936 ret = 2;
937 break;
938 default:
939 moan_device("Unknown ITE887x", dev);
940 ret = -ENODEV;
941 }
942
943 /* configure all serial ports */
944 for (i = 0; i < ret; i++) {
945 /* read the I/O port from the device */
946 pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
947 &ioport);
948 ioport &= 0x0000FF00; /* the actual base address */
949 pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
950 ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
951 ITE_887x_POSIO_IOSIZE_8 | ioport);
952
953 /* write the ioport to the UARTBAR */
954 pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
955 uartbar &= ~(0xffff << (16 * i)); /* clear half the reg */
956 uartbar |= (ioport << (16 * i)); /* set the ioport */
957 pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
958
959 /* get current config */
960 pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
961 /* disable interrupts (UARTx_Routing[3:0]) */
962 miscr &= ~(0xf << (12 - 4 * i));
963 /* activate the UART (UARTx_En) */
964 miscr |= 1 << (23 - i);
965 /* write new config with activated UART */
966 pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
967 }
968
969 if (ret <= 0) {
970 /* the device has no UARTs if we get here */
971 release_region(iobase->start, ITE_887x_IOSIZE);
972 }
973
974 return ret;
975 }
976
pci_ite887x_exit(struct pci_dev * dev)977 static void pci_ite887x_exit(struct pci_dev *dev)
978 {
979 u32 ioport;
980 /* the ioport is bit 0-15 in POSIO0R */
981 pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
982 ioport &= 0xffff;
983 release_region(ioport, ITE_887x_IOSIZE);
984 }
985
986 /*
987 * EndRun Technologies.
988 * Determine the number of ports available on the device.
989 */
990 #define PCI_VENDOR_ID_ENDRUN 0x7401
991 #define PCI_DEVICE_ID_ENDRUN_1588 0xe100
992
pci_endrun_init(struct pci_dev * dev)993 static int pci_endrun_init(struct pci_dev *dev)
994 {
995 u8 __iomem *p;
996 unsigned long deviceID;
997 unsigned int number_uarts = 0;
998
999 /* EndRun device is all 0xexxx */
1000 if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1001 (dev->device & 0xf000) != 0xe000)
1002 return 0;
1003
1004 p = pci_iomap(dev, 0, 5);
1005 if (p == NULL)
1006 return -ENOMEM;
1007
1008 deviceID = ioread32(p);
1009 /* EndRun device */
1010 if (deviceID == 0x07000200) {
1011 number_uarts = ioread8(p + 4);
1012 dev_dbg(&dev->dev,
1013 "%d ports detected on EndRun PCI Express device\n",
1014 number_uarts);
1015 }
1016 pci_iounmap(dev, p);
1017 return number_uarts;
1018 }
1019
1020 /*
1021 * Oxford Semiconductor Inc.
1022 * Check that device is part of the Tornado range of devices, then determine
1023 * the number of ports available on the device.
1024 */
pci_oxsemi_tornado_init(struct pci_dev * dev)1025 static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1026 {
1027 u8 __iomem *p;
1028 unsigned long deviceID;
1029 unsigned int number_uarts = 0;
1030
1031 /* OxSemi Tornado devices are all 0xCxxx */
1032 if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1033 (dev->device & 0xF000) != 0xC000)
1034 return 0;
1035
1036 p = pci_iomap(dev, 0, 5);
1037 if (p == NULL)
1038 return -ENOMEM;
1039
1040 deviceID = ioread32(p);
1041 /* Tornado device */
1042 if (deviceID == 0x07000200) {
1043 number_uarts = ioread8(p + 4);
1044 dev_dbg(&dev->dev,
1045 "%d ports detected on Oxford PCI Express device\n",
1046 number_uarts);
1047 }
1048 pci_iounmap(dev, p);
1049 return number_uarts;
1050 }
1051
pci_asix_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1052 static int pci_asix_setup(struct serial_private *priv,
1053 const struct pciserial_board *board,
1054 struct uart_8250_port *port, int idx)
1055 {
1056 port->bugs |= UART_BUG_PARITY;
1057 return pci_default_setup(priv, board, port, idx);
1058 }
1059
1060 /* Quatech devices have their own extra interface features */
1061
1062 struct quatech_feature {
1063 u16 devid;
1064 bool amcc;
1065 };
1066
1067 #define QPCR_TEST_FOR1 0x3F
1068 #define QPCR_TEST_GET1 0x00
1069 #define QPCR_TEST_FOR2 0x40
1070 #define QPCR_TEST_GET2 0x40
1071 #define QPCR_TEST_FOR3 0x80
1072 #define QPCR_TEST_GET3 0x40
1073 #define QPCR_TEST_FOR4 0xC0
1074 #define QPCR_TEST_GET4 0x80
1075
1076 #define QOPR_CLOCK_X1 0x0000
1077 #define QOPR_CLOCK_X2 0x0001
1078 #define QOPR_CLOCK_X4 0x0002
1079 #define QOPR_CLOCK_X8 0x0003
1080 #define QOPR_CLOCK_RATE_MASK 0x0003
1081
1082
1083 static struct quatech_feature quatech_cards[] = {
1084 { PCI_DEVICE_ID_QUATECH_QSC100, 1 },
1085 { PCI_DEVICE_ID_QUATECH_DSC100, 1 },
1086 { PCI_DEVICE_ID_QUATECH_DSC100E, 0 },
1087 { PCI_DEVICE_ID_QUATECH_DSC200, 1 },
1088 { PCI_DEVICE_ID_QUATECH_DSC200E, 0 },
1089 { PCI_DEVICE_ID_QUATECH_ESC100D, 1 },
1090 { PCI_DEVICE_ID_QUATECH_ESC100M, 1 },
1091 { PCI_DEVICE_ID_QUATECH_QSCP100, 1 },
1092 { PCI_DEVICE_ID_QUATECH_DSCP100, 1 },
1093 { PCI_DEVICE_ID_QUATECH_QSCP200, 1 },
1094 { PCI_DEVICE_ID_QUATECH_DSCP200, 1 },
1095 { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1096 { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1097 { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1098 { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1099 { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1100 { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1101 { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1102 { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1103 { 0, }
1104 };
1105
pci_quatech_amcc(u16 devid)1106 static int pci_quatech_amcc(u16 devid)
1107 {
1108 struct quatech_feature *qf = &quatech_cards[0];
1109 while (qf->devid) {
1110 if (qf->devid == devid)
1111 return qf->amcc;
1112 qf++;
1113 }
1114 pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1115 return 0;
1116 };
1117
pci_quatech_rqopr(struct uart_8250_port * port)1118 static int pci_quatech_rqopr(struct uart_8250_port *port)
1119 {
1120 unsigned long base = port->port.iobase;
1121 u8 LCR, val;
1122
1123 LCR = inb(base + UART_LCR);
1124 outb(0xBF, base + UART_LCR);
1125 val = inb(base + UART_SCR);
1126 outb(LCR, base + UART_LCR);
1127 return val;
1128 }
1129
pci_quatech_wqopr(struct uart_8250_port * port,u8 qopr)1130 static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1131 {
1132 unsigned long base = port->port.iobase;
1133 u8 LCR;
1134
1135 LCR = inb(base + UART_LCR);
1136 outb(0xBF, base + UART_LCR);
1137 inb(base + UART_SCR);
1138 outb(qopr, base + UART_SCR);
1139 outb(LCR, base + UART_LCR);
1140 }
1141
pci_quatech_rqmcr(struct uart_8250_port * port)1142 static int pci_quatech_rqmcr(struct uart_8250_port *port)
1143 {
1144 unsigned long base = port->port.iobase;
1145 u8 LCR, val, qmcr;
1146
1147 LCR = inb(base + UART_LCR);
1148 outb(0xBF, base + UART_LCR);
1149 val = inb(base + UART_SCR);
1150 outb(val | 0x10, base + UART_SCR);
1151 qmcr = inb(base + UART_MCR);
1152 outb(val, base + UART_SCR);
1153 outb(LCR, base + UART_LCR);
1154
1155 return qmcr;
1156 }
1157
pci_quatech_wqmcr(struct uart_8250_port * port,u8 qmcr)1158 static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1159 {
1160 unsigned long base = port->port.iobase;
1161 u8 LCR, val;
1162
1163 LCR = inb(base + UART_LCR);
1164 outb(0xBF, base + UART_LCR);
1165 val = inb(base + UART_SCR);
1166 outb(val | 0x10, base + UART_SCR);
1167 outb(qmcr, base + UART_MCR);
1168 outb(val, base + UART_SCR);
1169 outb(LCR, base + UART_LCR);
1170 }
1171
pci_quatech_has_qmcr(struct uart_8250_port * port)1172 static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1173 {
1174 unsigned long base = port->port.iobase;
1175 u8 LCR, val;
1176
1177 LCR = inb(base + UART_LCR);
1178 outb(0xBF, base + UART_LCR);
1179 val = inb(base + UART_SCR);
1180 if (val & 0x20) {
1181 outb(0x80, UART_LCR);
1182 if (!(inb(UART_SCR) & 0x20)) {
1183 outb(LCR, base + UART_LCR);
1184 return 1;
1185 }
1186 }
1187 return 0;
1188 }
1189
pci_quatech_test(struct uart_8250_port * port)1190 static int pci_quatech_test(struct uart_8250_port *port)
1191 {
1192 u8 reg, qopr;
1193
1194 qopr = pci_quatech_rqopr(port);
1195 pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1196 reg = pci_quatech_rqopr(port) & 0xC0;
1197 if (reg != QPCR_TEST_GET1)
1198 return -EINVAL;
1199 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1200 reg = pci_quatech_rqopr(port) & 0xC0;
1201 if (reg != QPCR_TEST_GET2)
1202 return -EINVAL;
1203 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1204 reg = pci_quatech_rqopr(port) & 0xC0;
1205 if (reg != QPCR_TEST_GET3)
1206 return -EINVAL;
1207 pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1208 reg = pci_quatech_rqopr(port) & 0xC0;
1209 if (reg != QPCR_TEST_GET4)
1210 return -EINVAL;
1211
1212 pci_quatech_wqopr(port, qopr);
1213 return 0;
1214 }
1215
pci_quatech_clock(struct uart_8250_port * port)1216 static int pci_quatech_clock(struct uart_8250_port *port)
1217 {
1218 u8 qopr, reg, set;
1219 unsigned long clock;
1220
1221 if (pci_quatech_test(port) < 0)
1222 return 1843200;
1223
1224 qopr = pci_quatech_rqopr(port);
1225
1226 pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1227 reg = pci_quatech_rqopr(port);
1228 if (reg & QOPR_CLOCK_X8) {
1229 clock = 1843200;
1230 goto out;
1231 }
1232 pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1233 reg = pci_quatech_rqopr(port);
1234 if (!(reg & QOPR_CLOCK_X8)) {
1235 clock = 1843200;
1236 goto out;
1237 }
1238 reg &= QOPR_CLOCK_X8;
1239 if (reg == QOPR_CLOCK_X2) {
1240 clock = 3685400;
1241 set = QOPR_CLOCK_X2;
1242 } else if (reg == QOPR_CLOCK_X4) {
1243 clock = 7372800;
1244 set = QOPR_CLOCK_X4;
1245 } else if (reg == QOPR_CLOCK_X8) {
1246 clock = 14745600;
1247 set = QOPR_CLOCK_X8;
1248 } else {
1249 clock = 1843200;
1250 set = QOPR_CLOCK_X1;
1251 }
1252 qopr &= ~QOPR_CLOCK_RATE_MASK;
1253 qopr |= set;
1254
1255 out:
1256 pci_quatech_wqopr(port, qopr);
1257 return clock;
1258 }
1259
pci_quatech_rs422(struct uart_8250_port * port)1260 static int pci_quatech_rs422(struct uart_8250_port *port)
1261 {
1262 u8 qmcr;
1263 int rs422 = 0;
1264
1265 if (!pci_quatech_has_qmcr(port))
1266 return 0;
1267 qmcr = pci_quatech_rqmcr(port);
1268 pci_quatech_wqmcr(port, 0xFF);
1269 if (pci_quatech_rqmcr(port))
1270 rs422 = 1;
1271 pci_quatech_wqmcr(port, qmcr);
1272 return rs422;
1273 }
1274
pci_quatech_init(struct pci_dev * dev)1275 static int pci_quatech_init(struct pci_dev *dev)
1276 {
1277 if (pci_quatech_amcc(dev->device)) {
1278 unsigned long base = pci_resource_start(dev, 0);
1279 if (base) {
1280 u32 tmp;
1281
1282 outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1283 tmp = inl(base + 0x3c);
1284 outl(tmp | 0x01000000, base + 0x3c);
1285 outl(tmp &= ~0x01000000, base + 0x3c);
1286 }
1287 }
1288 return 0;
1289 }
1290
pci_quatech_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1291 static int pci_quatech_setup(struct serial_private *priv,
1292 const struct pciserial_board *board,
1293 struct uart_8250_port *port, int idx)
1294 {
1295 /* Needed by pci_quatech calls below */
1296 port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1297 /* Set up the clocking */
1298 port->port.uartclk = pci_quatech_clock(port);
1299 /* For now just warn about RS422 */
1300 if (pci_quatech_rs422(port))
1301 pr_warn("quatech: software control of RS422 features not currently supported.\n");
1302 return pci_default_setup(priv, board, port, idx);
1303 }
1304
pci_quatech_exit(struct pci_dev * dev)1305 static void pci_quatech_exit(struct pci_dev *dev)
1306 {
1307 }
1308
pci_default_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1309 static int pci_default_setup(struct serial_private *priv,
1310 const struct pciserial_board *board,
1311 struct uart_8250_port *port, int idx)
1312 {
1313 unsigned int bar, offset = board->first_offset, maxnr;
1314
1315 bar = FL_GET_BASE(board->flags);
1316 if (board->flags & FL_BASE_BARS)
1317 bar += idx;
1318 else
1319 offset += idx * board->uart_offset;
1320
1321 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1322 (board->reg_shift + 3);
1323
1324 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1325 return 1;
1326
1327 return setup_port(priv, port, bar, offset, board->reg_shift);
1328 }
1329
pci_pericom_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1330 static int pci_pericom_setup(struct serial_private *priv,
1331 const struct pciserial_board *board,
1332 struct uart_8250_port *port, int idx)
1333 {
1334 unsigned int bar, offset = board->first_offset, maxnr;
1335
1336 bar = FL_GET_BASE(board->flags);
1337 if (board->flags & FL_BASE_BARS)
1338 bar += idx;
1339 else
1340 offset += idx * board->uart_offset;
1341
1342 if (idx==3)
1343 offset = 0x38;
1344
1345 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1346 (board->reg_shift + 3);
1347
1348 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1349 return 1;
1350
1351 return setup_port(priv, port, bar, offset, board->reg_shift);
1352 }
1353
1354 static int
ce4100_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1355 ce4100_serial_setup(struct serial_private *priv,
1356 const struct pciserial_board *board,
1357 struct uart_8250_port *port, int idx)
1358 {
1359 int ret;
1360
1361 ret = setup_port(priv, port, idx, 0, board->reg_shift);
1362 port->port.iotype = UPIO_MEM32;
1363 port->port.type = PORT_XSCALE;
1364 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1365 port->port.regshift = 2;
1366
1367 return ret;
1368 }
1369
1370 static int
pci_omegapci_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1371 pci_omegapci_setup(struct serial_private *priv,
1372 const struct pciserial_board *board,
1373 struct uart_8250_port *port, int idx)
1374 {
1375 return setup_port(priv, port, 2, idx * 8, 0);
1376 }
1377
1378 static int
pci_brcm_trumanage_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1379 pci_brcm_trumanage_setup(struct serial_private *priv,
1380 const struct pciserial_board *board,
1381 struct uart_8250_port *port, int idx)
1382 {
1383 int ret = pci_default_setup(priv, board, port, idx);
1384
1385 port->port.type = PORT_BRCM_TRUMANAGE;
1386 port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1387 return ret;
1388 }
1389
1390 /* RTS will control by MCR if this bit is 0 */
1391 #define FINTEK_RTS_CONTROL_BY_HW BIT(4)
1392 /* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1393 #define FINTEK_RTS_INVERT BIT(5)
1394
1395 /* We should do proper H/W transceiver setting before change to RS485 mode */
pci_fintek_rs485_config(struct uart_port * port,struct serial_rs485 * rs485)1396 static int pci_fintek_rs485_config(struct uart_port *port,
1397 struct serial_rs485 *rs485)
1398 {
1399 struct pci_dev *pci_dev = to_pci_dev(port->dev);
1400 u8 setting;
1401 u8 *index = (u8 *) port->private_data;
1402
1403 pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1404
1405 if (!rs485)
1406 rs485 = &port->rs485;
1407 else if (rs485->flags & SER_RS485_ENABLED)
1408 memset(rs485->padding, 0, sizeof(rs485->padding));
1409 else
1410 memset(rs485, 0, sizeof(*rs485));
1411
1412 /* F81504/508/512 not support RTS delay before or after send */
1413 rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1414
1415 if (rs485->flags & SER_RS485_ENABLED) {
1416 /* Enable RTS H/W control mode */
1417 setting |= FINTEK_RTS_CONTROL_BY_HW;
1418
1419 if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1420 /* RTS driving high on TX */
1421 setting &= ~FINTEK_RTS_INVERT;
1422 } else {
1423 /* RTS driving low on TX */
1424 setting |= FINTEK_RTS_INVERT;
1425 }
1426
1427 rs485->delay_rts_after_send = 0;
1428 rs485->delay_rts_before_send = 0;
1429 } else {
1430 /* Disable RTS H/W control mode */
1431 setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1432 }
1433
1434 pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1435
1436 if (rs485 != &port->rs485)
1437 port->rs485 = *rs485;
1438
1439 return 0;
1440 }
1441
pci_fintek_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1442 static int pci_fintek_setup(struct serial_private *priv,
1443 const struct pciserial_board *board,
1444 struct uart_8250_port *port, int idx)
1445 {
1446 struct pci_dev *pdev = priv->dev;
1447 u8 *data;
1448 u8 config_base;
1449 u16 iobase;
1450
1451 config_base = 0x40 + 0x08 * idx;
1452
1453 /* Get the io address from configuration space */
1454 pci_read_config_word(pdev, config_base + 4, &iobase);
1455
1456 dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1457
1458 port->port.iotype = UPIO_PORT;
1459 port->port.iobase = iobase;
1460 port->port.rs485_config = pci_fintek_rs485_config;
1461
1462 data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1463 if (!data)
1464 return -ENOMEM;
1465
1466 /* preserve index in PCI configuration space */
1467 *data = idx;
1468 port->port.private_data = data;
1469
1470 return 0;
1471 }
1472
pci_fintek_init(struct pci_dev * dev)1473 static int pci_fintek_init(struct pci_dev *dev)
1474 {
1475 unsigned long iobase;
1476 u32 max_port, i;
1477 resource_size_t bar_data[3];
1478 u8 config_base;
1479 struct serial_private *priv = pci_get_drvdata(dev);
1480 struct uart_8250_port *port;
1481
1482 if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1483 !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1484 !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1485 return -ENODEV;
1486
1487 switch (dev->device) {
1488 case 0x1104: /* 4 ports */
1489 case 0x1108: /* 8 ports */
1490 max_port = dev->device & 0xff;
1491 break;
1492 case 0x1112: /* 12 ports */
1493 max_port = 12;
1494 break;
1495 default:
1496 return -EINVAL;
1497 }
1498
1499 /* Get the io address dispatch from the BIOS */
1500 bar_data[0] = pci_resource_start(dev, 5);
1501 bar_data[1] = pci_resource_start(dev, 4);
1502 bar_data[2] = pci_resource_start(dev, 3);
1503
1504 for (i = 0; i < max_port; ++i) {
1505 /* UART0 configuration offset start from 0x40 */
1506 config_base = 0x40 + 0x08 * i;
1507
1508 /* Calculate Real IO Port */
1509 iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1510
1511 /* Enable UART I/O port */
1512 pci_write_config_byte(dev, config_base + 0x00, 0x01);
1513
1514 /* Select 128-byte FIFO and 8x FIFO threshold */
1515 pci_write_config_byte(dev, config_base + 0x01, 0x33);
1516
1517 /* LSB UART */
1518 pci_write_config_byte(dev, config_base + 0x04,
1519 (u8)(iobase & 0xff));
1520
1521 /* MSB UART */
1522 pci_write_config_byte(dev, config_base + 0x05,
1523 (u8)((iobase & 0xff00) >> 8));
1524
1525 pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1526
1527 if (priv) {
1528 /* re-apply RS232/485 mode when
1529 * pciserial_resume_ports()
1530 */
1531 port = serial8250_get_port(priv->line[i]);
1532 pci_fintek_rs485_config(&port->port, NULL);
1533 } else {
1534 /* First init without port data
1535 * force init to RS232 Mode
1536 */
1537 pci_write_config_byte(dev, config_base + 0x07, 0x01);
1538 }
1539 }
1540
1541 return max_port;
1542 }
1543
skip_tx_en_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1544 static int skip_tx_en_setup(struct serial_private *priv,
1545 const struct pciserial_board *board,
1546 struct uart_8250_port *port, int idx)
1547 {
1548 port->port.quirks |= UPQ_NO_TXEN_TEST;
1549 dev_dbg(&priv->dev->dev,
1550 "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1551 priv->dev->vendor, priv->dev->device,
1552 priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1553
1554 return pci_default_setup(priv, board, port, idx);
1555 }
1556
kt_handle_break(struct uart_port * p)1557 static void kt_handle_break(struct uart_port *p)
1558 {
1559 struct uart_8250_port *up = up_to_u8250p(p);
1560 /*
1561 * On receipt of a BI, serial device in Intel ME (Intel
1562 * management engine) needs to have its fifos cleared for sane
1563 * SOL (Serial Over Lan) output.
1564 */
1565 serial8250_clear_and_reinit_fifos(up);
1566 }
1567
kt_serial_in(struct uart_port * p,int offset)1568 static unsigned int kt_serial_in(struct uart_port *p, int offset)
1569 {
1570 struct uart_8250_port *up = up_to_u8250p(p);
1571 unsigned int val;
1572
1573 /*
1574 * When the Intel ME (management engine) gets reset its serial
1575 * port registers could return 0 momentarily. Functions like
1576 * serial8250_console_write, read and save the IER, perform
1577 * some operation and then restore it. In order to avoid
1578 * setting IER register inadvertently to 0, if the value read
1579 * is 0, double check with ier value in uart_8250_port and use
1580 * that instead. up->ier should be the same value as what is
1581 * currently configured.
1582 */
1583 val = inb(p->iobase + offset);
1584 if (offset == UART_IER) {
1585 if (val == 0)
1586 val = up->ier;
1587 }
1588 return val;
1589 }
1590
kt_serial_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1591 static int kt_serial_setup(struct serial_private *priv,
1592 const struct pciserial_board *board,
1593 struct uart_8250_port *port, int idx)
1594 {
1595 port->port.flags |= UPF_BUG_THRE;
1596 port->port.serial_in = kt_serial_in;
1597 port->port.handle_break = kt_handle_break;
1598 return skip_tx_en_setup(priv, board, port, idx);
1599 }
1600
pci_eg20t_init(struct pci_dev * dev)1601 static int pci_eg20t_init(struct pci_dev *dev)
1602 {
1603 #if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1604 return -ENODEV;
1605 #else
1606 return 0;
1607 #endif
1608 }
1609
1610 static int
pci_wch_ch353_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1611 pci_wch_ch353_setup(struct serial_private *priv,
1612 const struct pciserial_board *board,
1613 struct uart_8250_port *port, int idx)
1614 {
1615 port->port.flags |= UPF_FIXED_TYPE;
1616 port->port.type = PORT_16550A;
1617 return pci_default_setup(priv, board, port, idx);
1618 }
1619
1620 static int
pci_wch_ch355_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1621 pci_wch_ch355_setup(struct serial_private *priv,
1622 const struct pciserial_board *board,
1623 struct uart_8250_port *port, int idx)
1624 {
1625 port->port.flags |= UPF_FIXED_TYPE;
1626 port->port.type = PORT_16550A;
1627 return pci_default_setup(priv, board, port, idx);
1628 }
1629
1630 static int
pci_wch_ch38x_setup(struct serial_private * priv,const struct pciserial_board * board,struct uart_8250_port * port,int idx)1631 pci_wch_ch38x_setup(struct serial_private *priv,
1632 const struct pciserial_board *board,
1633 struct uart_8250_port *port, int idx)
1634 {
1635 port->port.flags |= UPF_FIXED_TYPE;
1636 port->port.type = PORT_16850;
1637 return pci_default_setup(priv, board, port, idx);
1638 }
1639
1640 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
1641 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
1642 #define PCI_DEVICE_ID_OCTPRO 0x0001
1643 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
1644 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
1645 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
1646 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
1647 #define PCI_SUBDEVICE_ID_SIIG_DUAL_00 0x2500
1648 #define PCI_SUBDEVICE_ID_SIIG_DUAL_30 0x2530
1649 #define PCI_VENDOR_ID_ADVANTECH 0x13fe
1650 #define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1651 #define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1652 #define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1653 #define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1654 #define PCI_DEVICE_ID_TITAN_200I 0x8028
1655 #define PCI_DEVICE_ID_TITAN_400I 0x8048
1656 #define PCI_DEVICE_ID_TITAN_800I 0x8088
1657 #define PCI_DEVICE_ID_TITAN_800EH 0xA007
1658 #define PCI_DEVICE_ID_TITAN_800EHB 0xA008
1659 #define PCI_DEVICE_ID_TITAN_400EH 0xA009
1660 #define PCI_DEVICE_ID_TITAN_100E 0xA010
1661 #define PCI_DEVICE_ID_TITAN_200E 0xA012
1662 #define PCI_DEVICE_ID_TITAN_400E 0xA013
1663 #define PCI_DEVICE_ID_TITAN_800E 0xA014
1664 #define PCI_DEVICE_ID_TITAN_200EI 0xA016
1665 #define PCI_DEVICE_ID_TITAN_200EISI 0xA017
1666 #define PCI_DEVICE_ID_TITAN_200V3 0xA306
1667 #define PCI_DEVICE_ID_TITAN_400V3 0xA310
1668 #define PCI_DEVICE_ID_TITAN_410V3 0xA312
1669 #define PCI_DEVICE_ID_TITAN_800V3 0xA314
1670 #define PCI_DEVICE_ID_TITAN_800V3B 0xA315
1671 #define PCI_DEVICE_ID_OXSEMI_16PCI958 0x9538
1672 #define PCIE_DEVICE_ID_NEO_2_OX_IBM 0x00F6
1673 #define PCI_DEVICE_ID_PLX_CRONYX_OMEGA 0xc001
1674 #define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1675 #define PCI_VENDOR_ID_WCH 0x4348
1676 #define PCI_DEVICE_ID_WCH_CH352_2S 0x3253
1677 #define PCI_DEVICE_ID_WCH_CH353_4S 0x3453
1678 #define PCI_DEVICE_ID_WCH_CH353_2S1PF 0x5046
1679 #define PCI_DEVICE_ID_WCH_CH353_1S1P 0x5053
1680 #define PCI_DEVICE_ID_WCH_CH353_2S1P 0x7053
1681 #define PCI_DEVICE_ID_WCH_CH355_4S 0x7173
1682 #define PCI_VENDOR_ID_AGESTAR 0x5372
1683 #define PCI_DEVICE_ID_AGESTAR_9375 0x6872
1684 #define PCI_VENDOR_ID_ASIX 0x9710
1685 #define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1686 #define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1687
1688 #define PCIE_VENDOR_ID_WCH 0x1c00
1689 #define PCIE_DEVICE_ID_WCH_CH382_2S1P 0x3250
1690 #define PCIE_DEVICE_ID_WCH_CH384_4S 0x3470
1691 #define PCIE_DEVICE_ID_WCH_CH382_2S 0x3253
1692
1693 #define PCI_VENDOR_ID_ACCESIO 0x494f
1694 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB 0x1051
1695 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S 0x1053
1696 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB 0x105C
1697 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S 0x105E
1698 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB 0x1091
1699 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2 0x1093
1700 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB 0x1099
1701 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4 0x109B
1702 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB 0x10D1
1703 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM 0x10D3
1704 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB 0x10DA
1705 #define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM 0x10DC
1706 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1 0x1108
1707 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2 0x1110
1708 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2 0x1111
1709 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4 0x1118
1710 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4 0x1119
1711 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S 0x1152
1712 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S 0x115A
1713 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2 0x1190
1714 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2 0x1191
1715 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4 0x1198
1716 #define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4 0x1199
1717 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM 0x11D0
1718 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4 0x105A
1719 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4 0x105B
1720 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8 0x106A
1721 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8 0x106B
1722 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4 0x1098
1723 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8 0x10A9
1724 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM 0x10D9
1725 #define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM 0x10E9
1726 #define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM 0x11D8
1727
1728
1729
1730 /* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1731 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1732 #define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1733
1734 /*
1735 * Master list of serial port init/setup/exit quirks.
1736 * This does not describe the general nature of the port.
1737 * (ie, baud base, number and location of ports, etc)
1738 *
1739 * This list is ordered alphabetically by vendor then device.
1740 * Specific entries must come before more generic entries.
1741 */
1742 static struct pci_serial_quirk pci_serial_quirks[] __refdata = {
1743 /*
1744 * ADDI-DATA GmbH communication cards <info@addi-data.com>
1745 */
1746 {
1747 .vendor = PCI_VENDOR_ID_AMCC,
1748 .device = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1749 .subvendor = PCI_ANY_ID,
1750 .subdevice = PCI_ANY_ID,
1751 .setup = addidata_apci7800_setup,
1752 },
1753 /*
1754 * AFAVLAB cards - these may be called via parport_serial
1755 * It is not clear whether this applies to all products.
1756 */
1757 {
1758 .vendor = PCI_VENDOR_ID_AFAVLAB,
1759 .device = PCI_ANY_ID,
1760 .subvendor = PCI_ANY_ID,
1761 .subdevice = PCI_ANY_ID,
1762 .setup = afavlab_setup,
1763 },
1764 /*
1765 * HP Diva
1766 */
1767 {
1768 .vendor = PCI_VENDOR_ID_HP,
1769 .device = PCI_DEVICE_ID_HP_DIVA,
1770 .subvendor = PCI_ANY_ID,
1771 .subdevice = PCI_ANY_ID,
1772 .init = pci_hp_diva_init,
1773 .setup = pci_hp_diva_setup,
1774 },
1775 /*
1776 * Intel
1777 */
1778 {
1779 .vendor = PCI_VENDOR_ID_INTEL,
1780 .device = PCI_DEVICE_ID_INTEL_80960_RP,
1781 .subvendor = 0xe4bf,
1782 .subdevice = PCI_ANY_ID,
1783 .init = pci_inteli960ni_init,
1784 .setup = pci_default_setup,
1785 },
1786 {
1787 .vendor = PCI_VENDOR_ID_INTEL,
1788 .device = PCI_DEVICE_ID_INTEL_8257X_SOL,
1789 .subvendor = PCI_ANY_ID,
1790 .subdevice = PCI_ANY_ID,
1791 .setup = skip_tx_en_setup,
1792 },
1793 {
1794 .vendor = PCI_VENDOR_ID_INTEL,
1795 .device = PCI_DEVICE_ID_INTEL_82573L_SOL,
1796 .subvendor = PCI_ANY_ID,
1797 .subdevice = PCI_ANY_ID,
1798 .setup = skip_tx_en_setup,
1799 },
1800 {
1801 .vendor = PCI_VENDOR_ID_INTEL,
1802 .device = PCI_DEVICE_ID_INTEL_82573E_SOL,
1803 .subvendor = PCI_ANY_ID,
1804 .subdevice = PCI_ANY_ID,
1805 .setup = skip_tx_en_setup,
1806 },
1807 {
1808 .vendor = PCI_VENDOR_ID_INTEL,
1809 .device = PCI_DEVICE_ID_INTEL_CE4100_UART,
1810 .subvendor = PCI_ANY_ID,
1811 .subdevice = PCI_ANY_ID,
1812 .setup = ce4100_serial_setup,
1813 },
1814 {
1815 .vendor = PCI_VENDOR_ID_INTEL,
1816 .device = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
1817 .subvendor = PCI_ANY_ID,
1818 .subdevice = PCI_ANY_ID,
1819 .setup = kt_serial_setup,
1820 },
1821 /*
1822 * ITE
1823 */
1824 {
1825 .vendor = PCI_VENDOR_ID_ITE,
1826 .device = PCI_DEVICE_ID_ITE_8872,
1827 .subvendor = PCI_ANY_ID,
1828 .subdevice = PCI_ANY_ID,
1829 .init = pci_ite887x_init,
1830 .setup = pci_default_setup,
1831 .exit = pci_ite887x_exit,
1832 },
1833 /*
1834 * National Instruments
1835 */
1836 {
1837 .vendor = PCI_VENDOR_ID_NI,
1838 .device = PCI_DEVICE_ID_NI_PCI23216,
1839 .subvendor = PCI_ANY_ID,
1840 .subdevice = PCI_ANY_ID,
1841 .init = pci_ni8420_init,
1842 .setup = pci_default_setup,
1843 .exit = pci_ni8420_exit,
1844 },
1845 {
1846 .vendor = PCI_VENDOR_ID_NI,
1847 .device = PCI_DEVICE_ID_NI_PCI2328,
1848 .subvendor = PCI_ANY_ID,
1849 .subdevice = PCI_ANY_ID,
1850 .init = pci_ni8420_init,
1851 .setup = pci_default_setup,
1852 .exit = pci_ni8420_exit,
1853 },
1854 {
1855 .vendor = PCI_VENDOR_ID_NI,
1856 .device = PCI_DEVICE_ID_NI_PCI2324,
1857 .subvendor = PCI_ANY_ID,
1858 .subdevice = PCI_ANY_ID,
1859 .init = pci_ni8420_init,
1860 .setup = pci_default_setup,
1861 .exit = pci_ni8420_exit,
1862 },
1863 {
1864 .vendor = PCI_VENDOR_ID_NI,
1865 .device = PCI_DEVICE_ID_NI_PCI2322,
1866 .subvendor = PCI_ANY_ID,
1867 .subdevice = PCI_ANY_ID,
1868 .init = pci_ni8420_init,
1869 .setup = pci_default_setup,
1870 .exit = pci_ni8420_exit,
1871 },
1872 {
1873 .vendor = PCI_VENDOR_ID_NI,
1874 .device = PCI_DEVICE_ID_NI_PCI2324I,
1875 .subvendor = PCI_ANY_ID,
1876 .subdevice = PCI_ANY_ID,
1877 .init = pci_ni8420_init,
1878 .setup = pci_default_setup,
1879 .exit = pci_ni8420_exit,
1880 },
1881 {
1882 .vendor = PCI_VENDOR_ID_NI,
1883 .device = PCI_DEVICE_ID_NI_PCI2322I,
1884 .subvendor = PCI_ANY_ID,
1885 .subdevice = PCI_ANY_ID,
1886 .init = pci_ni8420_init,
1887 .setup = pci_default_setup,
1888 .exit = pci_ni8420_exit,
1889 },
1890 {
1891 .vendor = PCI_VENDOR_ID_NI,
1892 .device = PCI_DEVICE_ID_NI_PXI8420_23216,
1893 .subvendor = PCI_ANY_ID,
1894 .subdevice = PCI_ANY_ID,
1895 .init = pci_ni8420_init,
1896 .setup = pci_default_setup,
1897 .exit = pci_ni8420_exit,
1898 },
1899 {
1900 .vendor = PCI_VENDOR_ID_NI,
1901 .device = PCI_DEVICE_ID_NI_PXI8420_2328,
1902 .subvendor = PCI_ANY_ID,
1903 .subdevice = PCI_ANY_ID,
1904 .init = pci_ni8420_init,
1905 .setup = pci_default_setup,
1906 .exit = pci_ni8420_exit,
1907 },
1908 {
1909 .vendor = PCI_VENDOR_ID_NI,
1910 .device = PCI_DEVICE_ID_NI_PXI8420_2324,
1911 .subvendor = PCI_ANY_ID,
1912 .subdevice = PCI_ANY_ID,
1913 .init = pci_ni8420_init,
1914 .setup = pci_default_setup,
1915 .exit = pci_ni8420_exit,
1916 },
1917 {
1918 .vendor = PCI_VENDOR_ID_NI,
1919 .device = PCI_DEVICE_ID_NI_PXI8420_2322,
1920 .subvendor = PCI_ANY_ID,
1921 .subdevice = PCI_ANY_ID,
1922 .init = pci_ni8420_init,
1923 .setup = pci_default_setup,
1924 .exit = pci_ni8420_exit,
1925 },
1926 {
1927 .vendor = PCI_VENDOR_ID_NI,
1928 .device = PCI_DEVICE_ID_NI_PXI8422_2324,
1929 .subvendor = PCI_ANY_ID,
1930 .subdevice = PCI_ANY_ID,
1931 .init = pci_ni8420_init,
1932 .setup = pci_default_setup,
1933 .exit = pci_ni8420_exit,
1934 },
1935 {
1936 .vendor = PCI_VENDOR_ID_NI,
1937 .device = PCI_DEVICE_ID_NI_PXI8422_2322,
1938 .subvendor = PCI_ANY_ID,
1939 .subdevice = PCI_ANY_ID,
1940 .init = pci_ni8420_init,
1941 .setup = pci_default_setup,
1942 .exit = pci_ni8420_exit,
1943 },
1944 {
1945 .vendor = PCI_VENDOR_ID_NI,
1946 .device = PCI_ANY_ID,
1947 .subvendor = PCI_ANY_ID,
1948 .subdevice = PCI_ANY_ID,
1949 .init = pci_ni8430_init,
1950 .setup = pci_ni8430_setup,
1951 .exit = pci_ni8430_exit,
1952 },
1953 /* Quatech */
1954 {
1955 .vendor = PCI_VENDOR_ID_QUATECH,
1956 .device = PCI_ANY_ID,
1957 .subvendor = PCI_ANY_ID,
1958 .subdevice = PCI_ANY_ID,
1959 .init = pci_quatech_init,
1960 .setup = pci_quatech_setup,
1961 .exit = pci_quatech_exit,
1962 },
1963 /*
1964 * Panacom
1965 */
1966 {
1967 .vendor = PCI_VENDOR_ID_PANACOM,
1968 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
1969 .subvendor = PCI_ANY_ID,
1970 .subdevice = PCI_ANY_ID,
1971 .init = pci_plx9050_init,
1972 .setup = pci_default_setup,
1973 .exit = pci_plx9050_exit,
1974 },
1975 {
1976 .vendor = PCI_VENDOR_ID_PANACOM,
1977 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
1978 .subvendor = PCI_ANY_ID,
1979 .subdevice = PCI_ANY_ID,
1980 .init = pci_plx9050_init,
1981 .setup = pci_default_setup,
1982 .exit = pci_plx9050_exit,
1983 },
1984 /*
1985 * Pericom (Only 7954 - It have a offset jump for port 4)
1986 */
1987 {
1988 .vendor = PCI_VENDOR_ID_PERICOM,
1989 .device = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
1990 .subvendor = PCI_ANY_ID,
1991 .subdevice = PCI_ANY_ID,
1992 .setup = pci_pericom_setup,
1993 },
1994 /*
1995 * PLX
1996 */
1997 {
1998 .vendor = PCI_VENDOR_ID_PLX,
1999 .device = PCI_DEVICE_ID_PLX_9050,
2000 .subvendor = PCI_SUBVENDOR_ID_EXSYS,
2001 .subdevice = PCI_SUBDEVICE_ID_EXSYS_4055,
2002 .init = pci_plx9050_init,
2003 .setup = pci_default_setup,
2004 .exit = pci_plx9050_exit,
2005 },
2006 {
2007 .vendor = PCI_VENDOR_ID_PLX,
2008 .device = PCI_DEVICE_ID_PLX_9050,
2009 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
2010 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2011 .init = pci_plx9050_init,
2012 .setup = pci_default_setup,
2013 .exit = pci_plx9050_exit,
2014 },
2015 {
2016 .vendor = PCI_VENDOR_ID_PLX,
2017 .device = PCI_DEVICE_ID_PLX_ROMULUS,
2018 .subvendor = PCI_VENDOR_ID_PLX,
2019 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
2020 .init = pci_plx9050_init,
2021 .setup = pci_default_setup,
2022 .exit = pci_plx9050_exit,
2023 },
2024 {
2025 .vendor = PCI_VENDOR_ID_ACCESIO,
2026 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2027 .subvendor = PCI_ANY_ID,
2028 .subdevice = PCI_ANY_ID,
2029 .setup = pci_pericom_setup,
2030 },
2031 {
2032 .vendor = PCI_VENDOR_ID_ACCESIO,
2033 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2034 .subvendor = PCI_ANY_ID,
2035 .subdevice = PCI_ANY_ID,
2036 .setup = pci_pericom_setup,
2037 },
2038 {
2039 .vendor = PCI_VENDOR_ID_ACCESIO,
2040 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2041 .subvendor = PCI_ANY_ID,
2042 .subdevice = PCI_ANY_ID,
2043 .setup = pci_pericom_setup,
2044 },
2045 {
2046 .vendor = PCI_VENDOR_ID_ACCESIO,
2047 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2048 .subvendor = PCI_ANY_ID,
2049 .subdevice = PCI_ANY_ID,
2050 .setup = pci_pericom_setup,
2051 },
2052 {
2053 .vendor = PCI_VENDOR_ID_ACCESIO,
2054 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2055 .subvendor = PCI_ANY_ID,
2056 .subdevice = PCI_ANY_ID,
2057 .setup = pci_pericom_setup,
2058 },
2059 {
2060 .vendor = PCI_VENDOR_ID_ACCESIO,
2061 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2062 .subvendor = PCI_ANY_ID,
2063 .subdevice = PCI_ANY_ID,
2064 .setup = pci_pericom_setup,
2065 },
2066 {
2067 .vendor = PCI_VENDOR_ID_ACCESIO,
2068 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2069 .subvendor = PCI_ANY_ID,
2070 .subdevice = PCI_ANY_ID,
2071 .setup = pci_pericom_setup,
2072 },
2073 {
2074 .vendor = PCI_VENDOR_ID_ACCESIO,
2075 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2076 .subvendor = PCI_ANY_ID,
2077 .subdevice = PCI_ANY_ID,
2078 .setup = pci_pericom_setup,
2079 },
2080 {
2081 .vendor = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2082 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2083 .subvendor = PCI_ANY_ID,
2084 .subdevice = PCI_ANY_ID,
2085 .setup = pci_pericom_setup,
2086 },
2087 {
2088 .vendor = PCI_VENDOR_ID_ACCESIO,
2089 .device = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2090 .subvendor = PCI_ANY_ID,
2091 .subdevice = PCI_ANY_ID,
2092 .setup = pci_pericom_setup,
2093 },
2094 {
2095 .vendor = PCI_VENDOR_ID_ACCESIO,
2096 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2097 .subvendor = PCI_ANY_ID,
2098 .subdevice = PCI_ANY_ID,
2099 .setup = pci_pericom_setup,
2100 },
2101 {
2102 .vendor = PCI_VENDOR_ID_ACCESIO,
2103 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2104 .subvendor = PCI_ANY_ID,
2105 .subdevice = PCI_ANY_ID,
2106 .setup = pci_pericom_setup,
2107 },
2108 {
2109 .vendor = PCI_VENDOR_ID_ACCESIO,
2110 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2111 .subvendor = PCI_ANY_ID,
2112 .subdevice = PCI_ANY_ID,
2113 .setup = pci_pericom_setup,
2114 },
2115 {
2116 .vendor = PCI_VENDOR_ID_ACCESIO,
2117 .device = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2118 .subvendor = PCI_ANY_ID,
2119 .subdevice = PCI_ANY_ID,
2120 .setup = pci_pericom_setup,
2121 },
2122 {
2123 .vendor = PCI_VENDOR_ID_ACCESIO,
2124 .device = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2125 .subvendor = PCI_ANY_ID,
2126 .subdevice = PCI_ANY_ID,
2127 .setup = pci_pericom_setup,
2128 },
2129 /*
2130 * SBS Technologies, Inc., PMC-OCTALPRO 232
2131 */
2132 {
2133 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2134 .device = PCI_DEVICE_ID_OCTPRO,
2135 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2136 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
2137 .init = sbs_init,
2138 .setup = sbs_setup,
2139 .exit = sbs_exit,
2140 },
2141 /*
2142 * SBS Technologies, Inc., PMC-OCTALPRO 422
2143 */
2144 {
2145 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2146 .device = PCI_DEVICE_ID_OCTPRO,
2147 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2148 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
2149 .init = sbs_init,
2150 .setup = sbs_setup,
2151 .exit = sbs_exit,
2152 },
2153 /*
2154 * SBS Technologies, Inc., P-Octal 232
2155 */
2156 {
2157 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2158 .device = PCI_DEVICE_ID_OCTPRO,
2159 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2160 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
2161 .init = sbs_init,
2162 .setup = sbs_setup,
2163 .exit = sbs_exit,
2164 },
2165 /*
2166 * SBS Technologies, Inc., P-Octal 422
2167 */
2168 {
2169 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
2170 .device = PCI_DEVICE_ID_OCTPRO,
2171 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
2172 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
2173 .init = sbs_init,
2174 .setup = sbs_setup,
2175 .exit = sbs_exit,
2176 },
2177 /*
2178 * SIIG cards - these may be called via parport_serial
2179 */
2180 {
2181 .vendor = PCI_VENDOR_ID_SIIG,
2182 .device = PCI_ANY_ID,
2183 .subvendor = PCI_ANY_ID,
2184 .subdevice = PCI_ANY_ID,
2185 .init = pci_siig_init,
2186 .setup = pci_siig_setup,
2187 },
2188 /*
2189 * Titan cards
2190 */
2191 {
2192 .vendor = PCI_VENDOR_ID_TITAN,
2193 .device = PCI_DEVICE_ID_TITAN_400L,
2194 .subvendor = PCI_ANY_ID,
2195 .subdevice = PCI_ANY_ID,
2196 .setup = titan_400l_800l_setup,
2197 },
2198 {
2199 .vendor = PCI_VENDOR_ID_TITAN,
2200 .device = PCI_DEVICE_ID_TITAN_800L,
2201 .subvendor = PCI_ANY_ID,
2202 .subdevice = PCI_ANY_ID,
2203 .setup = titan_400l_800l_setup,
2204 },
2205 /*
2206 * Timedia cards
2207 */
2208 {
2209 .vendor = PCI_VENDOR_ID_TIMEDIA,
2210 .device = PCI_DEVICE_ID_TIMEDIA_1889,
2211 .subvendor = PCI_VENDOR_ID_TIMEDIA,
2212 .subdevice = PCI_ANY_ID,
2213 .probe = pci_timedia_probe,
2214 .init = pci_timedia_init,
2215 .setup = pci_timedia_setup,
2216 },
2217 {
2218 .vendor = PCI_VENDOR_ID_TIMEDIA,
2219 .device = PCI_ANY_ID,
2220 .subvendor = PCI_ANY_ID,
2221 .subdevice = PCI_ANY_ID,
2222 .setup = pci_timedia_setup,
2223 },
2224 /*
2225 * SUNIX (Timedia) cards
2226 * Do not "probe" for these cards as there is at least one combination
2227 * card that should be handled by parport_pc that doesn't match the
2228 * rule in pci_timedia_probe.
2229 * It is part number is MIO5079A but its subdevice ID is 0x0102.
2230 * There are some boards with part number SER5037AL that report
2231 * subdevice ID 0x0002.
2232 */
2233 {
2234 .vendor = PCI_VENDOR_ID_SUNIX,
2235 .device = PCI_DEVICE_ID_SUNIX_1999,
2236 .subvendor = PCI_VENDOR_ID_SUNIX,
2237 .subdevice = PCI_ANY_ID,
2238 .init = pci_timedia_init,
2239 .setup = pci_timedia_setup,
2240 },
2241 /*
2242 * Xircom cards
2243 */
2244 {
2245 .vendor = PCI_VENDOR_ID_XIRCOM,
2246 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2247 .subvendor = PCI_ANY_ID,
2248 .subdevice = PCI_ANY_ID,
2249 .init = pci_xircom_init,
2250 .setup = pci_default_setup,
2251 },
2252 /*
2253 * Netmos cards - these may be called via parport_serial
2254 */
2255 {
2256 .vendor = PCI_VENDOR_ID_NETMOS,
2257 .device = PCI_ANY_ID,
2258 .subvendor = PCI_ANY_ID,
2259 .subdevice = PCI_ANY_ID,
2260 .init = pci_netmos_init,
2261 .setup = pci_netmos_9900_setup,
2262 },
2263 /*
2264 * EndRun Technologies
2265 */
2266 {
2267 .vendor = PCI_VENDOR_ID_ENDRUN,
2268 .device = PCI_ANY_ID,
2269 .subvendor = PCI_ANY_ID,
2270 .subdevice = PCI_ANY_ID,
2271 .init = pci_endrun_init,
2272 .setup = pci_default_setup,
2273 },
2274 /*
2275 * For Oxford Semiconductor Tornado based devices
2276 */
2277 {
2278 .vendor = PCI_VENDOR_ID_OXSEMI,
2279 .device = PCI_ANY_ID,
2280 .subvendor = PCI_ANY_ID,
2281 .subdevice = PCI_ANY_ID,
2282 .init = pci_oxsemi_tornado_init,
2283 .setup = pci_default_setup,
2284 },
2285 {
2286 .vendor = PCI_VENDOR_ID_MAINPINE,
2287 .device = PCI_ANY_ID,
2288 .subvendor = PCI_ANY_ID,
2289 .subdevice = PCI_ANY_ID,
2290 .init = pci_oxsemi_tornado_init,
2291 .setup = pci_default_setup,
2292 },
2293 {
2294 .vendor = PCI_VENDOR_ID_DIGI,
2295 .device = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2296 .subvendor = PCI_SUBVENDOR_ID_IBM,
2297 .subdevice = PCI_ANY_ID,
2298 .init = pci_oxsemi_tornado_init,
2299 .setup = pci_default_setup,
2300 },
2301 {
2302 .vendor = PCI_VENDOR_ID_INTEL,
2303 .device = 0x8811,
2304 .subvendor = PCI_ANY_ID,
2305 .subdevice = PCI_ANY_ID,
2306 .init = pci_eg20t_init,
2307 .setup = pci_default_setup,
2308 },
2309 {
2310 .vendor = PCI_VENDOR_ID_INTEL,
2311 .device = 0x8812,
2312 .subvendor = PCI_ANY_ID,
2313 .subdevice = PCI_ANY_ID,
2314 .init = pci_eg20t_init,
2315 .setup = pci_default_setup,
2316 },
2317 {
2318 .vendor = PCI_VENDOR_ID_INTEL,
2319 .device = 0x8813,
2320 .subvendor = PCI_ANY_ID,
2321 .subdevice = PCI_ANY_ID,
2322 .init = pci_eg20t_init,
2323 .setup = pci_default_setup,
2324 },
2325 {
2326 .vendor = PCI_VENDOR_ID_INTEL,
2327 .device = 0x8814,
2328 .subvendor = PCI_ANY_ID,
2329 .subdevice = PCI_ANY_ID,
2330 .init = pci_eg20t_init,
2331 .setup = pci_default_setup,
2332 },
2333 {
2334 .vendor = 0x10DB,
2335 .device = 0x8027,
2336 .subvendor = PCI_ANY_ID,
2337 .subdevice = PCI_ANY_ID,
2338 .init = pci_eg20t_init,
2339 .setup = pci_default_setup,
2340 },
2341 {
2342 .vendor = 0x10DB,
2343 .device = 0x8028,
2344 .subvendor = PCI_ANY_ID,
2345 .subdevice = PCI_ANY_ID,
2346 .init = pci_eg20t_init,
2347 .setup = pci_default_setup,
2348 },
2349 {
2350 .vendor = 0x10DB,
2351 .device = 0x8029,
2352 .subvendor = PCI_ANY_ID,
2353 .subdevice = PCI_ANY_ID,
2354 .init = pci_eg20t_init,
2355 .setup = pci_default_setup,
2356 },
2357 {
2358 .vendor = 0x10DB,
2359 .device = 0x800C,
2360 .subvendor = PCI_ANY_ID,
2361 .subdevice = PCI_ANY_ID,
2362 .init = pci_eg20t_init,
2363 .setup = pci_default_setup,
2364 },
2365 {
2366 .vendor = 0x10DB,
2367 .device = 0x800D,
2368 .subvendor = PCI_ANY_ID,
2369 .subdevice = PCI_ANY_ID,
2370 .init = pci_eg20t_init,
2371 .setup = pci_default_setup,
2372 },
2373 /*
2374 * Cronyx Omega PCI (PLX-chip based)
2375 */
2376 {
2377 .vendor = PCI_VENDOR_ID_PLX,
2378 .device = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2379 .subvendor = PCI_ANY_ID,
2380 .subdevice = PCI_ANY_ID,
2381 .setup = pci_omegapci_setup,
2382 },
2383 /* WCH CH353 1S1P card (16550 clone) */
2384 {
2385 .vendor = PCI_VENDOR_ID_WCH,
2386 .device = PCI_DEVICE_ID_WCH_CH353_1S1P,
2387 .subvendor = PCI_ANY_ID,
2388 .subdevice = PCI_ANY_ID,
2389 .setup = pci_wch_ch353_setup,
2390 },
2391 /* WCH CH353 2S1P card (16550 clone) */
2392 {
2393 .vendor = PCI_VENDOR_ID_WCH,
2394 .device = PCI_DEVICE_ID_WCH_CH353_2S1P,
2395 .subvendor = PCI_ANY_ID,
2396 .subdevice = PCI_ANY_ID,
2397 .setup = pci_wch_ch353_setup,
2398 },
2399 /* WCH CH353 4S card (16550 clone) */
2400 {
2401 .vendor = PCI_VENDOR_ID_WCH,
2402 .device = PCI_DEVICE_ID_WCH_CH353_4S,
2403 .subvendor = PCI_ANY_ID,
2404 .subdevice = PCI_ANY_ID,
2405 .setup = pci_wch_ch353_setup,
2406 },
2407 /* WCH CH353 2S1PF card (16550 clone) */
2408 {
2409 .vendor = PCI_VENDOR_ID_WCH,
2410 .device = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2411 .subvendor = PCI_ANY_ID,
2412 .subdevice = PCI_ANY_ID,
2413 .setup = pci_wch_ch353_setup,
2414 },
2415 /* WCH CH352 2S card (16550 clone) */
2416 {
2417 .vendor = PCI_VENDOR_ID_WCH,
2418 .device = PCI_DEVICE_ID_WCH_CH352_2S,
2419 .subvendor = PCI_ANY_ID,
2420 .subdevice = PCI_ANY_ID,
2421 .setup = pci_wch_ch353_setup,
2422 },
2423 /* WCH CH355 4S card (16550 clone) */
2424 {
2425 .vendor = PCI_VENDOR_ID_WCH,
2426 .device = PCI_DEVICE_ID_WCH_CH355_4S,
2427 .subvendor = PCI_ANY_ID,
2428 .subdevice = PCI_ANY_ID,
2429 .setup = pci_wch_ch355_setup,
2430 },
2431 /* WCH CH382 2S card (16850 clone) */
2432 {
2433 .vendor = PCIE_VENDOR_ID_WCH,
2434 .device = PCIE_DEVICE_ID_WCH_CH382_2S,
2435 .subvendor = PCI_ANY_ID,
2436 .subdevice = PCI_ANY_ID,
2437 .setup = pci_wch_ch38x_setup,
2438 },
2439 /* WCH CH382 2S1P card (16850 clone) */
2440 {
2441 .vendor = PCIE_VENDOR_ID_WCH,
2442 .device = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2443 .subvendor = PCI_ANY_ID,
2444 .subdevice = PCI_ANY_ID,
2445 .setup = pci_wch_ch38x_setup,
2446 },
2447 /* WCH CH384 4S card (16850 clone) */
2448 {
2449 .vendor = PCIE_VENDOR_ID_WCH,
2450 .device = PCIE_DEVICE_ID_WCH_CH384_4S,
2451 .subvendor = PCI_ANY_ID,
2452 .subdevice = PCI_ANY_ID,
2453 .setup = pci_wch_ch38x_setup,
2454 },
2455 /*
2456 * ASIX devices with FIFO bug
2457 */
2458 {
2459 .vendor = PCI_VENDOR_ID_ASIX,
2460 .device = PCI_ANY_ID,
2461 .subvendor = PCI_ANY_ID,
2462 .subdevice = PCI_ANY_ID,
2463 .setup = pci_asix_setup,
2464 },
2465 /*
2466 * Broadcom TruManage (NetXtreme)
2467 */
2468 {
2469 .vendor = PCI_VENDOR_ID_BROADCOM,
2470 .device = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2471 .subvendor = PCI_ANY_ID,
2472 .subdevice = PCI_ANY_ID,
2473 .setup = pci_brcm_trumanage_setup,
2474 },
2475 {
2476 .vendor = 0x1c29,
2477 .device = 0x1104,
2478 .subvendor = PCI_ANY_ID,
2479 .subdevice = PCI_ANY_ID,
2480 .setup = pci_fintek_setup,
2481 .init = pci_fintek_init,
2482 },
2483 {
2484 .vendor = 0x1c29,
2485 .device = 0x1108,
2486 .subvendor = PCI_ANY_ID,
2487 .subdevice = PCI_ANY_ID,
2488 .setup = pci_fintek_setup,
2489 .init = pci_fintek_init,
2490 },
2491 {
2492 .vendor = 0x1c29,
2493 .device = 0x1112,
2494 .subvendor = PCI_ANY_ID,
2495 .subdevice = PCI_ANY_ID,
2496 .setup = pci_fintek_setup,
2497 .init = pci_fintek_init,
2498 },
2499
2500 /*
2501 * Default "match everything" terminator entry
2502 */
2503 {
2504 .vendor = PCI_ANY_ID,
2505 .device = PCI_ANY_ID,
2506 .subvendor = PCI_ANY_ID,
2507 .subdevice = PCI_ANY_ID,
2508 .setup = pci_default_setup,
2509 }
2510 };
2511
quirk_id_matches(u32 quirk_id,u32 dev_id)2512 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2513 {
2514 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2515 }
2516
find_quirk(struct pci_dev * dev)2517 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2518 {
2519 struct pci_serial_quirk *quirk;
2520
2521 for (quirk = pci_serial_quirks; ; quirk++)
2522 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2523 quirk_id_matches(quirk->device, dev->device) &&
2524 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2525 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2526 break;
2527 return quirk;
2528 }
2529
get_pci_irq(struct pci_dev * dev,const struct pciserial_board * board)2530 static inline int get_pci_irq(struct pci_dev *dev,
2531 const struct pciserial_board *board)
2532 {
2533 if (board->flags & FL_NOIRQ)
2534 return 0;
2535 else
2536 return dev->irq;
2537 }
2538
2539 /*
2540 * This is the configuration table for all of the PCI serial boards
2541 * which we support. It is directly indexed by the pci_board_num_t enum
2542 * value, which is encoded in the pci_device_id PCI probe table's
2543 * driver_data member.
2544 *
2545 * The makeup of these names are:
2546 * pbn_bn{_bt}_n_baud{_offsetinhex}
2547 *
2548 * bn = PCI BAR number
2549 * bt = Index using PCI BARs
2550 * n = number of serial ports
2551 * baud = baud rate
2552 * offsetinhex = offset for each sequential port (in hex)
2553 *
2554 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2555 *
2556 * Please note: in theory if n = 1, _bt infix should make no difference.
2557 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2558 */
2559 enum pci_board_num_t {
2560 pbn_default = 0,
2561
2562 pbn_b0_1_115200,
2563 pbn_b0_2_115200,
2564 pbn_b0_4_115200,
2565 pbn_b0_5_115200,
2566 pbn_b0_8_115200,
2567
2568 pbn_b0_1_921600,
2569 pbn_b0_2_921600,
2570 pbn_b0_4_921600,
2571
2572 pbn_b0_2_1130000,
2573
2574 pbn_b0_4_1152000,
2575
2576 pbn_b0_4_1250000,
2577
2578 pbn_b0_2_1843200,
2579 pbn_b0_4_1843200,
2580
2581 pbn_b0_1_4000000,
2582
2583 pbn_b0_bt_1_115200,
2584 pbn_b0_bt_2_115200,
2585 pbn_b0_bt_4_115200,
2586 pbn_b0_bt_8_115200,
2587
2588 pbn_b0_bt_1_460800,
2589 pbn_b0_bt_2_460800,
2590 pbn_b0_bt_4_460800,
2591
2592 pbn_b0_bt_1_921600,
2593 pbn_b0_bt_2_921600,
2594 pbn_b0_bt_4_921600,
2595 pbn_b0_bt_8_921600,
2596
2597 pbn_b1_1_115200,
2598 pbn_b1_2_115200,
2599 pbn_b1_4_115200,
2600 pbn_b1_8_115200,
2601 pbn_b1_16_115200,
2602
2603 pbn_b1_1_921600,
2604 pbn_b1_2_921600,
2605 pbn_b1_4_921600,
2606 pbn_b1_8_921600,
2607
2608 pbn_b1_2_1250000,
2609
2610 pbn_b1_bt_1_115200,
2611 pbn_b1_bt_2_115200,
2612 pbn_b1_bt_4_115200,
2613
2614 pbn_b1_bt_2_921600,
2615
2616 pbn_b1_1_1382400,
2617 pbn_b1_2_1382400,
2618 pbn_b1_4_1382400,
2619 pbn_b1_8_1382400,
2620
2621 pbn_b2_1_115200,
2622 pbn_b2_2_115200,
2623 pbn_b2_4_115200,
2624 pbn_b2_8_115200,
2625
2626 pbn_b2_1_460800,
2627 pbn_b2_4_460800,
2628 pbn_b2_8_460800,
2629 pbn_b2_16_460800,
2630
2631 pbn_b2_1_921600,
2632 pbn_b2_4_921600,
2633 pbn_b2_8_921600,
2634
2635 pbn_b2_8_1152000,
2636
2637 pbn_b2_bt_1_115200,
2638 pbn_b2_bt_2_115200,
2639 pbn_b2_bt_4_115200,
2640
2641 pbn_b2_bt_2_921600,
2642 pbn_b2_bt_4_921600,
2643
2644 pbn_b3_2_115200,
2645 pbn_b3_4_115200,
2646 pbn_b3_8_115200,
2647
2648 pbn_b4_bt_2_921600,
2649 pbn_b4_bt_4_921600,
2650 pbn_b4_bt_8_921600,
2651
2652 /*
2653 * Board-specific versions.
2654 */
2655 pbn_panacom,
2656 pbn_panacom2,
2657 pbn_panacom4,
2658 pbn_plx_romulus,
2659 pbn_endrun_2_4000000,
2660 pbn_oxsemi,
2661 pbn_oxsemi_1_4000000,
2662 pbn_oxsemi_2_4000000,
2663 pbn_oxsemi_4_4000000,
2664 pbn_oxsemi_8_4000000,
2665 pbn_intel_i960,
2666 pbn_sgi_ioc3,
2667 pbn_computone_4,
2668 pbn_computone_6,
2669 pbn_computone_8,
2670 pbn_sbsxrsio,
2671 pbn_pasemi_1682M,
2672 pbn_ni8430_2,
2673 pbn_ni8430_4,
2674 pbn_ni8430_8,
2675 pbn_ni8430_16,
2676 pbn_ADDIDATA_PCIe_1_3906250,
2677 pbn_ADDIDATA_PCIe_2_3906250,
2678 pbn_ADDIDATA_PCIe_4_3906250,
2679 pbn_ADDIDATA_PCIe_8_3906250,
2680 pbn_ce4100_1_115200,
2681 pbn_omegapci,
2682 pbn_NETMOS9900_2s_115200,
2683 pbn_brcm_trumanage,
2684 pbn_fintek_4,
2685 pbn_fintek_8,
2686 pbn_fintek_12,
2687 pbn_wch382_2,
2688 pbn_wch384_4,
2689 pbn_pericom_PI7C9X7951,
2690 pbn_pericom_PI7C9X7952,
2691 pbn_pericom_PI7C9X7954,
2692 pbn_pericom_PI7C9X7958,
2693 };
2694
2695 /*
2696 * uart_offset - the space between channels
2697 * reg_shift - describes how the UART registers are mapped
2698 * to PCI memory by the card.
2699 * For example IER register on SBS, Inc. PMC-OctPro is located at
2700 * offset 0x10 from the UART base, while UART_IER is defined as 1
2701 * in include/linux/serial_reg.h,
2702 * see first lines of serial_in() and serial_out() in 8250.c
2703 */
2704
2705 static struct pciserial_board pci_boards[] = {
2706 [pbn_default] = {
2707 .flags = FL_BASE0,
2708 .num_ports = 1,
2709 .base_baud = 115200,
2710 .uart_offset = 8,
2711 },
2712 [pbn_b0_1_115200] = {
2713 .flags = FL_BASE0,
2714 .num_ports = 1,
2715 .base_baud = 115200,
2716 .uart_offset = 8,
2717 },
2718 [pbn_b0_2_115200] = {
2719 .flags = FL_BASE0,
2720 .num_ports = 2,
2721 .base_baud = 115200,
2722 .uart_offset = 8,
2723 },
2724 [pbn_b0_4_115200] = {
2725 .flags = FL_BASE0,
2726 .num_ports = 4,
2727 .base_baud = 115200,
2728 .uart_offset = 8,
2729 },
2730 [pbn_b0_5_115200] = {
2731 .flags = FL_BASE0,
2732 .num_ports = 5,
2733 .base_baud = 115200,
2734 .uart_offset = 8,
2735 },
2736 [pbn_b0_8_115200] = {
2737 .flags = FL_BASE0,
2738 .num_ports = 8,
2739 .base_baud = 115200,
2740 .uart_offset = 8,
2741 },
2742 [pbn_b0_1_921600] = {
2743 .flags = FL_BASE0,
2744 .num_ports = 1,
2745 .base_baud = 921600,
2746 .uart_offset = 8,
2747 },
2748 [pbn_b0_2_921600] = {
2749 .flags = FL_BASE0,
2750 .num_ports = 2,
2751 .base_baud = 921600,
2752 .uart_offset = 8,
2753 },
2754 [pbn_b0_4_921600] = {
2755 .flags = FL_BASE0,
2756 .num_ports = 4,
2757 .base_baud = 921600,
2758 .uart_offset = 8,
2759 },
2760
2761 [pbn_b0_2_1130000] = {
2762 .flags = FL_BASE0,
2763 .num_ports = 2,
2764 .base_baud = 1130000,
2765 .uart_offset = 8,
2766 },
2767
2768 [pbn_b0_4_1152000] = {
2769 .flags = FL_BASE0,
2770 .num_ports = 4,
2771 .base_baud = 1152000,
2772 .uart_offset = 8,
2773 },
2774
2775 [pbn_b0_4_1250000] = {
2776 .flags = FL_BASE0,
2777 .num_ports = 4,
2778 .base_baud = 1250000,
2779 .uart_offset = 8,
2780 },
2781
2782 [pbn_b0_2_1843200] = {
2783 .flags = FL_BASE0,
2784 .num_ports = 2,
2785 .base_baud = 1843200,
2786 .uart_offset = 8,
2787 },
2788 [pbn_b0_4_1843200] = {
2789 .flags = FL_BASE0,
2790 .num_ports = 4,
2791 .base_baud = 1843200,
2792 .uart_offset = 8,
2793 },
2794
2795 [pbn_b0_1_4000000] = {
2796 .flags = FL_BASE0,
2797 .num_ports = 1,
2798 .base_baud = 4000000,
2799 .uart_offset = 8,
2800 },
2801
2802 [pbn_b0_bt_1_115200] = {
2803 .flags = FL_BASE0|FL_BASE_BARS,
2804 .num_ports = 1,
2805 .base_baud = 115200,
2806 .uart_offset = 8,
2807 },
2808 [pbn_b0_bt_2_115200] = {
2809 .flags = FL_BASE0|FL_BASE_BARS,
2810 .num_ports = 2,
2811 .base_baud = 115200,
2812 .uart_offset = 8,
2813 },
2814 [pbn_b0_bt_4_115200] = {
2815 .flags = FL_BASE0|FL_BASE_BARS,
2816 .num_ports = 4,
2817 .base_baud = 115200,
2818 .uart_offset = 8,
2819 },
2820 [pbn_b0_bt_8_115200] = {
2821 .flags = FL_BASE0|FL_BASE_BARS,
2822 .num_ports = 8,
2823 .base_baud = 115200,
2824 .uart_offset = 8,
2825 },
2826
2827 [pbn_b0_bt_1_460800] = {
2828 .flags = FL_BASE0|FL_BASE_BARS,
2829 .num_ports = 1,
2830 .base_baud = 460800,
2831 .uart_offset = 8,
2832 },
2833 [pbn_b0_bt_2_460800] = {
2834 .flags = FL_BASE0|FL_BASE_BARS,
2835 .num_ports = 2,
2836 .base_baud = 460800,
2837 .uart_offset = 8,
2838 },
2839 [pbn_b0_bt_4_460800] = {
2840 .flags = FL_BASE0|FL_BASE_BARS,
2841 .num_ports = 4,
2842 .base_baud = 460800,
2843 .uart_offset = 8,
2844 },
2845
2846 [pbn_b0_bt_1_921600] = {
2847 .flags = FL_BASE0|FL_BASE_BARS,
2848 .num_ports = 1,
2849 .base_baud = 921600,
2850 .uart_offset = 8,
2851 },
2852 [pbn_b0_bt_2_921600] = {
2853 .flags = FL_BASE0|FL_BASE_BARS,
2854 .num_ports = 2,
2855 .base_baud = 921600,
2856 .uart_offset = 8,
2857 },
2858 [pbn_b0_bt_4_921600] = {
2859 .flags = FL_BASE0|FL_BASE_BARS,
2860 .num_ports = 4,
2861 .base_baud = 921600,
2862 .uart_offset = 8,
2863 },
2864 [pbn_b0_bt_8_921600] = {
2865 .flags = FL_BASE0|FL_BASE_BARS,
2866 .num_ports = 8,
2867 .base_baud = 921600,
2868 .uart_offset = 8,
2869 },
2870
2871 [pbn_b1_1_115200] = {
2872 .flags = FL_BASE1,
2873 .num_ports = 1,
2874 .base_baud = 115200,
2875 .uart_offset = 8,
2876 },
2877 [pbn_b1_2_115200] = {
2878 .flags = FL_BASE1,
2879 .num_ports = 2,
2880 .base_baud = 115200,
2881 .uart_offset = 8,
2882 },
2883 [pbn_b1_4_115200] = {
2884 .flags = FL_BASE1,
2885 .num_ports = 4,
2886 .base_baud = 115200,
2887 .uart_offset = 8,
2888 },
2889 [pbn_b1_8_115200] = {
2890 .flags = FL_BASE1,
2891 .num_ports = 8,
2892 .base_baud = 115200,
2893 .uart_offset = 8,
2894 },
2895 [pbn_b1_16_115200] = {
2896 .flags = FL_BASE1,
2897 .num_ports = 16,
2898 .base_baud = 115200,
2899 .uart_offset = 8,
2900 },
2901
2902 [pbn_b1_1_921600] = {
2903 .flags = FL_BASE1,
2904 .num_ports = 1,
2905 .base_baud = 921600,
2906 .uart_offset = 8,
2907 },
2908 [pbn_b1_2_921600] = {
2909 .flags = FL_BASE1,
2910 .num_ports = 2,
2911 .base_baud = 921600,
2912 .uart_offset = 8,
2913 },
2914 [pbn_b1_4_921600] = {
2915 .flags = FL_BASE1,
2916 .num_ports = 4,
2917 .base_baud = 921600,
2918 .uart_offset = 8,
2919 },
2920 [pbn_b1_8_921600] = {
2921 .flags = FL_BASE1,
2922 .num_ports = 8,
2923 .base_baud = 921600,
2924 .uart_offset = 8,
2925 },
2926 [pbn_b1_2_1250000] = {
2927 .flags = FL_BASE1,
2928 .num_ports = 2,
2929 .base_baud = 1250000,
2930 .uart_offset = 8,
2931 },
2932
2933 [pbn_b1_bt_1_115200] = {
2934 .flags = FL_BASE1|FL_BASE_BARS,
2935 .num_ports = 1,
2936 .base_baud = 115200,
2937 .uart_offset = 8,
2938 },
2939 [pbn_b1_bt_2_115200] = {
2940 .flags = FL_BASE1|FL_BASE_BARS,
2941 .num_ports = 2,
2942 .base_baud = 115200,
2943 .uart_offset = 8,
2944 },
2945 [pbn_b1_bt_4_115200] = {
2946 .flags = FL_BASE1|FL_BASE_BARS,
2947 .num_ports = 4,
2948 .base_baud = 115200,
2949 .uart_offset = 8,
2950 },
2951
2952 [pbn_b1_bt_2_921600] = {
2953 .flags = FL_BASE1|FL_BASE_BARS,
2954 .num_ports = 2,
2955 .base_baud = 921600,
2956 .uart_offset = 8,
2957 },
2958
2959 [pbn_b1_1_1382400] = {
2960 .flags = FL_BASE1,
2961 .num_ports = 1,
2962 .base_baud = 1382400,
2963 .uart_offset = 8,
2964 },
2965 [pbn_b1_2_1382400] = {
2966 .flags = FL_BASE1,
2967 .num_ports = 2,
2968 .base_baud = 1382400,
2969 .uart_offset = 8,
2970 },
2971 [pbn_b1_4_1382400] = {
2972 .flags = FL_BASE1,
2973 .num_ports = 4,
2974 .base_baud = 1382400,
2975 .uart_offset = 8,
2976 },
2977 [pbn_b1_8_1382400] = {
2978 .flags = FL_BASE1,
2979 .num_ports = 8,
2980 .base_baud = 1382400,
2981 .uart_offset = 8,
2982 },
2983
2984 [pbn_b2_1_115200] = {
2985 .flags = FL_BASE2,
2986 .num_ports = 1,
2987 .base_baud = 115200,
2988 .uart_offset = 8,
2989 },
2990 [pbn_b2_2_115200] = {
2991 .flags = FL_BASE2,
2992 .num_ports = 2,
2993 .base_baud = 115200,
2994 .uart_offset = 8,
2995 },
2996 [pbn_b2_4_115200] = {
2997 .flags = FL_BASE2,
2998 .num_ports = 4,
2999 .base_baud = 115200,
3000 .uart_offset = 8,
3001 },
3002 [pbn_b2_8_115200] = {
3003 .flags = FL_BASE2,
3004 .num_ports = 8,
3005 .base_baud = 115200,
3006 .uart_offset = 8,
3007 },
3008
3009 [pbn_b2_1_460800] = {
3010 .flags = FL_BASE2,
3011 .num_ports = 1,
3012 .base_baud = 460800,
3013 .uart_offset = 8,
3014 },
3015 [pbn_b2_4_460800] = {
3016 .flags = FL_BASE2,
3017 .num_ports = 4,
3018 .base_baud = 460800,
3019 .uart_offset = 8,
3020 },
3021 [pbn_b2_8_460800] = {
3022 .flags = FL_BASE2,
3023 .num_ports = 8,
3024 .base_baud = 460800,
3025 .uart_offset = 8,
3026 },
3027 [pbn_b2_16_460800] = {
3028 .flags = FL_BASE2,
3029 .num_ports = 16,
3030 .base_baud = 460800,
3031 .uart_offset = 8,
3032 },
3033
3034 [pbn_b2_1_921600] = {
3035 .flags = FL_BASE2,
3036 .num_ports = 1,
3037 .base_baud = 921600,
3038 .uart_offset = 8,
3039 },
3040 [pbn_b2_4_921600] = {
3041 .flags = FL_BASE2,
3042 .num_ports = 4,
3043 .base_baud = 921600,
3044 .uart_offset = 8,
3045 },
3046 [pbn_b2_8_921600] = {
3047 .flags = FL_BASE2,
3048 .num_ports = 8,
3049 .base_baud = 921600,
3050 .uart_offset = 8,
3051 },
3052
3053 [pbn_b2_8_1152000] = {
3054 .flags = FL_BASE2,
3055 .num_ports = 8,
3056 .base_baud = 1152000,
3057 .uart_offset = 8,
3058 },
3059
3060 [pbn_b2_bt_1_115200] = {
3061 .flags = FL_BASE2|FL_BASE_BARS,
3062 .num_ports = 1,
3063 .base_baud = 115200,
3064 .uart_offset = 8,
3065 },
3066 [pbn_b2_bt_2_115200] = {
3067 .flags = FL_BASE2|FL_BASE_BARS,
3068 .num_ports = 2,
3069 .base_baud = 115200,
3070 .uart_offset = 8,
3071 },
3072 [pbn_b2_bt_4_115200] = {
3073 .flags = FL_BASE2|FL_BASE_BARS,
3074 .num_ports = 4,
3075 .base_baud = 115200,
3076 .uart_offset = 8,
3077 },
3078
3079 [pbn_b2_bt_2_921600] = {
3080 .flags = FL_BASE2|FL_BASE_BARS,
3081 .num_ports = 2,
3082 .base_baud = 921600,
3083 .uart_offset = 8,
3084 },
3085 [pbn_b2_bt_4_921600] = {
3086 .flags = FL_BASE2|FL_BASE_BARS,
3087 .num_ports = 4,
3088 .base_baud = 921600,
3089 .uart_offset = 8,
3090 },
3091
3092 [pbn_b3_2_115200] = {
3093 .flags = FL_BASE3,
3094 .num_ports = 2,
3095 .base_baud = 115200,
3096 .uart_offset = 8,
3097 },
3098 [pbn_b3_4_115200] = {
3099 .flags = FL_BASE3,
3100 .num_ports = 4,
3101 .base_baud = 115200,
3102 .uart_offset = 8,
3103 },
3104 [pbn_b3_8_115200] = {
3105 .flags = FL_BASE3,
3106 .num_ports = 8,
3107 .base_baud = 115200,
3108 .uart_offset = 8,
3109 },
3110
3111 [pbn_b4_bt_2_921600] = {
3112 .flags = FL_BASE4,
3113 .num_ports = 2,
3114 .base_baud = 921600,
3115 .uart_offset = 8,
3116 },
3117 [pbn_b4_bt_4_921600] = {
3118 .flags = FL_BASE4,
3119 .num_ports = 4,
3120 .base_baud = 921600,
3121 .uart_offset = 8,
3122 },
3123 [pbn_b4_bt_8_921600] = {
3124 .flags = FL_BASE4,
3125 .num_ports = 8,
3126 .base_baud = 921600,
3127 .uart_offset = 8,
3128 },
3129
3130 /*
3131 * Entries following this are board-specific.
3132 */
3133
3134 /*
3135 * Panacom - IOMEM
3136 */
3137 [pbn_panacom] = {
3138 .flags = FL_BASE2,
3139 .num_ports = 2,
3140 .base_baud = 921600,
3141 .uart_offset = 0x400,
3142 .reg_shift = 7,
3143 },
3144 [pbn_panacom2] = {
3145 .flags = FL_BASE2|FL_BASE_BARS,
3146 .num_ports = 2,
3147 .base_baud = 921600,
3148 .uart_offset = 0x400,
3149 .reg_shift = 7,
3150 },
3151 [pbn_panacom4] = {
3152 .flags = FL_BASE2|FL_BASE_BARS,
3153 .num_ports = 4,
3154 .base_baud = 921600,
3155 .uart_offset = 0x400,
3156 .reg_shift = 7,
3157 },
3158
3159 /* I think this entry is broken - the first_offset looks wrong --rmk */
3160 [pbn_plx_romulus] = {
3161 .flags = FL_BASE2,
3162 .num_ports = 4,
3163 .base_baud = 921600,
3164 .uart_offset = 8 << 2,
3165 .reg_shift = 2,
3166 .first_offset = 0x03,
3167 },
3168
3169 /*
3170 * EndRun Technologies
3171 * Uses the size of PCI Base region 0 to
3172 * signal now many ports are available
3173 * 2 port 952 Uart support
3174 */
3175 [pbn_endrun_2_4000000] = {
3176 .flags = FL_BASE0,
3177 .num_ports = 2,
3178 .base_baud = 4000000,
3179 .uart_offset = 0x200,
3180 .first_offset = 0x1000,
3181 },
3182
3183 /*
3184 * This board uses the size of PCI Base region 0 to
3185 * signal now many ports are available
3186 */
3187 [pbn_oxsemi] = {
3188 .flags = FL_BASE0|FL_REGION_SZ_CAP,
3189 .num_ports = 32,
3190 .base_baud = 115200,
3191 .uart_offset = 8,
3192 },
3193 [pbn_oxsemi_1_4000000] = {
3194 .flags = FL_BASE0,
3195 .num_ports = 1,
3196 .base_baud = 4000000,
3197 .uart_offset = 0x200,
3198 .first_offset = 0x1000,
3199 },
3200 [pbn_oxsemi_2_4000000] = {
3201 .flags = FL_BASE0,
3202 .num_ports = 2,
3203 .base_baud = 4000000,
3204 .uart_offset = 0x200,
3205 .first_offset = 0x1000,
3206 },
3207 [pbn_oxsemi_4_4000000] = {
3208 .flags = FL_BASE0,
3209 .num_ports = 4,
3210 .base_baud = 4000000,
3211 .uart_offset = 0x200,
3212 .first_offset = 0x1000,
3213 },
3214 [pbn_oxsemi_8_4000000] = {
3215 .flags = FL_BASE0,
3216 .num_ports = 8,
3217 .base_baud = 4000000,
3218 .uart_offset = 0x200,
3219 .first_offset = 0x1000,
3220 },
3221
3222
3223 /*
3224 * EKF addition for i960 Boards form EKF with serial port.
3225 * Max 256 ports.
3226 */
3227 [pbn_intel_i960] = {
3228 .flags = FL_BASE0,
3229 .num_ports = 32,
3230 .base_baud = 921600,
3231 .uart_offset = 8 << 2,
3232 .reg_shift = 2,
3233 .first_offset = 0x10000,
3234 },
3235 [pbn_sgi_ioc3] = {
3236 .flags = FL_BASE0|FL_NOIRQ,
3237 .num_ports = 1,
3238 .base_baud = 458333,
3239 .uart_offset = 8,
3240 .reg_shift = 0,
3241 .first_offset = 0x20178,
3242 },
3243
3244 /*
3245 * Computone - uses IOMEM.
3246 */
3247 [pbn_computone_4] = {
3248 .flags = FL_BASE0,
3249 .num_ports = 4,
3250 .base_baud = 921600,
3251 .uart_offset = 0x40,
3252 .reg_shift = 2,
3253 .first_offset = 0x200,
3254 },
3255 [pbn_computone_6] = {
3256 .flags = FL_BASE0,
3257 .num_ports = 6,
3258 .base_baud = 921600,
3259 .uart_offset = 0x40,
3260 .reg_shift = 2,
3261 .first_offset = 0x200,
3262 },
3263 [pbn_computone_8] = {
3264 .flags = FL_BASE0,
3265 .num_ports = 8,
3266 .base_baud = 921600,
3267 .uart_offset = 0x40,
3268 .reg_shift = 2,
3269 .first_offset = 0x200,
3270 },
3271 [pbn_sbsxrsio] = {
3272 .flags = FL_BASE0,
3273 .num_ports = 8,
3274 .base_baud = 460800,
3275 .uart_offset = 256,
3276 .reg_shift = 4,
3277 },
3278 /*
3279 * PA Semi PWRficient PA6T-1682M on-chip UART
3280 */
3281 [pbn_pasemi_1682M] = {
3282 .flags = FL_BASE0,
3283 .num_ports = 1,
3284 .base_baud = 8333333,
3285 },
3286 /*
3287 * National Instruments 843x
3288 */
3289 [pbn_ni8430_16] = {
3290 .flags = FL_BASE0,
3291 .num_ports = 16,
3292 .base_baud = 3686400,
3293 .uart_offset = 0x10,
3294 .first_offset = 0x800,
3295 },
3296 [pbn_ni8430_8] = {
3297 .flags = FL_BASE0,
3298 .num_ports = 8,
3299 .base_baud = 3686400,
3300 .uart_offset = 0x10,
3301 .first_offset = 0x800,
3302 },
3303 [pbn_ni8430_4] = {
3304 .flags = FL_BASE0,
3305 .num_ports = 4,
3306 .base_baud = 3686400,
3307 .uart_offset = 0x10,
3308 .first_offset = 0x800,
3309 },
3310 [pbn_ni8430_2] = {
3311 .flags = FL_BASE0,
3312 .num_ports = 2,
3313 .base_baud = 3686400,
3314 .uart_offset = 0x10,
3315 .first_offset = 0x800,
3316 },
3317 /*
3318 * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3319 */
3320 [pbn_ADDIDATA_PCIe_1_3906250] = {
3321 .flags = FL_BASE0,
3322 .num_ports = 1,
3323 .base_baud = 3906250,
3324 .uart_offset = 0x200,
3325 .first_offset = 0x1000,
3326 },
3327 [pbn_ADDIDATA_PCIe_2_3906250] = {
3328 .flags = FL_BASE0,
3329 .num_ports = 2,
3330 .base_baud = 3906250,
3331 .uart_offset = 0x200,
3332 .first_offset = 0x1000,
3333 },
3334 [pbn_ADDIDATA_PCIe_4_3906250] = {
3335 .flags = FL_BASE0,
3336 .num_ports = 4,
3337 .base_baud = 3906250,
3338 .uart_offset = 0x200,
3339 .first_offset = 0x1000,
3340 },
3341 [pbn_ADDIDATA_PCIe_8_3906250] = {
3342 .flags = FL_BASE0,
3343 .num_ports = 8,
3344 .base_baud = 3906250,
3345 .uart_offset = 0x200,
3346 .first_offset = 0x1000,
3347 },
3348 [pbn_ce4100_1_115200] = {
3349 .flags = FL_BASE_BARS,
3350 .num_ports = 2,
3351 .base_baud = 921600,
3352 .reg_shift = 2,
3353 },
3354 [pbn_omegapci] = {
3355 .flags = FL_BASE0,
3356 .num_ports = 8,
3357 .base_baud = 115200,
3358 .uart_offset = 0x200,
3359 },
3360 [pbn_NETMOS9900_2s_115200] = {
3361 .flags = FL_BASE0,
3362 .num_ports = 2,
3363 .base_baud = 115200,
3364 },
3365 [pbn_brcm_trumanage] = {
3366 .flags = FL_BASE0,
3367 .num_ports = 1,
3368 .reg_shift = 2,
3369 .base_baud = 115200,
3370 },
3371 [pbn_fintek_4] = {
3372 .num_ports = 4,
3373 .uart_offset = 8,
3374 .base_baud = 115200,
3375 .first_offset = 0x40,
3376 },
3377 [pbn_fintek_8] = {
3378 .num_ports = 8,
3379 .uart_offset = 8,
3380 .base_baud = 115200,
3381 .first_offset = 0x40,
3382 },
3383 [pbn_fintek_12] = {
3384 .num_ports = 12,
3385 .uart_offset = 8,
3386 .base_baud = 115200,
3387 .first_offset = 0x40,
3388 },
3389 [pbn_wch382_2] = {
3390 .flags = FL_BASE0,
3391 .num_ports = 2,
3392 .base_baud = 115200,
3393 .uart_offset = 8,
3394 .first_offset = 0xC0,
3395 },
3396 [pbn_wch384_4] = {
3397 .flags = FL_BASE0,
3398 .num_ports = 4,
3399 .base_baud = 115200,
3400 .uart_offset = 8,
3401 .first_offset = 0xC0,
3402 },
3403 /*
3404 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3405 */
3406 [pbn_pericom_PI7C9X7951] = {
3407 .flags = FL_BASE0,
3408 .num_ports = 1,
3409 .base_baud = 921600,
3410 .uart_offset = 0x8,
3411 },
3412 [pbn_pericom_PI7C9X7952] = {
3413 .flags = FL_BASE0,
3414 .num_ports = 2,
3415 .base_baud = 921600,
3416 .uart_offset = 0x8,
3417 },
3418 [pbn_pericom_PI7C9X7954] = {
3419 .flags = FL_BASE0,
3420 .num_ports = 4,
3421 .base_baud = 921600,
3422 .uart_offset = 0x8,
3423 },
3424 [pbn_pericom_PI7C9X7958] = {
3425 .flags = FL_BASE0,
3426 .num_ports = 8,
3427 .base_baud = 921600,
3428 .uart_offset = 0x8,
3429 },
3430 };
3431
3432 static const struct pci_device_id blacklist[] = {
3433 /* softmodems */
3434 { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3435 { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3436 { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3437
3438 /* multi-io cards handled by parport_serial */
3439 { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3440 { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3441 { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3442
3443 /* Moxa Smartio MUE boards handled by 8250_moxa */
3444 { PCI_VDEVICE(MOXA, 0x1024), },
3445 { PCI_VDEVICE(MOXA, 0x1025), },
3446 { PCI_VDEVICE(MOXA, 0x1045), },
3447 { PCI_VDEVICE(MOXA, 0x1144), },
3448 { PCI_VDEVICE(MOXA, 0x1160), },
3449 { PCI_VDEVICE(MOXA, 0x1161), },
3450 { PCI_VDEVICE(MOXA, 0x1182), },
3451 { PCI_VDEVICE(MOXA, 0x1183), },
3452 { PCI_VDEVICE(MOXA, 0x1322), },
3453 { PCI_VDEVICE(MOXA, 0x1342), },
3454 { PCI_VDEVICE(MOXA, 0x1381), },
3455 { PCI_VDEVICE(MOXA, 0x1683), },
3456
3457 /* Intel platforms with MID UART */
3458 { PCI_VDEVICE(INTEL, 0x081b), },
3459 { PCI_VDEVICE(INTEL, 0x081c), },
3460 { PCI_VDEVICE(INTEL, 0x081d), },
3461 { PCI_VDEVICE(INTEL, 0x1191), },
3462 { PCI_VDEVICE(INTEL, 0x18d8), },
3463 { PCI_VDEVICE(INTEL, 0x19d8), },
3464
3465 /* Intel platforms with DesignWare UART */
3466 { PCI_VDEVICE(INTEL, 0x0936), },
3467 { PCI_VDEVICE(INTEL, 0x0f0a), },
3468 { PCI_VDEVICE(INTEL, 0x0f0c), },
3469 { PCI_VDEVICE(INTEL, 0x228a), },
3470 { PCI_VDEVICE(INTEL, 0x228c), },
3471 { PCI_VDEVICE(INTEL, 0x9ce3), },
3472 { PCI_VDEVICE(INTEL, 0x9ce4), },
3473
3474 /* Exar devices */
3475 { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3476 { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3477 };
3478
serial_pci_is_class_communication(struct pci_dev * dev)3479 static int serial_pci_is_class_communication(struct pci_dev *dev)
3480 {
3481 /*
3482 * If it is not a communications device or the programming
3483 * interface is greater than 6, give up.
3484 */
3485 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3486 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3487 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3488 (dev->class & 0xff) > 6)
3489 return -ENODEV;
3490
3491 return 0;
3492 }
3493
serial_pci_is_blacklisted(struct pci_dev * dev)3494 static int serial_pci_is_blacklisted(struct pci_dev *dev)
3495 {
3496 const struct pci_device_id *bldev;
3497
3498 /*
3499 * Do not access blacklisted devices that are known not to
3500 * feature serial ports or are handled by other modules.
3501 */
3502 for (bldev = blacklist;
3503 bldev < blacklist + ARRAY_SIZE(blacklist);
3504 bldev++) {
3505 if (dev->vendor == bldev->vendor &&
3506 dev->device == bldev->device)
3507 return -ENODEV;
3508 }
3509
3510 return 0;
3511 }
3512
3513 /*
3514 * Given a complete unknown PCI device, try to use some heuristics to
3515 * guess what the configuration might be, based on the pitiful PCI
3516 * serial specs. Returns 0 on success, -ENODEV on failure.
3517 */
3518 static int
serial_pci_guess_board(struct pci_dev * dev,struct pciserial_board * board)3519 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3520 {
3521 int num_iomem, num_port, first_port = -1, i;
3522 int rc;
3523
3524 rc = serial_pci_is_class_communication(dev);
3525 if (rc)
3526 return rc;
3527
3528 /*
3529 * Should we try to make guesses for multiport serial devices later?
3530 */
3531 if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3532 return -ENODEV;
3533
3534 num_iomem = num_port = 0;
3535 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3536 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3537 num_port++;
3538 if (first_port == -1)
3539 first_port = i;
3540 }
3541 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3542 num_iomem++;
3543 }
3544
3545 /*
3546 * If there is 1 or 0 iomem regions, and exactly one port,
3547 * use it. We guess the number of ports based on the IO
3548 * region size.
3549 */
3550 if (num_iomem <= 1 && num_port == 1) {
3551 board->flags = first_port;
3552 board->num_ports = pci_resource_len(dev, first_port) / 8;
3553 return 0;
3554 }
3555
3556 /*
3557 * Now guess if we've got a board which indexes by BARs.
3558 * Each IO BAR should be 8 bytes, and they should follow
3559 * consecutively.
3560 */
3561 first_port = -1;
3562 num_port = 0;
3563 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
3564 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3565 pci_resource_len(dev, i) == 8 &&
3566 (first_port == -1 || (first_port + num_port) == i)) {
3567 num_port++;
3568 if (first_port == -1)
3569 first_port = i;
3570 }
3571 }
3572
3573 if (num_port > 1) {
3574 board->flags = first_port | FL_BASE_BARS;
3575 board->num_ports = num_port;
3576 return 0;
3577 }
3578
3579 return -ENODEV;
3580 }
3581
3582 static inline int
serial_pci_matches(const struct pciserial_board * board,const struct pciserial_board * guessed)3583 serial_pci_matches(const struct pciserial_board *board,
3584 const struct pciserial_board *guessed)
3585 {
3586 return
3587 board->num_ports == guessed->num_ports &&
3588 board->base_baud == guessed->base_baud &&
3589 board->uart_offset == guessed->uart_offset &&
3590 board->reg_shift == guessed->reg_shift &&
3591 board->first_offset == guessed->first_offset;
3592 }
3593
3594 struct serial_private *
pciserial_init_ports(struct pci_dev * dev,const struct pciserial_board * board)3595 pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3596 {
3597 struct uart_8250_port uart;
3598 struct serial_private *priv;
3599 struct pci_serial_quirk *quirk;
3600 int rc, nr_ports, i;
3601
3602 nr_ports = board->num_ports;
3603
3604 /*
3605 * Find an init and setup quirks.
3606 */
3607 quirk = find_quirk(dev);
3608
3609 /*
3610 * Run the new-style initialization function.
3611 * The initialization function returns:
3612 * <0 - error
3613 * 0 - use board->num_ports
3614 * >0 - number of ports
3615 */
3616 if (quirk->init) {
3617 rc = quirk->init(dev);
3618 if (rc < 0) {
3619 priv = ERR_PTR(rc);
3620 goto err_out;
3621 }
3622 if (rc)
3623 nr_ports = rc;
3624 }
3625
3626 priv = kzalloc(sizeof(struct serial_private) +
3627 sizeof(unsigned int) * nr_ports,
3628 GFP_KERNEL);
3629 if (!priv) {
3630 priv = ERR_PTR(-ENOMEM);
3631 goto err_deinit;
3632 }
3633
3634 priv->dev = dev;
3635 priv->quirk = quirk;
3636
3637 memset(&uart, 0, sizeof(uart));
3638 uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3639 uart.port.uartclk = board->base_baud * 16;
3640 uart.port.irq = get_pci_irq(dev, board);
3641 uart.port.dev = &dev->dev;
3642
3643 for (i = 0; i < nr_ports; i++) {
3644 if (quirk->setup(priv, board, &uart, i))
3645 break;
3646
3647 dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
3648 uart.port.iobase, uart.port.irq, uart.port.iotype);
3649
3650 priv->line[i] = serial8250_register_8250_port(&uart);
3651 if (priv->line[i] < 0) {
3652 dev_err(&dev->dev,
3653 "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
3654 uart.port.iobase, uart.port.irq,
3655 uart.port.iotype, priv->line[i]);
3656 break;
3657 }
3658 }
3659 priv->nr = i;
3660 priv->board = board;
3661 return priv;
3662
3663 err_deinit:
3664 if (quirk->exit)
3665 quirk->exit(dev);
3666 err_out:
3667 return priv;
3668 }
3669 EXPORT_SYMBOL_GPL(pciserial_init_ports);
3670
pciserial_detach_ports(struct serial_private * priv)3671 static void pciserial_detach_ports(struct serial_private *priv)
3672 {
3673 struct pci_serial_quirk *quirk;
3674 int i;
3675
3676 for (i = 0; i < priv->nr; i++)
3677 serial8250_unregister_port(priv->line[i]);
3678
3679 /*
3680 * Find the exit quirks.
3681 */
3682 quirk = find_quirk(priv->dev);
3683 if (quirk->exit)
3684 quirk->exit(priv->dev);
3685 }
3686
pciserial_remove_ports(struct serial_private * priv)3687 void pciserial_remove_ports(struct serial_private *priv)
3688 {
3689 pciserial_detach_ports(priv);
3690 kfree(priv);
3691 }
3692 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
3693
pciserial_suspend_ports(struct serial_private * priv)3694 void pciserial_suspend_ports(struct serial_private *priv)
3695 {
3696 int i;
3697
3698 for (i = 0; i < priv->nr; i++)
3699 if (priv->line[i] >= 0)
3700 serial8250_suspend_port(priv->line[i]);
3701
3702 /*
3703 * Ensure that every init quirk is properly torn down
3704 */
3705 if (priv->quirk->exit)
3706 priv->quirk->exit(priv->dev);
3707 }
3708 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
3709
pciserial_resume_ports(struct serial_private * priv)3710 void pciserial_resume_ports(struct serial_private *priv)
3711 {
3712 int i;
3713
3714 /*
3715 * Ensure that the board is correctly configured.
3716 */
3717 if (priv->quirk->init)
3718 priv->quirk->init(priv->dev);
3719
3720 for (i = 0; i < priv->nr; i++)
3721 if (priv->line[i] >= 0)
3722 serial8250_resume_port(priv->line[i]);
3723 }
3724 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
3725
3726 /*
3727 * Probe one serial board. Unfortunately, there is no rhyme nor reason
3728 * to the arrangement of serial ports on a PCI card.
3729 */
3730 static int
pciserial_init_one(struct pci_dev * dev,const struct pci_device_id * ent)3731 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
3732 {
3733 struct pci_serial_quirk *quirk;
3734 struct serial_private *priv;
3735 const struct pciserial_board *board;
3736 struct pciserial_board tmp;
3737 int rc;
3738
3739 quirk = find_quirk(dev);
3740 if (quirk->probe) {
3741 rc = quirk->probe(dev);
3742 if (rc)
3743 return rc;
3744 }
3745
3746 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
3747 dev_err(&dev->dev, "invalid driver_data: %ld\n",
3748 ent->driver_data);
3749 return -EINVAL;
3750 }
3751
3752 board = &pci_boards[ent->driver_data];
3753
3754 rc = serial_pci_is_blacklisted(dev);
3755 if (rc)
3756 return rc;
3757
3758 rc = pcim_enable_device(dev);
3759 pci_save_state(dev);
3760 if (rc)
3761 return rc;
3762
3763 if (ent->driver_data == pbn_default) {
3764 /*
3765 * Use a copy of the pci_board entry for this;
3766 * avoid changing entries in the table.
3767 */
3768 memcpy(&tmp, board, sizeof(struct pciserial_board));
3769 board = &tmp;
3770
3771 /*
3772 * We matched one of our class entries. Try to
3773 * determine the parameters of this board.
3774 */
3775 rc = serial_pci_guess_board(dev, &tmp);
3776 if (rc)
3777 return rc;
3778 } else {
3779 /*
3780 * We matched an explicit entry. If we are able to
3781 * detect this boards settings with our heuristic,
3782 * then we no longer need this entry.
3783 */
3784 memcpy(&tmp, &pci_boards[pbn_default],
3785 sizeof(struct pciserial_board));
3786 rc = serial_pci_guess_board(dev, &tmp);
3787 if (rc == 0 && serial_pci_matches(board, &tmp))
3788 moan_device("Redundant entry in serial pci_table.",
3789 dev);
3790 }
3791
3792 priv = pciserial_init_ports(dev, board);
3793 if (IS_ERR(priv))
3794 return PTR_ERR(priv);
3795
3796 pci_set_drvdata(dev, priv);
3797 return 0;
3798 }
3799
pciserial_remove_one(struct pci_dev * dev)3800 static void pciserial_remove_one(struct pci_dev *dev)
3801 {
3802 struct serial_private *priv = pci_get_drvdata(dev);
3803
3804 pciserial_remove_ports(priv);
3805 }
3806
3807 #ifdef CONFIG_PM_SLEEP
pciserial_suspend_one(struct device * dev)3808 static int pciserial_suspend_one(struct device *dev)
3809 {
3810 struct pci_dev *pdev = to_pci_dev(dev);
3811 struct serial_private *priv = pci_get_drvdata(pdev);
3812
3813 if (priv)
3814 pciserial_suspend_ports(priv);
3815
3816 return 0;
3817 }
3818
pciserial_resume_one(struct device * dev)3819 static int pciserial_resume_one(struct device *dev)
3820 {
3821 struct pci_dev *pdev = to_pci_dev(dev);
3822 struct serial_private *priv = pci_get_drvdata(pdev);
3823 int err;
3824
3825 if (priv) {
3826 /*
3827 * The device may have been disabled. Re-enable it.
3828 */
3829 err = pci_enable_device(pdev);
3830 /* FIXME: We cannot simply error out here */
3831 if (err)
3832 dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
3833 pciserial_resume_ports(priv);
3834 }
3835 return 0;
3836 }
3837 #endif
3838
3839 static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
3840 pciserial_resume_one);
3841
3842 static const struct pci_device_id serial_pci_tbl[] = {
3843 /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
3844 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
3845 PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
3846 pbn_b2_8_921600 },
3847 /* Advantech also use 0x3618 and 0xf618 */
3848 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
3849 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3850 pbn_b0_4_921600 },
3851 { PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
3852 PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
3853 pbn_b0_4_921600 },
3854 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3855 PCI_SUBVENDOR_ID_CONNECT_TECH,
3856 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3857 pbn_b1_8_1382400 },
3858 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3859 PCI_SUBVENDOR_ID_CONNECT_TECH,
3860 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3861 pbn_b1_4_1382400 },
3862 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
3863 PCI_SUBVENDOR_ID_CONNECT_TECH,
3864 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3865 pbn_b1_2_1382400 },
3866 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3867 PCI_SUBVENDOR_ID_CONNECT_TECH,
3868 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
3869 pbn_b1_8_1382400 },
3870 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3871 PCI_SUBVENDOR_ID_CONNECT_TECH,
3872 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
3873 pbn_b1_4_1382400 },
3874 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3875 PCI_SUBVENDOR_ID_CONNECT_TECH,
3876 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
3877 pbn_b1_2_1382400 },
3878 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3879 PCI_SUBVENDOR_ID_CONNECT_TECH,
3880 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
3881 pbn_b1_8_921600 },
3882 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3883 PCI_SUBVENDOR_ID_CONNECT_TECH,
3884 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
3885 pbn_b1_8_921600 },
3886 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3887 PCI_SUBVENDOR_ID_CONNECT_TECH,
3888 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
3889 pbn_b1_4_921600 },
3890 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3891 PCI_SUBVENDOR_ID_CONNECT_TECH,
3892 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
3893 pbn_b1_4_921600 },
3894 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3895 PCI_SUBVENDOR_ID_CONNECT_TECH,
3896 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
3897 pbn_b1_2_921600 },
3898 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3899 PCI_SUBVENDOR_ID_CONNECT_TECH,
3900 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
3901 pbn_b1_8_921600 },
3902 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3903 PCI_SUBVENDOR_ID_CONNECT_TECH,
3904 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
3905 pbn_b1_8_921600 },
3906 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3907 PCI_SUBVENDOR_ID_CONNECT_TECH,
3908 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
3909 pbn_b1_4_921600 },
3910 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
3911 PCI_SUBVENDOR_ID_CONNECT_TECH,
3912 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
3913 pbn_b1_2_1250000 },
3914 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3915 PCI_SUBVENDOR_ID_CONNECT_TECH,
3916 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
3917 pbn_b0_2_1843200 },
3918 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3919 PCI_SUBVENDOR_ID_CONNECT_TECH,
3920 PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
3921 pbn_b0_4_1843200 },
3922 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
3923 PCI_VENDOR_ID_AFAVLAB,
3924 PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
3925 pbn_b0_4_1152000 },
3926 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
3927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3928 pbn_b2_bt_1_115200 },
3929 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
3930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3931 pbn_b2_bt_2_115200 },
3932 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
3933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3934 pbn_b2_bt_4_115200 },
3935 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
3936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3937 pbn_b2_bt_2_115200 },
3938 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
3939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3940 pbn_b2_bt_4_115200 },
3941 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
3942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3943 pbn_b2_8_115200 },
3944 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
3945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3946 pbn_b2_8_460800 },
3947 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
3948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3949 pbn_b2_8_115200 },
3950
3951 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
3952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3953 pbn_b2_bt_2_115200 },
3954 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
3955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3956 pbn_b2_bt_2_921600 },
3957 /*
3958 * VScom SPCOM800, from sl@s.pl
3959 */
3960 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
3961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3962 pbn_b2_8_921600 },
3963 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
3964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3965 pbn_b2_4_921600 },
3966 /* Unknown card - subdevice 0x1584 */
3967 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3968 PCI_VENDOR_ID_PLX,
3969 PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
3970 pbn_b2_4_115200 },
3971 /* Unknown card - subdevice 0x1588 */
3972 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3973 PCI_VENDOR_ID_PLX,
3974 PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
3975 pbn_b2_8_115200 },
3976 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3977 PCI_SUBVENDOR_ID_KEYSPAN,
3978 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
3979 pbn_panacom },
3980 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
3981 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3982 pbn_panacom4 },
3983 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
3984 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
3985 pbn_panacom2 },
3986 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
3987 PCI_VENDOR_ID_ESDGMBH,
3988 PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
3989 pbn_b2_4_115200 },
3990 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3991 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3992 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
3993 pbn_b2_4_460800 },
3994 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3995 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
3996 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
3997 pbn_b2_8_460800 },
3998 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
3999 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4000 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4001 pbn_b2_16_460800 },
4002 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4003 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4004 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4005 pbn_b2_16_460800 },
4006 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4007 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4008 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4009 pbn_b2_4_460800 },
4010 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4011 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4012 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4013 pbn_b2_8_460800 },
4014 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4015 PCI_SUBVENDOR_ID_EXSYS,
4016 PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4017 pbn_b2_4_115200 },
4018 /*
4019 * Megawolf Romulus PCI Serial Card, from Mike Hudson
4020 * (Exoray@isys.ca)
4021 */
4022 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4023 0x10b5, 0x106a, 0, 0,
4024 pbn_plx_romulus },
4025 /*
4026 * EndRun Technologies. PCI express device range.
4027 * EndRun PTP/1588 has 2 Native UARTs.
4028 */
4029 { PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4031 pbn_endrun_2_4000000 },
4032 /*
4033 * Quatech cards. These actually have configurable clocks but for
4034 * now we just use the default.
4035 *
4036 * 100 series are RS232, 200 series RS422,
4037 */
4038 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4039 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4040 pbn_b1_4_115200 },
4041 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4042 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4043 pbn_b1_2_115200 },
4044 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4045 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4046 pbn_b2_2_115200 },
4047 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4048 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4049 pbn_b1_2_115200 },
4050 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4051 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4052 pbn_b2_2_115200 },
4053 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4054 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4055 pbn_b1_4_115200 },
4056 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4057 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4058 pbn_b1_8_115200 },
4059 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4060 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4061 pbn_b1_8_115200 },
4062 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4063 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4064 pbn_b1_4_115200 },
4065 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4066 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4067 pbn_b1_2_115200 },
4068 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4069 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4070 pbn_b1_4_115200 },
4071 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4072 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4073 pbn_b1_2_115200 },
4074 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4075 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4076 pbn_b2_4_115200 },
4077 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP100,
4078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4079 pbn_b2_2_115200 },
4080 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP100,
4081 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4082 pbn_b2_1_115200 },
4083 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP200,
4084 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4085 pbn_b2_4_115200 },
4086 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCLP200,
4087 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4088 pbn_b2_2_115200 },
4089 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_SSCLP200,
4090 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4091 pbn_b2_1_115200 },
4092 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESCLP100,
4093 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4094 pbn_b0_8_115200 },
4095
4096 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
4097 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4,
4098 0, 0,
4099 pbn_b0_4_921600 },
4100 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4101 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL,
4102 0, 0,
4103 pbn_b0_4_1152000 },
4104 { PCI_VENDOR_ID_OXSEMI, 0x9505,
4105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4106 pbn_b0_bt_2_921600 },
4107
4108 /*
4109 * The below card is a little controversial since it is the
4110 * subject of a PCI vendor/device ID clash. (See
4111 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
4112 * For now just used the hex ID 0x950a.
4113 */
4114 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4115 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_00,
4116 0, 0, pbn_b0_2_115200 },
4117 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4118 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_DUAL_30,
4119 0, 0, pbn_b0_2_115200 },
4120 { PCI_VENDOR_ID_OXSEMI, 0x950a,
4121 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4122 pbn_b0_2_1130000 },
4123 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_C950,
4124 PCI_VENDOR_ID_OXSEMI, PCI_SUBDEVICE_ID_OXSEMI_C950, 0, 0,
4125 pbn_b0_1_921600 },
4126 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4127 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4128 pbn_b0_4_115200 },
4129 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
4130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4131 pbn_b0_bt_2_921600 },
4132 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI958,
4133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4134 pbn_b2_8_1152000 },
4135
4136 /*
4137 * Oxford Semiconductor Inc. Tornado PCI express device range.
4138 */
4139 { PCI_VENDOR_ID_OXSEMI, 0xc101, /* OXPCIe952 1 Legacy UART */
4140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4141 pbn_b0_1_4000000 },
4142 { PCI_VENDOR_ID_OXSEMI, 0xc105, /* OXPCIe952 1 Legacy UART */
4143 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4144 pbn_b0_1_4000000 },
4145 { PCI_VENDOR_ID_OXSEMI, 0xc11b, /* OXPCIe952 1 Native UART */
4146 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4147 pbn_oxsemi_1_4000000 },
4148 { PCI_VENDOR_ID_OXSEMI, 0xc11f, /* OXPCIe952 1 Native UART */
4149 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4150 pbn_oxsemi_1_4000000 },
4151 { PCI_VENDOR_ID_OXSEMI, 0xc120, /* OXPCIe952 1 Legacy UART */
4152 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4153 pbn_b0_1_4000000 },
4154 { PCI_VENDOR_ID_OXSEMI, 0xc124, /* OXPCIe952 1 Legacy UART */
4155 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4156 pbn_b0_1_4000000 },
4157 { PCI_VENDOR_ID_OXSEMI, 0xc138, /* OXPCIe952 1 Native UART */
4158 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4159 pbn_oxsemi_1_4000000 },
4160 { PCI_VENDOR_ID_OXSEMI, 0xc13d, /* OXPCIe952 1 Native UART */
4161 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4162 pbn_oxsemi_1_4000000 },
4163 { PCI_VENDOR_ID_OXSEMI, 0xc140, /* OXPCIe952 1 Legacy UART */
4164 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4165 pbn_b0_1_4000000 },
4166 { PCI_VENDOR_ID_OXSEMI, 0xc141, /* OXPCIe952 1 Legacy UART */
4167 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4168 pbn_b0_1_4000000 },
4169 { PCI_VENDOR_ID_OXSEMI, 0xc144, /* OXPCIe952 1 Legacy UART */
4170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4171 pbn_b0_1_4000000 },
4172 { PCI_VENDOR_ID_OXSEMI, 0xc145, /* OXPCIe952 1 Legacy UART */
4173 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4174 pbn_b0_1_4000000 },
4175 { PCI_VENDOR_ID_OXSEMI, 0xc158, /* OXPCIe952 2 Native UART */
4176 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4177 pbn_oxsemi_2_4000000 },
4178 { PCI_VENDOR_ID_OXSEMI, 0xc15d, /* OXPCIe952 2 Native UART */
4179 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4180 pbn_oxsemi_2_4000000 },
4181 { PCI_VENDOR_ID_OXSEMI, 0xc208, /* OXPCIe954 4 Native UART */
4182 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4183 pbn_oxsemi_4_4000000 },
4184 { PCI_VENDOR_ID_OXSEMI, 0xc20d, /* OXPCIe954 4 Native UART */
4185 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4186 pbn_oxsemi_4_4000000 },
4187 { PCI_VENDOR_ID_OXSEMI, 0xc308, /* OXPCIe958 8 Native UART */
4188 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4189 pbn_oxsemi_8_4000000 },
4190 { PCI_VENDOR_ID_OXSEMI, 0xc30d, /* OXPCIe958 8 Native UART */
4191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4192 pbn_oxsemi_8_4000000 },
4193 { PCI_VENDOR_ID_OXSEMI, 0xc40b, /* OXPCIe200 1 Native UART */
4194 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4195 pbn_oxsemi_1_4000000 },
4196 { PCI_VENDOR_ID_OXSEMI, 0xc40f, /* OXPCIe200 1 Native UART */
4197 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4198 pbn_oxsemi_1_4000000 },
4199 { PCI_VENDOR_ID_OXSEMI, 0xc41b, /* OXPCIe200 1 Native UART */
4200 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4201 pbn_oxsemi_1_4000000 },
4202 { PCI_VENDOR_ID_OXSEMI, 0xc41f, /* OXPCIe200 1 Native UART */
4203 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4204 pbn_oxsemi_1_4000000 },
4205 { PCI_VENDOR_ID_OXSEMI, 0xc42b, /* OXPCIe200 1 Native UART */
4206 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4207 pbn_oxsemi_1_4000000 },
4208 { PCI_VENDOR_ID_OXSEMI, 0xc42f, /* OXPCIe200 1 Native UART */
4209 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4210 pbn_oxsemi_1_4000000 },
4211 { PCI_VENDOR_ID_OXSEMI, 0xc43b, /* OXPCIe200 1 Native UART */
4212 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4213 pbn_oxsemi_1_4000000 },
4214 { PCI_VENDOR_ID_OXSEMI, 0xc43f, /* OXPCIe200 1 Native UART */
4215 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4216 pbn_oxsemi_1_4000000 },
4217 { PCI_VENDOR_ID_OXSEMI, 0xc44b, /* OXPCIe200 1 Native UART */
4218 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4219 pbn_oxsemi_1_4000000 },
4220 { PCI_VENDOR_ID_OXSEMI, 0xc44f, /* OXPCIe200 1 Native UART */
4221 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4222 pbn_oxsemi_1_4000000 },
4223 { PCI_VENDOR_ID_OXSEMI, 0xc45b, /* OXPCIe200 1 Native UART */
4224 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4225 pbn_oxsemi_1_4000000 },
4226 { PCI_VENDOR_ID_OXSEMI, 0xc45f, /* OXPCIe200 1 Native UART */
4227 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4228 pbn_oxsemi_1_4000000 },
4229 { PCI_VENDOR_ID_OXSEMI, 0xc46b, /* OXPCIe200 1 Native UART */
4230 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4231 pbn_oxsemi_1_4000000 },
4232 { PCI_VENDOR_ID_OXSEMI, 0xc46f, /* OXPCIe200 1 Native UART */
4233 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4234 pbn_oxsemi_1_4000000 },
4235 { PCI_VENDOR_ID_OXSEMI, 0xc47b, /* OXPCIe200 1 Native UART */
4236 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4237 pbn_oxsemi_1_4000000 },
4238 { PCI_VENDOR_ID_OXSEMI, 0xc47f, /* OXPCIe200 1 Native UART */
4239 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4240 pbn_oxsemi_1_4000000 },
4241 { PCI_VENDOR_ID_OXSEMI, 0xc48b, /* OXPCIe200 1 Native UART */
4242 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4243 pbn_oxsemi_1_4000000 },
4244 { PCI_VENDOR_ID_OXSEMI, 0xc48f, /* OXPCIe200 1 Native UART */
4245 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4246 pbn_oxsemi_1_4000000 },
4247 { PCI_VENDOR_ID_OXSEMI, 0xc49b, /* OXPCIe200 1 Native UART */
4248 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4249 pbn_oxsemi_1_4000000 },
4250 { PCI_VENDOR_ID_OXSEMI, 0xc49f, /* OXPCIe200 1 Native UART */
4251 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4252 pbn_oxsemi_1_4000000 },
4253 { PCI_VENDOR_ID_OXSEMI, 0xc4ab, /* OXPCIe200 1 Native UART */
4254 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4255 pbn_oxsemi_1_4000000 },
4256 { PCI_VENDOR_ID_OXSEMI, 0xc4af, /* OXPCIe200 1 Native UART */
4257 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4258 pbn_oxsemi_1_4000000 },
4259 { PCI_VENDOR_ID_OXSEMI, 0xc4bb, /* OXPCIe200 1 Native UART */
4260 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4261 pbn_oxsemi_1_4000000 },
4262 { PCI_VENDOR_ID_OXSEMI, 0xc4bf, /* OXPCIe200 1 Native UART */
4263 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4264 pbn_oxsemi_1_4000000 },
4265 { PCI_VENDOR_ID_OXSEMI, 0xc4cb, /* OXPCIe200 1 Native UART */
4266 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4267 pbn_oxsemi_1_4000000 },
4268 { PCI_VENDOR_ID_OXSEMI, 0xc4cf, /* OXPCIe200 1 Native UART */
4269 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4270 pbn_oxsemi_1_4000000 },
4271 /*
4272 * Mainpine Inc. IQ Express "Rev3" utilizing OxSemi Tornado
4273 */
4274 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 1 Port V.34 Super-G3 Fax */
4275 PCI_VENDOR_ID_MAINPINE, 0x4001, 0, 0,
4276 pbn_oxsemi_1_4000000 },
4277 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 2 Port V.34 Super-G3 Fax */
4278 PCI_VENDOR_ID_MAINPINE, 0x4002, 0, 0,
4279 pbn_oxsemi_2_4000000 },
4280 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 4 Port V.34 Super-G3 Fax */
4281 PCI_VENDOR_ID_MAINPINE, 0x4004, 0, 0,
4282 pbn_oxsemi_4_4000000 },
4283 { PCI_VENDOR_ID_MAINPINE, 0x4000, /* IQ Express 8 Port V.34 Super-G3 Fax */
4284 PCI_VENDOR_ID_MAINPINE, 0x4008, 0, 0,
4285 pbn_oxsemi_8_4000000 },
4286
4287 /*
4288 * Digi/IBM PCIe 2-port Async EIA-232 Adapter utilizing OxSemi Tornado
4289 */
4290 { PCI_VENDOR_ID_DIGI, PCIE_DEVICE_ID_NEO_2_OX_IBM,
4291 PCI_SUBVENDOR_ID_IBM, PCI_ANY_ID, 0, 0,
4292 pbn_oxsemi_2_4000000 },
4293
4294 /*
4295 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
4296 * from skokodyn@yahoo.com
4297 */
4298 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4299 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
4300 pbn_sbsxrsio },
4301 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4302 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
4303 pbn_sbsxrsio },
4304 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4305 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
4306 pbn_sbsxrsio },
4307 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
4308 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
4309 pbn_sbsxrsio },
4310
4311 /*
4312 * Digitan DS560-558, from jimd@esoft.com
4313 */
4314 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
4315 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316 pbn_b1_1_115200 },
4317
4318 /*
4319 * Titan Electronic cards
4320 * The 400L and 800L have a custom setup quirk.
4321 */
4322 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
4323 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4324 pbn_b0_1_921600 },
4325 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
4326 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4327 pbn_b0_2_921600 },
4328 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
4329 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4330 pbn_b0_4_921600 },
4331 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
4332 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4333 pbn_b0_4_921600 },
4334 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
4335 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4336 pbn_b1_1_921600 },
4337 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
4338 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4339 pbn_b1_bt_2_921600 },
4340 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
4341 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4342 pbn_b0_bt_4_921600 },
4343 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
4344 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4345 pbn_b0_bt_8_921600 },
4346 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200I,
4347 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4348 pbn_b4_bt_2_921600 },
4349 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400I,
4350 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4351 pbn_b4_bt_4_921600 },
4352 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800I,
4353 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4354 pbn_b4_bt_8_921600 },
4355 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400EH,
4356 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4357 pbn_b0_4_921600 },
4358 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EH,
4359 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4360 pbn_b0_4_921600 },
4361 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800EHB,
4362 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4363 pbn_b0_4_921600 },
4364 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100E,
4365 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4366 pbn_oxsemi_1_4000000 },
4367 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200E,
4368 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4369 pbn_oxsemi_2_4000000 },
4370 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400E,
4371 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4372 pbn_oxsemi_4_4000000 },
4373 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800E,
4374 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4375 pbn_oxsemi_8_4000000 },
4376 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EI,
4377 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4378 pbn_oxsemi_2_4000000 },
4379 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200EISI,
4380 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4381 pbn_oxsemi_2_4000000 },
4382 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200V3,
4383 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4384 pbn_b0_bt_2_921600 },
4385 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400V3,
4386 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4387 pbn_b0_4_921600 },
4388 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_410V3,
4389 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4390 pbn_b0_4_921600 },
4391 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3,
4392 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4393 pbn_b0_4_921600 },
4394 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800V3B,
4395 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4396 pbn_b0_4_921600 },
4397
4398 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
4399 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4400 pbn_b2_1_460800 },
4401 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
4402 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4403 pbn_b2_1_460800 },
4404 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
4405 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4406 pbn_b2_1_460800 },
4407 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
4408 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4409 pbn_b2_bt_2_921600 },
4410 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
4411 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4412 pbn_b2_bt_2_921600 },
4413 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
4414 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4415 pbn_b2_bt_2_921600 },
4416 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
4417 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4418 pbn_b2_bt_4_921600 },
4419 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
4420 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4421 pbn_b2_bt_4_921600 },
4422 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
4423 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4424 pbn_b2_bt_4_921600 },
4425 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
4426 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4427 pbn_b0_1_921600 },
4428 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
4429 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4430 pbn_b0_1_921600 },
4431 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
4432 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4433 pbn_b0_1_921600 },
4434 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
4435 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4436 pbn_b0_bt_2_921600 },
4437 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
4438 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4439 pbn_b0_bt_2_921600 },
4440 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
4441 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4442 pbn_b0_bt_2_921600 },
4443 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
4444 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4445 pbn_b0_bt_4_921600 },
4446 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
4447 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4448 pbn_b0_bt_4_921600 },
4449 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
4450 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4451 pbn_b0_bt_4_921600 },
4452 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_550,
4453 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4454 pbn_b0_bt_8_921600 },
4455 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_650,
4456 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4457 pbn_b0_bt_8_921600 },
4458 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_8S_20x_850,
4459 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4460 pbn_b0_bt_8_921600 },
4461
4462 /*
4463 * Computone devices submitted by Doug McNash dmcnash@computone.com
4464 */
4465 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4466 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
4467 0, 0, pbn_computone_4 },
4468 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4469 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
4470 0, 0, pbn_computone_8 },
4471 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
4472 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
4473 0, 0, pbn_computone_6 },
4474
4475 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
4476 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4477 pbn_oxsemi },
4478 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
4479 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
4480 pbn_b0_bt_1_921600 },
4481
4482 /*
4483 * SUNIX (TIMEDIA)
4484 */
4485 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4486 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4487 PCI_CLASS_COMMUNICATION_SERIAL << 8, 0xffff00,
4488 pbn_b0_bt_1_921600 },
4489
4490 { PCI_VENDOR_ID_SUNIX, PCI_DEVICE_ID_SUNIX_1999,
4491 PCI_VENDOR_ID_SUNIX, PCI_ANY_ID,
4492 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4493 pbn_b0_bt_1_921600 },
4494
4495 /*
4496 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
4497 */
4498 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
4499 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4500 pbn_b0_bt_8_115200 },
4501 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
4502 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4503 pbn_b0_bt_8_115200 },
4504
4505 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
4506 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4507 pbn_b0_bt_2_115200 },
4508 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
4509 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4510 pbn_b0_bt_2_115200 },
4511 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
4512 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4513 pbn_b0_bt_2_115200 },
4514 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_A,
4515 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4516 pbn_b0_bt_2_115200 },
4517 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATTRO_B,
4518 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4519 pbn_b0_bt_2_115200 },
4520 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
4521 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4522 pbn_b0_bt_4_460800 },
4523 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
4524 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4525 pbn_b0_bt_4_460800 },
4526 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
4527 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4528 pbn_b0_bt_2_460800 },
4529 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
4530 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4531 pbn_b0_bt_2_460800 },
4532 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
4533 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4534 pbn_b0_bt_2_460800 },
4535 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
4536 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4537 pbn_b0_bt_1_115200 },
4538 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
4539 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4540 pbn_b0_bt_1_460800 },
4541
4542 /*
4543 * Korenix Jetcard F0/F1 cards (JC1204, JC1208, JC1404, JC1408).
4544 * Cards are identified by their subsystem vendor IDs, which
4545 * (in hex) match the model number.
4546 *
4547 * Note that JC140x are RS422/485 cards which require ox950
4548 * ACR = 0x10, and as such are not currently fully supported.
4549 */
4550 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4551 0x1204, 0x0004, 0, 0,
4552 pbn_b0_4_921600 },
4553 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4554 0x1208, 0x0004, 0, 0,
4555 pbn_b0_4_921600 },
4556 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4557 0x1402, 0x0002, 0, 0,
4558 pbn_b0_2_921600 }, */
4559 /* { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF0,
4560 0x1404, 0x0004, 0, 0,
4561 pbn_b0_4_921600 }, */
4562 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF1,
4563 0x1208, 0x0004, 0, 0,
4564 pbn_b0_4_921600 },
4565
4566 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4567 0x1204, 0x0004, 0, 0,
4568 pbn_b0_4_921600 },
4569 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF2,
4570 0x1208, 0x0004, 0, 0,
4571 pbn_b0_4_921600 },
4572 { PCI_VENDOR_ID_KORENIX, PCI_DEVICE_ID_KORENIX_JETCARDF3,
4573 0x1208, 0x0004, 0, 0,
4574 pbn_b0_4_921600 },
4575 /*
4576 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
4577 */
4578 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
4579 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4580 pbn_b1_1_1382400 },
4581
4582 /*
4583 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
4584 */
4585 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
4586 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4587 pbn_b1_1_1382400 },
4588
4589 /*
4590 * RAStel 2 port modem, gerg@moreton.com.au
4591 */
4592 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
4593 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4594 pbn_b2_bt_2_115200 },
4595
4596 /*
4597 * EKF addition for i960 Boards form EKF with serial port
4598 */
4599 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
4600 0xE4BF, PCI_ANY_ID, 0, 0,
4601 pbn_intel_i960 },
4602
4603 /*
4604 * Xircom Cardbus/Ethernet combos
4605 */
4606 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
4607 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4608 pbn_b0_1_115200 },
4609 /*
4610 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
4611 */
4612 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
4613 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4614 pbn_b0_1_115200 },
4615
4616 /*
4617 * Untested PCI modems, sent in from various folks...
4618 */
4619
4620 /*
4621 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
4622 */
4623 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
4624 0x1048, 0x1500, 0, 0,
4625 pbn_b1_1_115200 },
4626
4627 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
4628 0xFF00, 0, 0, 0,
4629 pbn_sgi_ioc3 },
4630
4631 /*
4632 * HP Diva card
4633 */
4634 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4635 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
4636 pbn_b1_1_115200 },
4637 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
4638 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4639 pbn_b0_5_115200 },
4640 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
4641 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4642 pbn_b2_1_115200 },
4643
4644 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM2,
4645 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4646 pbn_b3_2_115200 },
4647 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
4648 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4649 pbn_b3_4_115200 },
4650 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
4651 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4652 pbn_b3_8_115200 },
4653 /*
4654 * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
4655 */
4656 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7951,
4657 PCI_ANY_ID, PCI_ANY_ID,
4658 0,
4659 0, pbn_pericom_PI7C9X7951 },
4660 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7952,
4661 PCI_ANY_ID, PCI_ANY_ID,
4662 0,
4663 0, pbn_pericom_PI7C9X7952 },
4664 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7954,
4665 PCI_ANY_ID, PCI_ANY_ID,
4666 0,
4667 0, pbn_pericom_PI7C9X7954 },
4668 { PCI_VENDOR_ID_PERICOM, PCI_DEVICE_ID_PERICOM_PI7C9X7958,
4669 PCI_ANY_ID, PCI_ANY_ID,
4670 0,
4671 0, pbn_pericom_PI7C9X7958 },
4672 /*
4673 * ACCES I/O Products quad
4674 */
4675 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB,
4676 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4677 pbn_pericom_PI7C9X7952 },
4678 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S,
4679 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4680 pbn_pericom_PI7C9X7952 },
4681 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
4682 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4683 pbn_pericom_PI7C9X7954 },
4684 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
4685 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4686 pbn_pericom_PI7C9X7954 },
4687 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB,
4688 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4689 pbn_pericom_PI7C9X7952 },
4690 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2,
4691 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4692 pbn_pericom_PI7C9X7952 },
4693 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
4694 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4695 pbn_pericom_PI7C9X7954 },
4696 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
4697 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4698 pbn_pericom_PI7C9X7954 },
4699 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB,
4700 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4701 pbn_pericom_PI7C9X7952 },
4702 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM,
4703 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4704 pbn_pericom_PI7C9X7952 },
4705 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
4706 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4707 pbn_pericom_PI7C9X7954 },
4708 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
4709 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4710 pbn_pericom_PI7C9X7954 },
4711 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1,
4712 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4713 pbn_pericom_PI7C9X7951 },
4714 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2,
4715 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4716 pbn_pericom_PI7C9X7952 },
4717 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2,
4718 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4719 pbn_pericom_PI7C9X7952 },
4720 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
4721 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4722 pbn_pericom_PI7C9X7954 },
4723 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
4724 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4725 pbn_pericom_PI7C9X7954 },
4726 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S,
4727 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4728 pbn_pericom_PI7C9X7952 },
4729 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
4730 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4731 pbn_pericom_PI7C9X7954 },
4732 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2,
4733 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4734 pbn_pericom_PI7C9X7952 },
4735 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2,
4736 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4737 pbn_pericom_PI7C9X7952 },
4738 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
4739 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4740 pbn_pericom_PI7C9X7954 },
4741 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
4742 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4743 pbn_pericom_PI7C9X7954 },
4744 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM,
4745 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4746 pbn_pericom_PI7C9X7952 },
4747 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
4748 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4749 pbn_pericom_PI7C9X7954 },
4750 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
4751 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4752 pbn_pericom_PI7C9X7954 },
4753 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8,
4754 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4755 pbn_pericom_PI7C9X7958 },
4756 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8,
4757 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4758 pbn_pericom_PI7C9X7958 },
4759 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
4760 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4761 pbn_pericom_PI7C9X7954 },
4762 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8,
4763 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4764 pbn_pericom_PI7C9X7958 },
4765 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
4766 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4767 pbn_pericom_PI7C9X7954 },
4768 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM,
4769 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4770 pbn_pericom_PI7C9X7958 },
4771 { PCI_VENDOR_ID_ACCESIO, PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
4772 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4773 pbn_pericom_PI7C9X7954 },
4774 /*
4775 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
4776 */
4777 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
4778 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4779 pbn_b0_1_115200 },
4780 /*
4781 * ITE
4782 */
4783 { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_8872,
4784 PCI_ANY_ID, PCI_ANY_ID,
4785 0, 0,
4786 pbn_b1_bt_1_115200 },
4787
4788 /*
4789 * IntaShield IS-200
4790 */
4791 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS200,
4792 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0811 */
4793 pbn_b2_2_115200 },
4794 /*
4795 * IntaShield IS-400
4796 */
4797 { PCI_VENDOR_ID_INTASHIELD, PCI_DEVICE_ID_INTASHIELD_IS400,
4798 PCI_ANY_ID, PCI_ANY_ID, 0, 0, /* 135a.0dc0 */
4799 pbn_b2_4_115200 },
4800 /*
4801 * BrainBoxes UC-260
4802 */
4803 { PCI_VENDOR_ID_INTASHIELD, 0x0D21,
4804 PCI_ANY_ID, PCI_ANY_ID,
4805 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4806 pbn_b2_4_115200 },
4807 { PCI_VENDOR_ID_INTASHIELD, 0x0E34,
4808 PCI_ANY_ID, PCI_ANY_ID,
4809 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8, 0xffff00,
4810 pbn_b2_4_115200 },
4811 /*
4812 * Perle PCI-RAS cards
4813 */
4814 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4815 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS4,
4816 0, 0, pbn_b2_4_921600 },
4817 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4818 PCI_SUBVENDOR_ID_PERLE, PCI_SUBDEVICE_ID_PCI_RAS8,
4819 0, 0, pbn_b2_8_921600 },
4820
4821 /*
4822 * Mainpine series cards: Fairly standard layout but fools
4823 * parts of the autodetect in some cases and uses otherwise
4824 * unmatched communications subclasses in the PCI Express case
4825 */
4826
4827 { /* RockForceDUO */
4828 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4829 PCI_VENDOR_ID_MAINPINE, 0x0200,
4830 0, 0, pbn_b0_2_115200 },
4831 { /* RockForceQUATRO */
4832 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4833 PCI_VENDOR_ID_MAINPINE, 0x0300,
4834 0, 0, pbn_b0_4_115200 },
4835 { /* RockForceDUO+ */
4836 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4837 PCI_VENDOR_ID_MAINPINE, 0x0400,
4838 0, 0, pbn_b0_2_115200 },
4839 { /* RockForceQUATRO+ */
4840 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4841 PCI_VENDOR_ID_MAINPINE, 0x0500,
4842 0, 0, pbn_b0_4_115200 },
4843 { /* RockForce+ */
4844 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4845 PCI_VENDOR_ID_MAINPINE, 0x0600,
4846 0, 0, pbn_b0_2_115200 },
4847 { /* RockForce+ */
4848 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4849 PCI_VENDOR_ID_MAINPINE, 0x0700,
4850 0, 0, pbn_b0_4_115200 },
4851 { /* RockForceOCTO+ */
4852 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4853 PCI_VENDOR_ID_MAINPINE, 0x0800,
4854 0, 0, pbn_b0_8_115200 },
4855 { /* RockForceDUO+ */
4856 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4857 PCI_VENDOR_ID_MAINPINE, 0x0C00,
4858 0, 0, pbn_b0_2_115200 },
4859 { /* RockForceQUARTRO+ */
4860 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4861 PCI_VENDOR_ID_MAINPINE, 0x0D00,
4862 0, 0, pbn_b0_4_115200 },
4863 { /* RockForceOCTO+ */
4864 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4865 PCI_VENDOR_ID_MAINPINE, 0x1D00,
4866 0, 0, pbn_b0_8_115200 },
4867 { /* RockForceD1 */
4868 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4869 PCI_VENDOR_ID_MAINPINE, 0x2000,
4870 0, 0, pbn_b0_1_115200 },
4871 { /* RockForceF1 */
4872 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4873 PCI_VENDOR_ID_MAINPINE, 0x2100,
4874 0, 0, pbn_b0_1_115200 },
4875 { /* RockForceD2 */
4876 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4877 PCI_VENDOR_ID_MAINPINE, 0x2200,
4878 0, 0, pbn_b0_2_115200 },
4879 { /* RockForceF2 */
4880 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4881 PCI_VENDOR_ID_MAINPINE, 0x2300,
4882 0, 0, pbn_b0_2_115200 },
4883 { /* RockForceD4 */
4884 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4885 PCI_VENDOR_ID_MAINPINE, 0x2400,
4886 0, 0, pbn_b0_4_115200 },
4887 { /* RockForceF4 */
4888 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4889 PCI_VENDOR_ID_MAINPINE, 0x2500,
4890 0, 0, pbn_b0_4_115200 },
4891 { /* RockForceD8 */
4892 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4893 PCI_VENDOR_ID_MAINPINE, 0x2600,
4894 0, 0, pbn_b0_8_115200 },
4895 { /* RockForceF8 */
4896 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4897 PCI_VENDOR_ID_MAINPINE, 0x2700,
4898 0, 0, pbn_b0_8_115200 },
4899 { /* IQ Express D1 */
4900 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4901 PCI_VENDOR_ID_MAINPINE, 0x3000,
4902 0, 0, pbn_b0_1_115200 },
4903 { /* IQ Express F1 */
4904 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4905 PCI_VENDOR_ID_MAINPINE, 0x3100,
4906 0, 0, pbn_b0_1_115200 },
4907 { /* IQ Express D2 */
4908 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4909 PCI_VENDOR_ID_MAINPINE, 0x3200,
4910 0, 0, pbn_b0_2_115200 },
4911 { /* IQ Express F2 */
4912 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4913 PCI_VENDOR_ID_MAINPINE, 0x3300,
4914 0, 0, pbn_b0_2_115200 },
4915 { /* IQ Express D4 */
4916 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4917 PCI_VENDOR_ID_MAINPINE, 0x3400,
4918 0, 0, pbn_b0_4_115200 },
4919 { /* IQ Express F4 */
4920 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4921 PCI_VENDOR_ID_MAINPINE, 0x3500,
4922 0, 0, pbn_b0_4_115200 },
4923 { /* IQ Express D8 */
4924 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4925 PCI_VENDOR_ID_MAINPINE, 0x3C00,
4926 0, 0, pbn_b0_8_115200 },
4927 { /* IQ Express F8 */
4928 PCI_VENDOR_ID_MAINPINE, PCI_DEVICE_ID_MAINPINE_PBRIDGE,
4929 PCI_VENDOR_ID_MAINPINE, 0x3D00,
4930 0, 0, pbn_b0_8_115200 },
4931
4932
4933 /*
4934 * PA Semi PA6T-1682M on-chip UART
4935 */
4936 { PCI_VENDOR_ID_PASEMI, 0xa004,
4937 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4938 pbn_pasemi_1682M },
4939
4940 /*
4941 * National Instruments
4942 */
4943 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI23216,
4944 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4945 pbn_b1_16_115200 },
4946 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2328,
4947 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4948 pbn_b1_8_115200 },
4949 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324,
4950 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4951 pbn_b1_bt_4_115200 },
4952 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322,
4953 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4954 pbn_b1_bt_2_115200 },
4955 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2324I,
4956 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4957 pbn_b1_bt_4_115200 },
4958 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI2322I,
4959 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4960 pbn_b1_bt_2_115200 },
4961 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_23216,
4962 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4963 pbn_b1_16_115200 },
4964 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2328,
4965 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4966 pbn_b1_8_115200 },
4967 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2324,
4968 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4969 pbn_b1_bt_4_115200 },
4970 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8420_2322,
4971 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4972 pbn_b1_bt_2_115200 },
4973 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2324,
4974 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4975 pbn_b1_bt_4_115200 },
4976 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8422_2322,
4977 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4978 pbn_b1_bt_2_115200 },
4979 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2322,
4980 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4981 pbn_ni8430_2 },
4982 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2322,
4983 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4984 pbn_ni8430_2 },
4985 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2324,
4986 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4987 pbn_ni8430_4 },
4988 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2324,
4989 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4990 pbn_ni8430_4 },
4991 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_2328,
4992 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4993 pbn_ni8430_8 },
4994 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_2328,
4995 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4996 pbn_ni8430_8 },
4997 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8430_23216,
4998 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4999 pbn_ni8430_16 },
5000 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8430_23216,
5001 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5002 pbn_ni8430_16 },
5003 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2322,
5004 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5005 pbn_ni8430_2 },
5006 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2322,
5007 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5008 pbn_ni8430_2 },
5009 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PXI8432_2324,
5010 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5011 pbn_ni8430_4 },
5012 { PCI_VENDOR_ID_NI, PCI_DEVICE_ID_NI_PCI8432_2324,
5013 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5014 pbn_ni8430_4 },
5015
5016 /*
5017 * ADDI-DATA GmbH communication cards <info@addi-data.com>
5018 */
5019 { PCI_VENDOR_ID_ADDIDATA,
5020 PCI_DEVICE_ID_ADDIDATA_APCI7500,
5021 PCI_ANY_ID,
5022 PCI_ANY_ID,
5023 0,
5024 0,
5025 pbn_b0_4_115200 },
5026
5027 { PCI_VENDOR_ID_ADDIDATA,
5028 PCI_DEVICE_ID_ADDIDATA_APCI7420,
5029 PCI_ANY_ID,
5030 PCI_ANY_ID,
5031 0,
5032 0,
5033 pbn_b0_2_115200 },
5034
5035 { PCI_VENDOR_ID_ADDIDATA,
5036 PCI_DEVICE_ID_ADDIDATA_APCI7300,
5037 PCI_ANY_ID,
5038 PCI_ANY_ID,
5039 0,
5040 0,
5041 pbn_b0_1_115200 },
5042
5043 { PCI_VENDOR_ID_AMCC,
5044 PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
5045 PCI_ANY_ID,
5046 PCI_ANY_ID,
5047 0,
5048 0,
5049 pbn_b1_8_115200 },
5050
5051 { PCI_VENDOR_ID_ADDIDATA,
5052 PCI_DEVICE_ID_ADDIDATA_APCI7500_2,
5053 PCI_ANY_ID,
5054 PCI_ANY_ID,
5055 0,
5056 0,
5057 pbn_b0_4_115200 },
5058
5059 { PCI_VENDOR_ID_ADDIDATA,
5060 PCI_DEVICE_ID_ADDIDATA_APCI7420_2,
5061 PCI_ANY_ID,
5062 PCI_ANY_ID,
5063 0,
5064 0,
5065 pbn_b0_2_115200 },
5066
5067 { PCI_VENDOR_ID_ADDIDATA,
5068 PCI_DEVICE_ID_ADDIDATA_APCI7300_2,
5069 PCI_ANY_ID,
5070 PCI_ANY_ID,
5071 0,
5072 0,
5073 pbn_b0_1_115200 },
5074
5075 { PCI_VENDOR_ID_ADDIDATA,
5076 PCI_DEVICE_ID_ADDIDATA_APCI7500_3,
5077 PCI_ANY_ID,
5078 PCI_ANY_ID,
5079 0,
5080 0,
5081 pbn_b0_4_115200 },
5082
5083 { PCI_VENDOR_ID_ADDIDATA,
5084 PCI_DEVICE_ID_ADDIDATA_APCI7420_3,
5085 PCI_ANY_ID,
5086 PCI_ANY_ID,
5087 0,
5088 0,
5089 pbn_b0_2_115200 },
5090
5091 { PCI_VENDOR_ID_ADDIDATA,
5092 PCI_DEVICE_ID_ADDIDATA_APCI7300_3,
5093 PCI_ANY_ID,
5094 PCI_ANY_ID,
5095 0,
5096 0,
5097 pbn_b0_1_115200 },
5098
5099 { PCI_VENDOR_ID_ADDIDATA,
5100 PCI_DEVICE_ID_ADDIDATA_APCI7800_3,
5101 PCI_ANY_ID,
5102 PCI_ANY_ID,
5103 0,
5104 0,
5105 pbn_b0_8_115200 },
5106
5107 { PCI_VENDOR_ID_ADDIDATA,
5108 PCI_DEVICE_ID_ADDIDATA_APCIe7500,
5109 PCI_ANY_ID,
5110 PCI_ANY_ID,
5111 0,
5112 0,
5113 pbn_ADDIDATA_PCIe_4_3906250 },
5114
5115 { PCI_VENDOR_ID_ADDIDATA,
5116 PCI_DEVICE_ID_ADDIDATA_APCIe7420,
5117 PCI_ANY_ID,
5118 PCI_ANY_ID,
5119 0,
5120 0,
5121 pbn_ADDIDATA_PCIe_2_3906250 },
5122
5123 { PCI_VENDOR_ID_ADDIDATA,
5124 PCI_DEVICE_ID_ADDIDATA_APCIe7300,
5125 PCI_ANY_ID,
5126 PCI_ANY_ID,
5127 0,
5128 0,
5129 pbn_ADDIDATA_PCIe_1_3906250 },
5130
5131 { PCI_VENDOR_ID_ADDIDATA,
5132 PCI_DEVICE_ID_ADDIDATA_APCIe7800,
5133 PCI_ANY_ID,
5134 PCI_ANY_ID,
5135 0,
5136 0,
5137 pbn_ADDIDATA_PCIe_8_3906250 },
5138
5139 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9835,
5140 PCI_VENDOR_ID_IBM, 0x0299,
5141 0, 0, pbn_b0_bt_2_115200 },
5142
5143 /*
5144 * other NetMos 9835 devices are most likely handled by the
5145 * parport_serial driver, check drivers/parport/parport_serial.c
5146 * before adding them here.
5147 */
5148
5149 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9901,
5150 0xA000, 0x1000,
5151 0, 0, pbn_b0_1_115200 },
5152
5153 /* the 9901 is a rebranded 9912 */
5154 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
5155 0xA000, 0x1000,
5156 0, 0, pbn_b0_1_115200 },
5157
5158 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
5159 0xA000, 0x1000,
5160 0, 0, pbn_b0_1_115200 },
5161
5162 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9904,
5163 0xA000, 0x1000,
5164 0, 0, pbn_b0_1_115200 },
5165
5166 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5167 0xA000, 0x1000,
5168 0, 0, pbn_b0_1_115200 },
5169
5170 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
5171 0xA000, 0x3002,
5172 0, 0, pbn_NETMOS9900_2s_115200 },
5173
5174 /*
5175 * Best Connectivity and Rosewill PCI Multi I/O cards
5176 */
5177
5178 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5179 0xA000, 0x1000,
5180 0, 0, pbn_b0_1_115200 },
5181
5182 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5183 0xA000, 0x3002,
5184 0, 0, pbn_b0_bt_2_115200 },
5185
5186 { PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9865,
5187 0xA000, 0x3004,
5188 0, 0, pbn_b0_bt_4_115200 },
5189 /* Intel CE4100 */
5190 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CE4100_UART,
5191 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5192 pbn_ce4100_1_115200 },
5193
5194 /*
5195 * Cronyx Omega PCI
5196 */
5197 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
5198 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5199 pbn_omegapci },
5200
5201 /*
5202 * Broadcom TruManage
5203 */
5204 { PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
5205 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
5206 pbn_brcm_trumanage },
5207
5208 /*
5209 * AgeStar as-prs2-009
5210 */
5211 { PCI_VENDOR_ID_AGESTAR, PCI_DEVICE_ID_AGESTAR_9375,
5212 PCI_ANY_ID, PCI_ANY_ID,
5213 0, 0, pbn_b0_bt_2_115200 },
5214
5215 /*
5216 * WCH CH353 series devices: The 2S1P is handled by parport_serial
5217 * so not listed here.
5218 */
5219 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_4S,
5220 PCI_ANY_ID, PCI_ANY_ID,
5221 0, 0, pbn_b0_bt_4_115200 },
5222
5223 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH353_2S1PF,
5224 PCI_ANY_ID, PCI_ANY_ID,
5225 0, 0, pbn_b0_bt_2_115200 },
5226
5227 { PCI_VENDOR_ID_WCH, PCI_DEVICE_ID_WCH_CH355_4S,
5228 PCI_ANY_ID, PCI_ANY_ID,
5229 0, 0, pbn_b0_bt_4_115200 },
5230
5231 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH382_2S,
5232 PCI_ANY_ID, PCI_ANY_ID,
5233 0, 0, pbn_wch382_2 },
5234
5235 { PCIE_VENDOR_ID_WCH, PCIE_DEVICE_ID_WCH_CH384_4S,
5236 PCI_ANY_ID, PCI_ANY_ID,
5237 0, 0, pbn_wch384_4 },
5238
5239 /*
5240 * Realtek RealManage
5241 */
5242 { PCI_VENDOR_ID_REALTEK, 0x816a,
5243 PCI_ANY_ID, PCI_ANY_ID,
5244 0, 0, pbn_b0_1_115200 },
5245
5246 { PCI_VENDOR_ID_REALTEK, 0x816b,
5247 PCI_ANY_ID, PCI_ANY_ID,
5248 0, 0, pbn_b0_1_115200 },
5249
5250 /* Fintek PCI serial cards */
5251 { PCI_DEVICE(0x1c29, 0x1104), .driver_data = pbn_fintek_4 },
5252 { PCI_DEVICE(0x1c29, 0x1108), .driver_data = pbn_fintek_8 },
5253 { PCI_DEVICE(0x1c29, 0x1112), .driver_data = pbn_fintek_12 },
5254
5255 /* MKS Tenta SCOM-080x serial cards */
5256 { PCI_DEVICE(0x1601, 0x0800), .driver_data = pbn_b0_4_1250000 },
5257 { PCI_DEVICE(0x1601, 0xa801), .driver_data = pbn_b0_4_1250000 },
5258
5259 /* Amazon PCI serial device */
5260 { PCI_DEVICE(0x1d0f, 0x8250), .driver_data = pbn_b0_1_115200 },
5261
5262 /*
5263 * These entries match devices with class COMMUNICATION_SERIAL,
5264 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
5265 */
5266 { PCI_ANY_ID, PCI_ANY_ID,
5267 PCI_ANY_ID, PCI_ANY_ID,
5268 PCI_CLASS_COMMUNICATION_SERIAL << 8,
5269 0xffff00, pbn_default },
5270 { PCI_ANY_ID, PCI_ANY_ID,
5271 PCI_ANY_ID, PCI_ANY_ID,
5272 PCI_CLASS_COMMUNICATION_MODEM << 8,
5273 0xffff00, pbn_default },
5274 { PCI_ANY_ID, PCI_ANY_ID,
5275 PCI_ANY_ID, PCI_ANY_ID,
5276 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
5277 0xffff00, pbn_default },
5278 { 0, }
5279 };
5280
serial8250_io_error_detected(struct pci_dev * dev,pci_channel_state_t state)5281 static pci_ers_result_t serial8250_io_error_detected(struct pci_dev *dev,
5282 pci_channel_state_t state)
5283 {
5284 struct serial_private *priv = pci_get_drvdata(dev);
5285
5286 if (state == pci_channel_io_perm_failure)
5287 return PCI_ERS_RESULT_DISCONNECT;
5288
5289 if (priv)
5290 pciserial_detach_ports(priv);
5291
5292 pci_disable_device(dev);
5293
5294 return PCI_ERS_RESULT_NEED_RESET;
5295 }
5296
serial8250_io_slot_reset(struct pci_dev * dev)5297 static pci_ers_result_t serial8250_io_slot_reset(struct pci_dev *dev)
5298 {
5299 int rc;
5300
5301 rc = pci_enable_device(dev);
5302
5303 if (rc)
5304 return PCI_ERS_RESULT_DISCONNECT;
5305
5306 pci_restore_state(dev);
5307 pci_save_state(dev);
5308
5309 return PCI_ERS_RESULT_RECOVERED;
5310 }
5311
serial8250_io_resume(struct pci_dev * dev)5312 static void serial8250_io_resume(struct pci_dev *dev)
5313 {
5314 struct serial_private *priv = pci_get_drvdata(dev);
5315 struct serial_private *new;
5316
5317 if (!priv)
5318 return;
5319
5320 new = pciserial_init_ports(dev, priv->board);
5321 if (!IS_ERR(new)) {
5322 pci_set_drvdata(dev, new);
5323 kfree(priv);
5324 }
5325 }
5326
5327 static const struct pci_error_handlers serial8250_err_handler = {
5328 .error_detected = serial8250_io_error_detected,
5329 .slot_reset = serial8250_io_slot_reset,
5330 .resume = serial8250_io_resume,
5331 };
5332
5333 static struct pci_driver serial_pci_driver = {
5334 .name = "serial",
5335 .probe = pciserial_init_one,
5336 .remove = pciserial_remove_one,
5337 .driver = {
5338 .pm = &pciserial_pm_ops,
5339 },
5340 .id_table = serial_pci_tbl,
5341 .err_handler = &serial8250_err_handler,
5342 };
5343
5344 module_pci_driver(serial_pci_driver);
5345
5346 MODULE_LICENSE("GPL");
5347 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
5348 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
5349