1 // SPDX-License-Identifier: GPL-2.0
2 /**
3 * dwc3-pci.c - PCI Specific glue layer
4 *
5 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
6 *
7 * Authors: Felipe Balbi <balbi@ti.com>,
8 * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
9 */
10
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/slab.h>
14 #include <linux/pci.h>
15 #include <linux/workqueue.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/platform_device.h>
18 #include <linux/gpio/consumer.h>
19 #include <linux/gpio/machine.h>
20 #include <linux/acpi.h>
21 #include <linux/delay.h>
22
23 #define PCI_DEVICE_ID_INTEL_BYT 0x0f37
24 #define PCI_DEVICE_ID_INTEL_MRFLD 0x119e
25 #define PCI_DEVICE_ID_INTEL_BSW 0x22b7
26 #define PCI_DEVICE_ID_INTEL_SPTLP 0x9d30
27 #define PCI_DEVICE_ID_INTEL_SPTH 0xa130
28 #define PCI_DEVICE_ID_INTEL_BXT 0x0aaa
29 #define PCI_DEVICE_ID_INTEL_BXT_M 0x1aaa
30 #define PCI_DEVICE_ID_INTEL_APL 0x5aaa
31 #define PCI_DEVICE_ID_INTEL_KBP 0xa2b0
32 #define PCI_DEVICE_ID_INTEL_CMLLP 0x02ee
33 #define PCI_DEVICE_ID_INTEL_CMLH 0x06ee
34 #define PCI_DEVICE_ID_INTEL_GLK 0x31aa
35 #define PCI_DEVICE_ID_INTEL_CNPLP 0x9dee
36 #define PCI_DEVICE_ID_INTEL_CNPH 0xa36e
37 #define PCI_DEVICE_ID_INTEL_CNPV 0xa3b0
38 #define PCI_DEVICE_ID_INTEL_ICLLP 0x34ee
39
40 #define PCI_INTEL_BXT_DSM_GUID "732b85d5-b7a7-4a1b-9ba0-4bbd00ffd511"
41 #define PCI_INTEL_BXT_FUNC_PMU_PWR 4
42 #define PCI_INTEL_BXT_STATE_D0 0
43 #define PCI_INTEL_BXT_STATE_D3 3
44
45 #define GP_RWBAR 1
46 #define GP_RWREG1 0xa0
47 #define GP_RWREG1_ULPI_REFCLK_DISABLE (1 << 17)
48
49 /**
50 * struct dwc3_pci - Driver private structure
51 * @dwc3: child dwc3 platform_device
52 * @pci: our link to PCI bus
53 * @guid: _DSM GUID
54 * @has_dsm_for_pm: true for devices which need to run _DSM on runtime PM
55 * @wakeup_work: work for asynchronous resume
56 */
57 struct dwc3_pci {
58 struct platform_device *dwc3;
59 struct pci_dev *pci;
60
61 guid_t guid;
62
63 unsigned int has_dsm_for_pm:1;
64 struct work_struct wakeup_work;
65 };
66
67 static const struct acpi_gpio_params reset_gpios = { 0, 0, false };
68 static const struct acpi_gpio_params cs_gpios = { 1, 0, false };
69
70 static const struct acpi_gpio_mapping acpi_dwc3_byt_gpios[] = {
71 { "reset-gpios", &reset_gpios, 1 },
72 { "cs-gpios", &cs_gpios, 1 },
73 { },
74 };
75
76 static struct gpiod_lookup_table platform_bytcr_gpios = {
77 .dev_id = "0000:00:16.0",
78 .table = {
79 GPIO_LOOKUP("INT33FC:00", 54, "reset", GPIO_ACTIVE_HIGH),
80 GPIO_LOOKUP("INT33FC:02", 14, "cs", GPIO_ACTIVE_HIGH),
81 {}
82 },
83 };
84
dwc3_byt_enable_ulpi_refclock(struct pci_dev * pci)85 static int dwc3_byt_enable_ulpi_refclock(struct pci_dev *pci)
86 {
87 void __iomem *reg;
88 u32 value;
89
90 reg = pcim_iomap(pci, GP_RWBAR, 0);
91 if (!reg)
92 return -ENOMEM;
93
94 value = readl(reg + GP_RWREG1);
95 if (!(value & GP_RWREG1_ULPI_REFCLK_DISABLE))
96 goto unmap; /* ULPI refclk already enabled */
97
98 value &= ~GP_RWREG1_ULPI_REFCLK_DISABLE;
99 writel(value, reg + GP_RWREG1);
100 /* This comes from the Intel Android x86 tree w/o any explanation */
101 msleep(100);
102 unmap:
103 pcim_iounmap(pci, reg);
104 return 0;
105 }
106
107 static const struct property_entry dwc3_pci_intel_properties[] = {
108 PROPERTY_ENTRY_STRING("dr_mode", "peripheral"),
109 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
110 {}
111 };
112
113 static const struct property_entry dwc3_pci_mrfld_properties[] = {
114 PROPERTY_ENTRY_STRING("dr_mode", "otg"),
115 PROPERTY_ENTRY_STRING("linux,extcon-name", "mrfld_bcove_pwrsrc"),
116 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
117 {}
118 };
119
120 static const struct property_entry dwc3_pci_amd_properties[] = {
121 PROPERTY_ENTRY_BOOL("snps,has-lpm-erratum"),
122 PROPERTY_ENTRY_U8("snps,lpm-nyet-threshold", 0xf),
123 PROPERTY_ENTRY_BOOL("snps,u2exit_lfps_quirk"),
124 PROPERTY_ENTRY_BOOL("snps,u2ss_inp3_quirk"),
125 PROPERTY_ENTRY_BOOL("snps,req_p1p2p3_quirk"),
126 PROPERTY_ENTRY_BOOL("snps,del_p1p2p3_quirk"),
127 PROPERTY_ENTRY_BOOL("snps,del_phy_power_chg_quirk"),
128 PROPERTY_ENTRY_BOOL("snps,lfps_filter_quirk"),
129 PROPERTY_ENTRY_BOOL("snps,rx_detect_poll_quirk"),
130 PROPERTY_ENTRY_BOOL("snps,tx_de_emphasis_quirk"),
131 PROPERTY_ENTRY_U8("snps,tx_de_emphasis", 1),
132 /* FIXME these quirks should be removed when AMD NL tapes out */
133 PROPERTY_ENTRY_BOOL("snps,disable_scramble_quirk"),
134 PROPERTY_ENTRY_BOOL("snps,dis_u3_susphy_quirk"),
135 PROPERTY_ENTRY_BOOL("snps,dis_u2_susphy_quirk"),
136 PROPERTY_ENTRY_BOOL("linux,sysdev_is_parent"),
137 {}
138 };
139
dwc3_pci_quirks(struct dwc3_pci * dwc)140 static int dwc3_pci_quirks(struct dwc3_pci *dwc)
141 {
142 struct pci_dev *pdev = dwc->pci;
143
144 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
145 if (pdev->device == PCI_DEVICE_ID_INTEL_BXT ||
146 pdev->device == PCI_DEVICE_ID_INTEL_BXT_M) {
147 guid_parse(PCI_INTEL_BXT_DSM_GUID, &dwc->guid);
148 dwc->has_dsm_for_pm = true;
149 }
150
151 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT) {
152 struct gpio_desc *gpio;
153 int ret;
154
155 /* On BYT the FW does not always enable the refclock */
156 ret = dwc3_byt_enable_ulpi_refclock(pdev);
157 if (ret)
158 return ret;
159
160 ret = devm_acpi_dev_add_driver_gpios(&pdev->dev,
161 acpi_dwc3_byt_gpios);
162 if (ret)
163 dev_dbg(&pdev->dev, "failed to add mapping table\n");
164
165 /*
166 * A lot of BYT devices lack ACPI resource entries for
167 * the GPIOs, add a fallback mapping to the reference
168 * design GPIOs which all boards seem to use.
169 */
170 gpiod_add_lookup_table(&platform_bytcr_gpios);
171
172 /*
173 * These GPIOs will turn on the USB2 PHY. Note that we have to
174 * put the gpio descriptors again here because the phy driver
175 * might want to grab them, too.
176 */
177 gpio = gpiod_get_optional(&pdev->dev, "cs", GPIOD_OUT_LOW);
178 if (IS_ERR(gpio))
179 return PTR_ERR(gpio);
180
181 gpiod_set_value_cansleep(gpio, 1);
182 gpiod_put(gpio);
183
184 gpio = gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
185 if (IS_ERR(gpio))
186 return PTR_ERR(gpio);
187
188 if (gpio) {
189 gpiod_set_value_cansleep(gpio, 1);
190 gpiod_put(gpio);
191 usleep_range(10000, 11000);
192 }
193 }
194 }
195
196 return 0;
197 }
198
199 #ifdef CONFIG_PM
dwc3_pci_resume_work(struct work_struct * work)200 static void dwc3_pci_resume_work(struct work_struct *work)
201 {
202 struct dwc3_pci *dwc = container_of(work, struct dwc3_pci, wakeup_work);
203 struct platform_device *dwc3 = dwc->dwc3;
204 int ret;
205
206 ret = pm_runtime_get_sync(&dwc3->dev);
207 if (ret) {
208 pm_runtime_put_sync_autosuspend(&dwc3->dev);
209 return;
210 }
211
212 pm_runtime_mark_last_busy(&dwc3->dev);
213 pm_runtime_put_sync_autosuspend(&dwc3->dev);
214 }
215 #endif
216
dwc3_pci_probe(struct pci_dev * pci,const struct pci_device_id * id)217 static int dwc3_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
218 {
219 struct property_entry *p = (struct property_entry *)id->driver_data;
220 struct dwc3_pci *dwc;
221 struct resource res[2];
222 int ret;
223 struct device *dev = &pci->dev;
224
225 ret = pcim_enable_device(pci);
226 if (ret) {
227 dev_err(dev, "failed to enable pci device\n");
228 return -ENODEV;
229 }
230
231 pci_set_master(pci);
232
233 dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
234 if (!dwc)
235 return -ENOMEM;
236
237 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
238 if (!dwc->dwc3)
239 return -ENOMEM;
240
241 memset(res, 0x00, sizeof(struct resource) * ARRAY_SIZE(res));
242
243 res[0].start = pci_resource_start(pci, 0);
244 res[0].end = pci_resource_end(pci, 0);
245 res[0].name = "dwc_usb3";
246 res[0].flags = IORESOURCE_MEM;
247
248 res[1].start = pci->irq;
249 res[1].name = "dwc_usb3";
250 res[1].flags = IORESOURCE_IRQ;
251
252 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res));
253 if (ret) {
254 dev_err(dev, "couldn't add resources to dwc3 device\n");
255 goto err;
256 }
257
258 dwc->pci = pci;
259 dwc->dwc3->dev.parent = dev;
260 ACPI_COMPANION_SET(&dwc->dwc3->dev, ACPI_COMPANION(dev));
261
262 ret = platform_device_add_properties(dwc->dwc3, p);
263 if (ret < 0)
264 goto err;
265
266 ret = dwc3_pci_quirks(dwc);
267 if (ret)
268 goto err;
269
270 ret = platform_device_add(dwc->dwc3);
271 if (ret) {
272 dev_err(dev, "failed to register dwc3 device\n");
273 goto err;
274 }
275
276 device_init_wakeup(dev, true);
277 pci_set_drvdata(pci, dwc);
278 pm_runtime_put(dev);
279 #ifdef CONFIG_PM
280 INIT_WORK(&dwc->wakeup_work, dwc3_pci_resume_work);
281 #endif
282
283 return 0;
284 err:
285 platform_device_put(dwc->dwc3);
286 return ret;
287 }
288
dwc3_pci_remove(struct pci_dev * pci)289 static void dwc3_pci_remove(struct pci_dev *pci)
290 {
291 struct dwc3_pci *dwc = pci_get_drvdata(pci);
292 struct pci_dev *pdev = dwc->pci;
293
294 if (pdev->device == PCI_DEVICE_ID_INTEL_BYT)
295 gpiod_remove_lookup_table(&platform_bytcr_gpios);
296 #ifdef CONFIG_PM
297 cancel_work_sync(&dwc->wakeup_work);
298 #endif
299 device_init_wakeup(&pci->dev, false);
300 pm_runtime_get(&pci->dev);
301 platform_device_unregister(dwc->dwc3);
302 }
303
304 static const struct pci_device_id dwc3_pci_id_table[] = {
305 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BSW),
306 (kernel_ulong_t) &dwc3_pci_intel_properties },
307
308 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BYT),
309 (kernel_ulong_t) &dwc3_pci_intel_properties, },
310
311 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_MRFLD),
312 (kernel_ulong_t) &dwc3_pci_mrfld_properties, },
313
314 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLLP),
315 (kernel_ulong_t) &dwc3_pci_intel_properties, },
316
317 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CMLH),
318 (kernel_ulong_t) &dwc3_pci_intel_properties, },
319
320 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTLP),
321 (kernel_ulong_t) &dwc3_pci_intel_properties, },
322
323 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_SPTH),
324 (kernel_ulong_t) &dwc3_pci_intel_properties, },
325
326 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT),
327 (kernel_ulong_t) &dwc3_pci_intel_properties, },
328
329 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_BXT_M),
330 (kernel_ulong_t) &dwc3_pci_intel_properties, },
331
332 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_APL),
333 (kernel_ulong_t) &dwc3_pci_intel_properties, },
334
335 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_KBP),
336 (kernel_ulong_t) &dwc3_pci_intel_properties, },
337
338 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_GLK),
339 (kernel_ulong_t) &dwc3_pci_intel_properties, },
340
341 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPLP),
342 (kernel_ulong_t) &dwc3_pci_intel_properties, },
343
344 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPH),
345 (kernel_ulong_t) &dwc3_pci_intel_properties, },
346
347 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_CNPV),
348 (kernel_ulong_t) &dwc3_pci_intel_properties, },
349
350 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICLLP),
351 (kernel_ulong_t) &dwc3_pci_intel_properties, },
352
353 { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_NL_USB),
354 (kernel_ulong_t) &dwc3_pci_amd_properties, },
355 { } /* Terminating Entry */
356 };
357 MODULE_DEVICE_TABLE(pci, dwc3_pci_id_table);
358
359 #if defined(CONFIG_PM) || defined(CONFIG_PM_SLEEP)
dwc3_pci_dsm(struct dwc3_pci * dwc,int param)360 static int dwc3_pci_dsm(struct dwc3_pci *dwc, int param)
361 {
362 union acpi_object *obj;
363 union acpi_object tmp;
364 union acpi_object argv4 = ACPI_INIT_DSM_ARGV4(1, &tmp);
365
366 if (!dwc->has_dsm_for_pm)
367 return 0;
368
369 tmp.type = ACPI_TYPE_INTEGER;
370 tmp.integer.value = param;
371
372 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dwc->pci->dev), &dwc->guid,
373 1, PCI_INTEL_BXT_FUNC_PMU_PWR, &argv4);
374 if (!obj) {
375 dev_err(&dwc->pci->dev, "failed to evaluate _DSM\n");
376 return -EIO;
377 }
378
379 ACPI_FREE(obj);
380
381 return 0;
382 }
383 #endif /* CONFIG_PM || CONFIG_PM_SLEEP */
384
385 #ifdef CONFIG_PM
dwc3_pci_runtime_suspend(struct device * dev)386 static int dwc3_pci_runtime_suspend(struct device *dev)
387 {
388 struct dwc3_pci *dwc = dev_get_drvdata(dev);
389
390 if (device_can_wakeup(dev))
391 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
392
393 return -EBUSY;
394 }
395
dwc3_pci_runtime_resume(struct device * dev)396 static int dwc3_pci_runtime_resume(struct device *dev)
397 {
398 struct dwc3_pci *dwc = dev_get_drvdata(dev);
399 int ret;
400
401 ret = dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
402 if (ret)
403 return ret;
404
405 queue_work(pm_wq, &dwc->wakeup_work);
406
407 return 0;
408 }
409 #endif /* CONFIG_PM */
410
411 #ifdef CONFIG_PM_SLEEP
dwc3_pci_suspend(struct device * dev)412 static int dwc3_pci_suspend(struct device *dev)
413 {
414 struct dwc3_pci *dwc = dev_get_drvdata(dev);
415
416 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D3);
417 }
418
dwc3_pci_resume(struct device * dev)419 static int dwc3_pci_resume(struct device *dev)
420 {
421 struct dwc3_pci *dwc = dev_get_drvdata(dev);
422
423 return dwc3_pci_dsm(dwc, PCI_INTEL_BXT_STATE_D0);
424 }
425 #endif /* CONFIG_PM_SLEEP */
426
427 static const struct dev_pm_ops dwc3_pci_dev_pm_ops = {
428 SET_SYSTEM_SLEEP_PM_OPS(dwc3_pci_suspend, dwc3_pci_resume)
429 SET_RUNTIME_PM_OPS(dwc3_pci_runtime_suspend, dwc3_pci_runtime_resume,
430 NULL)
431 };
432
433 static struct pci_driver dwc3_pci_driver = {
434 .name = "dwc3-pci",
435 .id_table = dwc3_pci_id_table,
436 .probe = dwc3_pci_probe,
437 .remove = dwc3_pci_remove,
438 .driver = {
439 .pm = &dwc3_pci_dev_pm_ops,
440 }
441 };
442
443 MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
444 MODULE_LICENSE("GPL v2");
445 MODULE_DESCRIPTION("DesignWare USB3 PCI Glue Layer");
446
447 module_pci_driver(dwc3_pci_driver);
448