1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * xHCI host controller driver PCI Bus Glue.
4 *
5 * Copyright (C) 2008 Intel Corp.
6 *
7 * Author: Sarah Sharp
8 * Some code borrowed from the Linux EHCI driver.
9 */
10
11 #include <linux/pci.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/acpi.h>
15
16 #include "xhci.h"
17 #include "xhci-trace.h"
18
19 #define SSIC_PORT_NUM 2
20 #define SSIC_PORT_CFG2 0x880c
21 #define SSIC_PORT_CFG2_OFFSET 0x30
22 #define PROG_DONE (1 << 30)
23 #define SSIC_PORT_UNUSED (1 << 31)
24 #define SPARSE_DISABLE_BIT 17
25 #define SPARSE_CNTL_ENABLE 0xC12C
26
27 /* Device for a quirk */
28 #define PCI_VENDOR_ID_FRESCO_LOGIC 0x1b73
29 #define PCI_DEVICE_ID_FRESCO_LOGIC_PDK 0x1000
30 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1009 0x1009
31 #define PCI_DEVICE_ID_FRESCO_LOGIC_FL1400 0x1400
32
33 #define PCI_VENDOR_ID_ETRON 0x1b6f
34 #define PCI_DEVICE_ID_EJ168 0x7023
35
36 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_XHCI 0x8c31
37 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI 0x9c31
38 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI 0x9cb1
39 #define PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI 0x22b5
40 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI 0xa12f
41 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI 0x9d2f
42 #define PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI 0x0aa8
43 #define PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI 0x1aa8
44 #define PCI_DEVICE_ID_INTEL_APL_XHCI 0x5aa8
45 #define PCI_DEVICE_ID_INTEL_DNV_XHCI 0x19d0
46 #define PCI_DEVICE_ID_INTEL_CML_XHCI 0xa3af
47
48 #define PCI_DEVICE_ID_AMD_PROMONTORYA_4 0x43b9
49 #define PCI_DEVICE_ID_AMD_PROMONTORYA_3 0x43ba
50 #define PCI_DEVICE_ID_AMD_PROMONTORYA_2 0x43bb
51 #define PCI_DEVICE_ID_AMD_PROMONTORYA_1 0x43bc
52 #define PCI_DEVICE_ID_ASMEDIA_1042_XHCI 0x1042
53 #define PCI_DEVICE_ID_ASMEDIA_1042A_XHCI 0x1142
54 #define PCI_DEVICE_ID_ASMEDIA_1142_XHCI 0x1242
55 #define PCI_DEVICE_ID_ASMEDIA_2142_XHCI 0x2142
56
57 static const char hcd_name[] = "xhci_hcd";
58
59 static struct hc_driver __read_mostly xhci_pci_hc_driver;
60
61 static int xhci_pci_setup(struct usb_hcd *hcd);
62
63 static const struct xhci_driver_overrides xhci_pci_overrides __initconst = {
64 .reset = xhci_pci_setup,
65 };
66
67 /* called after powerup, by probe or system-pm "wakeup" */
xhci_pci_reinit(struct xhci_hcd * xhci,struct pci_dev * pdev)68 static int xhci_pci_reinit(struct xhci_hcd *xhci, struct pci_dev *pdev)
69 {
70 /*
71 * TODO: Implement finding debug ports later.
72 * TODO: see if there are any quirks that need to be added to handle
73 * new extended capabilities.
74 */
75
76 /* PCI Memory-Write-Invalidate cycle support is optional (uncommon) */
77 if (!pci_set_mwi(pdev))
78 xhci_dbg(xhci, "MWI active\n");
79
80 xhci_dbg(xhci, "Finished xhci_pci_reinit\n");
81 return 0;
82 }
83
xhci_pci_quirks(struct device * dev,struct xhci_hcd * xhci)84 static void xhci_pci_quirks(struct device *dev, struct xhci_hcd *xhci)
85 {
86 struct pci_dev *pdev = to_pci_dev(dev);
87
88 /* Look for vendor-specific quirks */
89 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
90 (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK ||
91 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1400)) {
92 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
93 pdev->revision == 0x0) {
94 xhci->quirks |= XHCI_RESET_EP_QUIRK;
95 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
96 "QUIRK: Fresco Logic xHC needs configure"
97 " endpoint cmd after reset endpoint");
98 }
99 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK &&
100 pdev->revision == 0x4) {
101 xhci->quirks |= XHCI_SLOW_SUSPEND;
102 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
103 "QUIRK: Fresco Logic xHC revision %u"
104 "must be suspended extra slowly",
105 pdev->revision);
106 }
107 if (pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_PDK)
108 xhci->quirks |= XHCI_BROKEN_STREAMS;
109 /* Fresco Logic confirms: all revisions of this chip do not
110 * support MSI, even though some of them claim to in their PCI
111 * capabilities.
112 */
113 xhci->quirks |= XHCI_BROKEN_MSI;
114 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
115 "QUIRK: Fresco Logic revision %u "
116 "has broken MSI implementation",
117 pdev->revision);
118 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
119 }
120
121 if (pdev->vendor == PCI_VENDOR_ID_FRESCO_LOGIC &&
122 pdev->device == PCI_DEVICE_ID_FRESCO_LOGIC_FL1009)
123 xhci->quirks |= XHCI_BROKEN_STREAMS;
124
125 if (pdev->vendor == PCI_VENDOR_ID_NEC)
126 xhci->quirks |= XHCI_NEC_HOST;
127
128 if (pdev->vendor == PCI_VENDOR_ID_AMD && xhci->hci_version == 0x96)
129 xhci->quirks |= XHCI_AMD_0x96_HOST;
130
131 /* AMD PLL quirk */
132 if (pdev->vendor == PCI_VENDOR_ID_AMD && usb_amd_find_chipset_info())
133 xhci->quirks |= XHCI_AMD_PLL_FIX;
134
135 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
136 (pdev->device == 0x145c ||
137 pdev->device == 0x15e0 ||
138 pdev->device == 0x15e1 ||
139 pdev->device == 0x43bb))
140 xhci->quirks |= XHCI_SUSPEND_DELAY;
141
142 if (pdev->vendor == PCI_VENDOR_ID_AMD &&
143 (pdev->device == 0x15e0 || pdev->device == 0x15e1))
144 xhci->quirks |= XHCI_SNPS_BROKEN_SUSPEND;
145
146 if (pdev->vendor == PCI_VENDOR_ID_AMD && pdev->device == 0x15e5)
147 xhci->quirks |= XHCI_DISABLE_SPARSE;
148
149 if (pdev->vendor == PCI_VENDOR_ID_AMD)
150 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
151
152 if ((pdev->vendor == PCI_VENDOR_ID_AMD) &&
153 ((pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_4) ||
154 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_3) ||
155 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_2) ||
156 (pdev->device == PCI_DEVICE_ID_AMD_PROMONTORYA_1)))
157 xhci->quirks |= XHCI_U2_DISABLE_WAKE;
158
159 if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
160 xhci->quirks |= XHCI_LPM_SUPPORT;
161 xhci->quirks |= XHCI_INTEL_HOST;
162 xhci->quirks |= XHCI_AVOID_BEI;
163 }
164 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
165 pdev->device == PCI_DEVICE_ID_INTEL_PANTHERPOINT_XHCI) {
166 xhci->quirks |= XHCI_EP_LIMIT_QUIRK;
167 xhci->limit_active_eps = 64;
168 xhci->quirks |= XHCI_SW_BW_CHECKING;
169 /*
170 * PPT desktop boards DH77EB and DH77DF will power back on after
171 * a few seconds of being shutdown. The fix for this is to
172 * switch the ports from xHCI to EHCI on shutdown. We can't use
173 * DMI information to find those particular boards (since each
174 * vendor will change the board name), so we have to key off all
175 * PPT chipsets.
176 */
177 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
178 }
179 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
180 (pdev->device == PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_XHCI ||
181 pdev->device == PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_XHCI)) {
182 xhci->quirks |= XHCI_SPURIOUS_REBOOT;
183 xhci->quirks |= XHCI_SPURIOUS_WAKEUP;
184 }
185 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
186 (pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
187 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
188 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
189 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_M_XHCI ||
190 pdev->device == PCI_DEVICE_ID_INTEL_BROXTON_B_XHCI ||
191 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
192 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI ||
193 pdev->device == PCI_DEVICE_ID_INTEL_CML_XHCI)) {
194 xhci->quirks |= XHCI_PME_STUCK_QUIRK;
195 }
196 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
197 pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI)
198 xhci->quirks |= XHCI_SSIC_PORT_UNUSED;
199 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
200 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
201 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
202 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI))
203 xhci->quirks |= XHCI_INTEL_USB_ROLE_SW;
204 if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
205 (pdev->device == PCI_DEVICE_ID_INTEL_CHERRYVIEW_XHCI ||
206 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_XHCI ||
207 pdev->device == PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_XHCI ||
208 pdev->device == PCI_DEVICE_ID_INTEL_APL_XHCI ||
209 pdev->device == PCI_DEVICE_ID_INTEL_DNV_XHCI))
210 xhci->quirks |= XHCI_MISSING_CAS;
211
212 if (pdev->vendor == PCI_VENDOR_ID_ETRON &&
213 pdev->device == PCI_DEVICE_ID_EJ168) {
214 xhci->quirks |= XHCI_RESET_ON_RESUME;
215 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
216 xhci->quirks |= XHCI_BROKEN_STREAMS;
217 }
218 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
219 pdev->device == 0x0014) {
220 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
221 xhci->quirks |= XHCI_ZERO_64B_REGS;
222 }
223 if (pdev->vendor == PCI_VENDOR_ID_RENESAS &&
224 pdev->device == 0x0015) {
225 xhci->quirks |= XHCI_RESET_ON_RESUME;
226 xhci->quirks |= XHCI_ZERO_64B_REGS;
227 }
228 if (pdev->vendor == PCI_VENDOR_ID_VIA)
229 xhci->quirks |= XHCI_RESET_ON_RESUME;
230
231 /* See https://bugzilla.kernel.org/show_bug.cgi?id=79511 */
232 if (pdev->vendor == PCI_VENDOR_ID_VIA &&
233 pdev->device == 0x3432)
234 xhci->quirks |= XHCI_BROKEN_STREAMS;
235
236 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
237 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042_XHCI)
238 xhci->quirks |= XHCI_BROKEN_STREAMS;
239 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
240 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
241 xhci->quirks |= XHCI_TRUST_TX_LENGTH;
242 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
243 (pdev->device == PCI_DEVICE_ID_ASMEDIA_1142_XHCI ||
244 pdev->device == PCI_DEVICE_ID_ASMEDIA_2142_XHCI))
245 xhci->quirks |= XHCI_NO_64BIT_SUPPORT;
246
247 if (pdev->vendor == PCI_VENDOR_ID_ASMEDIA &&
248 pdev->device == PCI_DEVICE_ID_ASMEDIA_1042A_XHCI)
249 xhci->quirks |= XHCI_ASMEDIA_MODIFY_FLOWCONTROL;
250
251 if (pdev->vendor == PCI_VENDOR_ID_TI && pdev->device == 0x8241)
252 xhci->quirks |= XHCI_LIMIT_ENDPOINT_INTERVAL_7;
253
254 if ((pdev->vendor == PCI_VENDOR_ID_BROADCOM ||
255 pdev->vendor == PCI_VENDOR_ID_CAVIUM) &&
256 pdev->device == 0x9026)
257 xhci->quirks |= XHCI_RESET_PLL_ON_DISCONNECT;
258
259 if (xhci->quirks & XHCI_RESET_ON_RESUME)
260 xhci_dbg_trace(xhci, trace_xhci_dbg_quirks,
261 "QUIRK: Resetting on resume");
262 }
263
264 #ifdef CONFIG_ACPI
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)265 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev)
266 {
267 static const guid_t intel_dsm_guid =
268 GUID_INIT(0xac340cb7, 0xe901, 0x45bf,
269 0xb7, 0xe6, 0x2b, 0x34, 0xec, 0x93, 0x1e, 0x23);
270 union acpi_object *obj;
271
272 obj = acpi_evaluate_dsm(ACPI_HANDLE(&dev->dev), &intel_dsm_guid, 3, 1,
273 NULL);
274 ACPI_FREE(obj);
275 }
276 #else
xhci_pme_acpi_rtd3_enable(struct pci_dev * dev)277 static void xhci_pme_acpi_rtd3_enable(struct pci_dev *dev) { }
278 #endif /* CONFIG_ACPI */
279
280 /* called during probe() after chip reset completes */
xhci_pci_setup(struct usb_hcd * hcd)281 static int xhci_pci_setup(struct usb_hcd *hcd)
282 {
283 struct xhci_hcd *xhci;
284 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
285 int retval;
286
287 xhci = hcd_to_xhci(hcd);
288 if (!xhci->sbrn)
289 pci_read_config_byte(pdev, XHCI_SBRN_OFFSET, &xhci->sbrn);
290
291 /* imod_interval is the interrupt moderation value in nanoseconds. */
292 xhci->imod_interval = 40000;
293
294 retval = xhci_gen_setup(hcd, xhci_pci_quirks);
295 if (retval)
296 return retval;
297
298 if (!usb_hcd_is_primary_hcd(hcd))
299 return 0;
300
301 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
302 xhci_pme_acpi_rtd3_enable(pdev);
303
304 xhci_dbg(xhci, "Got SBRN %u\n", (unsigned int) xhci->sbrn);
305
306 /* Find any debug ports */
307 return xhci_pci_reinit(xhci, pdev);
308 }
309
310 /*
311 * We need to register our own PCI probe function (instead of the USB core's
312 * function) in order to create a second roothub under xHCI.
313 */
xhci_pci_probe(struct pci_dev * dev,const struct pci_device_id * id)314 static int xhci_pci_probe(struct pci_dev *dev, const struct pci_device_id *id)
315 {
316 int retval;
317 struct xhci_hcd *xhci;
318 struct hc_driver *driver;
319 struct usb_hcd *hcd;
320
321 driver = (struct hc_driver *)id->driver_data;
322
323 /* Prevent runtime suspending between USB-2 and USB-3 initialization */
324 pm_runtime_get_noresume(&dev->dev);
325
326 /* Register the USB 2.0 roothub.
327 * FIXME: USB core must know to register the USB 2.0 roothub first.
328 * This is sort of silly, because we could just set the HCD driver flags
329 * to say USB 2.0, but I'm not sure what the implications would be in
330 * the other parts of the HCD code.
331 */
332 retval = usb_hcd_pci_probe(dev, id);
333
334 if (retval)
335 goto put_runtime_pm;
336
337 /* USB 2.0 roothub is stored in the PCI device now. */
338 hcd = dev_get_drvdata(&dev->dev);
339 xhci = hcd_to_xhci(hcd);
340 xhci->shared_hcd = usb_create_shared_hcd(driver, &dev->dev,
341 pci_name(dev), hcd);
342 if (!xhci->shared_hcd) {
343 retval = -ENOMEM;
344 goto dealloc_usb2_hcd;
345 }
346
347 retval = xhci_ext_cap_init(xhci);
348 if (retval)
349 goto put_usb3_hcd;
350
351 retval = usb_add_hcd(xhci->shared_hcd, dev->irq,
352 IRQF_SHARED);
353 if (retval)
354 goto put_usb3_hcd;
355 /* Roothub already marked as USB 3.0 speed */
356
357 if (!(xhci->quirks & XHCI_BROKEN_STREAMS) &&
358 HCC_MAX_PSA(xhci->hcc_params) >= 4)
359 xhci->shared_hcd->can_do_streams = 1;
360
361 /* USB-2 and USB-3 roothubs initialized, allow runtime pm suspend */
362 pm_runtime_put_noidle(&dev->dev);
363
364 return 0;
365
366 put_usb3_hcd:
367 usb_put_hcd(xhci->shared_hcd);
368 dealloc_usb2_hcd:
369 usb_hcd_pci_remove(dev);
370 put_runtime_pm:
371 pm_runtime_put_noidle(&dev->dev);
372 return retval;
373 }
374
xhci_pci_remove(struct pci_dev * dev)375 static void xhci_pci_remove(struct pci_dev *dev)
376 {
377 struct xhci_hcd *xhci;
378
379 xhci = hcd_to_xhci(pci_get_drvdata(dev));
380 xhci->xhc_state |= XHCI_STATE_REMOVING;
381 if (xhci->shared_hcd) {
382 usb_remove_hcd(xhci->shared_hcd);
383 usb_put_hcd(xhci->shared_hcd);
384 xhci->shared_hcd = NULL;
385 }
386
387 /* Workaround for spurious wakeups at shutdown with HSW */
388 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
389 pci_set_power_state(dev, PCI_D3hot);
390
391 usb_hcd_pci_remove(dev);
392 }
393
394 #ifdef CONFIG_PM
395 /*
396 * In some Intel xHCI controllers, in order to get D3 working,
397 * through a vendor specific SSIC CONFIG register at offset 0x883c,
398 * SSIC PORT need to be marked as "unused" before putting xHCI
399 * into D3. After D3 exit, the SSIC port need to be marked as "used".
400 * Without this change, xHCI might not enter D3 state.
401 */
xhci_ssic_port_unused_quirk(struct usb_hcd * hcd,bool suspend)402 static void xhci_ssic_port_unused_quirk(struct usb_hcd *hcd, bool suspend)
403 {
404 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
405 u32 val;
406 void __iomem *reg;
407 int i;
408
409 for (i = 0; i < SSIC_PORT_NUM; i++) {
410 reg = (void __iomem *) xhci->cap_regs +
411 SSIC_PORT_CFG2 +
412 i * SSIC_PORT_CFG2_OFFSET;
413
414 /* Notify SSIC that SSIC profile programming is not done. */
415 val = readl(reg) & ~PROG_DONE;
416 writel(val, reg);
417
418 /* Mark SSIC port as unused(suspend) or used(resume) */
419 val = readl(reg);
420 if (suspend)
421 val |= SSIC_PORT_UNUSED;
422 else
423 val &= ~SSIC_PORT_UNUSED;
424 writel(val, reg);
425
426 /* Notify SSIC that SSIC profile programming is done */
427 val = readl(reg) | PROG_DONE;
428 writel(val, reg);
429 readl(reg);
430 }
431 }
432
433 /*
434 * Make sure PME works on some Intel xHCI controllers by writing 1 to clear
435 * the Internal PME flag bit in vendor specific PMCTRL register at offset 0x80a4
436 */
xhci_pme_quirk(struct usb_hcd * hcd)437 static void xhci_pme_quirk(struct usb_hcd *hcd)
438 {
439 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
440 void __iomem *reg;
441 u32 val;
442
443 reg = (void __iomem *) xhci->cap_regs + 0x80a4;
444 val = readl(reg);
445 writel(val | BIT(28), reg);
446 readl(reg);
447 }
448
xhci_sparse_control_quirk(struct usb_hcd * hcd)449 static void xhci_sparse_control_quirk(struct usb_hcd *hcd)
450 {
451 u32 reg;
452
453 reg = readl(hcd->regs + SPARSE_CNTL_ENABLE);
454 reg &= ~BIT(SPARSE_DISABLE_BIT);
455 writel(reg, hcd->regs + SPARSE_CNTL_ENABLE);
456 }
457
xhci_pci_suspend(struct usb_hcd * hcd,bool do_wakeup)458 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
459 {
460 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
461 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
462 int ret;
463
464 /*
465 * Systems with the TI redriver that loses port status change events
466 * need to have the registers polled during D3, so avoid D3cold.
467 */
468 if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
469 pci_d3cold_disable(pdev);
470
471 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
472 xhci_pme_quirk(hcd);
473
474 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
475 xhci_ssic_port_unused_quirk(hcd, true);
476
477 if (xhci->quirks & XHCI_DISABLE_SPARSE)
478 xhci_sparse_control_quirk(hcd);
479
480 ret = xhci_suspend(xhci, do_wakeup);
481 if (ret && (xhci->quirks & XHCI_SSIC_PORT_UNUSED))
482 xhci_ssic_port_unused_quirk(hcd, false);
483
484 return ret;
485 }
486
xhci_pci_resume(struct usb_hcd * hcd,bool hibernated)487 static int xhci_pci_resume(struct usb_hcd *hcd, bool hibernated)
488 {
489 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
490 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
491 int retval = 0;
492
493 /* The BIOS on systems with the Intel Panther Point chipset may or may
494 * not support xHCI natively. That means that during system resume, it
495 * may switch the ports back to EHCI so that users can use their
496 * keyboard to select a kernel from GRUB after resume from hibernate.
497 *
498 * The BIOS is supposed to remember whether the OS had xHCI ports
499 * enabled before resume, and switch the ports back to xHCI when the
500 * BIOS/OS semaphore is written, but we all know we can't trust BIOS
501 * writers.
502 *
503 * Unconditionally switch the ports back to xHCI after a system resume.
504 * It should not matter whether the EHCI or xHCI controller is
505 * resumed first. It's enough to do the switchover in xHCI because
506 * USB core won't notice anything as the hub driver doesn't start
507 * running again until after all the devices (including both EHCI and
508 * xHCI host controllers) have been resumed.
509 */
510
511 if (pdev->vendor == PCI_VENDOR_ID_INTEL)
512 usb_enable_intel_xhci_ports(pdev);
513
514 if (xhci->quirks & XHCI_SSIC_PORT_UNUSED)
515 xhci_ssic_port_unused_quirk(hcd, false);
516
517 if (xhci->quirks & XHCI_PME_STUCK_QUIRK)
518 xhci_pme_quirk(hcd);
519
520 retval = xhci_resume(xhci, hibernated);
521 return retval;
522 }
523
xhci_pci_shutdown(struct usb_hcd * hcd)524 static void xhci_pci_shutdown(struct usb_hcd *hcd)
525 {
526 struct xhci_hcd *xhci = hcd_to_xhci(hcd);
527 struct pci_dev *pdev = to_pci_dev(hcd->self.controller);
528
529 xhci_shutdown(hcd);
530
531 /* Yet another workaround for spurious wakeups at shutdown with HSW */
532 if (xhci->quirks & XHCI_SPURIOUS_WAKEUP)
533 pci_set_power_state(pdev, PCI_D3hot);
534 }
535 #endif /* CONFIG_PM */
536
537 /*-------------------------------------------------------------------------*/
538
539 /* PCI driver selection metadata; PCI hotplugging uses this */
540 static const struct pci_device_id pci_ids[] = { {
541 /* handle any USB 3.0 xHCI controller */
542 PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_XHCI, ~0),
543 .driver_data = (unsigned long) &xhci_pci_hc_driver,
544 },
545 { /* end: all zeroes */ }
546 };
547 MODULE_DEVICE_TABLE(pci, pci_ids);
548
549 /* pci driver glue; this is a "new style" PCI driver module */
550 static struct pci_driver xhci_pci_driver = {
551 .name = (char *) hcd_name,
552 .id_table = pci_ids,
553
554 .probe = xhci_pci_probe,
555 .remove = xhci_pci_remove,
556 /* suspend and resume implemented later */
557
558 .shutdown = usb_hcd_pci_shutdown,
559 #ifdef CONFIG_PM
560 .driver = {
561 .pm = &usb_hcd_pci_pm_ops
562 },
563 #endif
564 };
565
xhci_pci_init(void)566 static int __init xhci_pci_init(void)
567 {
568 xhci_init_driver(&xhci_pci_hc_driver, &xhci_pci_overrides);
569 #ifdef CONFIG_PM
570 xhci_pci_hc_driver.pci_suspend = xhci_pci_suspend;
571 xhci_pci_hc_driver.pci_resume = xhci_pci_resume;
572 xhci_pci_hc_driver.shutdown = xhci_pci_shutdown;
573 #endif
574 return pci_register_driver(&xhci_pci_driver);
575 }
576 module_init(xhci_pci_init);
577
xhci_pci_exit(void)578 static void __exit xhci_pci_exit(void)
579 {
580 pci_unregister_driver(&xhci_pci_driver);
581 }
582 module_exit(xhci_pci_exit);
583
584 MODULE_DESCRIPTION("xHCI PCI Host Controller Driver");
585 MODULE_LICENSE("GPL");
586