1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * mtu3_core.c - hardware access layer and gadget init/exit of
4 * MediaTek usb3 Dual-Role Controller Driver
5 *
6 * Copyright (C) 2016 MediaTek Inc.
7 *
8 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
9 */
10
11 #include <linux/dma-mapping.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of_address.h>
15 #include <linux/of_irq.h>
16 #include <linux/platform_device.h>
17
18 #include "mtu3.h"
19
ep_fifo_alloc(struct mtu3_ep * mep,u32 seg_size)20 static int ep_fifo_alloc(struct mtu3_ep *mep, u32 seg_size)
21 {
22 struct mtu3_fifo_info *fifo = mep->fifo;
23 u32 num_bits = DIV_ROUND_UP(seg_size, MTU3_EP_FIFO_UNIT);
24 u32 start_bit;
25
26 /* ensure that @mep->fifo_seg_size is power of two */
27 num_bits = roundup_pow_of_two(num_bits);
28 if (num_bits > fifo->limit)
29 return -EINVAL;
30
31 mep->fifo_seg_size = num_bits * MTU3_EP_FIFO_UNIT;
32 num_bits = num_bits * (mep->slot + 1);
33 start_bit = bitmap_find_next_zero_area(fifo->bitmap,
34 fifo->limit, 0, num_bits, 0);
35 if (start_bit >= fifo->limit)
36 return -EOVERFLOW;
37
38 bitmap_set(fifo->bitmap, start_bit, num_bits);
39 mep->fifo_size = num_bits * MTU3_EP_FIFO_UNIT;
40 mep->fifo_addr = fifo->base + MTU3_EP_FIFO_UNIT * start_bit;
41
42 dev_dbg(mep->mtu->dev, "%s fifo:%#x/%#x, start_bit: %d\n",
43 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
44
45 return mep->fifo_addr;
46 }
47
ep_fifo_free(struct mtu3_ep * mep)48 static void ep_fifo_free(struct mtu3_ep *mep)
49 {
50 struct mtu3_fifo_info *fifo = mep->fifo;
51 u32 addr = mep->fifo_addr;
52 u32 bits = mep->fifo_size / MTU3_EP_FIFO_UNIT;
53 u32 start_bit;
54
55 if (unlikely(addr < fifo->base || bits > fifo->limit))
56 return;
57
58 start_bit = (addr - fifo->base) / MTU3_EP_FIFO_UNIT;
59 bitmap_clear(fifo->bitmap, start_bit, bits);
60 mep->fifo_size = 0;
61 mep->fifo_seg_size = 0;
62
63 dev_dbg(mep->mtu->dev, "%s size:%#x/%#x, start_bit: %d\n",
64 __func__, mep->fifo_seg_size, mep->fifo_size, start_bit);
65 }
66
67 /* enable/disable U3D SS function */
mtu3_ss_func_set(struct mtu3 * mtu,bool enable)68 static inline void mtu3_ss_func_set(struct mtu3 *mtu, bool enable)
69 {
70 /* If usb3_en==0, LTSSM will go to SS.Disable state */
71 if (enable)
72 mtu3_setbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
73 else
74 mtu3_clrbits(mtu->mac_base, U3D_USB3_CONFIG, USB3_EN);
75
76 dev_dbg(mtu->dev, "USB3_EN = %d\n", !!enable);
77 }
78
79 /* set/clear U3D HS device soft connect */
mtu3_hs_softconn_set(struct mtu3 * mtu,bool enable)80 static inline void mtu3_hs_softconn_set(struct mtu3 *mtu, bool enable)
81 {
82 if (enable) {
83 mtu3_setbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
84 SOFT_CONN | SUSPENDM_ENABLE);
85 } else {
86 mtu3_clrbits(mtu->mac_base, U3D_POWER_MANAGEMENT,
87 SOFT_CONN | SUSPENDM_ENABLE);
88 }
89 dev_dbg(mtu->dev, "SOFTCONN = %d\n", !!enable);
90 }
91
92 /* only port0 of U2/U3 supports device mode */
mtu3_device_enable(struct mtu3 * mtu)93 static int mtu3_device_enable(struct mtu3 *mtu)
94 {
95 void __iomem *ibase = mtu->ippc_base;
96 u32 check_clk = 0;
97
98 mtu3_clrbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
99
100 if (mtu->is_u3_ip) {
101 check_clk = SSUSB_U3_MAC_RST_B_STS;
102 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
103 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN |
104 SSUSB_U3_PORT_HOST_SEL));
105 }
106 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0),
107 (SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN |
108 SSUSB_U2_PORT_HOST_SEL));
109
110 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
111 mtu3_setbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
112 if (mtu->is_u3_ip)
113 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
114 SSUSB_U3_PORT_DUAL_MODE);
115 }
116
117 return ssusb_check_clocks(mtu->ssusb, check_clk);
118 }
119
mtu3_device_disable(struct mtu3 * mtu)120 static void mtu3_device_disable(struct mtu3 *mtu)
121 {
122 void __iomem *ibase = mtu->ippc_base;
123
124 if (mtu->is_u3_ip)
125 mtu3_setbits(ibase, SSUSB_U3_CTRL(0),
126 (SSUSB_U3_PORT_DIS | SSUSB_U3_PORT_PDN));
127
128 mtu3_setbits(ibase, SSUSB_U2_CTRL(0),
129 SSUSB_U2_PORT_DIS | SSUSB_U2_PORT_PDN);
130
131 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG) {
132 mtu3_clrbits(ibase, SSUSB_U2_CTRL(0), SSUSB_U2_PORT_OTG_SEL);
133 if (mtu->is_u3_ip)
134 mtu3_clrbits(ibase, SSUSB_U3_CTRL(0),
135 SSUSB_U3_PORT_DUAL_MODE);
136 }
137
138 mtu3_setbits(ibase, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
139 }
140
141 /* reset U3D's device module. */
mtu3_device_reset(struct mtu3 * mtu)142 static void mtu3_device_reset(struct mtu3 *mtu)
143 {
144 void __iomem *ibase = mtu->ippc_base;
145
146 mtu3_setbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
147 udelay(1);
148 mtu3_clrbits(ibase, U3D_SSUSB_DEV_RST_CTRL, SSUSB_DEV_SW_RST);
149 }
150
151 /* disable all interrupts */
mtu3_intr_disable(struct mtu3 * mtu)152 static void mtu3_intr_disable(struct mtu3 *mtu)
153 {
154 void __iomem *mbase = mtu->mac_base;
155
156 /* Disable level 1 interrupts */
157 mtu3_writel(mbase, U3D_LV1IECR, ~0x0);
158 /* Disable endpoint interrupts */
159 mtu3_writel(mbase, U3D_EPIECR, ~0x0);
160 }
161
mtu3_intr_status_clear(struct mtu3 * mtu)162 static void mtu3_intr_status_clear(struct mtu3 *mtu)
163 {
164 void __iomem *mbase = mtu->mac_base;
165
166 /* Clear EP0 and Tx/Rx EPn interrupts status */
167 mtu3_writel(mbase, U3D_EPISR, ~0x0);
168 /* Clear U2 USB common interrupts status */
169 mtu3_writel(mbase, U3D_COMMON_USB_INTR, ~0x0);
170 /* Clear U3 LTSSM interrupts status */
171 mtu3_writel(mbase, U3D_LTSSM_INTR, ~0x0);
172 /* Clear speed change interrupt status */
173 mtu3_writel(mbase, U3D_DEV_LINK_INTR, ~0x0);
174 }
175
176 /* enable system global interrupt */
mtu3_intr_enable(struct mtu3 * mtu)177 static void mtu3_intr_enable(struct mtu3 *mtu)
178 {
179 void __iomem *mbase = mtu->mac_base;
180 u32 value;
181
182 /*Enable level 1 interrupts (BMU, QMU, MAC3, DMA, MAC2, EPCTL) */
183 value = BMU_INTR | QMU_INTR | MAC3_INTR | MAC2_INTR | EP_CTRL_INTR;
184 mtu3_writel(mbase, U3D_LV1IESR, value);
185
186 /* Enable U2 common USB interrupts */
187 value = SUSPEND_INTR | RESUME_INTR | RESET_INTR | LPM_RESUME_INTR;
188 mtu3_writel(mbase, U3D_COMMON_USB_INTR_ENABLE, value);
189
190 if (mtu->is_u3_ip) {
191 /* Enable U3 LTSSM interrupts */
192 value = HOT_RST_INTR | WARM_RST_INTR |
193 ENTER_U3_INTR | EXIT_U3_INTR;
194 mtu3_writel(mbase, U3D_LTSSM_INTR_ENABLE, value);
195 }
196
197 /* Enable QMU interrupts. */
198 value = TXQ_CSERR_INT | TXQ_LENERR_INT | RXQ_CSERR_INT |
199 RXQ_LENERR_INT | RXQ_ZLPERR_INT;
200 mtu3_writel(mbase, U3D_QIESR1, value);
201
202 /* Enable speed change interrupt */
203 mtu3_writel(mbase, U3D_DEV_LINK_INTR_ENABLE, SSUSB_DEV_SPEED_CHG_INTR);
204 }
205
206 /* reset: u2 - data toggle, u3 - SeqN, flow control status etc */
mtu3_ep_reset(struct mtu3_ep * mep)207 static void mtu3_ep_reset(struct mtu3_ep *mep)
208 {
209 struct mtu3 *mtu = mep->mtu;
210 u32 rst_bit = EP_RST(mep->is_in, mep->epnum);
211
212 mtu3_setbits(mtu->mac_base, U3D_EP_RST, rst_bit);
213 mtu3_clrbits(mtu->mac_base, U3D_EP_RST, rst_bit);
214 }
215
216 /* set/clear the stall and toggle bits for non-ep0 */
mtu3_ep_stall_set(struct mtu3_ep * mep,bool set)217 void mtu3_ep_stall_set(struct mtu3_ep *mep, bool set)
218 {
219 struct mtu3 *mtu = mep->mtu;
220 void __iomem *mbase = mtu->mac_base;
221 u8 epnum = mep->epnum;
222 u32 csr;
223
224 if (mep->is_in) { /* TX */
225 csr = mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)) & TX_W1C_BITS;
226 if (set)
227 csr |= TX_SENDSTALL;
228 else
229 csr = (csr & (~TX_SENDSTALL)) | TX_SENTSTALL;
230 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr);
231 } else { /* RX */
232 csr = mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)) & RX_W1C_BITS;
233 if (set)
234 csr |= RX_SENDSTALL;
235 else
236 csr = (csr & (~RX_SENDSTALL)) | RX_SENTSTALL;
237 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr);
238 }
239
240 if (!set) {
241 mtu3_ep_reset(mep);
242 mep->flags &= ~MTU3_EP_STALL;
243 } else {
244 mep->flags |= MTU3_EP_STALL;
245 }
246
247 dev_dbg(mtu->dev, "%s: %s\n", mep->name,
248 set ? "SEND STALL" : "CLEAR STALL, with EP RESET");
249 }
250
mtu3_dev_on_off(struct mtu3 * mtu,int is_on)251 void mtu3_dev_on_off(struct mtu3 *mtu, int is_on)
252 {
253 if (mtu->is_u3_ip && mtu->max_speed >= USB_SPEED_SUPER)
254 mtu3_ss_func_set(mtu, is_on);
255 else
256 mtu3_hs_softconn_set(mtu, is_on);
257
258 dev_info(mtu->dev, "gadget (%s) pullup D%s\n",
259 usb_speed_string(mtu->max_speed), is_on ? "+" : "-");
260 }
261
mtu3_start(struct mtu3 * mtu)262 void mtu3_start(struct mtu3 *mtu)
263 {
264 void __iomem *mbase = mtu->mac_base;
265
266 dev_dbg(mtu->dev, "%s devctl 0x%x\n", __func__,
267 mtu3_readl(mbase, U3D_DEVICE_CONTROL));
268
269 mtu3_clrbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
270
271 /*
272 * When disable U2 port, USB2_CSR's register will be reset to
273 * default value after re-enable it again(HS is enabled by default).
274 * So if force mac to work as FS, disable HS function.
275 */
276 if (mtu->max_speed == USB_SPEED_FULL)
277 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
278
279 /* Initialize the default interrupts */
280 mtu3_intr_enable(mtu);
281 mtu->is_active = 1;
282
283 if (mtu->softconnect)
284 mtu3_dev_on_off(mtu, 1);
285 }
286
mtu3_stop(struct mtu3 * mtu)287 void mtu3_stop(struct mtu3 *mtu)
288 {
289 dev_dbg(mtu->dev, "%s\n", __func__);
290
291 mtu3_intr_disable(mtu);
292 mtu3_intr_status_clear(mtu);
293
294 if (mtu->softconnect)
295 mtu3_dev_on_off(mtu, 0);
296
297 mtu->is_active = 0;
298 mtu3_setbits(mtu->ippc_base, U3D_SSUSB_IP_PW_CTRL2, SSUSB_IP_DEV_PDN);
299 }
300
301 /* for non-ep0 */
mtu3_config_ep(struct mtu3 * mtu,struct mtu3_ep * mep,int interval,int burst,int mult)302 int mtu3_config_ep(struct mtu3 *mtu, struct mtu3_ep *mep,
303 int interval, int burst, int mult)
304 {
305 void __iomem *mbase = mtu->mac_base;
306 int epnum = mep->epnum;
307 u32 csr0, csr1, csr2;
308 int fifo_sgsz, fifo_addr;
309 int num_pkts;
310
311 fifo_addr = ep_fifo_alloc(mep, mep->maxp);
312 if (fifo_addr < 0) {
313 dev_err(mtu->dev, "alloc ep fifo failed(%d)\n", mep->maxp);
314 return -ENOMEM;
315 }
316 fifo_sgsz = ilog2(mep->fifo_seg_size);
317 dev_dbg(mtu->dev, "%s fifosz: %x(%x/%x)\n", __func__, fifo_sgsz,
318 mep->fifo_seg_size, mep->fifo_size);
319
320 if (mep->is_in) {
321 csr0 = TX_TXMAXPKTSZ(mep->maxp);
322 csr0 |= TX_DMAREQEN;
323
324 num_pkts = (burst + 1) * (mult + 1) - 1;
325 csr1 = TX_SS_BURST(burst) | TX_SLOT(mep->slot);
326 csr1 |= TX_MAX_PKT(num_pkts) | TX_MULT(mult);
327
328 csr2 = TX_FIFOADDR(fifo_addr >> 4);
329 csr2 |= TX_FIFOSEGSIZE(fifo_sgsz);
330
331 switch (mep->type) {
332 case USB_ENDPOINT_XFER_BULK:
333 csr1 |= TX_TYPE(TYPE_BULK);
334 break;
335 case USB_ENDPOINT_XFER_ISOC:
336 csr1 |= TX_TYPE(TYPE_ISO);
337 csr2 |= TX_BINTERVAL(interval);
338 break;
339 case USB_ENDPOINT_XFER_INT:
340 csr1 |= TX_TYPE(TYPE_INT);
341 csr2 |= TX_BINTERVAL(interval);
342 break;
343 }
344
345 /* Enable QMU Done interrupt */
346 mtu3_setbits(mbase, U3D_QIESR0, QMU_TX_DONE_INT(epnum));
347
348 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), csr0);
349 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), csr1);
350 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), csr2);
351
352 dev_dbg(mtu->dev, "U3D_TX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
353 epnum, mtu3_readl(mbase, MU3D_EP_TXCR0(epnum)),
354 mtu3_readl(mbase, MU3D_EP_TXCR1(epnum)),
355 mtu3_readl(mbase, MU3D_EP_TXCR2(epnum)));
356 } else {
357 csr0 = RX_RXMAXPKTSZ(mep->maxp);
358 csr0 |= RX_DMAREQEN;
359
360 num_pkts = (burst + 1) * (mult + 1) - 1;
361 csr1 = RX_SS_BURST(burst) | RX_SLOT(mep->slot);
362 csr1 |= RX_MAX_PKT(num_pkts) | RX_MULT(mult);
363
364 csr2 = RX_FIFOADDR(fifo_addr >> 4);
365 csr2 |= RX_FIFOSEGSIZE(fifo_sgsz);
366
367 switch (mep->type) {
368 case USB_ENDPOINT_XFER_BULK:
369 csr1 |= RX_TYPE(TYPE_BULK);
370 break;
371 case USB_ENDPOINT_XFER_ISOC:
372 csr1 |= RX_TYPE(TYPE_ISO);
373 csr2 |= RX_BINTERVAL(interval);
374 break;
375 case USB_ENDPOINT_XFER_INT:
376 csr1 |= RX_TYPE(TYPE_INT);
377 csr2 |= RX_BINTERVAL(interval);
378 break;
379 }
380
381 /*Enable QMU Done interrupt */
382 mtu3_setbits(mbase, U3D_QIESR0, QMU_RX_DONE_INT(epnum));
383
384 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), csr0);
385 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), csr1);
386 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), csr2);
387
388 dev_dbg(mtu->dev, "U3D_RX%d CSR0:%#x, CSR1:%#x, CSR2:%#x\n",
389 epnum, mtu3_readl(mbase, MU3D_EP_RXCR0(epnum)),
390 mtu3_readl(mbase, MU3D_EP_RXCR1(epnum)),
391 mtu3_readl(mbase, MU3D_EP_RXCR2(epnum)));
392 }
393
394 dev_dbg(mtu->dev, "csr0:%#x, csr1:%#x, csr2:%#x\n", csr0, csr1, csr2);
395 dev_dbg(mtu->dev, "%s: %s, fifo-addr:%#x, fifo-size:%#x(%#x/%#x)\n",
396 __func__, mep->name, mep->fifo_addr, mep->fifo_size,
397 fifo_sgsz, mep->fifo_seg_size);
398
399 return 0;
400 }
401
402 /* for non-ep0 */
mtu3_deconfig_ep(struct mtu3 * mtu,struct mtu3_ep * mep)403 void mtu3_deconfig_ep(struct mtu3 *mtu, struct mtu3_ep *mep)
404 {
405 void __iomem *mbase = mtu->mac_base;
406 int epnum = mep->epnum;
407
408 if (mep->is_in) {
409 mtu3_writel(mbase, MU3D_EP_TXCR0(epnum), 0);
410 mtu3_writel(mbase, MU3D_EP_TXCR1(epnum), 0);
411 mtu3_writel(mbase, MU3D_EP_TXCR2(epnum), 0);
412 mtu3_setbits(mbase, U3D_QIECR0, QMU_TX_DONE_INT(epnum));
413 } else {
414 mtu3_writel(mbase, MU3D_EP_RXCR0(epnum), 0);
415 mtu3_writel(mbase, MU3D_EP_RXCR1(epnum), 0);
416 mtu3_writel(mbase, MU3D_EP_RXCR2(epnum), 0);
417 mtu3_setbits(mbase, U3D_QIECR0, QMU_RX_DONE_INT(epnum));
418 }
419
420 mtu3_ep_reset(mep);
421 ep_fifo_free(mep);
422
423 dev_dbg(mtu->dev, "%s: %s\n", __func__, mep->name);
424 }
425
426 /*
427 * Two scenarios:
428 * 1. when device IP supports SS, the fifo of EP0, TX EPs, RX EPs
429 * are separated;
430 * 2. when supports only HS, the fifo is shared for all EPs, and
431 * the capability registers of @EPNTXFFSZ or @EPNRXFFSZ indicate
432 * the total fifo size of non-ep0, and ep0's is fixed to 64B,
433 * so the total fifo size is 64B + @EPNTXFFSZ;
434 * Due to the first 64B should be reserved for EP0, non-ep0's fifo
435 * starts from offset 64 and are divided into two equal parts for
436 * TX or RX EPs for simplification.
437 */
get_ep_fifo_config(struct mtu3 * mtu)438 static void get_ep_fifo_config(struct mtu3 *mtu)
439 {
440 struct mtu3_fifo_info *tx_fifo;
441 struct mtu3_fifo_info *rx_fifo;
442 u32 fifosize;
443
444 if (mtu->is_u3_ip) {
445 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
446 tx_fifo = &mtu->tx_fifo;
447 tx_fifo->base = 0;
448 tx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
449 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
450
451 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNRXFFSZ);
452 rx_fifo = &mtu->rx_fifo;
453 rx_fifo->base = 0;
454 rx_fifo->limit = fifosize / MTU3_EP_FIFO_UNIT;
455 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
456 mtu->slot = MTU3_U3_IP_SLOT_DEFAULT;
457 } else {
458 fifosize = mtu3_readl(mtu->mac_base, U3D_CAP_EPNTXFFSZ);
459 tx_fifo = &mtu->tx_fifo;
460 tx_fifo->base = MTU3_U2_IP_EP0_FIFO_SIZE;
461 tx_fifo->limit = (fifosize / MTU3_EP_FIFO_UNIT) >> 1;
462 bitmap_zero(tx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
463
464 rx_fifo = &mtu->rx_fifo;
465 rx_fifo->base =
466 tx_fifo->base + tx_fifo->limit * MTU3_EP_FIFO_UNIT;
467 rx_fifo->limit = tx_fifo->limit;
468 bitmap_zero(rx_fifo->bitmap, MTU3_FIFO_BIT_SIZE);
469 mtu->slot = MTU3_U2_IP_SLOT_DEFAULT;
470 }
471
472 dev_dbg(mtu->dev, "%s, TX: base-%d, limit-%d; RX: base-%d, limit-%d\n",
473 __func__, tx_fifo->base, tx_fifo->limit,
474 rx_fifo->base, rx_fifo->limit);
475 }
476
mtu3_ep0_setup(struct mtu3 * mtu)477 void mtu3_ep0_setup(struct mtu3 *mtu)
478 {
479 u32 maxpacket = mtu->g.ep0->maxpacket;
480 u32 csr;
481
482 dev_dbg(mtu->dev, "%s maxpacket: %d\n", __func__, maxpacket);
483
484 csr = mtu3_readl(mtu->mac_base, U3D_EP0CSR);
485 csr &= ~EP0_MAXPKTSZ_MSK;
486 csr |= EP0_MAXPKTSZ(maxpacket);
487 csr &= EP0_W1C_BITS;
488 mtu3_writel(mtu->mac_base, U3D_EP0CSR, csr);
489
490 /* Enable EP0 interrupt */
491 mtu3_writel(mtu->mac_base, U3D_EPIESR, EP0ISR);
492 }
493
mtu3_mem_alloc(struct mtu3 * mtu)494 static int mtu3_mem_alloc(struct mtu3 *mtu)
495 {
496 void __iomem *mbase = mtu->mac_base;
497 struct mtu3_ep *ep_array;
498 int in_ep_num, out_ep_num;
499 u32 cap_epinfo;
500 int ret;
501 int i;
502
503 cap_epinfo = mtu3_readl(mbase, U3D_CAP_EPINFO);
504 in_ep_num = CAP_TX_EP_NUM(cap_epinfo);
505 out_ep_num = CAP_RX_EP_NUM(cap_epinfo);
506
507 dev_info(mtu->dev, "fifosz/epnum: Tx=%#x/%d, Rx=%#x/%d\n",
508 mtu3_readl(mbase, U3D_CAP_EPNTXFFSZ), in_ep_num,
509 mtu3_readl(mbase, U3D_CAP_EPNRXFFSZ), out_ep_num);
510
511 /* one for ep0, another is reserved */
512 mtu->num_eps = min(in_ep_num, out_ep_num) + 1;
513 ep_array = kcalloc(mtu->num_eps * 2, sizeof(*ep_array), GFP_KERNEL);
514 if (ep_array == NULL)
515 return -ENOMEM;
516
517 mtu->ep_array = ep_array;
518 mtu->in_eps = ep_array;
519 mtu->out_eps = &ep_array[mtu->num_eps];
520 /* ep0 uses in_eps[0], out_eps[0] is reserved */
521 mtu->ep0 = mtu->in_eps;
522 mtu->ep0->mtu = mtu;
523 mtu->ep0->epnum = 0;
524
525 for (i = 1; i < mtu->num_eps; i++) {
526 struct mtu3_ep *mep = mtu->in_eps + i;
527
528 mep->fifo = &mtu->tx_fifo;
529 mep = mtu->out_eps + i;
530 mep->fifo = &mtu->rx_fifo;
531 }
532
533 get_ep_fifo_config(mtu);
534
535 ret = mtu3_qmu_init(mtu);
536 if (ret)
537 kfree(mtu->ep_array);
538
539 return ret;
540 }
541
mtu3_mem_free(struct mtu3 * mtu)542 static void mtu3_mem_free(struct mtu3 *mtu)
543 {
544 mtu3_qmu_exit(mtu);
545 kfree(mtu->ep_array);
546 }
547
mtu3_set_speed(struct mtu3 * mtu)548 static void mtu3_set_speed(struct mtu3 *mtu)
549 {
550 void __iomem *mbase = mtu->mac_base;
551
552 if (!mtu->is_u3_ip && (mtu->max_speed > USB_SPEED_HIGH))
553 mtu->max_speed = USB_SPEED_HIGH;
554
555 if (mtu->max_speed == USB_SPEED_FULL) {
556 /* disable U3 SS function */
557 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
558 /* disable HS function */
559 mtu3_clrbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
560 } else if (mtu->max_speed == USB_SPEED_HIGH) {
561 mtu3_clrbits(mbase, U3D_USB3_CONFIG, USB3_EN);
562 /* HS/FS detected by HW */
563 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT, HS_ENABLE);
564 } else if (mtu->max_speed == USB_SPEED_SUPER) {
565 mtu3_clrbits(mtu->ippc_base, SSUSB_U3_CTRL(0),
566 SSUSB_U3_PORT_SSP_SPEED);
567 }
568
569 dev_info(mtu->dev, "max_speed: %s\n",
570 usb_speed_string(mtu->max_speed));
571 }
572
mtu3_regs_init(struct mtu3 * mtu)573 static void mtu3_regs_init(struct mtu3 *mtu)
574 {
575
576 void __iomem *mbase = mtu->mac_base;
577
578 /* be sure interrupts are disabled before registration of ISR */
579 mtu3_intr_disable(mtu);
580 mtu3_intr_status_clear(mtu);
581
582 if (mtu->is_u3_ip) {
583 /* disable LGO_U1/U2 by default */
584 mtu3_clrbits(mbase, U3D_LINK_POWER_CONTROL,
585 SW_U1_REQUEST_ENABLE | SW_U2_REQUEST_ENABLE);
586 /* enable accept LGO_U1/U2 link command from host */
587 mtu3_setbits(mbase, U3D_LINK_POWER_CONTROL,
588 SW_U1_ACCEPT_ENABLE | SW_U2_ACCEPT_ENABLE);
589 /* device responses to u3_exit from host automatically */
590 mtu3_clrbits(mbase, U3D_LTSSM_CTRL, SOFT_U3_EXIT_EN);
591 /* automatically build U2 link when U3 detect fail */
592 mtu3_setbits(mbase, U3D_USB2_TEST_MODE, U2U3_AUTO_SWITCH);
593 }
594
595 mtu3_set_speed(mtu);
596
597 /* delay about 0.1us from detecting reset to send chirp-K */
598 mtu3_clrbits(mbase, U3D_LINK_RESET_INFO, WTCHRP_MSK);
599 /* U2/U3 detected by HW */
600 mtu3_writel(mbase, U3D_DEVICE_CONF, 0);
601 /* enable QMU 16B checksum */
602 mtu3_setbits(mbase, U3D_QCR0, QMU_CS16B_EN);
603 /* vbus detected by HW */
604 mtu3_clrbits(mbase, U3D_MISC_CTRL, VBUS_FRC_EN | VBUS_ON);
605 }
606
mtu3_link_isr(struct mtu3 * mtu)607 static irqreturn_t mtu3_link_isr(struct mtu3 *mtu)
608 {
609 void __iomem *mbase = mtu->mac_base;
610 enum usb_device_speed udev_speed;
611 u32 maxpkt = 64;
612 u32 link;
613 u32 speed;
614
615 link = mtu3_readl(mbase, U3D_DEV_LINK_INTR);
616 link &= mtu3_readl(mbase, U3D_DEV_LINK_INTR_ENABLE);
617 mtu3_writel(mbase, U3D_DEV_LINK_INTR, link); /* W1C */
618 dev_dbg(mtu->dev, "=== LINK[%x] ===\n", link);
619
620 if (!(link & SSUSB_DEV_SPEED_CHG_INTR))
621 return IRQ_NONE;
622
623 speed = SSUSB_DEV_SPEED(mtu3_readl(mbase, U3D_DEVICE_CONF));
624
625 switch (speed) {
626 case MTU3_SPEED_FULL:
627 udev_speed = USB_SPEED_FULL;
628 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
629 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
630 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
631 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
632 LPM_BESL_STALL | LPM_BESLD_STALL);
633 break;
634 case MTU3_SPEED_HIGH:
635 udev_speed = USB_SPEED_HIGH;
636 /*BESLCK = 4 < BESLCK_U3 = 10 < BESLDCK = 15 */
637 mtu3_writel(mbase, U3D_USB20_LPM_PARAMETER, LPM_BESLDCK(0xf)
638 | LPM_BESLCK(4) | LPM_BESLCK_U3(0xa));
639 mtu3_setbits(mbase, U3D_POWER_MANAGEMENT,
640 LPM_BESL_STALL | LPM_BESLD_STALL);
641 break;
642 case MTU3_SPEED_SUPER:
643 udev_speed = USB_SPEED_SUPER;
644 maxpkt = 512;
645 break;
646 case MTU3_SPEED_SUPER_PLUS:
647 udev_speed = USB_SPEED_SUPER_PLUS;
648 maxpkt = 512;
649 break;
650 default:
651 udev_speed = USB_SPEED_UNKNOWN;
652 break;
653 }
654 dev_dbg(mtu->dev, "%s: %s\n", __func__, usb_speed_string(udev_speed));
655
656 mtu->g.speed = udev_speed;
657 mtu->g.ep0->maxpacket = maxpkt;
658 mtu->ep0_state = MU3D_EP0_STATE_SETUP;
659
660 if (udev_speed == USB_SPEED_UNKNOWN)
661 mtu3_gadget_disconnect(mtu);
662 else
663 mtu3_ep0_setup(mtu);
664
665 return IRQ_HANDLED;
666 }
667
mtu3_u3_ltssm_isr(struct mtu3 * mtu)668 static irqreturn_t mtu3_u3_ltssm_isr(struct mtu3 *mtu)
669 {
670 void __iomem *mbase = mtu->mac_base;
671 u32 ltssm;
672
673 ltssm = mtu3_readl(mbase, U3D_LTSSM_INTR);
674 ltssm &= mtu3_readl(mbase, U3D_LTSSM_INTR_ENABLE);
675 mtu3_writel(mbase, U3D_LTSSM_INTR, ltssm); /* W1C */
676 dev_dbg(mtu->dev, "=== LTSSM[%x] ===\n", ltssm);
677
678 if (ltssm & (HOT_RST_INTR | WARM_RST_INTR))
679 mtu3_gadget_reset(mtu);
680
681 if (ltssm & VBUS_FALL_INTR) {
682 mtu3_ss_func_set(mtu, false);
683 mtu3_gadget_reset(mtu);
684 }
685
686 if (ltssm & VBUS_RISE_INTR)
687 mtu3_ss_func_set(mtu, true);
688
689 if (ltssm & EXIT_U3_INTR)
690 mtu3_gadget_resume(mtu);
691
692 if (ltssm & ENTER_U3_INTR)
693 mtu3_gadget_suspend(mtu);
694
695 return IRQ_HANDLED;
696 }
697
mtu3_u2_common_isr(struct mtu3 * mtu)698 static irqreturn_t mtu3_u2_common_isr(struct mtu3 *mtu)
699 {
700 void __iomem *mbase = mtu->mac_base;
701 u32 u2comm;
702
703 u2comm = mtu3_readl(mbase, U3D_COMMON_USB_INTR);
704 u2comm &= mtu3_readl(mbase, U3D_COMMON_USB_INTR_ENABLE);
705 mtu3_writel(mbase, U3D_COMMON_USB_INTR, u2comm); /* W1C */
706 dev_dbg(mtu->dev, "=== U2COMM[%x] ===\n", u2comm);
707
708 if (u2comm & SUSPEND_INTR)
709 mtu3_gadget_suspend(mtu);
710
711 if (u2comm & RESUME_INTR)
712 mtu3_gadget_resume(mtu);
713
714 if (u2comm & RESET_INTR)
715 mtu3_gadget_reset(mtu);
716
717 if (u2comm & LPM_RESUME_INTR) {
718 if (!(mtu3_readl(mbase, U3D_POWER_MANAGEMENT) & LPM_HRWE))
719 mtu3_setbits(mbase, U3D_USB20_MISC_CONTROL,
720 LPM_U3_ACK_EN);
721 }
722
723 return IRQ_HANDLED;
724 }
725
mtu3_irq(int irq,void * data)726 static irqreturn_t mtu3_irq(int irq, void *data)
727 {
728 struct mtu3 *mtu = (struct mtu3 *)data;
729 unsigned long flags;
730 u32 level1;
731
732 spin_lock_irqsave(&mtu->lock, flags);
733
734 /* U3D_LV1ISR is RU */
735 level1 = mtu3_readl(mtu->mac_base, U3D_LV1ISR);
736 level1 &= mtu3_readl(mtu->mac_base, U3D_LV1IER);
737
738 if (level1 & EP_CTRL_INTR)
739 mtu3_link_isr(mtu);
740
741 if (level1 & MAC2_INTR)
742 mtu3_u2_common_isr(mtu);
743
744 if (level1 & MAC3_INTR)
745 mtu3_u3_ltssm_isr(mtu);
746
747 if (level1 & BMU_INTR)
748 mtu3_ep0_isr(mtu);
749
750 if (level1 & QMU_INTR)
751 mtu3_qmu_isr(mtu);
752
753 spin_unlock_irqrestore(&mtu->lock, flags);
754
755 return IRQ_HANDLED;
756 }
757
mtu3_hw_init(struct mtu3 * mtu)758 static int mtu3_hw_init(struct mtu3 *mtu)
759 {
760 u32 cap_dev;
761 int ret;
762
763 mtu->hw_version = mtu3_readl(mtu->ippc_base, U3D_SSUSB_HW_ID);
764
765 cap_dev = mtu3_readl(mtu->ippc_base, U3D_SSUSB_IP_DEV_CAP);
766 mtu->is_u3_ip = !!SSUSB_IP_DEV_U3_PORT_NUM(cap_dev);
767
768 dev_info(mtu->dev, "IP version 0x%x(%s IP)\n", mtu->hw_version,
769 mtu->is_u3_ip ? "U3" : "U2");
770
771 mtu3_device_reset(mtu);
772
773 ret = mtu3_device_enable(mtu);
774 if (ret) {
775 dev_err(mtu->dev, "device enable failed %d\n", ret);
776 return ret;
777 }
778
779 ret = mtu3_mem_alloc(mtu);
780 if (ret)
781 return -ENOMEM;
782
783 mtu3_regs_init(mtu);
784
785 return 0;
786 }
787
mtu3_hw_exit(struct mtu3 * mtu)788 static void mtu3_hw_exit(struct mtu3 *mtu)
789 {
790 mtu3_device_disable(mtu);
791 mtu3_mem_free(mtu);
792 }
793
794 /**
795 * we set 32-bit DMA mask by default, here check whether the controller
796 * supports 36-bit DMA or not, if it does, set 36-bit DMA mask.
797 */
mtu3_set_dma_mask(struct mtu3 * mtu)798 static int mtu3_set_dma_mask(struct mtu3 *mtu)
799 {
800 struct device *dev = mtu->dev;
801 bool is_36bit = false;
802 int ret = 0;
803 u32 value;
804
805 value = mtu3_readl(mtu->mac_base, U3D_MISC_CTRL);
806 if (value & DMA_ADDR_36BIT) {
807 is_36bit = true;
808 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(36));
809 /* If set 36-bit DMA mask fails, fall back to 32-bit DMA mask */
810 if (ret) {
811 is_36bit = false;
812 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
813 }
814 }
815 dev_info(dev, "dma mask: %s bits\n", is_36bit ? "36" : "32");
816
817 return ret;
818 }
819
ssusb_gadget_init(struct ssusb_mtk * ssusb)820 int ssusb_gadget_init(struct ssusb_mtk *ssusb)
821 {
822 struct device *dev = ssusb->dev;
823 struct platform_device *pdev = to_platform_device(dev);
824 struct mtu3 *mtu = NULL;
825 struct resource *res;
826 int ret = -ENOMEM;
827
828 mtu = devm_kzalloc(dev, sizeof(struct mtu3), GFP_KERNEL);
829 if (mtu == NULL)
830 return -ENOMEM;
831
832 mtu->irq = platform_get_irq(pdev, 0);
833 if (mtu->irq < 0) {
834 dev_err(dev, "fail to get irq number\n");
835 return mtu->irq;
836 }
837 dev_info(dev, "irq %d\n", mtu->irq);
838
839 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac");
840 mtu->mac_base = devm_ioremap_resource(dev, res);
841 if (IS_ERR(mtu->mac_base)) {
842 dev_err(dev, "error mapping memory for dev mac\n");
843 return PTR_ERR(mtu->mac_base);
844 }
845
846 spin_lock_init(&mtu->lock);
847 mtu->dev = dev;
848 mtu->ippc_base = ssusb->ippc_base;
849 ssusb->mac_base = mtu->mac_base;
850 ssusb->u3d = mtu;
851 mtu->ssusb = ssusb;
852 mtu->max_speed = usb_get_maximum_speed(dev);
853
854 /* check the max_speed parameter */
855 switch (mtu->max_speed) {
856 case USB_SPEED_FULL:
857 case USB_SPEED_HIGH:
858 case USB_SPEED_SUPER:
859 case USB_SPEED_SUPER_PLUS:
860 break;
861 default:
862 dev_err(dev, "invalid max_speed: %s\n",
863 usb_speed_string(mtu->max_speed));
864 /* fall through */
865 case USB_SPEED_UNKNOWN:
866 /* default as SSP */
867 mtu->max_speed = USB_SPEED_SUPER_PLUS;
868 break;
869 }
870
871 dev_dbg(dev, "mac_base=0x%p, ippc_base=0x%p\n",
872 mtu->mac_base, mtu->ippc_base);
873
874 ret = mtu3_hw_init(mtu);
875 if (ret) {
876 dev_err(dev, "mtu3 hw init failed:%d\n", ret);
877 return ret;
878 }
879
880 ret = mtu3_set_dma_mask(mtu);
881 if (ret) {
882 dev_err(dev, "mtu3 set dma_mask failed:%d\n", ret);
883 goto dma_mask_err;
884 }
885
886 ret = devm_request_irq(dev, mtu->irq, mtu3_irq, 0, dev_name(dev), mtu);
887 if (ret) {
888 dev_err(dev, "request irq %d failed!\n", mtu->irq);
889 goto irq_err;
890 }
891
892 device_init_wakeup(dev, true);
893
894 ret = mtu3_gadget_setup(mtu);
895 if (ret) {
896 dev_err(dev, "mtu3 gadget init failed:%d\n", ret);
897 goto gadget_err;
898 }
899
900 /* init as host mode, power down device IP for power saving */
901 if (mtu->ssusb->dr_mode == USB_DR_MODE_OTG)
902 mtu3_stop(mtu);
903
904 dev_dbg(dev, " %s() done...\n", __func__);
905
906 return 0;
907
908 gadget_err:
909 device_init_wakeup(dev, false);
910
911 dma_mask_err:
912 irq_err:
913 mtu3_hw_exit(mtu);
914 ssusb->u3d = NULL;
915 dev_err(dev, " %s() fail...\n", __func__);
916
917 return ret;
918 }
919
ssusb_gadget_exit(struct ssusb_mtk * ssusb)920 void ssusb_gadget_exit(struct ssusb_mtk *ssusb)
921 {
922 struct mtu3 *mtu = ssusb->u3d;
923
924 mtu3_gadget_cleanup(mtu);
925 device_init_wakeup(ssusb->dev, false);
926 mtu3_hw_exit(mtu);
927 }
928