1 /*
2 * Copyright 2016 IBM Corporation
3 *
4 * Joel Stanley <joel@jms.id.au>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/delay.h>
13 #include <linux/io.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of.h>
17 #include <linux/platform_device.h>
18 #include <linux/watchdog.h>
19
20 struct aspeed_wdt {
21 struct watchdog_device wdd;
22 void __iomem *base;
23 u32 ctrl;
24 };
25
26 struct aspeed_wdt_config {
27 u32 ext_pulse_width_mask;
28 };
29
30 static const struct aspeed_wdt_config ast2400_config = {
31 .ext_pulse_width_mask = 0xff,
32 };
33
34 static const struct aspeed_wdt_config ast2500_config = {
35 .ext_pulse_width_mask = 0xfffff,
36 };
37
38 static const struct of_device_id aspeed_wdt_of_table[] = {
39 { .compatible = "aspeed,ast2400-wdt", .data = &ast2400_config },
40 { .compatible = "aspeed,ast2500-wdt", .data = &ast2500_config },
41 { .compatible = "aspeed,ast2600-wdt", .data = &ast2500_config },
42 { },
43 };
44 MODULE_DEVICE_TABLE(of, aspeed_wdt_of_table);
45
46 #define WDT_STATUS 0x00
47 #define WDT_RELOAD_VALUE 0x04
48 #define WDT_RESTART 0x08
49 #define WDT_CTRL 0x0C
50 #define WDT_CTRL_BOOT_SECONDARY BIT(7)
51 #define WDT_CTRL_RESET_MODE_SOC (0x00 << 5)
52 #define WDT_CTRL_RESET_MODE_FULL_CHIP (0x01 << 5)
53 #define WDT_CTRL_RESET_MODE_ARM_CPU (0x10 << 5)
54 #define WDT_CTRL_1MHZ_CLK BIT(4)
55 #define WDT_CTRL_WDT_EXT BIT(3)
56 #define WDT_CTRL_WDT_INTR BIT(2)
57 #define WDT_CTRL_RESET_SYSTEM BIT(1)
58 #define WDT_CTRL_ENABLE BIT(0)
59 #define WDT_TIMEOUT_STATUS 0x10
60 #define WDT_TIMEOUT_STATUS_BOOT_SECONDARY BIT(1)
61
62 /*
63 * WDT_RESET_WIDTH controls the characteristics of the external pulse (if
64 * enabled), specifically:
65 *
66 * * Pulse duration
67 * * Drive mode: push-pull vs open-drain
68 * * Polarity: Active high or active low
69 *
70 * Pulse duration configuration is available on both the AST2400 and AST2500,
71 * though the field changes between SoCs:
72 *
73 * AST2400: Bits 7:0
74 * AST2500: Bits 19:0
75 *
76 * This difference is captured in struct aspeed_wdt_config.
77 *
78 * The AST2500 exposes the drive mode and polarity options, but not in a
79 * regular fashion. For read purposes, bit 31 represents active high or low,
80 * and bit 30 represents push-pull or open-drain. With respect to write, magic
81 * values need to be written to the top byte to change the state of the drive
82 * mode and polarity bits. Any other value written to the top byte has no
83 * effect on the state of the drive mode or polarity bits. However, the pulse
84 * width value must be preserved (as desired) if written.
85 */
86 #define WDT_RESET_WIDTH 0x18
87 #define WDT_RESET_WIDTH_ACTIVE_HIGH BIT(31)
88 #define WDT_ACTIVE_HIGH_MAGIC (0xA5 << 24)
89 #define WDT_ACTIVE_LOW_MAGIC (0x5A << 24)
90 #define WDT_RESET_WIDTH_PUSH_PULL BIT(30)
91 #define WDT_PUSH_PULL_MAGIC (0xA8 << 24)
92 #define WDT_OPEN_DRAIN_MAGIC (0x8A << 24)
93
94 #define WDT_RESTART_MAGIC 0x4755
95
96 /* 32 bits at 1MHz, in milliseconds */
97 #define WDT_MAX_TIMEOUT_MS 4294967
98 #define WDT_DEFAULT_TIMEOUT 30
99 #define WDT_RATE_1MHZ 1000000
100
to_aspeed_wdt(struct watchdog_device * wdd)101 static struct aspeed_wdt *to_aspeed_wdt(struct watchdog_device *wdd)
102 {
103 return container_of(wdd, struct aspeed_wdt, wdd);
104 }
105
aspeed_wdt_enable(struct aspeed_wdt * wdt,int count)106 static void aspeed_wdt_enable(struct aspeed_wdt *wdt, int count)
107 {
108 wdt->ctrl |= WDT_CTRL_ENABLE;
109
110 writel(0, wdt->base + WDT_CTRL);
111 writel(count, wdt->base + WDT_RELOAD_VALUE);
112 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
113 writel(wdt->ctrl, wdt->base + WDT_CTRL);
114 }
115
aspeed_wdt_start(struct watchdog_device * wdd)116 static int aspeed_wdt_start(struct watchdog_device *wdd)
117 {
118 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
119
120 aspeed_wdt_enable(wdt, wdd->timeout * WDT_RATE_1MHZ);
121
122 return 0;
123 }
124
aspeed_wdt_stop(struct watchdog_device * wdd)125 static int aspeed_wdt_stop(struct watchdog_device *wdd)
126 {
127 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
128
129 wdt->ctrl &= ~WDT_CTRL_ENABLE;
130 writel(wdt->ctrl, wdt->base + WDT_CTRL);
131
132 return 0;
133 }
134
aspeed_wdt_ping(struct watchdog_device * wdd)135 static int aspeed_wdt_ping(struct watchdog_device *wdd)
136 {
137 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
138
139 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
140
141 return 0;
142 }
143
aspeed_wdt_set_timeout(struct watchdog_device * wdd,unsigned int timeout)144 static int aspeed_wdt_set_timeout(struct watchdog_device *wdd,
145 unsigned int timeout)
146 {
147 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
148 u32 actual;
149
150 wdd->timeout = timeout;
151
152 actual = min(timeout, wdd->max_hw_heartbeat_ms * 1000);
153
154 writel(actual * WDT_RATE_1MHZ, wdt->base + WDT_RELOAD_VALUE);
155 writel(WDT_RESTART_MAGIC, wdt->base + WDT_RESTART);
156
157 return 0;
158 }
159
aspeed_wdt_restart(struct watchdog_device * wdd,unsigned long action,void * data)160 static int aspeed_wdt_restart(struct watchdog_device *wdd,
161 unsigned long action, void *data)
162 {
163 struct aspeed_wdt *wdt = to_aspeed_wdt(wdd);
164
165 wdt->ctrl &= ~WDT_CTRL_BOOT_SECONDARY;
166 aspeed_wdt_enable(wdt, 128 * WDT_RATE_1MHZ / 1000);
167
168 mdelay(1000);
169
170 return 0;
171 }
172
173 static const struct watchdog_ops aspeed_wdt_ops = {
174 .start = aspeed_wdt_start,
175 .stop = aspeed_wdt_stop,
176 .ping = aspeed_wdt_ping,
177 .set_timeout = aspeed_wdt_set_timeout,
178 .restart = aspeed_wdt_restart,
179 .owner = THIS_MODULE,
180 };
181
182 static const struct watchdog_info aspeed_wdt_info = {
183 .options = WDIOF_KEEPALIVEPING
184 | WDIOF_MAGICCLOSE
185 | WDIOF_SETTIMEOUT,
186 .identity = KBUILD_MODNAME,
187 };
188
aspeed_wdt_probe(struct platform_device * pdev)189 static int aspeed_wdt_probe(struct platform_device *pdev)
190 {
191 const struct aspeed_wdt_config *config;
192 const struct of_device_id *ofdid;
193 struct aspeed_wdt *wdt;
194 struct resource *res;
195 struct device_node *np;
196 const char *reset_type;
197 u32 duration;
198 u32 status;
199 int ret;
200
201 wdt = devm_kzalloc(&pdev->dev, sizeof(*wdt), GFP_KERNEL);
202 if (!wdt)
203 return -ENOMEM;
204
205 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
206 wdt->base = devm_ioremap_resource(&pdev->dev, res);
207 if (IS_ERR(wdt->base))
208 return PTR_ERR(wdt->base);
209
210 wdt->wdd.info = &aspeed_wdt_info;
211 wdt->wdd.ops = &aspeed_wdt_ops;
212 wdt->wdd.max_hw_heartbeat_ms = WDT_MAX_TIMEOUT_MS;
213 wdt->wdd.parent = &pdev->dev;
214
215 wdt->wdd.timeout = WDT_DEFAULT_TIMEOUT;
216 watchdog_init_timeout(&wdt->wdd, 0, &pdev->dev);
217
218 np = pdev->dev.of_node;
219
220 ofdid = of_match_node(aspeed_wdt_of_table, np);
221 if (!ofdid)
222 return -EINVAL;
223 config = ofdid->data;
224
225 /*
226 * On clock rates:
227 * - ast2400 wdt can run at PCLK, or 1MHz
228 * - ast2500 only runs at 1MHz, hard coding bit 4 to 1
229 * - ast2600 always runs at 1MHz
230 *
231 * Set the ast2400 to run at 1MHz as it simplifies the driver.
232 */
233 if (of_device_is_compatible(np, "aspeed,ast2400-wdt"))
234 wdt->ctrl = WDT_CTRL_1MHZ_CLK;
235
236 /*
237 * Control reset on a per-device basis to ensure the
238 * host is not affected by a BMC reboot
239 */
240 ret = of_property_read_string(np, "aspeed,reset-type", &reset_type);
241 if (ret) {
242 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
243 } else {
244 if (!strcmp(reset_type, "cpu"))
245 wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
246 WDT_CTRL_RESET_SYSTEM;
247 else if (!strcmp(reset_type, "soc"))
248 wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
249 WDT_CTRL_RESET_SYSTEM;
250 else if (!strcmp(reset_type, "system"))
251 wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
252 WDT_CTRL_RESET_SYSTEM;
253 else if (strcmp(reset_type, "none"))
254 return -EINVAL;
255 }
256 if (of_property_read_bool(np, "aspeed,external-signal"))
257 wdt->ctrl |= WDT_CTRL_WDT_EXT;
258 if (of_property_read_bool(np, "aspeed,alt-boot"))
259 wdt->ctrl |= WDT_CTRL_BOOT_SECONDARY;
260
261 if (readl(wdt->base + WDT_CTRL) & WDT_CTRL_ENABLE) {
262 /*
263 * The watchdog is running, but invoke aspeed_wdt_start() to
264 * write wdt->ctrl to WDT_CTRL to ensure the watchdog's
265 * configuration conforms to the driver's expectations.
266 * Primarily, ensure we're using the 1MHz clock source.
267 */
268 aspeed_wdt_start(&wdt->wdd);
269 set_bit(WDOG_HW_RUNNING, &wdt->wdd.status);
270 }
271
272 if ((of_device_is_compatible(np, "aspeed,ast2500-wdt")) ||
273 (of_device_is_compatible(np, "aspeed,ast2600-wdt"))) {
274 u32 reg = readl(wdt->base + WDT_RESET_WIDTH);
275
276 reg &= config->ext_pulse_width_mask;
277 if (of_property_read_bool(np, "aspeed,ext-push-pull"))
278 reg |= WDT_PUSH_PULL_MAGIC;
279 else
280 reg |= WDT_OPEN_DRAIN_MAGIC;
281
282 writel(reg, wdt->base + WDT_RESET_WIDTH);
283
284 reg &= config->ext_pulse_width_mask;
285 if (of_property_read_bool(np, "aspeed,ext-active-high"))
286 reg |= WDT_ACTIVE_HIGH_MAGIC;
287 else
288 reg |= WDT_ACTIVE_LOW_MAGIC;
289
290 writel(reg, wdt->base + WDT_RESET_WIDTH);
291 }
292
293 if (!of_property_read_u32(np, "aspeed,ext-pulse-duration", &duration)) {
294 u32 max_duration = config->ext_pulse_width_mask + 1;
295
296 if (duration == 0 || duration > max_duration) {
297 dev_err(&pdev->dev, "Invalid pulse duration: %uus\n",
298 duration);
299 duration = max(1U, min(max_duration, duration));
300 dev_info(&pdev->dev, "Pulse duration set to %uus\n",
301 duration);
302 }
303
304 /*
305 * The watchdog is always configured with a 1MHz source, so
306 * there is no need to scale the microsecond value. However we
307 * need to offset it - from the datasheet:
308 *
309 * "This register decides the asserting duration of wdt_ext and
310 * wdt_rstarm signal. The default value is 0xFF. It means the
311 * default asserting duration of wdt_ext and wdt_rstarm is
312 * 256us."
313 *
314 * This implies a value of 0 gives a 1us pulse.
315 */
316 writel(duration - 1, wdt->base + WDT_RESET_WIDTH);
317 }
318
319 status = readl(wdt->base + WDT_TIMEOUT_STATUS);
320 if (status & WDT_TIMEOUT_STATUS_BOOT_SECONDARY)
321 wdt->wdd.bootstatus = WDIOF_CARDRESET;
322
323 ret = devm_watchdog_register_device(&pdev->dev, &wdt->wdd);
324 if (ret) {
325 dev_err(&pdev->dev, "failed to register\n");
326 return ret;
327 }
328
329 return 0;
330 }
331
332 static struct platform_driver aspeed_watchdog_driver = {
333 .probe = aspeed_wdt_probe,
334 .driver = {
335 .name = KBUILD_MODNAME,
336 .of_match_table = of_match_ptr(aspeed_wdt_of_table),
337 },
338 };
339
aspeed_wdt_init(void)340 static int __init aspeed_wdt_init(void)
341 {
342 return platform_driver_register(&aspeed_watchdog_driver);
343 }
344 arch_initcall(aspeed_wdt_init);
345
aspeed_wdt_exit(void)346 static void __exit aspeed_wdt_exit(void)
347 {
348 platform_driver_unregister(&aspeed_watchdog_driver);
349 }
350 module_exit(aspeed_wdt_exit);
351
352 MODULE_DESCRIPTION("Aspeed Watchdog Driver");
353 MODULE_LICENSE("GPL");
354