1/* 2 * Copyright (C) 2016 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* 10 * AM335x ICE V2 board 11 * http://www.ti.com/tool/tmdsice3359 12 */ 13 14/dts-v1/; 15 16#include "am33xx.dtsi" 17 18/ { 19 model = "TI AM3359 ICE-V2"; 20 compatible = "ti,am3359-icev2", "ti,am33xx"; 21 22 memory@80000000 { 23 device_type = "memory"; 24 reg = <0x80000000 0x10000000>; /* 256 MB */ 25 }; 26 27 chosen { 28 stdout-path = &uart3; 29 }; 30 31 vbat: fixedregulator0 { 32 compatible = "regulator-fixed"; 33 regulator-name = "vbat"; 34 regulator-min-microvolt = <5000000>; 35 regulator-max-microvolt = <5000000>; 36 regulator-boot-on; 37 }; 38 39 vtt_fixed: fixedregulator1 { 40 compatible = "regulator-fixed"; 41 regulator-name = "vtt"; 42 regulator-min-microvolt = <1500000>; 43 regulator-max-microvolt = <1500000>; 44 gpio = <&gpio0 18 GPIO_ACTIVE_HIGH>; 45 regulator-always-on; 46 regulator-boot-on; 47 enable-active-high; 48 }; 49 50 leds-iio { 51 status = "disabled"; 52 compatible = "gpio-leds"; 53 led-out0 { 54 label = "out0"; 55 gpios = <&tpic2810 0 GPIO_ACTIVE_HIGH>; 56 default-state = "off"; 57 }; 58 59 led-out1 { 60 label = "out1"; 61 gpios = <&tpic2810 1 GPIO_ACTIVE_HIGH>; 62 default-state = "off"; 63 }; 64 65 led-out2 { 66 label = "out2"; 67 gpios = <&tpic2810 2 GPIO_ACTIVE_HIGH>; 68 default-state = "off"; 69 }; 70 71 led-out3 { 72 label = "out3"; 73 gpios = <&tpic2810 3 GPIO_ACTIVE_HIGH>; 74 default-state = "off"; 75 }; 76 77 led-out4 { 78 label = "out4"; 79 gpios = <&tpic2810 4 GPIO_ACTIVE_HIGH>; 80 default-state = "off"; 81 }; 82 83 led-out5 { 84 label = "out5"; 85 gpios = <&tpic2810 5 GPIO_ACTIVE_HIGH>; 86 default-state = "off"; 87 }; 88 89 led-out6 { 90 label = "out6"; 91 gpios = <&tpic2810 6 GPIO_ACTIVE_HIGH>; 92 default-state = "off"; 93 }; 94 95 led-out7 { 96 label = "out7"; 97 gpios = <&tpic2810 7 GPIO_ACTIVE_HIGH>; 98 default-state = "off"; 99 }; 100 }; 101 102 /* Tricolor status LEDs */ 103 leds1 { 104 compatible = "gpio-leds"; 105 pinctrl-names = "default"; 106 pinctrl-0 = <&user_leds>; 107 108 led0 { 109 label = "status0:red:cpu0"; 110 gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; 111 default-state = "off"; 112 linux,default-trigger = "cpu0"; 113 }; 114 115 led1 { 116 label = "status0:green:usr"; 117 gpios = <&gpio0 16 GPIO_ACTIVE_HIGH>; 118 default-state = "off"; 119 }; 120 121 led2 { 122 label = "status0:yellow:usr"; 123 gpios = <&gpio3 9 GPIO_ACTIVE_HIGH>; 124 default-state = "off"; 125 }; 126 127 led3 { 128 label = "status1:red:mmc0"; 129 gpios = <&gpio1 30 GPIO_ACTIVE_HIGH>; 130 default-state = "off"; 131 linux,default-trigger = "mmc0"; 132 }; 133 134 led4 { 135 label = "status1:green:usr"; 136 gpios = <&gpio0 20 GPIO_ACTIVE_HIGH>; 137 default-state = "off"; 138 }; 139 140 led5 { 141 label = "status1:yellow:usr"; 142 gpios = <&gpio0 19 GPIO_ACTIVE_HIGH>; 143 default-state = "off"; 144 }; 145 }; 146 gpio-decoder { 147 compatible = "gpio-decoder"; 148 gpios = <&pca9536 3 GPIO_ACTIVE_HIGH>, 149 <&pca9536 2 GPIO_ACTIVE_HIGH>, 150 <&pca9536 1 GPIO_ACTIVE_HIGH>, 151 <&pca9536 0 GPIO_ACTIVE_HIGH>; 152 linux,axis = <0>; /* ABS_X */ 153 decoder-max-value = <9>; 154 }; 155}; 156 157&am33xx_pinmux { 158 user_leds: user_leds { 159 pinctrl-single,pins = < 160 AM33XX_IOPAD(0x91c, PIN_OUTPUT | MUX_MODE7) /* (J18) gmii1_txd3.gpio0[16] */ 161 AM33XX_IOPAD(0x920, PIN_OUTPUT | MUX_MODE7) /* (K15) gmii1_txd2.gpio0[17] */ 162 AM33XX_IOPAD(0x9b0, PIN_OUTPUT | MUX_MODE7) /* (A15) xdma_event_intr0.gpio0[19] */ 163 AM33XX_IOPAD(0x9b4, PIN_OUTPUT | MUX_MODE7) /* (D14) xdma_event_intr1.gpio0[20] */ 164 AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* (U9) gpmc_csn1.gpio1[30] */ 165 AM33XX_IOPAD(0x92c, PIN_OUTPUT | MUX_MODE7) /* (K18) gmii1_txclk.gpio3[9] */ 166 >; 167 }; 168 169 mmc0_pins_default: mmc0_pins_default { 170 pinctrl-single,pins = < 171 AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ 172 AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ 173 AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ 174 AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ 175 AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ 176 AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ 177 >; 178 }; 179 180 i2c0_pins_default: i2c0_pins_default { 181 pinctrl-single,pins = < 182 AM33XX_IOPAD(0x988, PIN_INPUT | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ 183 AM33XX_IOPAD(0x98c, PIN_INPUT | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ 184 >; 185 }; 186 187 spi0_pins_default: spi0_pins_default { 188 pinctrl-single,pins = < 189 AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ 190 AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ 191 AM33XX_IOPAD(0x958, PIN_INPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ 192 AM33XX_IOPAD(0x95c, PIN_INPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ 193 AM33XX_IOPAD(0x960, PIN_INPUT_PULLUP | MUX_MODE0) /* (C15) spi0_cs1.spi0_cs1 */ 194 AM33XX_IOPAD(0x9a0, PIN_INPUT_PULLUP | MUX_MODE7) /* (B12) mcasp0_aclkr.gpio3[18] */ 195 >; 196 }; 197 198 uart3_pins_default: uart3_pins_default { 199 pinctrl-single,pins = < 200 AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ 201 AM33XX_IOPAD(0x938, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (L16) gmii1_rxd2.uart3_txd */ 202 >; 203 }; 204 205 cpsw_default: cpsw_default { 206 pinctrl-single,pins = < 207 /* Slave 1, RMII mode */ 208 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_crs.rmii1_crs_dv */ 209 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLUP | MUX_MODE0)) /* rmii1_refclk.rmii1_refclk */ 210 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd0.rmii1_rxd0 */ 211 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxd1.rmii1_rxd1 */ 212 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_rxerr.rmii1_rxerr */ 213 AM33XX_IOPAD(0x928, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd0.rmii1_txd0 */ 214 AM33XX_IOPAD(0x924, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txd1.rmii1_txd1 */ 215 AM33XX_IOPAD(0x914, (PIN_OUTPUT_PULLDOWN | MUX_MODE1)) /* mii1_txen.rmii1_txen */ 216 /* Slave 2, RMII mode */ 217 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wait0.rmii2_crs_dv */ 218 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLUP | MUX_MODE1)) /* mii1_col.rmii2_refclk */ 219 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a11.rmii2_rxd0 */ 220 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_a10.rmii2_rxd1 */ 221 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLUP | MUX_MODE3)) /* gpmc_wpn.rmii2_rxerr */ 222 AM33XX_IOPAD(0x854, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a5.rmii2_txd0 */ 223 AM33XX_IOPAD(0x850, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a4.rmii2_txd1 */ 224 AM33XX_IOPAD(0x840, (PIN_OUTPUT_PULLDOWN | MUX_MODE3)) /* gpmc_a0.rmii2_txen */ 225 >; 226 }; 227 228 cpsw_sleep: cpsw_sleep { 229 pinctrl-single,pins = < 230 /* Slave 1 reset value */ 231 AM33XX_IOPAD(0x90c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 232 AM33XX_IOPAD(0x944, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 233 AM33XX_IOPAD(0x940, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 234 AM33XX_IOPAD(0x93c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 235 AM33XX_IOPAD(0x910, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 236 AM33XX_IOPAD(0x928, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 237 AM33XX_IOPAD(0x924, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 238 AM33XX_IOPAD(0x914, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 239 240 /* Slave 2 reset value */ 241 AM33XX_IOPAD(0x870, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 242 AM33XX_IOPAD(0x908, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 243 AM33XX_IOPAD(0x86c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 244 AM33XX_IOPAD(0x868, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 245 AM33XX_IOPAD(0x874, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 246 AM33XX_IOPAD(0x854, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 247 AM33XX_IOPAD(0x850, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 248 AM33XX_IOPAD(0x840, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 249 >; 250 }; 251 252 davinci_mdio_default: davinci_mdio_default { 253 pinctrl-single,pins = < 254 /* MDIO */ 255 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0)) /* mdio_data.mdio_data */ 256 AM33XX_IOPAD(0x94c, (PIN_OUTPUT_PULLUP | MUX_MODE0)) /* mdio_clk.mdio_clk */ 257 >; 258 }; 259 260 davinci_mdio_sleep: davinci_mdio_sleep { 261 pinctrl-single,pins = < 262 /* MDIO reset value */ 263 AM33XX_IOPAD(0x948, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 264 AM33XX_IOPAD(0x94c, (PIN_INPUT_PULLDOWN | MUX_MODE7)) 265 >; 266 }; 267}; 268 269&i2c0 { 270 pinctrl-names = "default"; 271 pinctrl-0 = <&i2c0_pins_default>; 272 273 status = "okay"; 274 clock-frequency = <400000>; 275 276 tps: power-controller@2d { 277 reg = <0x2d>; 278 }; 279 280 tpic2810: gpio@60 { 281 compatible = "ti,tpic2810"; 282 reg = <0x60>; 283 gpio-controller; 284 #gpio-cells = <2>; 285 }; 286 287 pca9536: gpio@41 { 288 compatible = "ti,pca9536"; 289 reg = <0x41>; 290 gpio-controller; 291 #gpio-cells = <2>; 292 }; 293}; 294 295&spi0 { 296 status = "okay"; 297 pinctrl-names = "default"; 298 pinctrl-0 = <&spi0_pins_default>; 299 300 sn65hvs882@1 { 301 compatible = "pisosr-gpio"; 302 gpio-controller; 303 #gpio-cells = <2>; 304 305 load-gpios = <&gpio3 18 GPIO_ACTIVE_LOW>; 306 307 reg = <1>; 308 spi-max-frequency = <1000000>; 309 spi-cpol; 310 }; 311 312 spi_nor: flash@0 { 313 #address-cells = <1>; 314 #size-cells = <1>; 315 compatible = "winbond,w25q64", "jedec,spi-nor"; 316 spi-max-frequency = <80000000>; 317 m25p,fast-read; 318 reg = <0>; 319 320 partition@0 { 321 label = "u-boot-spl"; 322 reg = <0x0 0x80000>; 323 read-only; 324 }; 325 326 partition@1 { 327 label = "u-boot"; 328 reg = <0x80000 0x100000>; 329 read-only; 330 }; 331 332 partition@2 { 333 label = "u-boot-env"; 334 reg = <0x180000 0x20000>; 335 read-only; 336 }; 337 338 partition@3 { 339 label = "misc"; 340 reg = <0x1A0000 0x660000>; 341 }; 342 }; 343 344}; 345 346&tscadc { 347 status = "okay"; 348 adc { 349 ti,adc-channels = <1 2 3 4 5 6 7>; 350 }; 351}; 352 353#include "tps65910.dtsi" 354 355&tps { 356 vcc1-supply = <&vbat>; 357 vcc2-supply = <&vbat>; 358 vcc3-supply = <&vbat>; 359 vcc4-supply = <&vbat>; 360 vcc5-supply = <&vbat>; 361 vcc6-supply = <&vbat>; 362 vcc7-supply = <&vbat>; 363 vccio-supply = <&vbat>; 364 365 regulators { 366 vrtc_reg: regulator@0 { 367 regulator-always-on; 368 }; 369 370 vio_reg: regulator@1 { 371 regulator-always-on; 372 }; 373 374 vdd1_reg: regulator@2 { 375 regulator-name = "vdd_mpu"; 376 regulator-min-microvolt = <912500>; 377 regulator-max-microvolt = <1326000>; 378 regulator-boot-on; 379 regulator-always-on; 380 }; 381 382 vdd2_reg: regulator@3 { 383 regulator-name = "vdd_core"; 384 regulator-min-microvolt = <912500>; 385 regulator-max-microvolt = <1144000>; 386 regulator-boot-on; 387 regulator-always-on; 388 }; 389 390 vdd3_reg: regulator@4 { 391 regulator-always-on; 392 }; 393 394 vdig1_reg: regulator@5 { 395 regulator-always-on; 396 }; 397 398 vdig2_reg: regulator@6 { 399 regulator-always-on; 400 }; 401 402 vpll_reg: regulator@7 { 403 regulator-always-on; 404 }; 405 406 vdac_reg: regulator@8 { 407 regulator-always-on; 408 }; 409 410 vaux1_reg: regulator@9 { 411 regulator-always-on; 412 }; 413 414 vaux2_reg: regulator@10 { 415 regulator-always-on; 416 }; 417 418 vaux33_reg: regulator@11 { 419 regulator-always-on; 420 }; 421 422 vmmc_reg: regulator@12 { 423 regulator-min-microvolt = <1800000>; 424 regulator-max-microvolt = <3300000>; 425 regulator-always-on; 426 }; 427 }; 428}; 429 430&mmc1 { 431 status = "okay"; 432 vmmc-supply = <&vmmc_reg>; 433 bus-width = <4>; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&mmc0_pins_default>; 436}; 437 438&gpio0 { 439 /* Do not idle the GPIO used for holding the VTT regulator */ 440 ti,no-reset-on-init; 441 ti,no-idle-on-init; 442}; 443 444&uart3 { 445 pinctrl-names = "default"; 446 pinctrl-0 = <&uart3_pins_default>; 447 status = "okay"; 448}; 449 450&gpio3 { 451 p4 { 452 gpio-hog; 453 gpios = <4 GPIO_ACTIVE_HIGH>; 454 output-high; 455 line-name = "PR1_MII_CTRL"; 456 }; 457 458 p10 { 459 gpio-hog; 460 gpios = <10 GPIO_ACTIVE_HIGH>; 461 /* ETH1 mux: Low for MII-PRU, high for RMII-CPSW */ 462 output-high; 463 line-name = "MUX_MII_CTL1"; 464 }; 465}; 466 467&cpsw_emac0 { 468 phy-handle = <ðphy0>; 469 phy-mode = "rmii"; 470 dual_emac_res_vlan = <1>; 471}; 472 473&cpsw_emac1 { 474 phy-handle = <ðphy1>; 475 phy-mode = "rmii"; 476 dual_emac_res_vlan = <2>; 477}; 478 479&mac { 480 pinctrl-names = "default", "sleep"; 481 pinctrl-0 = <&cpsw_default>; 482 pinctrl-1 = <&cpsw_sleep>; 483 status = "okay"; 484 dual_emac; 485}; 486 487&phy_sel { 488 rmii-clock-ext; 489}; 490 491&davinci_mdio { 492 pinctrl-names = "default", "sleep"; 493 pinctrl-0 = <&davinci_mdio_default>; 494 pinctrl-1 = <&davinci_mdio_sleep>; 495 status = "okay"; 496 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; 497 reset-delay-us = <2>; /* PHY datasheet states 1uS min */ 498 499 ethphy0: ethernet-phy@1 { 500 reg = <1>; 501 }; 502 503 ethphy1: ethernet-phy@3 { 504 reg = <3>; 505 }; 506}; 507