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1/*
2 * Copyright (c) 2017 MediaTek Inc.
3 * Author: Ming Huang <ming.huang@mediatek.com>
4 *	   Sean Wang <sean.wang@mediatek.com>
5 *
6 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
7 */
8
9/dts-v1/;
10#include <dt-bindings/input/input.h>
11#include <dt-bindings/gpio/gpio.h>
12
13#include "mt7622.dtsi"
14#include "mt6380.dtsi"
15
16/ {
17	model = "MediaTek MT7622 RFB1 board";
18	compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
19
20	aliases {
21		serial0 = &uart0;
22	};
23
24	chosen {
25		stdout-path = "serial0:115200n8";
26		bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
27	};
28
29	cpus {
30		cpu@0 {
31			proc-supply = <&mt6380_vcpu_reg>;
32			sram-supply = <&mt6380_vm_reg>;
33		};
34
35		cpu@1 {
36			proc-supply = <&mt6380_vcpu_reg>;
37			sram-supply = <&mt6380_vm_reg>;
38		};
39	};
40
41	gpio-keys {
42		compatible = "gpio-keys";
43		poll-interval = <100>;
44
45		factory {
46			label = "factory";
47			linux,code = <BTN_0>;
48			gpios = <&pio 0 0>;
49		};
50
51		wps {
52			label = "wps";
53			linux,code = <KEY_WPS_BUTTON>;
54			gpios = <&pio 102 0>;
55		};
56	};
57
58	memory {
59		reg = <0 0x40000000 0 0x3F000000>;
60	};
61
62	reg_1p8v: regulator-1p8v {
63		compatible = "regulator-fixed";
64		regulator-name = "fixed-1.8V";
65		regulator-min-microvolt = <1800000>;
66		regulator-max-microvolt = <1800000>;
67		regulator-always-on;
68	};
69
70	reg_3p3v: regulator-3p3v {
71		compatible = "regulator-fixed";
72		regulator-name = "fixed-3.3V";
73		regulator-min-microvolt = <3300000>;
74		regulator-max-microvolt = <3300000>;
75		regulator-boot-on;
76		regulator-always-on;
77	};
78
79	reg_5v: regulator-5v {
80		compatible = "regulator-fixed";
81		regulator-name = "fixed-5V";
82		regulator-min-microvolt = <5000000>;
83		regulator-max-microvolt = <5000000>;
84		regulator-boot-on;
85		regulator-always-on;
86	};
87};
88
89&pcie {
90	pinctrl-names = "default";
91	pinctrl-0 = <&pcie0_pins>;
92	status = "okay";
93
94	pcie@0,0 {
95		status = "okay";
96	};
97};
98
99&pio {
100	/* eMMC is shared pin with parallel NAND */
101	emmc_pins_default: emmc-pins-default {
102		mux {
103			function = "emmc", "emmc_rst";
104			groups = "emmc";
105		};
106
107		/* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
108		 * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
109		 * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
110		 */
111		conf-cmd-dat {
112			pins = "NDL0", "NDL1", "NDL2",
113			       "NDL3", "NDL4", "NDL5",
114			       "NDL6", "NDL7", "NRB";
115			input-enable;
116			bias-pull-up;
117		};
118
119		conf-clk {
120			pins = "NCLE";
121			bias-pull-down;
122		};
123	};
124
125	emmc_pins_uhs: emmc-pins-uhs {
126		mux {
127			function = "emmc";
128			groups = "emmc";
129		};
130
131		conf-cmd-dat {
132			pins = "NDL0", "NDL1", "NDL2",
133			       "NDL3", "NDL4", "NDL5",
134			       "NDL6", "NDL7", "NRB";
135			input-enable;
136			drive-strength = <4>;
137			bias-pull-up;
138		};
139
140		conf-clk {
141			pins = "NCLE";
142			drive-strength = <4>;
143			bias-pull-down;
144		};
145	};
146
147	eth_pins: eth-pins {
148		mux {
149			function = "eth";
150			groups = "mdc_mdio", "rgmii_via_gmac2";
151		};
152	};
153
154	i2c1_pins: i2c1-pins {
155		mux {
156			function = "i2c";
157			groups =  "i2c1_0";
158		};
159	};
160
161	i2c2_pins: i2c2-pins {
162		mux {
163			function = "i2c";
164			groups =  "i2c2_0";
165		};
166	};
167
168	i2s1_pins: i2s1-pins {
169		mux {
170			function = "i2s";
171			groups =  "i2s_out_mclk_bclk_ws",
172				  "i2s1_in_data",
173				  "i2s1_out_data";
174		};
175
176		conf {
177			pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
178			       "I2S_WS", "I2S_MCLK";
179			drive-strength = <12>;
180			bias-pull-down;
181		};
182	};
183
184	irrx_pins: irrx-pins {
185		mux {
186			function = "ir";
187			groups =  "ir_1_rx";
188		};
189	};
190
191	irtx_pins: irtx-pins {
192		mux {
193			function = "ir";
194			groups =  "ir_1_tx";
195		};
196	};
197
198	/* Parallel nand is shared pin with eMMC */
199	parallel_nand_pins: parallel-nand-pins {
200		mux {
201			function = "flash";
202			groups = "par_nand";
203		};
204	};
205
206	pcie0_pins: pcie0-pins {
207		mux {
208			function = "pcie";
209			groups = "pcie0_pad_perst",
210				 "pcie0_1_waken",
211				 "pcie0_1_clkreq";
212		};
213	};
214
215	pcie1_pins: pcie1-pins {
216		mux {
217			function = "pcie";
218			groups = "pcie1_pad_perst",
219				 "pcie1_0_waken",
220				 "pcie1_0_clkreq";
221		};
222	};
223
224	pmic_bus_pins: pmic-bus-pins {
225		mux {
226			function = "pmic";
227			groups = "pmic_bus";
228		};
229	};
230
231	pwm7_pins: pwm1-2-pins {
232		mux {
233			function = "pwm";
234			groups = "pwm_ch7_2";
235		};
236	};
237
238	wled_pins: wled-pins {
239		mux {
240			function = "led";
241			groups = "wled";
242		};
243	};
244
245	sd0_pins_default: sd0-pins-default {
246		mux {
247			function = "sd";
248			groups = "sd_0";
249		};
250
251		/* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
252		 *  "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
253		 *  DAT2, DAT3, CMD, CLK for SD respectively.
254		 */
255		conf-cmd-data {
256			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
257			       "I2S2_IN","I2S4_OUT";
258			input-enable;
259			drive-strength = <8>;
260			bias-pull-up;
261		};
262		conf-clk {
263			pins = "I2S3_OUT";
264			drive-strength = <12>;
265			bias-pull-down;
266		};
267		conf-cd {
268			pins = "TXD3";
269			bias-pull-up;
270		};
271	};
272
273	sd0_pins_uhs: sd0-pins-uhs {
274		mux {
275			function = "sd";
276			groups = "sd_0";
277		};
278
279		conf-cmd-data {
280			pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
281			       "I2S2_IN","I2S4_OUT";
282			input-enable;
283			bias-pull-up;
284		};
285
286		conf-clk {
287			pins = "I2S3_OUT";
288			bias-pull-down;
289		};
290	};
291
292	/* Serial NAND is shared pin with SPI-NOR */
293	serial_nand_pins: serial-nand-pins {
294		mux {
295			function = "flash";
296			groups = "snfi";
297		};
298	};
299
300	spic0_pins: spic0-pins {
301		mux {
302			function = "spi";
303			groups = "spic0_0";
304		};
305	};
306
307	spic1_pins: spic1-pins {
308		mux {
309			function = "spi";
310			groups = "spic1_0";
311		};
312	};
313
314	/* SPI-NOR is shared pin with serial NAND */
315	spi_nor_pins: spi-nor-pins {
316		mux {
317			function = "flash";
318			groups = "spi_nor";
319		};
320	};
321
322	/* serial NAND is shared pin with SPI-NOR */
323	serial_nand_pins: serial-nand-pins {
324		mux {
325			function = "flash";
326			groups = "snfi";
327		};
328	};
329
330	uart0_pins: uart0-pins {
331		mux {
332			function = "uart";
333			groups = "uart0_0_tx_rx" ;
334		};
335	};
336
337	uart2_pins: uart2-pins {
338		mux {
339			function = "uart";
340			groups = "uart2_1_tx_rx" ;
341		};
342	};
343
344	watchdog_pins: watchdog-pins {
345		mux {
346			function = "watchdog";
347			groups = "watchdog";
348		};
349	};
350};
351
352&bch {
353	status = "disabled";
354};
355
356&btif {
357	status = "okay";
358};
359
360&cir {
361	pinctrl-names = "default";
362	pinctrl-0 = <&irrx_pins>;
363	status = "okay";
364};
365
366&eth {
367	pinctrl-names = "default";
368	pinctrl-0 = <&eth_pins>;
369	status = "okay";
370
371	gmac1: mac@1 {
372		compatible = "mediatek,eth-mac";
373		reg = <1>;
374		phy-handle = <&phy5>;
375	};
376
377	mdio-bus {
378		#address-cells = <1>;
379		#size-cells = <0>;
380
381		phy5: ethernet-phy@5 {
382			reg = <5>;
383			phy-mode = "sgmii";
384		};
385	};
386};
387
388&i2c1 {
389	pinctrl-names = "default";
390	pinctrl-0 = <&i2c1_pins>;
391	status = "okay";
392};
393
394&i2c2 {
395	pinctrl-names = "default";
396	pinctrl-0 = <&i2c2_pins>;
397	status = "okay";
398};
399
400&mmc0 {
401	pinctrl-names = "default", "state_uhs";
402	pinctrl-0 = <&emmc_pins_default>;
403	pinctrl-1 = <&emmc_pins_uhs>;
404	status = "okay";
405	bus-width = <8>;
406	max-frequency = <50000000>;
407	cap-mmc-highspeed;
408	mmc-hs200-1_8v;
409	vmmc-supply = <&reg_3p3v>;
410	vqmmc-supply = <&reg_1p8v>;
411	assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
412	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
413	non-removable;
414};
415
416&mmc1 {
417	pinctrl-names = "default", "state_uhs";
418	pinctrl-0 = <&sd0_pins_default>;
419	pinctrl-1 = <&sd0_pins_uhs>;
420	status = "okay";
421	bus-width = <4>;
422	max-frequency = <50000000>;
423	cap-sd-highspeed;
424	r_smpl = <1>;
425	cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
426	vmmc-supply = <&reg_3p3v>;
427	vqmmc-supply = <&reg_3p3v>;
428	assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
429	assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
430};
431
432&nandc {
433	pinctrl-names = "default";
434	pinctrl-0 = <&parallel_nand_pins>;
435	status = "disabled";
436};
437
438&nor_flash {
439	pinctrl-names = "default";
440	pinctrl-0 = <&spi_nor_pins>;
441	status = "disabled";
442
443	flash@0 {
444		compatible = "jedec,spi-nor";
445		reg = <0>;
446	};
447};
448
449&pwm {
450	pinctrl-names = "default";
451	pinctrl-0 = <&pwm7_pins>;
452	status = "okay";
453};
454
455&pwrap {
456	pinctrl-names = "default";
457	pinctrl-0 = <&pmic_bus_pins>;
458
459	status = "okay";
460};
461
462&sata {
463	status = "okay";
464};
465
466&sata_phy {
467	status = "okay";
468};
469
470&spi0 {
471	pinctrl-names = "default";
472	pinctrl-0 = <&spic0_pins>;
473	status = "okay";
474};
475
476&spi1 {
477	pinctrl-names = "default";
478	pinctrl-0 = <&spic1_pins>;
479	status = "okay";
480};
481
482&ssusb {
483	vusb33-supply = <&reg_3p3v>;
484	vbus-supply = <&reg_5v>;
485	status = "okay";
486};
487
488&u3phy {
489	status = "okay";
490};
491
492&uart0 {
493	pinctrl-names = "default";
494	pinctrl-0 = <&uart0_pins>;
495	status = "okay";
496};
497
498&uart2 {
499	pinctrl-names = "default";
500	pinctrl-0 = <&uart2_pins>;
501	status = "okay";
502};
503
504&watchdog {
505	pinctrl-names = "default";
506	pinctrl-0 = <&watchdog_pins>;
507	status = "okay";
508};
509