1 /*
2 * PCM3168A codec driver
3 *
4 * Copyright (C) 2015 Imagination Technologies Ltd.
5 *
6 * Author: Damien Horsley <Damien.Horsley@imgtec.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms and conditions of the GNU General Public License,
10 * version 2, as published by the Free Software Foundation.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/module.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/regulator/consumer.h>
18
19 #include <sound/pcm_params.h>
20 #include <sound/soc.h>
21 #include <sound/tlv.h>
22
23 #include "pcm3168a.h"
24
25 #define PCM3168A_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
26 SNDRV_PCM_FMTBIT_S24_3LE | \
27 SNDRV_PCM_FMTBIT_S24_LE)
28
29 #define PCM3168A_FMT_I2S 0x0
30 #define PCM3168A_FMT_LEFT_J 0x1
31 #define PCM3168A_FMT_RIGHT_J 0x2
32 #define PCM3168A_FMT_RIGHT_J_16 0x3
33 #define PCM3168A_FMT_DSP_A 0x4
34 #define PCM3168A_FMT_DSP_B 0x5
35 #define PCM3168A_FMT_DSP_MASK 0x4
36
37 #define PCM3168A_NUM_SUPPLIES 6
38 static const char *const pcm3168a_supply_names[PCM3168A_NUM_SUPPLIES] = {
39 "VDD1",
40 "VDD2",
41 "VCCAD1",
42 "VCCAD2",
43 "VCCDA1",
44 "VCCDA2"
45 };
46
47 struct pcm3168a_priv {
48 struct regulator_bulk_data supplies[PCM3168A_NUM_SUPPLIES];
49 struct regmap *regmap;
50 struct clk *scki;
51 bool adc_master_mode;
52 bool dac_master_mode;
53 unsigned long sysclk;
54 unsigned int adc_fmt;
55 unsigned int dac_fmt;
56 };
57
58 static const char *const pcm3168a_roll_off[] = { "Sharp", "Slow" };
59
60 static SOC_ENUM_SINGLE_DECL(pcm3168a_d1_roll_off, PCM3168A_DAC_OP_FLT,
61 PCM3168A_DAC_FLT_SHIFT, pcm3168a_roll_off);
62 static SOC_ENUM_SINGLE_DECL(pcm3168a_d2_roll_off, PCM3168A_DAC_OP_FLT,
63 PCM3168A_DAC_FLT_SHIFT + 1, pcm3168a_roll_off);
64 static SOC_ENUM_SINGLE_DECL(pcm3168a_d3_roll_off, PCM3168A_DAC_OP_FLT,
65 PCM3168A_DAC_FLT_SHIFT + 2, pcm3168a_roll_off);
66 static SOC_ENUM_SINGLE_DECL(pcm3168a_d4_roll_off, PCM3168A_DAC_OP_FLT,
67 PCM3168A_DAC_FLT_SHIFT + 3, pcm3168a_roll_off);
68
69 static const char *const pcm3168a_volume_type[] = {
70 "Individual", "Master + Individual" };
71
72 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_volume_type, PCM3168A_DAC_ATT_DEMP_ZF,
73 PCM3168A_DAC_ATMDDA_SHIFT, pcm3168a_volume_type);
74
75 static const char *const pcm3168a_att_speed_mult[] = { "2048", "4096" };
76
77 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_att_mult, PCM3168A_DAC_ATT_DEMP_ZF,
78 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_att_speed_mult);
79
80 static const char *const pcm3168a_demp[] = {
81 "Disabled", "48khz", "44.1khz", "32khz" };
82
83 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_demp, PCM3168A_DAC_ATT_DEMP_ZF,
84 PCM3168A_DAC_DEMP_SHIFT, pcm3168a_demp);
85
86 static const char *const pcm3168a_zf_func[] = {
87 "DAC 1/2/3/4 AND", "DAC 1/2/3/4 OR", "DAC 1/2/3 AND",
88 "DAC 1/2/3 OR", "DAC 4 AND", "DAC 4 OR" };
89
90 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_func, PCM3168A_DAC_ATT_DEMP_ZF,
91 PCM3168A_DAC_AZRO_SHIFT, pcm3168a_zf_func);
92
93 static const char *const pcm3168a_pol[] = { "Active High", "Active Low" };
94
95 static SOC_ENUM_SINGLE_DECL(pcm3168a_dac_zf_pol, PCM3168A_DAC_ATT_DEMP_ZF,
96 PCM3168A_DAC_ATSPDA_SHIFT, pcm3168a_pol);
97
98 static const char *const pcm3168a_con[] = { "Differential", "Single-Ended" };
99
100 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc1_con, PCM3168A_ADC_SEAD,
101 0, 1, pcm3168a_con);
102 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc2_con, PCM3168A_ADC_SEAD,
103 2, 3, pcm3168a_con);
104 static SOC_ENUM_DOUBLE_DECL(pcm3168a_adc3_con, PCM3168A_ADC_SEAD,
105 4, 5, pcm3168a_con);
106
107 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_volume_type, PCM3168A_ADC_ATT_OVF,
108 PCM3168A_ADC_ATMDAD_SHIFT, pcm3168a_volume_type);
109
110 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_att_mult, PCM3168A_ADC_ATT_OVF,
111 PCM3168A_ADC_ATSPAD_SHIFT, pcm3168a_att_speed_mult);
112
113 static SOC_ENUM_SINGLE_DECL(pcm3168a_adc_ov_pol, PCM3168A_ADC_ATT_OVF,
114 PCM3168A_ADC_OVFP_SHIFT, pcm3168a_pol);
115
116 /* -100db to 0db, register values 0-54 cause mute */
117 static const DECLARE_TLV_DB_SCALE(pcm3168a_dac_tlv, -10050, 50, 1);
118
119 /* -100db to 20db, register values 0-14 cause mute */
120 static const DECLARE_TLV_DB_SCALE(pcm3168a_adc_tlv, -10050, 50, 1);
121
122 static const struct snd_kcontrol_new pcm3168a_snd_controls[] = {
123 SOC_SINGLE("DAC Power-Save Switch", PCM3168A_DAC_PWR_MST_FMT,
124 PCM3168A_DAC_PSMDA_SHIFT, 1, 1),
125 SOC_ENUM("DAC1 Digital Filter roll-off", pcm3168a_d1_roll_off),
126 SOC_ENUM("DAC2 Digital Filter roll-off", pcm3168a_d2_roll_off),
127 SOC_ENUM("DAC3 Digital Filter roll-off", pcm3168a_d3_roll_off),
128 SOC_ENUM("DAC4 Digital Filter roll-off", pcm3168a_d4_roll_off),
129 SOC_DOUBLE("DAC1 Invert Switch", PCM3168A_DAC_INV, 0, 1, 1, 0),
130 SOC_DOUBLE("DAC2 Invert Switch", PCM3168A_DAC_INV, 2, 3, 1, 0),
131 SOC_DOUBLE("DAC3 Invert Switch", PCM3168A_DAC_INV, 4, 5, 1, 0),
132 SOC_DOUBLE("DAC4 Invert Switch", PCM3168A_DAC_INV, 6, 7, 1, 0),
133 SOC_DOUBLE_STS("DAC1 Zero Flag", PCM3168A_DAC_ZERO, 0, 1, 1, 0),
134 SOC_DOUBLE_STS("DAC2 Zero Flag", PCM3168A_DAC_ZERO, 2, 3, 1, 0),
135 SOC_DOUBLE_STS("DAC3 Zero Flag", PCM3168A_DAC_ZERO, 4, 5, 1, 0),
136 SOC_DOUBLE_STS("DAC4 Zero Flag", PCM3168A_DAC_ZERO, 6, 7, 1, 0),
137 SOC_ENUM("DAC Volume Control Type", pcm3168a_dac_volume_type),
138 SOC_ENUM("DAC Volume Rate Multiplier", pcm3168a_dac_att_mult),
139 SOC_ENUM("DAC De-Emphasis", pcm3168a_dac_demp),
140 SOC_ENUM("DAC Zero Flag Function", pcm3168a_dac_zf_func),
141 SOC_ENUM("DAC Zero Flag Polarity", pcm3168a_dac_zf_pol),
142 SOC_SINGLE_RANGE_TLV("Master Playback Volume",
143 PCM3168A_DAC_VOL_MASTER, 0, 54, 255, 0,
144 pcm3168a_dac_tlv),
145 SOC_DOUBLE_R_RANGE_TLV("DAC1 Playback Volume",
146 PCM3168A_DAC_VOL_CHAN_START,
147 PCM3168A_DAC_VOL_CHAN_START + 1,
148 0, 54, 255, 0, pcm3168a_dac_tlv),
149 SOC_DOUBLE_R_RANGE_TLV("DAC2 Playback Volume",
150 PCM3168A_DAC_VOL_CHAN_START + 2,
151 PCM3168A_DAC_VOL_CHAN_START + 3,
152 0, 54, 255, 0, pcm3168a_dac_tlv),
153 SOC_DOUBLE_R_RANGE_TLV("DAC3 Playback Volume",
154 PCM3168A_DAC_VOL_CHAN_START + 4,
155 PCM3168A_DAC_VOL_CHAN_START + 5,
156 0, 54, 255, 0, pcm3168a_dac_tlv),
157 SOC_DOUBLE_R_RANGE_TLV("DAC4 Playback Volume",
158 PCM3168A_DAC_VOL_CHAN_START + 6,
159 PCM3168A_DAC_VOL_CHAN_START + 7,
160 0, 54, 255, 0, pcm3168a_dac_tlv),
161 SOC_SINGLE("ADC1 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
162 PCM3168A_ADC_BYP_SHIFT, 1, 1),
163 SOC_SINGLE("ADC2 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
164 PCM3168A_ADC_BYP_SHIFT + 1, 1, 1),
165 SOC_SINGLE("ADC3 High-Pass Filter Switch", PCM3168A_ADC_PWR_HPFB,
166 PCM3168A_ADC_BYP_SHIFT + 2, 1, 1),
167 SOC_ENUM("ADC1 Connection Type", pcm3168a_adc1_con),
168 SOC_ENUM("ADC2 Connection Type", pcm3168a_adc2_con),
169 SOC_ENUM("ADC3 Connection Type", pcm3168a_adc3_con),
170 SOC_DOUBLE("ADC1 Invert Switch", PCM3168A_ADC_INV, 0, 1, 1, 0),
171 SOC_DOUBLE("ADC2 Invert Switch", PCM3168A_ADC_INV, 2, 3, 1, 0),
172 SOC_DOUBLE("ADC3 Invert Switch", PCM3168A_ADC_INV, 4, 5, 1, 0),
173 SOC_DOUBLE("ADC1 Mute Switch", PCM3168A_ADC_MUTE, 0, 1, 1, 0),
174 SOC_DOUBLE("ADC2 Mute Switch", PCM3168A_ADC_MUTE, 2, 3, 1, 0),
175 SOC_DOUBLE("ADC3 Mute Switch", PCM3168A_ADC_MUTE, 4, 5, 1, 0),
176 SOC_DOUBLE_STS("ADC1 Overflow Flag", PCM3168A_ADC_OV, 0, 1, 1, 0),
177 SOC_DOUBLE_STS("ADC2 Overflow Flag", PCM3168A_ADC_OV, 2, 3, 1, 0),
178 SOC_DOUBLE_STS("ADC3 Overflow Flag", PCM3168A_ADC_OV, 4, 5, 1, 0),
179 SOC_ENUM("ADC Volume Control Type", pcm3168a_adc_volume_type),
180 SOC_ENUM("ADC Volume Rate Multiplier", pcm3168a_adc_att_mult),
181 SOC_ENUM("ADC Overflow Flag Polarity", pcm3168a_adc_ov_pol),
182 SOC_SINGLE_RANGE_TLV("Master Capture Volume",
183 PCM3168A_ADC_VOL_MASTER, 0, 14, 255, 0,
184 pcm3168a_adc_tlv),
185 SOC_DOUBLE_R_RANGE_TLV("ADC1 Capture Volume",
186 PCM3168A_ADC_VOL_CHAN_START,
187 PCM3168A_ADC_VOL_CHAN_START + 1,
188 0, 14, 255, 0, pcm3168a_adc_tlv),
189 SOC_DOUBLE_R_RANGE_TLV("ADC2 Capture Volume",
190 PCM3168A_ADC_VOL_CHAN_START + 2,
191 PCM3168A_ADC_VOL_CHAN_START + 3,
192 0, 14, 255, 0, pcm3168a_adc_tlv),
193 SOC_DOUBLE_R_RANGE_TLV("ADC3 Capture Volume",
194 PCM3168A_ADC_VOL_CHAN_START + 4,
195 PCM3168A_ADC_VOL_CHAN_START + 5,
196 0, 14, 255, 0, pcm3168a_adc_tlv)
197 };
198
199 static const struct snd_soc_dapm_widget pcm3168a_dapm_widgets[] = {
200 SND_SOC_DAPM_DAC("DAC1", "Playback", PCM3168A_DAC_OP_FLT,
201 PCM3168A_DAC_OPEDA_SHIFT, 1),
202 SND_SOC_DAPM_DAC("DAC2", "Playback", PCM3168A_DAC_OP_FLT,
203 PCM3168A_DAC_OPEDA_SHIFT + 1, 1),
204 SND_SOC_DAPM_DAC("DAC3", "Playback", PCM3168A_DAC_OP_FLT,
205 PCM3168A_DAC_OPEDA_SHIFT + 2, 1),
206 SND_SOC_DAPM_DAC("DAC4", "Playback", PCM3168A_DAC_OP_FLT,
207 PCM3168A_DAC_OPEDA_SHIFT + 3, 1),
208
209 SND_SOC_DAPM_OUTPUT("AOUT1L"),
210 SND_SOC_DAPM_OUTPUT("AOUT1R"),
211 SND_SOC_DAPM_OUTPUT("AOUT2L"),
212 SND_SOC_DAPM_OUTPUT("AOUT2R"),
213 SND_SOC_DAPM_OUTPUT("AOUT3L"),
214 SND_SOC_DAPM_OUTPUT("AOUT3R"),
215 SND_SOC_DAPM_OUTPUT("AOUT4L"),
216 SND_SOC_DAPM_OUTPUT("AOUT4R"),
217
218 SND_SOC_DAPM_ADC("ADC1", "Capture", PCM3168A_ADC_PWR_HPFB,
219 PCM3168A_ADC_PSVAD_SHIFT, 1),
220 SND_SOC_DAPM_ADC("ADC2", "Capture", PCM3168A_ADC_PWR_HPFB,
221 PCM3168A_ADC_PSVAD_SHIFT + 1, 1),
222 SND_SOC_DAPM_ADC("ADC3", "Capture", PCM3168A_ADC_PWR_HPFB,
223 PCM3168A_ADC_PSVAD_SHIFT + 2, 1),
224
225 SND_SOC_DAPM_INPUT("AIN1L"),
226 SND_SOC_DAPM_INPUT("AIN1R"),
227 SND_SOC_DAPM_INPUT("AIN2L"),
228 SND_SOC_DAPM_INPUT("AIN2R"),
229 SND_SOC_DAPM_INPUT("AIN3L"),
230 SND_SOC_DAPM_INPUT("AIN3R")
231 };
232
233 static const struct snd_soc_dapm_route pcm3168a_dapm_routes[] = {
234 /* Playback */
235 { "AOUT1L", NULL, "DAC1" },
236 { "AOUT1R", NULL, "DAC1" },
237
238 { "AOUT2L", NULL, "DAC2" },
239 { "AOUT2R", NULL, "DAC2" },
240
241 { "AOUT3L", NULL, "DAC3" },
242 { "AOUT3R", NULL, "DAC3" },
243
244 { "AOUT4L", NULL, "DAC4" },
245 { "AOUT4R", NULL, "DAC4" },
246
247 /* Capture */
248 { "ADC1", NULL, "AIN1L" },
249 { "ADC1", NULL, "AIN1R" },
250
251 { "ADC2", NULL, "AIN2L" },
252 { "ADC2", NULL, "AIN2R" },
253
254 { "ADC3", NULL, "AIN3L" },
255 { "ADC3", NULL, "AIN3R" }
256 };
257
258 static unsigned int pcm3168a_scki_ratios[] = {
259 768,
260 512,
261 384,
262 256,
263 192,
264 128
265 };
266
267 #define PCM3168A_NUM_SCKI_RATIOS_DAC ARRAY_SIZE(pcm3168a_scki_ratios)
268 #define PCM3168A_NUM_SCKI_RATIOS_ADC (ARRAY_SIZE(pcm3168a_scki_ratios) - 2)
269
270 #define PCM1368A_MAX_SYSCLK 36864000
271
pcm3168a_reset(struct pcm3168a_priv * pcm3168a)272 static int pcm3168a_reset(struct pcm3168a_priv *pcm3168a)
273 {
274 int ret;
275
276 ret = regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE, 0);
277 if (ret)
278 return ret;
279
280 /* Internal reset is de-asserted after 3846 SCKI cycles */
281 msleep(DIV_ROUND_UP(3846 * 1000, pcm3168a->sysclk));
282
283 return regmap_write(pcm3168a->regmap, PCM3168A_RST_SMODE,
284 PCM3168A_MRST_MASK | PCM3168A_SRST_MASK);
285 }
286
pcm3168a_digital_mute(struct snd_soc_dai * dai,int mute)287 static int pcm3168a_digital_mute(struct snd_soc_dai *dai, int mute)
288 {
289 struct snd_soc_component *component = dai->component;
290 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
291
292 regmap_write(pcm3168a->regmap, PCM3168A_DAC_MUTE, mute ? 0xff : 0);
293
294 return 0;
295 }
296
pcm3168a_set_dai_sysclk(struct snd_soc_dai * dai,int clk_id,unsigned int freq,int dir)297 static int pcm3168a_set_dai_sysclk(struct snd_soc_dai *dai,
298 int clk_id, unsigned int freq, int dir)
299 {
300 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(dai->component);
301 int ret;
302
303 if (freq > PCM1368A_MAX_SYSCLK)
304 return -EINVAL;
305
306 ret = clk_set_rate(pcm3168a->scki, freq);
307 if (ret)
308 return ret;
309
310 pcm3168a->sysclk = freq;
311
312 return 0;
313 }
314
pcm3168a_set_dai_fmt(struct snd_soc_dai * dai,unsigned int format,bool dac)315 static int pcm3168a_set_dai_fmt(struct snd_soc_dai *dai,
316 unsigned int format, bool dac)
317 {
318 struct snd_soc_component *component = dai->component;
319 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
320 u32 fmt, reg, mask, shift;
321 bool master_mode;
322
323 switch (format & SND_SOC_DAIFMT_FORMAT_MASK) {
324 case SND_SOC_DAIFMT_LEFT_J:
325 fmt = PCM3168A_FMT_LEFT_J;
326 break;
327 case SND_SOC_DAIFMT_I2S:
328 fmt = PCM3168A_FMT_I2S;
329 break;
330 case SND_SOC_DAIFMT_RIGHT_J:
331 fmt = PCM3168A_FMT_RIGHT_J;
332 break;
333 case SND_SOC_DAIFMT_DSP_A:
334 fmt = PCM3168A_FMT_DSP_A;
335 break;
336 case SND_SOC_DAIFMT_DSP_B:
337 fmt = PCM3168A_FMT_DSP_B;
338 break;
339 default:
340 dev_err(component->dev, "unsupported dai format\n");
341 return -EINVAL;
342 }
343
344 switch (format & SND_SOC_DAIFMT_MASTER_MASK) {
345 case SND_SOC_DAIFMT_CBS_CFS:
346 master_mode = false;
347 break;
348 case SND_SOC_DAIFMT_CBM_CFM:
349 master_mode = true;
350 break;
351 default:
352 dev_err(component->dev, "unsupported master/slave mode\n");
353 return -EINVAL;
354 }
355
356 switch (format & SND_SOC_DAIFMT_INV_MASK) {
357 case SND_SOC_DAIFMT_NB_NF:
358 break;
359 default:
360 return -EINVAL;
361 }
362
363 if (dac) {
364 reg = PCM3168A_DAC_PWR_MST_FMT;
365 mask = PCM3168A_DAC_FMT_MASK;
366 shift = PCM3168A_DAC_FMT_SHIFT;
367 pcm3168a->dac_master_mode = master_mode;
368 pcm3168a->dac_fmt = fmt;
369 } else {
370 reg = PCM3168A_ADC_MST_FMT;
371 mask = PCM3168A_ADC_FMTAD_MASK;
372 shift = PCM3168A_ADC_FMTAD_SHIFT;
373 pcm3168a->adc_master_mode = master_mode;
374 pcm3168a->adc_fmt = fmt;
375 }
376
377 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
378
379 return 0;
380 }
381
pcm3168a_set_dai_fmt_dac(struct snd_soc_dai * dai,unsigned int format)382 static int pcm3168a_set_dai_fmt_dac(struct snd_soc_dai *dai,
383 unsigned int format)
384 {
385 return pcm3168a_set_dai_fmt(dai, format, true);
386 }
387
pcm3168a_set_dai_fmt_adc(struct snd_soc_dai * dai,unsigned int format)388 static int pcm3168a_set_dai_fmt_adc(struct snd_soc_dai *dai,
389 unsigned int format)
390 {
391 return pcm3168a_set_dai_fmt(dai, format, false);
392 }
393
pcm3168a_hw_params(struct snd_pcm_substream * substream,struct snd_pcm_hw_params * params,struct snd_soc_dai * dai)394 static int pcm3168a_hw_params(struct snd_pcm_substream *substream,
395 struct snd_pcm_hw_params *params,
396 struct snd_soc_dai *dai)
397 {
398 struct snd_soc_component *component = dai->component;
399 struct pcm3168a_priv *pcm3168a = snd_soc_component_get_drvdata(component);
400 bool tx, master_mode;
401 u32 val, mask, shift, reg;
402 unsigned int rate, fmt, ratio, max_ratio;
403 int i, min_frame_size;
404
405 rate = params_rate(params);
406
407 ratio = pcm3168a->sysclk / rate;
408
409 tx = substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
410 if (tx) {
411 max_ratio = PCM3168A_NUM_SCKI_RATIOS_DAC;
412 reg = PCM3168A_DAC_PWR_MST_FMT;
413 mask = PCM3168A_DAC_MSDA_MASK;
414 shift = PCM3168A_DAC_MSDA_SHIFT;
415 master_mode = pcm3168a->dac_master_mode;
416 fmt = pcm3168a->dac_fmt;
417 } else {
418 max_ratio = PCM3168A_NUM_SCKI_RATIOS_ADC;
419 reg = PCM3168A_ADC_MST_FMT;
420 mask = PCM3168A_ADC_MSAD_MASK;
421 shift = PCM3168A_ADC_MSAD_SHIFT;
422 master_mode = pcm3168a->adc_master_mode;
423 fmt = pcm3168a->adc_fmt;
424 }
425
426 for (i = 0; i < max_ratio; i++) {
427 if (pcm3168a_scki_ratios[i] == ratio)
428 break;
429 }
430
431 if (i == max_ratio) {
432 dev_err(component->dev, "unsupported sysclk ratio\n");
433 return -EINVAL;
434 }
435
436 min_frame_size = params_width(params) * 2;
437 switch (min_frame_size) {
438 case 32:
439 if (master_mode || (fmt != PCM3168A_FMT_RIGHT_J)) {
440 dev_err(component->dev, "32-bit frames are supported only for slave mode using right justified\n");
441 return -EINVAL;
442 }
443 fmt = PCM3168A_FMT_RIGHT_J_16;
444 break;
445 case 48:
446 if (master_mode || (fmt & PCM3168A_FMT_DSP_MASK)) {
447 dev_err(component->dev, "48-bit frames not supported in master mode, or slave mode using DSP\n");
448 return -EINVAL;
449 }
450 break;
451 case 64:
452 break;
453 default:
454 dev_err(component->dev, "unsupported frame size: %d\n", min_frame_size);
455 return -EINVAL;
456 }
457
458 if (master_mode)
459 val = ((i + 1) << shift);
460 else
461 val = 0;
462
463 regmap_update_bits(pcm3168a->regmap, reg, mask, val);
464
465 if (tx) {
466 mask = PCM3168A_DAC_FMT_MASK;
467 shift = PCM3168A_DAC_FMT_SHIFT;
468 } else {
469 mask = PCM3168A_ADC_FMTAD_MASK;
470 shift = PCM3168A_ADC_FMTAD_SHIFT;
471 }
472
473 regmap_update_bits(pcm3168a->regmap, reg, mask, fmt << shift);
474
475 return 0;
476 }
477
478 static const struct snd_soc_dai_ops pcm3168a_dac_dai_ops = {
479 .set_fmt = pcm3168a_set_dai_fmt_dac,
480 .set_sysclk = pcm3168a_set_dai_sysclk,
481 .hw_params = pcm3168a_hw_params,
482 .digital_mute = pcm3168a_digital_mute
483 };
484
485 static const struct snd_soc_dai_ops pcm3168a_adc_dai_ops = {
486 .set_fmt = pcm3168a_set_dai_fmt_adc,
487 .set_sysclk = pcm3168a_set_dai_sysclk,
488 .hw_params = pcm3168a_hw_params
489 };
490
491 static struct snd_soc_dai_driver pcm3168a_dais[] = {
492 {
493 .name = "pcm3168a-dac",
494 .playback = {
495 .stream_name = "Playback",
496 .channels_min = 1,
497 .channels_max = 8,
498 .rates = SNDRV_PCM_RATE_8000_192000,
499 .formats = PCM3168A_FORMATS
500 },
501 .ops = &pcm3168a_dac_dai_ops
502 },
503 {
504 .name = "pcm3168a-adc",
505 .capture = {
506 .stream_name = "Capture",
507 .channels_min = 1,
508 .channels_max = 6,
509 .rates = SNDRV_PCM_RATE_8000_96000,
510 .formats = PCM3168A_FORMATS
511 },
512 .ops = &pcm3168a_adc_dai_ops
513 },
514 };
515
516 static const struct reg_default pcm3168a_reg_default[] = {
517 { PCM3168A_RST_SMODE, PCM3168A_MRST_MASK | PCM3168A_SRST_MASK },
518 { PCM3168A_DAC_PWR_MST_FMT, 0x00 },
519 { PCM3168A_DAC_OP_FLT, 0x00 },
520 { PCM3168A_DAC_INV, 0x00 },
521 { PCM3168A_DAC_MUTE, 0x00 },
522 { PCM3168A_DAC_ZERO, 0x00 },
523 { PCM3168A_DAC_ATT_DEMP_ZF, 0x00 },
524 { PCM3168A_DAC_VOL_MASTER, 0xff },
525 { PCM3168A_DAC_VOL_CHAN_START, 0xff },
526 { PCM3168A_DAC_VOL_CHAN_START + 1, 0xff },
527 { PCM3168A_DAC_VOL_CHAN_START + 2, 0xff },
528 { PCM3168A_DAC_VOL_CHAN_START + 3, 0xff },
529 { PCM3168A_DAC_VOL_CHAN_START + 4, 0xff },
530 { PCM3168A_DAC_VOL_CHAN_START + 5, 0xff },
531 { PCM3168A_DAC_VOL_CHAN_START + 6, 0xff },
532 { PCM3168A_DAC_VOL_CHAN_START + 7, 0xff },
533 { PCM3168A_ADC_SMODE, 0x00 },
534 { PCM3168A_ADC_MST_FMT, 0x00 },
535 { PCM3168A_ADC_PWR_HPFB, 0x00 },
536 { PCM3168A_ADC_SEAD, 0x00 },
537 { PCM3168A_ADC_INV, 0x00 },
538 { PCM3168A_ADC_MUTE, 0x00 },
539 { PCM3168A_ADC_OV, 0x00 },
540 { PCM3168A_ADC_ATT_OVF, 0x00 },
541 { PCM3168A_ADC_VOL_MASTER, 0xd3 },
542 { PCM3168A_ADC_VOL_CHAN_START, 0xd3 },
543 { PCM3168A_ADC_VOL_CHAN_START + 1, 0xd3 },
544 { PCM3168A_ADC_VOL_CHAN_START + 2, 0xd3 },
545 { PCM3168A_ADC_VOL_CHAN_START + 3, 0xd3 },
546 { PCM3168A_ADC_VOL_CHAN_START + 4, 0xd3 },
547 { PCM3168A_ADC_VOL_CHAN_START + 5, 0xd3 }
548 };
549
pcm3168a_readable_register(struct device * dev,unsigned int reg)550 static bool pcm3168a_readable_register(struct device *dev, unsigned int reg)
551 {
552 if (reg >= PCM3168A_RST_SMODE)
553 return true;
554 else
555 return false;
556 }
557
pcm3168a_volatile_register(struct device * dev,unsigned int reg)558 static bool pcm3168a_volatile_register(struct device *dev, unsigned int reg)
559 {
560 switch (reg) {
561 case PCM3168A_DAC_ZERO:
562 case PCM3168A_ADC_OV:
563 return true;
564 default:
565 return false;
566 }
567 }
568
pcm3168a_writeable_register(struct device * dev,unsigned int reg)569 static bool pcm3168a_writeable_register(struct device *dev, unsigned int reg)
570 {
571 if (reg < PCM3168A_RST_SMODE)
572 return false;
573
574 switch (reg) {
575 case PCM3168A_DAC_ZERO:
576 case PCM3168A_ADC_OV:
577 return false;
578 default:
579 return true;
580 }
581 }
582
583 const struct regmap_config pcm3168a_regmap = {
584 .reg_bits = 8,
585 .val_bits = 8,
586
587 .max_register = PCM3168A_ADC_VOL_CHAN_START + 5,
588 .reg_defaults = pcm3168a_reg_default,
589 .num_reg_defaults = ARRAY_SIZE(pcm3168a_reg_default),
590 .readable_reg = pcm3168a_readable_register,
591 .volatile_reg = pcm3168a_volatile_register,
592 .writeable_reg = pcm3168a_writeable_register,
593 .cache_type = REGCACHE_FLAT
594 };
595 EXPORT_SYMBOL_GPL(pcm3168a_regmap);
596
597 static const struct snd_soc_component_driver pcm3168a_driver = {
598 .controls = pcm3168a_snd_controls,
599 .num_controls = ARRAY_SIZE(pcm3168a_snd_controls),
600 .dapm_widgets = pcm3168a_dapm_widgets,
601 .num_dapm_widgets = ARRAY_SIZE(pcm3168a_dapm_widgets),
602 .dapm_routes = pcm3168a_dapm_routes,
603 .num_dapm_routes = ARRAY_SIZE(pcm3168a_dapm_routes),
604 .use_pmdown_time = 1,
605 .endianness = 1,
606 .non_legacy_dai_naming = 1,
607 };
608
pcm3168a_probe(struct device * dev,struct regmap * regmap)609 int pcm3168a_probe(struct device *dev, struct regmap *regmap)
610 {
611 struct pcm3168a_priv *pcm3168a;
612 int ret, i;
613
614 pcm3168a = devm_kzalloc(dev, sizeof(*pcm3168a), GFP_KERNEL);
615 if (pcm3168a == NULL)
616 return -ENOMEM;
617
618 dev_set_drvdata(dev, pcm3168a);
619
620 pcm3168a->scki = devm_clk_get(dev, "scki");
621 if (IS_ERR(pcm3168a->scki)) {
622 ret = PTR_ERR(pcm3168a->scki);
623 if (ret != -EPROBE_DEFER)
624 dev_err(dev, "failed to acquire clock 'scki': %d\n", ret);
625 return ret;
626 }
627
628 ret = clk_prepare_enable(pcm3168a->scki);
629 if (ret) {
630 dev_err(dev, "Failed to enable mclk: %d\n", ret);
631 return ret;
632 }
633
634 pcm3168a->sysclk = clk_get_rate(pcm3168a->scki);
635
636 for (i = 0; i < ARRAY_SIZE(pcm3168a->supplies); i++)
637 pcm3168a->supplies[i].supply = pcm3168a_supply_names[i];
638
639 ret = devm_regulator_bulk_get(dev,
640 ARRAY_SIZE(pcm3168a->supplies), pcm3168a->supplies);
641 if (ret) {
642 if (ret != -EPROBE_DEFER)
643 dev_err(dev, "failed to request supplies: %d\n", ret);
644 goto err_clk;
645 }
646
647 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
648 pcm3168a->supplies);
649 if (ret) {
650 dev_err(dev, "failed to enable supplies: %d\n", ret);
651 goto err_clk;
652 }
653
654 pcm3168a->regmap = regmap;
655 if (IS_ERR(pcm3168a->regmap)) {
656 ret = PTR_ERR(pcm3168a->regmap);
657 dev_err(dev, "failed to allocate regmap: %d\n", ret);
658 goto err_regulator;
659 }
660
661 ret = pcm3168a_reset(pcm3168a);
662 if (ret) {
663 dev_err(dev, "Failed to reset device: %d\n", ret);
664 goto err_regulator;
665 }
666
667 pm_runtime_set_active(dev);
668 pm_runtime_enable(dev);
669 pm_runtime_idle(dev);
670
671 ret = devm_snd_soc_register_component(dev, &pcm3168a_driver, pcm3168a_dais,
672 ARRAY_SIZE(pcm3168a_dais));
673 if (ret) {
674 dev_err(dev, "failed to register component: %d\n", ret);
675 goto err_regulator;
676 }
677
678 return 0;
679
680 err_regulator:
681 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
682 pcm3168a->supplies);
683 err_clk:
684 clk_disable_unprepare(pcm3168a->scki);
685
686 return ret;
687 }
688 EXPORT_SYMBOL_GPL(pcm3168a_probe);
689
pcm3168a_disable(struct device * dev)690 static void pcm3168a_disable(struct device *dev)
691 {
692 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
693
694 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
695 pcm3168a->supplies);
696 clk_disable_unprepare(pcm3168a->scki);
697 }
698
pcm3168a_remove(struct device * dev)699 void pcm3168a_remove(struct device *dev)
700 {
701 pm_runtime_disable(dev);
702 #ifndef CONFIG_PM
703 pcm3168a_disable(dev);
704 #endif
705 }
706 EXPORT_SYMBOL_GPL(pcm3168a_remove);
707
708 #ifdef CONFIG_PM
pcm3168a_rt_resume(struct device * dev)709 static int pcm3168a_rt_resume(struct device *dev)
710 {
711 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
712 int ret;
713
714 ret = clk_prepare_enable(pcm3168a->scki);
715 if (ret) {
716 dev_err(dev, "Failed to enable mclk: %d\n", ret);
717 return ret;
718 }
719
720 ret = regulator_bulk_enable(ARRAY_SIZE(pcm3168a->supplies),
721 pcm3168a->supplies);
722 if (ret) {
723 dev_err(dev, "Failed to enable supplies: %d\n", ret);
724 goto err_clk;
725 }
726
727 ret = pcm3168a_reset(pcm3168a);
728 if (ret) {
729 dev_err(dev, "Failed to reset device: %d\n", ret);
730 goto err_regulator;
731 }
732
733 regcache_cache_only(pcm3168a->regmap, false);
734
735 regcache_mark_dirty(pcm3168a->regmap);
736
737 ret = regcache_sync(pcm3168a->regmap);
738 if (ret) {
739 dev_err(dev, "Failed to sync regmap: %d\n", ret);
740 goto err_regulator;
741 }
742
743 return 0;
744
745 err_regulator:
746 regulator_bulk_disable(ARRAY_SIZE(pcm3168a->supplies),
747 pcm3168a->supplies);
748 err_clk:
749 clk_disable_unprepare(pcm3168a->scki);
750
751 return ret;
752 }
753
pcm3168a_rt_suspend(struct device * dev)754 static int pcm3168a_rt_suspend(struct device *dev)
755 {
756 struct pcm3168a_priv *pcm3168a = dev_get_drvdata(dev);
757
758 regcache_cache_only(pcm3168a->regmap, true);
759
760 pcm3168a_disable(dev);
761
762 return 0;
763 }
764 #endif
765
766 const struct dev_pm_ops pcm3168a_pm_ops = {
767 SET_RUNTIME_PM_OPS(pcm3168a_rt_suspend, pcm3168a_rt_resume, NULL)
768 };
769 EXPORT_SYMBOL_GPL(pcm3168a_pm_ops);
770
771 MODULE_DESCRIPTION("PCM3168A codec driver");
772 MODULE_AUTHOR("Damien Horsley <Damien.Horsley@imgtec.com>");
773 MODULE_LICENSE("GPL v2");
774